2 * probe.c - PCI detection and setup code
5 #include <linux/init.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/cpumask.h>
14 #define DBG(x...) printk(x)
19 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
20 #define CARDBUS_RESERVE_BUSNR 3
21 #define PCI_CFG_SPACE_SIZE 256
22 #define PCI_CFG_SPACE_EXP_SIZE 4096
24 /* Ugh. Need to stop exporting this to modules. */
25 LIST_HEAD(pci_root_buses);
26 EXPORT_SYMBOL(pci_root_buses);
28 LIST_HEAD(pci_devices);
33 static void release_pcibus_dev(struct class_device *class_dev)
35 struct pci_bus *pci_bus = to_pci_bus(class_dev);
37 put_device(pci_bus->bridge);
41 static struct class pcibus_class = {
43 .release = &release_pcibus_dev,
46 static int __init pcibus_class_init(void)
48 return class_register(&pcibus_class);
50 postcore_initcall(pcibus_class_init);
53 * PCI Bus Class Devices
55 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
57 cpumask_t cpumask = pcibus_to_cpumask((to_pci_bus(class_dev))->number);
60 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
65 static CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
68 * Translate the low bits of the PCI base
69 * to the resource type
71 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
73 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
76 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
77 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
79 return IORESOURCE_MEM;
83 * Find the extent of a PCI decode..
85 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
87 u32 size = mask & maxbase; /* Find the significant bits */
91 /* Get the lowest of them to find the decode size, and
92 from that the extent. */
93 size = (size & ~(size-1)) - 1;
95 /* base == maxbase can be valid only if the BAR has
96 already been programmed with all 1s. */
97 if (base == maxbase && ((base | size) & mask) != mask)
103 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
105 unsigned int pos, reg, next;
107 struct resource *res;
109 for(pos=0; pos<howmany; pos = next) {
111 res = &dev->resource[pos];
112 res->name = pci_name(dev);
113 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
114 pci_read_config_dword(dev, reg, &l);
115 pci_write_config_dword(dev, reg, ~0);
116 pci_read_config_dword(dev, reg, &sz);
117 pci_write_config_dword(dev, reg, l);
118 if (!sz || sz == 0xffffffff)
122 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
123 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
126 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
127 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
129 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
132 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
133 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
135 res->end = res->start + (unsigned long) sz;
136 res->flags |= pci_calc_resource_flags(l);
137 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
138 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
139 pci_read_config_dword(dev, reg+4, &l);
141 #if BITS_PER_LONG == 64
142 res->start |= ((unsigned long) l) << 32;
143 res->end = res->start + sz;
144 pci_write_config_dword(dev, reg+4, ~0);
145 pci_read_config_dword(dev, reg+4, &sz);
146 pci_write_config_dword(dev, reg+4, l);
147 sz = pci_size(l, sz, 0xffffffff);
149 /* This BAR needs > 4GB? Wow. */
150 res->end |= (unsigned long)sz<<32;
154 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
163 dev->rom_base_reg = rom;
164 res = &dev->resource[PCI_ROM_RESOURCE];
165 res->name = pci_name(dev);
166 pci_read_config_dword(dev, rom, &l);
167 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
168 pci_read_config_dword(dev, rom, &sz);
169 pci_write_config_dword(dev, rom, l);
172 if (sz && sz != 0xffffffff) {
173 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
175 res->flags = (l & IORESOURCE_ROM_ENABLE) |
176 IORESOURCE_MEM | IORESOURCE_PREFETCH |
177 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
178 res->start = l & PCI_ROM_ADDRESS_MASK;
179 res->end = res->start + (unsigned long) sz;
185 void __devinit pci_read_bridge_bases(struct pci_bus *child)
187 struct pci_dev *dev = child->self;
188 u8 io_base_lo, io_limit_lo;
189 u16 mem_base_lo, mem_limit_lo;
190 unsigned long base, limit;
191 struct resource *res;
194 if (!dev) /* It's a host bus, nothing to read */
197 if (dev->transparent) {
198 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
199 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
200 child->resource[i] = child->parent->resource[i];
205 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
207 res = child->resource[0];
208 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
209 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
210 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
211 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
213 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
214 u16 io_base_hi, io_limit_hi;
215 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
216 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
217 base |= (io_base_hi << 16);
218 limit |= (io_limit_hi << 16);
222 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
224 res->end = limit + 0xfff;
227 res = child->resource[1];
228 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
229 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
230 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
231 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
233 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
235 res->end = limit + 0xfffff;
238 res = child->resource[2];
239 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
240 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
241 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
242 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
244 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
245 u32 mem_base_hi, mem_limit_hi;
246 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
247 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
250 * Some bridges set the base > limit by default, and some
251 * (broken) BIOSes do not initialize them. If we find
252 * this, just assume they are not being used.
254 if (mem_base_hi <= mem_limit_hi) {
255 #if BITS_PER_LONG == 64
256 base |= ((long) mem_base_hi) << 32;
257 limit |= ((long) mem_limit_hi) << 32;
259 if (mem_base_hi || mem_limit_hi) {
260 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
267 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
269 res->end = limit + 0xfffff;
273 static struct pci_bus * __devinit pci_alloc_bus(void)
277 b = kmalloc(sizeof(*b), GFP_KERNEL);
279 memset(b, 0, sizeof(*b));
280 INIT_LIST_HEAD(&b->node);
281 INIT_LIST_HEAD(&b->children);
282 INIT_LIST_HEAD(&b->devices);
287 static struct pci_bus * __devinit
288 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
290 struct pci_bus *child;
294 * Allocate a new bus, and inherit stuff from the parent..
296 child = pci_alloc_bus();
300 child->self = bridge;
301 child->parent = parent;
302 child->ops = parent->ops;
303 child->sysdata = parent->sysdata;
304 child->bridge = get_device(&bridge->dev);
306 child->class_dev.class = &pcibus_class;
307 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
308 class_device_register(&child->class_dev);
309 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
312 * Set up the primary, secondary and subordinate
315 child->number = child->secondary = busnr;
316 child->primary = parent->secondary;
317 child->subordinate = 0xff;
319 /* Set up default resource pointers and names.. */
320 for (i = 0; i < 4; i++) {
321 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
322 child->resource[i]->name = child->name;
324 bridge->subordinate = child;
329 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
331 struct pci_bus *child;
333 child = pci_alloc_child_bus(parent, dev, busnr);
335 list_add_tail(&child->node, &parent->children);
339 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
342 * If it's a bridge, configure it and scan the bus behind it.
343 * For CardBus bridges, we don't scan behind as the devices will
344 * be handled by the bridge driver itself.
346 * We need to process bridges in two passes -- first we scan those
347 * already configured by the BIOS and after we are done with all of
348 * them, we proceed to assigning numbers to the remaining buses in
349 * order to avoid overlaps between old and new bus numbers.
351 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
353 struct pci_bus *child;
354 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
358 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
360 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n",
361 pci_name(dev), buses & 0xffffff, pass);
363 /* Disable MasterAbortMode during probing to avoid reporting
364 of bus errors (in some architectures) */
365 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
366 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
367 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
369 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
370 unsigned int cmax, busnr;
372 * Bus already configured by firmware, process it in the first
373 * pass and just note the configuration.
377 busnr = (buses >> 8) & 0xFF;
378 child = pci_alloc_child_bus(bus, dev, busnr);
381 child->primary = buses & 0xFF;
382 child->subordinate = (buses >> 16) & 0xFF;
383 child->bridge_ctl = bctl;
385 cmax = pci_scan_child_bus(child);
388 if (child->subordinate > max)
389 max = child->subordinate;
392 * We need to assign a number to this bus which we always
393 * do in the second pass.
399 pci_write_config_word(dev, PCI_STATUS, 0xffff);
401 child = pci_alloc_child_bus(bus, dev, ++max);
402 buses = (buses & 0xff000000)
403 | ((unsigned int)(child->primary) << 0)
404 | ((unsigned int)(child->secondary) << 8)
405 | ((unsigned int)(child->subordinate) << 16);
408 * yenta.c forces a secondary latency timer of 176.
409 * Copy that behaviour here.
412 buses &= ~0xff000000;
413 buses |= CARDBUS_LATENCY_TIMER << 24;
417 * We need to blast all three values with a single write.
419 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
422 child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
424 /* Now we can scan all subordinate buses... */
425 max = pci_scan_child_bus(child);
428 * For CardBus bridges, we leave 4 bus numbers
429 * as cards with a PCI-to-PCI bridge can be
432 max += CARDBUS_RESERVE_BUSNR;
435 * Set the subordinate bus number to its real value.
437 child->subordinate = max;
438 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
441 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
443 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
449 * Read interrupt line and base address registers.
450 * The architecture-dependent code can tweak these, of course.
452 static void pci_read_irq(struct pci_dev *dev)
456 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
458 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
463 * pci_setup_device - fill in class and map information of a device
464 * @dev: the device structure to fill
466 * Initialize the device structure with information about the device's
467 * vendor,class,memory and IO-space addresses,IRQ lines etc.
468 * Called at initialisation of the PCI subsystem and by CardBus services.
469 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
472 static int pci_setup_device(struct pci_dev * dev)
476 dev->slot_name = dev->dev.bus_id;
477 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
478 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
480 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
481 class >>= 8; /* upper 3 bytes */
485 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number,
486 dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
488 /* "Unknown power state" */
489 dev->current_state = 4;
491 /* Early fixups, before probing the BARs */
492 pci_fixup_device(pci_fixup_early, dev);
494 switch (dev->hdr_type) { /* header type */
495 case PCI_HEADER_TYPE_NORMAL: /* standard header */
496 if (class == PCI_CLASS_BRIDGE_PCI)
499 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
500 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
501 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
504 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
505 if (class != PCI_CLASS_BRIDGE_PCI)
507 /* The PCI-to-PCI bridge spec requires that subtractive
508 decoding (i.e. transparent) bridge must have programming
509 interface code of 0x01. */
510 dev->transparent = ((dev->class & 0xff) == 1);
511 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
514 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
515 if (class != PCI_CLASS_BRIDGE_CARDBUS)
518 pci_read_bases(dev, 1, 0);
519 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
520 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
523 default: /* unknown header */
524 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
525 pci_name(dev), dev->hdr_type);
529 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
530 pci_name(dev), class, dev->hdr_type);
531 dev->class = PCI_CLASS_NOT_DEFINED;
534 /* We found a fine healthy device, go go go... */
539 * pci_release_dev - free a pci device structure when all users of it are finished.
540 * @dev: device that's been disconnected
542 * Will be called only by the device core when all users of this pci device are
545 static void pci_release_dev(struct device *dev)
547 struct pci_dev *pci_dev;
549 pci_dev = to_pci_dev(dev);
554 * pci_cfg_space_size - get the configuration space size of the PCI device.
556 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
557 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
558 * access it. Maybe we don't have a way to generate extended config space
559 * accesses, or the device is behind a reverse Express bridge. So we try
560 * reading the dword at 0x100 which must either be 0 or a valid extended
563 static int pci_cfg_space_size(struct pci_dev *dev)
568 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
570 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
574 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
575 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
579 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
581 if (status == 0xffffffff)
584 return PCI_CFG_SPACE_EXP_SIZE;
587 return PCI_CFG_SPACE_SIZE;
590 static void pci_release_bus_bridge_dev(struct device *dev)
596 * Read the config data for a PCI device, sanity-check it
597 * and fill in the dev structure...
599 static struct pci_dev * __devinit
600 pci_scan_device(struct pci_bus *bus, int devfn)
606 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
609 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
612 /* some broken boards return 0 or ~0 if a slot is empty: */
613 if (l == 0xffffffff || l == 0x00000000 ||
614 l == 0x0000ffff || l == 0xffff0000)
617 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
621 memset(dev, 0, sizeof(struct pci_dev));
623 dev->sysdata = bus->sysdata;
624 dev->dev.parent = bus->bridge;
625 dev->dev.bus = &pci_bus_type;
627 dev->hdr_type = hdr_type & 0x7f;
628 dev->multifunction = !!(hdr_type & 0x80);
629 dev->vendor = l & 0xffff;
630 dev->device = (l >> 16) & 0xffff;
631 dev->cfg_size = pci_cfg_space_size(dev);
633 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
634 set this higher, assuming the system even supports it. */
635 dev->dma_mask = 0xffffffff;
636 if (pci_setup_device(dev) < 0) {
640 device_initialize(&dev->dev);
641 dev->dev.release = pci_release_dev;
644 pci_name_device(dev);
646 dev->dev.dma_mask = &dev->dma_mask;
647 dev->dev.coherent_dma_mask = 0xffffffffull;
652 struct pci_dev * __devinit
653 pci_scan_single_device(struct pci_bus *bus, int devfn)
657 dev = pci_scan_device(bus, devfn);
658 pci_scan_msi_device(dev);
663 /* Fix up broken headers */
664 pci_fixup_device(pci_fixup_header, dev);
667 * Add the device to our list of discovered devices
668 * and the bus list for fixup functions, etc.
670 INIT_LIST_HEAD(&dev->global_list);
671 list_add_tail(&dev->bus_list, &bus->devices);
677 * pci_scan_slot - scan a PCI slot on a bus for devices.
678 * @bus: PCI bus to scan
679 * @devfn: slot number to scan (must have zero function.)
681 * Scan a PCI slot on the specified PCI bus for devices, adding
682 * discovered devices to the @bus->devices list. New devices
683 * will have an empty dev->global_list head.
685 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
690 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
692 for (func = 0; func < 8; func++, devfn++) {
695 dev = pci_scan_single_device(bus, devfn);
700 * If this is a single function device,
701 * don't scan past the first function.
703 if (!dev->multifunction) {
705 dev->multifunction = 1;
711 if (func == 0 && !scan_all_fns)
718 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
720 unsigned int devfn, pass, max = bus->secondary;
723 DBG("Scanning bus %02x\n", bus->number);
725 /* Go find them, Rover! */
726 for (devfn = 0; devfn < 0x100; devfn += 8)
727 pci_scan_slot(bus, devfn);
730 * After performing arch-dependent fixup of the bus, look behind
731 * all PCI-to-PCI bridges on this bus.
733 DBG("Fixups for bus %02x\n", bus->number);
734 pcibios_fixup_bus(bus);
735 for (pass=0; pass < 2; pass++)
736 list_for_each_entry(dev, &bus->devices, bus_list) {
737 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
738 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
739 max = pci_scan_bridge(bus, dev, max, pass);
743 * We've scanned the bus and so we know all about what's on
744 * the other side of any bridges that may be on this bus plus
747 * Return how far we've got finding sub-buses.
749 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
753 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
757 max = pci_scan_child_bus(bus);
760 * Make the discovered devices available.
762 pci_bus_add_devices(bus);
767 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
777 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
783 b->sysdata = sysdata;
786 if (pci_find_bus(pci_domain_nr(b), bus)) {
787 /* If we already got to this bus through a different bridge, ignore it */
788 DBG("PCI: Bus %02x already known\n", bus);
791 list_add_tail(&b->node, &pci_root_buses);
793 memset(dev, 0, sizeof(*dev));
794 dev->parent = parent;
795 dev->release = pci_release_bus_bridge_dev;
796 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
797 error = device_register(dev);
800 b->bridge = get_device(dev);
802 b->class_dev.class = &pcibus_class;
803 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
804 error = class_device_register(&b->class_dev);
806 goto class_dev_reg_err;
807 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
809 goto class_dev_create_file_err;
811 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
813 goto sys_create_link_err;
815 b->number = b->secondary = bus;
816 b->resource[0] = &ioport_resource;
817 b->resource[1] = &iomem_resource;
819 b->subordinate = pci_scan_child_bus(b);
821 pci_bus_add_devices(b);
826 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
827 class_dev_create_file_err:
828 class_device_unregister(&b->class_dev);
830 device_unregister(dev);
838 EXPORT_SYMBOL(pci_scan_bus_parented);
840 #ifdef CONFIG_HOTPLUG
841 EXPORT_SYMBOL(pci_add_new_bus);
842 EXPORT_SYMBOL(pci_do_scan_bus);
843 EXPORT_SYMBOL(pci_scan_slot);
844 EXPORT_SYMBOL(pci_scan_bridge);
845 EXPORT_SYMBOL(pci_scan_single_device);
846 EXPORT_SYMBOL_GPL(pci_scan_child_bus);