2 * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
4 * This file contains work-arounds for many known PCI hardware
5 * bugs. Devices present only on certain architectures (host
6 * bridges et cetera) should be handled in arch-specific code.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit quirk_passive_release(struct pci_dev *dev)
28 struct pci_dev *d = NULL;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
38 pci_write_config_byte(d, 0x82, dlc);
43 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
47 This appears to be BIOS not version dependent. So presumably there is a
51 int isa_dma_bridge_buggy; /* Exported */
53 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
55 if (!isa_dma_bridge_buggy) {
56 isa_dma_bridge_buggy=1;
57 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
64 * Chipsets where PCI->PCI transfers vanish or hang
67 static void __devinit quirk_nopcipci(struct pci_dev *dev)
69 if((pci_pci_problems&PCIPCI_FAIL)==0)
71 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
72 pci_pci_problems|=PCIPCI_FAIL;
77 * Triton requires workarounds to be used by the drivers
80 static void __devinit quirk_triton(struct pci_dev *dev)
82 if((pci_pci_problems&PCIPCI_TRITON)==0)
84 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
85 pci_pci_problems|=PCIPCI_TRITON;
90 * VIA Apollo KT133 needs PCI latency patch
91 * Made according to a windows driver based patch by George E. Breese
92 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
93 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
94 * the info on which Mr Breese based his work.
96 * Updated based on further information from the site and also on
97 * information provided by VIA
99 static void __devinit quirk_vialatency(struct pci_dev *dev)
104 /* Ok we have a potential problem chipset here. Now see if we have
105 a buggy southbridge */
107 p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
110 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
111 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
112 /* Check for buggy part revisions */
113 if (rev < 0x40 || rev > 0x42)
118 p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
119 if(p==NULL) /* No problem parts */
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* Check for buggy part revisions */
123 if (rev < 0x10 || rev > 0x12)
128 * Ok we have the problem. Now set the PCI master grant to
129 * occur every master grant. The apparent bug is that under high
130 * PCI load (quite common in Linux of course) you can get data
131 * loss when the CPU is held off the bus for 3 bus master requests
132 * This happens to include the IDE controllers....
134 * VIA only apply this fix when an SB Live! is present but under
135 * both Linux and Windows this isnt enough, and we have seen
136 * corruption without SB Live! but with things like 3 UDMA IDE
137 * controllers. So we ignore that bit of the VIA recommendation..
140 pci_read_config_byte(dev, 0x76, &busarb);
141 /* Set bit 4 and bi 5 of byte 76 to 0x01
142 "Master priority rotation on every PCI master grant */
145 pci_write_config_byte(dev, 0x76, busarb);
146 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
150 * VIA Apollo VP3 needs ETBF on BT848/878
153 static void __devinit quirk_viaetbf(struct pci_dev *dev)
155 if((pci_pci_problems&PCIPCI_VIAETBF)==0)
157 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
158 pci_pci_problems|=PCIPCI_VIAETBF;
161 static void __devinit quirk_vsfx(struct pci_dev *dev)
163 if((pci_pci_problems&PCIPCI_VSFX)==0)
165 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
166 pci_pci_problems|=PCIPCI_VSFX;
171 * Ali Magik requires workarounds to be used by the drivers
172 * that DMA to AGP space. Latency must be set to 0xA and triton
173 * workaround applied too
174 * [Info kindly provided by ALi]
177 static void __init quirk_alimagik(struct pci_dev *dev)
179 if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
182 pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
188 * Natoma has some interesting boundary conditions with Zoran stuff
192 static void __devinit quirk_natoma(struct pci_dev *dev)
194 if((pci_pci_problems&PCIPCI_NATOMA)==0)
196 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
197 pci_pci_problems|=PCIPCI_NATOMA;
202 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
203 * If it's needed, re-allocate the region.
206 static void __devinit quirk_s3_64M(struct pci_dev *dev)
208 struct resource *r = &dev->resource[0];
210 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
216 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
220 struct resource *res = dev->resource + nr;
222 res->name = pci_name(dev);
224 res->end = region + size - 1;
225 res->flags = IORESOURCE_IO;
226 pci_claim_resource(dev, nr);
231 * ATI Northbridge setups MCE the processor if you even
232 * read somewhere between 0x3b0->0x3bb or read 0x3d3
235 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
237 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
238 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
239 request_region(0x3b0, 0x0C, "RadeonIGP");
240 request_region(0x3d3, 0x01, "RadeonIGP");
244 * Let's make the southbridge information explicit instead
245 * of having to worry about people probing the ACPI areas,
246 * for example.. (Yes, it happens, and if you read the wrong
247 * ACPI register it will put the machine to sleep with no
248 * way of waking it up again. Bummer).
250 * ALI M7101: Two IO regions pointed to by words at
251 * 0xE0 (64 bytes of ACPI registers)
252 * 0xE2 (32 bytes of SMB registers)
254 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
258 pci_read_config_word(dev, 0xE0, ®ion);
259 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
260 pci_read_config_word(dev, 0xE2, ®ion);
261 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
265 * PIIX4 ACPI: Two IO regions pointed to by longwords at
266 * 0x40 (64 bytes of ACPI registers)
267 * 0x90 (32 bytes of SMB registers)
269 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
273 pci_read_config_dword(dev, 0x40, ®ion);
274 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
275 pci_read_config_dword(dev, 0x90, ®ion);
276 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
280 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
281 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
282 * 0x58 (64 bytes of GPIO I/O space)
284 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
288 pci_read_config_dword(dev, 0x40, ®ion);
289 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
291 pci_read_config_dword(dev, 0x58, ®ion);
292 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
296 * VIA ACPI: One IO region pointed to by longword at
297 * 0x48 or 0x20 (256 bytes of ACPI registers)
299 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
304 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
306 pci_read_config_dword(dev, 0x48, ®ion);
307 region &= PCI_BASE_ADDRESS_IO_MASK;
308 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
313 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
314 * 0x48 (256 bytes of ACPI registers)
315 * 0x70 (128 bytes of hardware monitoring register)
316 * 0x90 (16 bytes of SMB registers)
318 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
323 quirk_vt82c586_acpi(dev);
325 pci_read_config_word(dev, 0x70, &hm);
326 hm &= PCI_BASE_ADDRESS_IO_MASK;
327 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
329 pci_read_config_dword(dev, 0x90, &smb);
330 smb &= PCI_BASE_ADDRESS_IO_MASK;
331 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
335 #ifdef CONFIG_X86_IO_APIC
337 #include <asm/io_apic.h>
340 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
341 * devices to the external APIC.
343 * TODO: When we have device-specific interrupt routers,
344 * this code will go away from quirks.
346 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
351 tmp = 0; /* nothing routed to external APIC */
353 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
355 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
356 tmp == 0 ? "Disa" : "Ena");
358 /* Offset 0x58: External APIC IRQ output control */
359 pci_write_config_byte (dev, 0x58, tmp);
363 * The AMD io apic can hang the box when an apic irq is masked.
364 * We check all revs >= B0 (yet not in the pre production!) as the bug
365 * is currently marked NoFix
367 * We have multiple reports of hangs with this chipset that went away with
368 * noapic specified. For the moment we assume its the errata. We may be wrong
369 * of course. However the advice is demonstrably good even if so..
372 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
376 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
379 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
380 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
384 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
386 if (dev->devfn == 0 && dev->bus->number == 0)
390 #define AMD8131_revA0 0x01
391 #define AMD8131_revB0 0x11
392 #define AMD8131_MISC 0x40
393 #define AMD8131_NIOAMODE_BIT 0
395 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
397 unsigned char revid, tmp;
402 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
403 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
404 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
405 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
406 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
407 pci_write_config_byte( dev, AMD8131_MISC, tmp);
411 #endif /* CONFIG_X86_IO_APIC */
415 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
416 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
417 * when written, it makes an internal connection to the PIC.
418 * For these devices, this register is defined to be 4 bits wide.
419 * Normally this is fine. However for IO-APIC motherboards, or
420 * non-x86 architectures (yes Via exists on PPC among other places),
421 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
422 * interrupts delivered properly.
424 * TODO: When we have device-specific interrupt routers,
425 * quirk_via_irqpic will go away from quirks.
429 * FIXME: it is questionable that quirk_via_acpi
430 * is needed. It shows up as an ISA bridge, and does not
431 * support the PCI_INTERRUPT_LINE register at all. Therefore
432 * it seems like setting the pci_dev's 'irq' to the
433 * value of the ACPI SCI interrupt is only done for convenience.
436 static void __devinit quirk_via_acpi(struct pci_dev *d)
439 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
442 pci_read_config_byte(d, 0x42, &irq);
444 if (irq && (irq != 2))
448 static void __devinit quirk_via_irqpic(struct pci_dev *dev)
450 u8 irq, new_irq = dev->irq & 0xf;
452 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
454 if (new_irq != irq) {
455 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
456 pci_name(dev), irq, new_irq);
459 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
465 * PIIX3 USB: We have to disable USB interrupts that are
466 * hardwired to PIRQD# and may be shared with an
469 * Legacy Support Register (LEGSUP):
470 * bit13: USB PIRQ Enable (USBPIRQDEN),
471 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
473 * We mask out all r/wc bits, too.
475 static void __devinit quirk_piix3_usb(struct pci_dev *dev)
479 pci_read_config_word(dev, 0xc0, &legsup);
481 pci_write_config_word(dev, 0xc0, legsup);
485 * VIA VT82C598 has its device ID settable and many BIOSes
486 * set it to the ID of VT82C597 for backward compatibility.
487 * We need to switch it off to be able to recognize the real
490 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
492 pci_write_config_byte(dev, 0xfc, 0);
493 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
497 * CardBus controllers have a legacy base address that enables them
498 * to respond as i82365 pcmcia controllers. We don't want them to
499 * do this even if the Linux CardBus driver is not loaded, because
500 * the Linux i82365 driver does not (and should not) handle CardBus.
502 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
504 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
506 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
510 * Following the PCI ordering rules is optional on the AMD762. I'm not
511 * sure what the designers were smoking but let's not inhale...
513 * To be fair to AMD, it follows the spec by default, its BIOS people
517 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
520 pci_read_config_dword(dev, 0x4C, &pcic);
524 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
525 pci_write_config_dword(dev, 0x4C, pcic);
526 pci_read_config_dword(dev, 0x84, &pcic);
527 pcic |= (1<<23); /* Required in this mode */
528 pci_write_config_dword(dev, 0x84, pcic);
533 * DreamWorks provided workaround for Dunord I-3000 problem
535 * This card decodes and responds to addresses not apparently
536 * assigned to it. We force a larger allocation to ensure that
537 * nothing gets put too close to it.
540 static void __devinit quirk_dunord ( struct pci_dev * dev )
542 struct resource * r = & dev -> resource [ 1 ];
547 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
549 dev->transparent = 1;
553 * Common misconfiguration of the MediaGX/Geode PCI master that will
554 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
555 * datasheets found at http://www.national.com/ds/GX for info on what
556 * these bits do. <christer@weinigel.se>
559 static void __init quirk_mediagx_master(struct pci_dev *dev)
562 pci_read_config_byte(dev, 0x41, ®);
565 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
566 pci_write_config_byte(dev, 0x41, reg);
571 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
572 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
573 * secondary channels respectively). If the device reports Compatible mode
574 * but does use BAR0-3 for address decoding, we assume that firmware has
575 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
576 * Exceptions (if they exist) must be handled in chip/architecture specific
579 * Note: for non x86 people. You may need an arch specific quirk to handle
580 * moving IDE devices to native mode as well. Some plug in card devices power
581 * up in compatible mode and assume the BIOS will adjust them.
583 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
584 * we do now ? We don't want is pci_enable_device to come along
585 * and assign new resources. Both approaches work for that.
588 static void __devinit quirk_ide_bases(struct pci_dev *dev)
590 struct resource *res;
591 int first_bar = 2, last_bar = 0;
593 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
596 res = &dev->resource[0];
598 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
599 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
600 res[0].start = res[0].end = res[0].flags = 0;
601 res[1].start = res[1].end = res[1].flags = 0;
606 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
607 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
608 res[2].start = res[2].end = res[2].flags = 0;
609 res[3].start = res[3].end = res[3].flags = 0;
616 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
617 first_bar, last_bar, pci_name(dev));
621 * Ensure C0 rev restreaming is off. This is normally done by
622 * the BIOS but in the odd case it is not the results are corruption
623 * hence the presence of a Linux check
626 static void __init quirk_disable_pxb(struct pci_dev *pdev)
631 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
632 if(rev != 0x04) /* Only C0 requires this */
634 pci_read_config_word(pdev, 0x40, &config);
638 pci_write_config_word(pdev, 0x40, config);
639 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
644 * VIA northbridges care about PCI_INTERRUPT_LINE
647 int interrupt_line_quirk;
649 static void __devinit quirk_via_bridge(struct pci_dev *pdev)
652 interrupt_line_quirk = 1;
656 * Serverworks CSB5 IDE does not fully support native mode
658 static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
661 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
665 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
666 /* need to re-assign BARs for compat mode */
667 quirk_ide_bases(pdev);
671 /* This was originally an Alpha specific thing, but it really fits here.
672 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
675 static void __init quirk_eisa_bridge(struct pci_dev *dev)
677 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
681 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
682 * is not activated. The myth is that Asus said that they do not want the
683 * users to be irritated by just another PCI Device in the Win98 device
684 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
685 * package 2.7.0 for details)
687 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
688 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
689 * becomes necessary to do this tweak in two steps -- I've chosen the Host
693 static int __initdata asus_hides_smbus = 0;
695 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
697 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
698 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
699 switch(dev->subsystem_device) {
700 case 0x8070: /* P4B */
701 case 0x8088: /* P4B533 */
702 asus_hides_smbus = 1;
704 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
705 switch(dev->subsystem_device) {
706 case 0x80b1: /* P4GE-V */
707 case 0x80b2: /* P4PE */
708 case 0x8093: /* P4B533-V */
709 asus_hides_smbus = 1;
711 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
712 switch(dev->subsystem_device) {
713 case 0x8030: /* P4T533 */
714 asus_hides_smbus = 1;
716 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
717 switch (dev->subsystem_device) {
718 case 0x8070: /* P4G8X Deluxe */
719 asus_hides_smbus = 1;
721 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
722 switch (dev->subsystem_device) {
723 case 0x1751: /* M2N notebook */
724 asus_hides_smbus = 1;
726 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
727 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
728 switch(dev->subsystem_device) {
729 case 0x088C: /* HP Compaq nc8000 */
730 case 0x0890: /* HP Compaq nc6000 */
731 asus_hides_smbus = 1;
736 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
740 if (likely(!asus_hides_smbus))
743 pci_read_config_word(dev, 0xF2, &val);
745 pci_write_config_word(dev, 0xF2, val & (~0x8));
746 pci_read_config_word(dev, 0xF2, &val);
748 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
750 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
755 * SiS 96x south bridge: BIOS typically hides SMBus device...
757 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
760 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
761 pci_read_config_byte(dev, 0x77, &val);
762 pci_write_config_byte(dev, 0x77, val & ~0x10);
763 pci_read_config_byte(dev, 0x77, &val);
767 * ... This is further complicated by the fact that some SiS96x south
768 * bridges pretend to be 85C503/5513 instead. In that case see if we
769 * spotted a compatible north bridge to make sure.
770 * (pci_find_device doesn't work yet)
772 * We can also enable the sis96x bit in the discovery register..
774 static int __devinitdata sis_96x_compatible = 0;
776 #define SIS_DETECT_REGISTER 0x40
778 static void __init quirk_sis_503(struct pci_dev *dev)
783 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
784 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
785 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
786 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
787 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
791 /* Make people aware that we changed the config.. */
792 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
795 * Ok, it now shows up as a 96x.. The 96x quirks are after
796 * the 503 quirk in the quirk table, so they'll automatically
797 * run and enable things like the SMBus device
802 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
804 sis_96x_compatible = 1;
807 #ifdef CONFIG_X86_IO_APIC
808 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
812 if ((pdev->class >> 8) != 0xff00)
815 /* the first BAR is the location of the IO APIC...we must
816 * not touch this (and it's already covered by the fixmap), so
817 * forcibly insert it into the resource tree */
818 if(pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
819 insert_resource(&iomem_resource, &pdev->resource[0]);
821 /* The next five BARs all seem to be rubbish, so just clean
823 for(i=1; i < 6; i++) {
824 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
830 #ifdef CONFIG_SCSI_SATA
831 static void __init quirk_intel_ide_combined(struct pci_dev *pdev)
837 * Narrow down to Intel SATA PCI devices.
839 switch (pdev->device) {
840 /* PCI ids taken from drivers/scsi/ata_piix.c */
853 /* we do not handle this PCI device */
858 * Read combined mode register.
860 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
863 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
864 if (tmp == 0x4) /* bits 10x */
865 comb = (1 << 0); /* SATA port 0, PATA port 1 */
866 else if (tmp == 0x6) /* bits 11x */
867 comb = (1 << 2); /* PATA port 0, SATA port 1 */
869 return; /* not in combined mode */
872 tmp &= 0x3; /* interesting bits 1:0 */
874 comb = (1 << 2); /* PATA port 0, SATA port 1 */
875 else if (tmp & (1 << 1))
876 comb = (1 << 0); /* SATA port 0, PATA port 1 */
878 return; /* not in combined mode */
882 * Read programming interface register.
883 * (Tells us if it's legacy or native mode)
885 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
887 /* if SATA port is in native mode, we're ok. */
891 /* SATA port is in legacy mode. Reserve port so that
892 * IDE driver does not attempt to use it. If request_region
893 * fails, it will be obvious at boot time, so we don't bother
894 * checking return values.
896 if (comb == (1 << 0))
897 request_region(0x1f0, 8, "libata"); /* port 0 */
899 request_region(0x170, 8, "libata"); /* port 1 */
901 #endif /* CONFIG_SCSI_SATA */
903 int pciehp_msi_quirk;
905 static void __devinit quirk_pciehp_msi(struct pci_dev *pdev)
907 pciehp_msi_quirk = 1;
911 * The main table of quirks.
913 * Note: any hooks for hotpluggable devices in this table must _NOT_
914 * be declared __init.
917 static struct pci_fixup pci_fixups[] __devinitdata = {
918 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord },
919 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
920 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
922 * Its not totally clear which chipsets are the problematic ones
923 * We know 82C586 and 82C596 variants are affected.
925 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs },
926 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs },
927 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs },
928 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs },
929 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb },
930 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs },
931 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs },
932 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs },
933 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M },
934 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M },
935 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton },
936 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton },
937 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton },
938 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton },
939 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma },
940 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma },
941 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma },
942 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma },
943 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma },
944 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma },
945 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci },
946 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci },
947 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 },
948 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus },
949 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible },
950 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible },
951 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible },
952 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible },
953 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible },
954 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible },
955 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus },
956 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus },
957 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus },
958 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik },
959 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik },
960 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency },
961 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency },
962 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
963 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx },
964 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf },
965 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id },
966 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi },
967 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi },
968 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi },
970 /* Intel LPC interface bridges all have 128 bytes of magic ACPI/TCO regs and 64 bytes of GPIO */
971 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi },
972 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi },
973 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi },
974 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi },
975 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi },
976 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi },
977 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi },
978 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi },
979 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi },
981 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi },
982 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb },
983 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb },
984 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases },
985 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge },
986 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy },
988 #ifdef CONFIG_X86_IO_APIC
989 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic },
990 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic },
991 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw },
992 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC,
993 quirk_amd_8131_ioapic },
994 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic },
996 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi },
997 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi },
998 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irqpic },
999 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irqpic },
1000 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_6, quirk_via_irqpic },
1002 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
1003 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce },
1005 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1006 * is subtractive decoding (transparent), and does indicate this
1007 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1010 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge },
1011 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge },
1013 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master },
1015 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide },
1017 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge },
1020 * on Asus P4B boards, the i801SMBus device is disabled at startup.
1021 * this also goes for boards in HP Compaq nc6000 and nc8000 notebooks.
1023 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge },
1024 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge },
1025 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge },
1026 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge },
1027 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge },
1028 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge },
1029 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc },
1030 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc },
1031 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc },
1033 #ifdef CONFIG_SCSI_SATA
1034 /* Fixup BIOSes that configure Parallel ATA (PATA / IDE) and
1035 * Serial ATA (SATA) into the same PCI ID.
1037 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1038 quirk_intel_ide_combined },
1039 #endif /* CONFIG_SCSI_SATA */
1041 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SMCH, quirk_pciehp_msi },
1047 static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
1050 if (f->pass == pass &&
1051 (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1052 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1054 printk(KERN_INFO "PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1062 void pci_fixup_device(int pass, struct pci_dev *dev)
1064 pci_do_fixups(dev, pass, pcibios_fixups);
1065 pci_do_fixups(dev, pass, pci_fixups);
1068 EXPORT_SYMBOL(pciehp_msi_quirk);