2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit quirk_passive_release(struct pci_dev *dev)
28 struct pci_dev *d = NULL;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
38 pci_write_config_byte(d, 0x82, dlc);
42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
48 This appears to be BIOS not version dependent. So presumably there is a
50 int isa_dma_bridge_buggy; /* Exported */
52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
54 if (!isa_dma_bridge_buggy) {
55 isa_dma_bridge_buggy=1;
56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
74 * Chipsets where PCI->PCI transfers vanish or hang
76 static void __devinit quirk_nopcipci(struct pci_dev *dev)
78 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems |= PCIPCI_FAIL;
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
87 * Triton requires workarounds to be used by the drivers
89 static void __devinit quirk_triton(struct pci_dev *dev)
91 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_TRITON;
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
108 * Updated based on further information from the site and also on
109 * information provided by VIA
111 static void __devinit quirk_vialatency(struct pci_dev *dev)
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev < 0x40 || rev > 0x42)
127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
128 if (p==NULL) /* No problem parts */
130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
131 /* Check for buggy part revisions */
132 if (rev < 0x10 || rev > 0x12)
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
149 pci_read_config_byte(dev, 0x76, &busarb);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
154 pci_write_config_byte(dev, 0x76, busarb);
155 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
164 * VIA Apollo VP3 needs ETBF on BT848/878
166 static void __devinit quirk_viaetbf(struct pci_dev *dev)
168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems |= PCIPCI_VIAETBF;
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
175 static void __devinit quirk_vsfx(struct pci_dev *dev)
177 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems |= PCIPCI_VSFX;
182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
190 static void __init quirk_alimagik(struct pci_dev *dev)
192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
201 * Natoma has some interesting boundary conditions with Zoran stuff
204 static void __devinit quirk_natoma(struct pci_dev *dev)
206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_NATOMA;
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
219 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
220 * If it's needed, re-allocate the region.
222 static void __devinit quirk_s3_64M(struct pci_dev *dev)
224 struct resource *r = &dev->resource[0];
226 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
234 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
238 struct resource *res = dev->resource + nr;
240 res->name = pci_name(dev);
242 res->end = region + size - 1;
243 res->flags = IORESOURCE_IO;
244 pci_claim_resource(dev, nr);
249 * ATI Northbridge setups MCE the processor if you even
250 * read somewhere between 0x3b0->0x3bb or read 0x3d3
252 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
254 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
255 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
256 request_region(0x3b0, 0x0C, "RadeonIGP");
257 request_region(0x3d3, 0x01, "RadeonIGP");
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
262 * Let's make the southbridge information explicit instead
263 * of having to worry about people probing the ACPI areas,
264 * for example.. (Yes, it happens, and if you read the wrong
265 * ACPI register it will put the machine to sleep with no
266 * way of waking it up again. Bummer).
268 * ALI M7101: Two IO regions pointed to by words at
269 * 0xE0 (64 bytes of ACPI registers)
270 * 0xE2 (32 bytes of SMB registers)
272 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
276 pci_read_config_word(dev, 0xE0, ®ion);
277 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
278 pci_read_config_word(dev, 0xE2, ®ion);
279 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
284 * PIIX4 ACPI: Two IO regions pointed to by longwords at
285 * 0x40 (64 bytes of ACPI registers)
286 * 0x90 (32 bytes of SMB registers)
288 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
292 pci_read_config_dword(dev, 0x40, ®ion);
293 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
294 pci_read_config_dword(dev, 0x90, ®ion);
295 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
300 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
301 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
302 * 0x58 (64 bytes of GPIO I/O space)
304 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
308 pci_read_config_dword(dev, 0x40, ®ion);
309 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
311 pci_read_config_dword(dev, 0x58, ®ion);
312 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
325 * VIA ACPI: One IO region pointed to by longword at
326 * 0x48 or 0x20 (256 bytes of ACPI registers)
328 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
333 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
335 pci_read_config_dword(dev, 0x48, ®ion);
336 region &= PCI_BASE_ADDRESS_IO_MASK;
337 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
343 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
344 * 0x48 (256 bytes of ACPI registers)
345 * 0x70 (128 bytes of hardware monitoring register)
346 * 0x90 (16 bytes of SMB registers)
348 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
353 quirk_vt82c586_acpi(dev);
355 pci_read_config_word(dev, 0x70, &hm);
356 hm &= PCI_BASE_ADDRESS_IO_MASK;
357 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
359 pci_read_config_dword(dev, 0x90, &smb);
360 smb &= PCI_BASE_ADDRESS_IO_MASK;
361 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
366 #ifdef CONFIG_X86_IO_APIC
368 #include <asm/io_apic.h>
371 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
372 * devices to the external APIC.
374 * TODO: When we have device-specific interrupt routers,
375 * this code will go away from quirks.
377 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
382 tmp = 0; /* nothing routed to external APIC */
384 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
386 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
387 tmp == 0 ? "Disa" : "Ena");
389 /* Offset 0x58: External APIC IRQ output control */
390 pci_write_config_byte (dev, 0x58, tmp);
392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
395 * The AMD io apic can hang the box when an apic irq is masked.
396 * We check all revs >= B0 (yet not in the pre production!) as the bug
397 * is currently marked NoFix
399 * We have multiple reports of hangs with this chipset that went away with
400 * noapic specified. For the moment we assume its the errata. We may be wrong
401 * of course. However the advice is demonstrably good even if so..
403 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
407 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
409 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
410 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
415 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
417 if (dev->devfn == 0 && dev->bus->number == 0)
420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
422 #define AMD8131_revA0 0x01
423 #define AMD8131_revB0 0x11
424 #define AMD8131_MISC 0x40
425 #define AMD8131_NIOAMODE_BIT 0
426 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
428 unsigned char revid, tmp;
433 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
434 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
435 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
436 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
437 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
438 pci_write_config_byte( dev, AMD8131_MISC, tmp);
441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
443 #endif /* CONFIG_X86_IO_APIC */
447 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
448 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
449 * when written, it makes an internal connection to the PIC.
450 * For these devices, this register is defined to be 4 bits wide.
451 * Normally this is fine. However for IO-APIC motherboards, or
452 * non-x86 architectures (yes Via exists on PPC among other places),
453 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
454 * interrupts delivered properly.
456 * TODO: When we have device-specific interrupt routers,
457 * quirk_via_irqpic will go away from quirks.
461 * FIXME: it is questionable that quirk_via_acpi
462 * is needed. It shows up as an ISA bridge, and does not
463 * support the PCI_INTERRUPT_LINE register at all. Therefore
464 * it seems like setting the pci_dev's 'irq' to the
465 * value of the ACPI SCI interrupt is only done for convenience.
468 static void __devinit quirk_via_acpi(struct pci_dev *d)
471 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
474 pci_read_config_byte(d, 0x42, &irq);
476 if (irq && (irq != 2))
479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
483 * PIIX3 USB: We have to disable USB interrupts that are
484 * hardwired to PIRQD# and may be shared with an
487 * Legacy Support Register (LEGSUP):
488 * bit13: USB PIRQ Enable (USBPIRQDEN),
489 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
491 * We mask out all r/wc bits, too.
493 static void __devinit quirk_piix3_usb(struct pci_dev *dev)
497 pci_read_config_word(dev, 0xc0, &legsup);
499 pci_write_config_word(dev, 0xc0, legsup);
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
505 * VIA VT82C598 has its device ID settable and many BIOSes
506 * set it to the ID of VT82C597 for backward compatibility.
507 * We need to switch it off to be able to recognize the real
510 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
512 pci_write_config_byte(dev, 0xfc, 0);
513 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
518 * CardBus controllers have a legacy base address that enables them
519 * to respond as i82365 pcmcia controllers. We don't want them to
520 * do this even if the Linux CardBus driver is not loaded, because
521 * the Linux i82365 driver does not (and should not) handle CardBus.
523 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
525 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
527 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
529 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy );
532 * Following the PCI ordering rules is optional on the AMD762. I'm not
533 * sure what the designers were smoking but let's not inhale...
535 * To be fair to AMD, it follows the spec by default, its BIOS people
538 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
541 pci_read_config_dword(dev, 0x4C, &pcic);
544 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
545 pci_write_config_dword(dev, 0x4C, pcic);
546 pci_read_config_dword(dev, 0x84, &pcic);
547 pcic |= (1<<23); /* Required in this mode */
548 pci_write_config_dword(dev, 0x84, pcic);
551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
554 * DreamWorks provided workaround for Dunord I-3000 problem
556 * This card decodes and responds to addresses not apparently
557 * assigned to it. We force a larger allocation to ensure that
558 * nothing gets put too close to it.
560 static void __devinit quirk_dunord ( struct pci_dev * dev )
562 struct resource *r = &dev->resource [1];
566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
569 * i82380FB mobile docking controller: its PCI-to-PCI bridge
570 * is subtractive decoding (transparent), and does indicate this
571 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
574 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
576 dev->transparent = 1;
578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
582 * Common misconfiguration of the MediaGX/Geode PCI master that will
583 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
584 * datasheets found at http://www.national.com/ds/GX for info on what
585 * these bits do. <christer@weinigel.se>
587 static void __init quirk_mediagx_master(struct pci_dev *dev)
590 pci_read_config_byte(dev, 0x41, ®);
593 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
594 pci_write_config_byte(dev, 0x41, reg);
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
600 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
601 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
602 * secondary channels respectively). If the device reports Compatible mode
603 * but does use BAR0-3 for address decoding, we assume that firmware has
604 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
605 * Exceptions (if they exist) must be handled in chip/architecture specific
608 * Note: for non x86 people. You may need an arch specific quirk to handle
609 * moving IDE devices to native mode as well. Some plug in card devices power
610 * up in compatible mode and assume the BIOS will adjust them.
612 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
613 * we do now ? We don't want is pci_enable_device to come along
614 * and assign new resources. Both approaches work for that.
616 static void __devinit quirk_ide_bases(struct pci_dev *dev)
618 struct resource *res;
619 int first_bar = 2, last_bar = 0;
621 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
624 res = &dev->resource[0];
626 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
627 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
628 res[0].start = res[0].end = res[0].flags = 0;
629 res[1].start = res[1].end = res[1].flags = 0;
634 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
635 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
636 res[2].start = res[2].end = res[2].flags = 0;
637 res[3].start = res[3].end = res[3].flags = 0;
644 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
645 first_bar, last_bar, pci_name(dev));
647 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases );
650 * Ensure C0 rev restreaming is off. This is normally done by
651 * the BIOS but in the odd case it is not the results are corruption
652 * hence the presence of a Linux check
654 static void __init quirk_disable_pxb(struct pci_dev *pdev)
659 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
660 if (rev != 0x04) /* Only C0 requires this */
662 pci_read_config_word(pdev, 0x40, &config);
663 if (config & (1<<6)) {
665 pci_write_config_word(pdev, 0x40, config);
666 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
672 * VIA northbridges care about PCI_INTERRUPT_LINE
674 int via_interrupt_line_quirk;
676 static void __devinit quirk_via_bridge(struct pci_dev *pdev)
678 if(pdev->devfn == 0) {
679 printk(KERN_INFO "PCI: Via IRQ fixup\n");
680 via_interrupt_line_quirk = 1;
683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
686 * Serverworks CSB5 IDE does not fully support native mode
688 static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
691 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
695 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
696 /* need to re-assign BARs for compat mode */
697 quirk_ide_bases(pdev);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
702 /* This was originally an Alpha specific thing, but it really fits here.
703 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
705 static void __init quirk_eisa_bridge(struct pci_dev *dev)
707 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
709 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
712 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
713 * is not activated. The myth is that Asus said that they do not want the
714 * users to be irritated by just another PCI Device in the Win98 device
715 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
716 * package 2.7.0 for details)
718 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
719 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
720 * becomes necessary to do this tweak in two steps -- I've chosen the Host
723 static int __initdata asus_hides_smbus = 0;
725 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
727 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
728 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
729 switch(dev->subsystem_device) {
730 case 0x8070: /* P4B */
731 case 0x8088: /* P4B533 */
732 case 0x1626: /* L3C notebook */
733 asus_hides_smbus = 1;
735 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
736 switch(dev->subsystem_device) {
737 case 0x80b1: /* P4GE-V */
738 case 0x80b2: /* P4PE */
739 case 0x8093: /* P4B533-V */
740 asus_hides_smbus = 1;
742 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
743 switch(dev->subsystem_device) {
744 case 0x8030: /* P4T533 */
745 asus_hides_smbus = 1;
747 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
748 switch (dev->subsystem_device) {
749 case 0x8070: /* P4G8X Deluxe */
750 asus_hides_smbus = 1;
752 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
753 switch (dev->subsystem_device) {
754 case 0x1751: /* M2N notebook */
755 asus_hides_smbus = 1;
757 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
758 switch (dev->subsystem_device) {
759 case 0x186a: /* M6Ne notebook */
760 asus_hides_smbus = 1;
762 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
763 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
764 switch(dev->subsystem_device) {
765 case 0x088C: /* HP Compaq nc8000 */
766 case 0x0890: /* HP Compaq nc6000 */
767 asus_hides_smbus = 1;
769 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
770 switch (dev->subsystem_device) {
771 case 0x12bc: /* HP D330L */
772 asus_hides_smbus = 1;
776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
777 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
778 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
784 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
788 if (likely(!asus_hides_smbus))
791 pci_read_config_word(dev, 0xF2, &val);
793 pci_write_config_word(dev, 0xF2, val & (~0x8));
794 pci_read_config_word(dev, 0xF2, &val);
796 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
798 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
804 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
805 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
808 * SiS 96x south bridge: BIOS typically hides SMBus device...
810 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
813 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
814 pci_read_config_byte(dev, 0x77, &val);
815 pci_write_config_byte(dev, 0x77, val & ~0x10);
816 pci_read_config_byte(dev, 0x77, &val);
820 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
821 #define UHCI_USBCMD 0 /* command register */
822 #define UHCI_USBSTS 2 /* status register */
823 #define UHCI_USBINTR 4 /* interrupt register */
824 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
825 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
826 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
827 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
828 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
830 #define OHCI_CONTROL 0x04
831 #define OHCI_CMDSTATUS 0x08
832 #define OHCI_INTRSTATUS 0x0c
833 #define OHCI_INTRENABLE 0x10
834 #define OHCI_INTRDISABLE 0x14
835 #define OHCI_OCR (1 << 3) /* ownership change request */
836 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
837 #define OHCI_INTR_OC (1 << 30) /* ownership change */
839 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
840 #define EHCI_USBCMD 0 /* command register */
841 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
842 #define EHCI_USBSTS 4 /* status register */
843 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
844 #define EHCI_USBINTR 8 /* interrupt register */
845 #define EHCI_USBLEGSUP 0 /* legacy support register */
846 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
847 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
848 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
849 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
851 int usb_early_handoff __devinitdata = 0;
852 static int __init usb_handoff_early(char *str)
854 usb_early_handoff = 1;
857 __setup("usb-handoff", usb_handoff_early);
859 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
861 unsigned long base = 0;
862 int wait_time, delta;
866 for (i = 0; i < PCI_ROM_RESOURCE; i++)
867 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
868 base = pci_resource_start(pdev, i);
878 sts = inw(base + UHCI_USBSTS);
879 val = inw(base + UHCI_USBCMD);
880 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
881 outw(val, base + UHCI_USBCMD);
884 * wait while it stops if it was running
886 if ((sts & UHCI_USBSTS_HALTED) == 0)
892 outw(0x1f, base + UHCI_USBSTS);
895 val = inw(base + UHCI_USBSTS);
896 if (val & UHCI_USBSTS_HALTED)
898 } while (wait_time > 0);
902 * disable interrupts & legacy support
904 outw(0, base + UHCI_USBINTR);
905 outw(0x1f, base + UHCI_USBSTS);
906 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
908 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
912 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
917 base = ioremap_nocache(pci_resource_start(pdev, 0),
918 pci_resource_len(pdev, 0));
919 if (base == NULL) return;
921 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
922 wait_time = 500; /* 0.5 seconds */
923 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
924 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
925 while (wait_time > 0 &&
926 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
935 writel(~(u32)0, base + OHCI_INTRDISABLE);
936 writel(~(u32)0, base + OHCI_INTRSTATUS);
941 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
943 int wait_time, delta;
944 void __iomem *base, *op_reg_base;
945 u32 hcc_params, val, temp;
948 base = ioremap_nocache(pci_resource_start(pdev, 0),
949 pci_resource_len(pdev, 0));
950 if (base == NULL) return;
952 cap_length = readb(base);
953 op_reg_base = base + cap_length;
954 hcc_params = readl(base + EHCI_HCC_PARAMS);
955 hcc_params = (hcc_params >> 8) & 0xff;
957 pci_read_config_dword(pdev,
958 hcc_params + EHCI_USBLEGSUP,
960 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
962 * Ok, BIOS is in smm mode, try to hand off...
964 pci_read_config_dword(pdev,
965 hcc_params + EHCI_USBLEGCTLSTS,
967 pci_write_config_dword(pdev,
968 hcc_params + EHCI_USBLEGCTLSTS,
969 temp | EHCI_USBLEGCTLSTS_SOOE);
970 val |= EHCI_USBLEGSUP_OS;
971 pci_write_config_dword(pdev,
972 hcc_params + EHCI_USBLEGSUP,
979 pci_read_config_dword(pdev,
980 hcc_params + EHCI_USBLEGSUP,
982 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
985 * well, possibly buggy BIOS...
987 printk(KERN_WARNING "EHCI early BIOS handoff "
988 "failed (BIOS bug ?)\n");
989 pci_write_config_dword(pdev,
990 hcc_params + EHCI_USBLEGSUP,
992 pci_write_config_dword(pdev,
993 hcc_params + EHCI_USBLEGCTLSTS,
1000 * halt EHCI & disable its interrupts in any case
1002 val = readl(op_reg_base + EHCI_USBSTS);
1003 if ((val & EHCI_USBSTS_HALTED) == 0) {
1004 val = readl(op_reg_base + EHCI_USBCMD);
1005 val &= ~EHCI_USBCMD_RUN;
1006 writel(val, op_reg_base + EHCI_USBCMD);
1011 writel(0x3f, op_reg_base + EHCI_USBSTS);
1014 val = readl(op_reg_base + EHCI_USBSTS);
1015 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1018 } while (wait_time > 0);
1020 writel(0, op_reg_base + EHCI_USBINTR);
1021 writel(0x3f, op_reg_base + EHCI_USBSTS);
1030 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1032 if (!usb_early_handoff)
1035 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1036 quirk_usb_handoff_uhci(pdev);
1037 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1038 quirk_usb_handoff_ohci(pdev);
1039 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1040 quirk_usb_disable_ehci(pdev);
1045 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1048 * ... This is further complicated by the fact that some SiS96x south
1049 * bridges pretend to be 85C503/5513 instead. In that case see if we
1050 * spotted a compatible north bridge to make sure.
1051 * (pci_find_device doesn't work yet)
1053 * We can also enable the sis96x bit in the discovery register..
1055 static int __devinitdata sis_96x_compatible = 0;
1057 #define SIS_DETECT_REGISTER 0x40
1059 static void __init quirk_sis_503(struct pci_dev *dev)
1064 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1065 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1066 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1067 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1068 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1072 /* Make people aware that we changed the config.. */
1073 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1076 * Ok, it now shows up as a 96x.. The 96x quirks are after
1077 * the 503 quirk in the quirk table, so they'll automatically
1078 * run and enable things like the SMBus device
1080 dev->device = devid;
1083 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1085 sis_96x_compatible = 1;
1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1099 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1101 #ifdef CONFIG_X86_IO_APIC
1102 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1106 if ((pdev->class >> 8) != 0xff00)
1109 /* the first BAR is the location of the IO APIC...we must
1110 * not touch this (and it's already covered by the fixmap), so
1111 * forcibly insert it into the resource tree */
1112 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1113 insert_resource(&iomem_resource, &pdev->resource[0]);
1115 /* The next five BARs all seem to be rubbish, so just clean
1117 for (i=1; i < 6; i++) {
1118 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1125 #ifdef CONFIG_SCSI_SATA
1126 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1132 * Narrow down to Intel SATA PCI devices.
1134 switch (pdev->device) {
1135 /* PCI ids taken from drivers/scsi/ata_piix.c */
1152 /* we do not handle this PCI device */
1157 * Read combined mode register.
1159 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1162 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1163 if (tmp == 0x4) /* bits 10x */
1164 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1165 else if (tmp == 0x6) /* bits 11x */
1166 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1168 return; /* not in combined mode */
1170 WARN_ON((ich != 6) && (ich != 7));
1171 tmp &= 0x3; /* interesting bits 1:0 */
1173 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1174 else if (tmp & (1 << 1))
1175 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1177 return; /* not in combined mode */
1181 * Read programming interface register.
1182 * (Tells us if it's legacy or native mode)
1184 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1186 /* if SATA port is in native mode, we're ok. */
1190 /* SATA port is in legacy mode. Reserve port so that
1191 * IDE driver does not attempt to use it. If request_region
1192 * fails, it will be obvious at boot time, so we don't bother
1193 * checking return values.
1195 if (comb == (1 << 0))
1196 request_region(0x1f0, 8, "libata"); /* port 0 */
1198 request_region(0x170, 8, "libata"); /* port 1 */
1200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1201 #endif /* CONFIG_SCSI_SATA */
1206 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1214 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1217 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1218 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1219 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1226 extern struct pci_fixup __start_pci_fixups_header[];
1227 extern struct pci_fixup __end_pci_fixups_header[];
1228 extern struct pci_fixup __start_pci_fixups_final[];
1229 extern struct pci_fixup __end_pci_fixups_final[];
1230 extern struct pci_fixup __start_pci_fixups_enable[];
1231 extern struct pci_fixup __end_pci_fixups_enable[];
1234 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1236 struct pci_fixup *start, *end;
1239 case pci_fixup_header:
1240 start = __start_pci_fixups_header;
1241 end = __end_pci_fixups_header;
1244 case pci_fixup_final:
1245 start = __start_pci_fixups_final;
1246 end = __end_pci_fixups_final;
1249 case pci_fixup_enable:
1250 start = __start_pci_fixups_enable;
1251 end = __end_pci_fixups_enable;
1255 /* stupid compiler warning, you would think with an enum... */
1258 pci_do_fixups(dev, start, end);
1261 EXPORT_SYMBOL(pcie_mch_quirk);
1262 #ifdef CONFIG_HOTPLUG
1263 EXPORT_SYMBOL(pci_fixup_device);