2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 #define DEBUG_CONFIG 1
32 # define DBGC(args) printk args
37 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
40 * FIXME: IO should be max 256 bytes. However, since we may
41 * have a P2P bridge below a cardbus bridge, we need 4K.
43 #define CARDBUS_IO_SIZE (4096)
44 #define CARDBUS_MEM_SIZE (32*1024*1024)
47 pbus_assign_resources_sorted(struct pci_bus *bus)
51 struct resource_list head, *list, *tmp;
54 bus->bridge_ctl &= ~PCI_BRIDGE_CTL_VGA;
57 list_for_each_entry(dev, &bus->devices, bus_list) {
58 u16 class = dev->class >> 8;
60 if (class == PCI_CLASS_DISPLAY_VGA
61 || class == PCI_CLASS_NOT_DEFINED_VGA)
62 bus->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
64 pdev_sort_resources(dev, &head);
67 for (list = head.next; list;) {
69 idx = res - &list->dev->resource[0];
70 pci_assign_resource(list->dev, idx);
78 pci_setup_cardbus(struct pci_bus *bus)
80 struct pci_dev *bridge = bus->self;
81 struct pci_bus_region region;
83 printk("PCI: Bus %d, cardbus bridge: %s\n",
84 bus->number, pci_name(bridge));
86 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
87 if (bus->resource[0]->flags & IORESOURCE_IO) {
89 * The IO resource is allocated a range twice as large as it
90 * would normally need. This allows us to set both IO regs.
92 printk(" IO window: %08lx-%08lx\n",
93 region.start, region.end);
94 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
96 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
100 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
101 if (bus->resource[1]->flags & IORESOURCE_IO) {
102 printk(" IO window: %08lx-%08lx\n",
103 region.start, region.end);
104 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
106 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
110 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
111 if (bus->resource[2]->flags & IORESOURCE_MEM) {
112 printk(" PREFETCH window: %08lx-%08lx\n",
113 region.start, region.end);
114 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
116 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
120 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
121 if (bus->resource[3]->flags & IORESOURCE_MEM) {
122 printk(" MEM window: %08lx-%08lx\n",
123 region.start, region.end);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
126 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
131 /* Initialize bridges with base/limit values we have collected.
132 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
133 requires that if there is no I/O ports or memory behind the
134 bridge, corresponding range must be turned off by writing base
135 value greater than limit to the bridge's base/limit registers.
137 Note: care must be taken when updating I/O base/limit registers
138 of bridges which support 32-bit I/O. This update requires two
139 config space writes, so it's quite possible that an I/O window of
140 the bridge will have some undesirable address (e.g. 0) after the
141 first write. Ditto 64-bit prefetchable MMIO. */
142 static void __devinit
143 pci_setup_bridge(struct pci_bus *bus)
145 struct pci_dev *bridge = bus->self;
146 struct pci_bus_region region;
149 DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
150 bus->number, pci_name(bridge)));
152 /* Set up the top and bottom of the PCI I/O segment for this bus. */
153 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
154 if (bus->resource[0]->flags & IORESOURCE_IO) {
155 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
157 l |= (region.start >> 8) & 0x00f0;
158 l |= region.end & 0xf000;
159 /* Set up upper 16 bits of I/O base/limit. */
160 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
161 DBGC((KERN_INFO " IO window: %04lx-%04lx\n",
162 region.start, region.end));
165 /* Clear upper 16 bits of I/O base/limit. */
168 DBGC((KERN_INFO " IO window: disabled.\n"));
170 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
171 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
172 /* Update lower 16 bits of I/O base/limit. */
173 pci_write_config_dword(bridge, PCI_IO_BASE, l);
174 /* Update upper 16 bits of I/O base/limit. */
175 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
177 /* Set up the top and bottom of the PCI Memory segment
179 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
180 if (bus->resource[1]->flags & IORESOURCE_MEM) {
181 l = (region.start >> 16) & 0xfff0;
182 l |= region.end & 0xfff00000;
183 DBGC((KERN_INFO " MEM window: %08lx-%08lx\n",
184 region.start, region.end));
188 DBGC((KERN_INFO " MEM window: disabled.\n"));
190 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
192 /* Clear out the upper 32 bits of PREF limit.
193 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
194 disables PREF range, which is ok. */
195 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
197 /* Set up PREF base/limit. */
198 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
199 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
200 l = (region.start >> 16) & 0xfff0;
201 l |= region.end & 0xfff00000;
202 DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n",
203 region.start, region.end));
207 DBGC((KERN_INFO " PREFETCH window: disabled.\n"));
209 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
211 /* Clear out the upper 32 bits of PREF base. */
212 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
214 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
217 /* Check whether the bridge supports optional I/O and
218 prefetchable memory ranges. If not, the respective
219 base/limit registers must be read-only and read as 0. */
220 static void __devinit
221 pci_bridge_check_ranges(struct pci_bus *bus)
225 struct pci_dev *bridge = bus->self;
226 struct resource *b_res;
228 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
229 b_res[1].flags |= IORESOURCE_MEM;
231 pci_read_config_word(bridge, PCI_IO_BASE, &io);
233 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
234 pci_read_config_word(bridge, PCI_IO_BASE, &io);
235 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
238 b_res[0].flags |= IORESOURCE_IO;
239 /* DECchip 21050 pass 2 errata: the bridge may miss an address
240 disconnect boundary by one PCI data phase.
241 Workaround: do not use prefetching on this device. */
242 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
244 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
246 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
248 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
249 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
252 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
255 /* Helper function for sizing routines: find first available
256 bus resource of a given type. Note: we intentionally skip
257 the bus resources which have already been assigned (that is,
258 have non-NULL parent resource). */
259 static struct resource * __devinit
260 find_free_bus_resource(struct pci_bus *bus, unsigned long type)
264 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
267 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
268 r = bus->resource[i];
269 if (r && (r->flags & type_mask) == type && !r->parent)
275 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
276 since these windows have 4K granularity and the IO ranges
277 of non-bridge PCI devices are limited to 256 bytes.
278 We must be careful with the ISA aliasing though. */
279 static void __devinit
280 pbus_size_io(struct pci_bus *bus)
283 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
284 unsigned long size = 0, size1 = 0;
289 list_for_each_entry(dev, &bus->devices, bus_list) {
292 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
293 struct resource *r = &dev->resource[i];
294 unsigned long r_size;
296 if (r->parent || !(r->flags & IORESOURCE_IO))
298 r_size = r->end - r->start + 1;
301 /* Might be re-aligned for ISA */
307 /* To be fixed in 2.5: we should have sort of HAVE_ISA
308 flag in the struct pci_bus. */
309 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
310 size = (size & 0xff) + ((size & ~0xffUL) << 2);
312 size = ROUND_UP(size + size1, 4096);
317 /* Alignment of the IO window is always 4K */
319 b_res->end = b_res->start + size - 1;
322 /* Calculate the size of the bus and minimal alignment which
323 guarantees that all child resources fit in this size. */
325 pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
328 unsigned long min_align, align, size;
329 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
330 int order, max_order;
331 struct resource *b_res = find_free_bus_resource(bus, type);
336 memset(aligns, 0, sizeof(aligns));
340 list_for_each_entry(dev, &bus->devices, bus_list) {
343 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
344 struct resource *r = &dev->resource[i];
345 unsigned long r_size;
347 if (r->parent || (r->flags & mask) != type)
349 r_size = r->end - r->start + 1;
350 /* For bridges size != alignment */
351 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
352 order = __ffs(align) - 20;
354 printk(KERN_WARNING "PCI: region %s/%d "
355 "too large: %lx-%lx\n",
356 pci_name(dev), i, r->start, r->end);
363 /* Exclude ranges with size > align from
364 calculation of the alignment. */
366 aligns[order] += align;
367 if (order > max_order)
374 for (order = 0; order <= max_order; order++) {
375 unsigned long align1 = 1UL << (order + 20);
379 else if (ROUND_UP(align + min_align, min_align) < align1)
380 min_align = align1 >> 1;
381 align += aligns[order];
383 size = ROUND_UP(size, min_align);
388 b_res->start = min_align;
389 b_res->end = size + min_align - 1;
393 static void __devinit
394 pci_bus_size_cardbus(struct pci_bus *bus)
396 struct pci_dev *bridge = bus->self;
397 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
401 * Reserve some resources for CardBus. We reserve
402 * a fixed amount of bus space for CardBus bridges.
404 b_res[0].start = CARDBUS_IO_SIZE;
405 b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
406 b_res[0].flags |= IORESOURCE_IO;
408 b_res[1].start = CARDBUS_IO_SIZE;
409 b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
410 b_res[1].flags |= IORESOURCE_IO;
413 * Check whether prefetchable memory is supported
416 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
417 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
418 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
419 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
420 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
424 * If we have prefetchable memory support, allocate
425 * two regions. Otherwise, allocate one region of
428 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
429 b_res[2].start = CARDBUS_MEM_SIZE;
430 b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
431 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
433 b_res[3].start = CARDBUS_MEM_SIZE;
434 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
435 b_res[3].flags |= IORESOURCE_MEM;
437 b_res[3].start = CARDBUS_MEM_SIZE * 2;
438 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
439 b_res[3].flags |= IORESOURCE_MEM;
444 pci_bus_size_bridges(struct pci_bus *bus)
447 unsigned long mask, prefmask;
449 list_for_each_entry(dev, &bus->devices, bus_list) {
450 struct pci_bus *b = dev->subordinate;
454 switch (dev->class >> 8) {
455 case PCI_CLASS_BRIDGE_CARDBUS:
456 pci_bus_size_cardbus(b);
459 case PCI_CLASS_BRIDGE_PCI:
461 pci_bus_size_bridges(b);
470 switch (bus->self->class >> 8) {
471 case PCI_CLASS_BRIDGE_CARDBUS:
472 /* don't size cardbuses yet. */
475 case PCI_CLASS_BRIDGE_PCI:
476 pci_bridge_check_ranges(bus);
479 /* If the bridge supports prefetchable range, size it
480 separately. If it doesn't, or its prefetchable window
481 has already been allocated by arch code, try
482 non-prefetchable range for both types of PCI memory
484 mask = IORESOURCE_MEM;
485 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
486 if (pbus_size_mem(bus, prefmask, prefmask))
487 mask = prefmask; /* Success, size non-prefetch only. */
488 pbus_size_mem(bus, mask, IORESOURCE_MEM);
492 EXPORT_SYMBOL(pci_bus_size_bridges);
495 pci_bus_assign_resources(struct pci_bus *bus)
500 pbus_assign_resources_sorted(bus);
502 if (bus->bridge_ctl & PCI_BRIDGE_CTL_VGA) {
503 /* Propagate presence of the VGA to upstream bridges */
504 for (b = bus; b->parent; b = b->parent) {
505 b->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
508 list_for_each_entry(dev, &bus->devices, bus_list) {
509 b = dev->subordinate;
513 pci_bus_assign_resources(b);
515 switch (dev->class >> 8) {
516 case PCI_CLASS_BRIDGE_PCI:
520 case PCI_CLASS_BRIDGE_CARDBUS:
521 pci_setup_cardbus(b);
525 printk(KERN_INFO "PCI: not setting up bridge %s "
526 "for bus %d\n", pci_name(dev), b->number);
531 EXPORT_SYMBOL(pci_bus_assign_resources);
534 pci_assign_unassigned_resources(void)
536 struct list_head *ln;
538 /* Depth first, calculate sizes and alignments of all
539 subordinate buses. */
540 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
541 pci_bus_size_bridges(pci_bus_b(ln));
542 /* Depth last, allocate resources and update the hardware. */
543 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) {
544 pci_bus_assign_resources(pci_bus_b(ln));
545 pci_enable_bridges(pci_bus_b(ln));