2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 #define DEBUG_CONFIG 1
32 # define DBGC(args) printk args
37 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
40 * FIXME: IO should be max 256 bytes. However, since we may
41 * have a P2P bridge below a cardbus bridge, we need 4K.
43 #define CARDBUS_IO_SIZE (4096)
44 #define CARDBUS_MEM_SIZE (32*1024*1024)
47 pbus_assign_resources_sorted(struct pci_bus *bus)
51 struct resource_list head, *list, *tmp;
54 bus->bridge_ctl &= ~PCI_BRIDGE_CTL_VGA;
57 list_for_each_entry(dev, &bus->devices, bus_list) {
58 u16 class = dev->class >> 8;
60 /* Don't touch classless devices and host bridges. */
61 if (class == PCI_CLASS_NOT_DEFINED ||
62 class == PCI_CLASS_BRIDGE_HOST)
65 if (class == PCI_CLASS_DISPLAY_VGA ||
66 class == PCI_CLASS_NOT_DEFINED_VGA)
67 bus->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
69 pdev_sort_resources(dev, &head);
72 for (list = head.next; list;) {
74 idx = res - &list->dev->resource[0];
75 pci_assign_resource(list->dev, idx);
83 pci_setup_cardbus(struct pci_bus *bus)
85 struct pci_dev *bridge = bus->self;
86 struct pci_bus_region region;
88 printk("PCI: Bus %d, cardbus bridge: %s\n",
89 bus->number, pci_name(bridge));
91 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
92 if (bus->resource[0]->flags & IORESOURCE_IO) {
94 * The IO resource is allocated a range twice as large as it
95 * would normally need. This allows us to set both IO regs.
97 printk(" IO window: %08lx-%08lx\n",
98 region.start, region.end);
99 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
101 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
105 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
106 if (bus->resource[1]->flags & IORESOURCE_IO) {
107 printk(" IO window: %08lx-%08lx\n",
108 region.start, region.end);
109 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
111 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
115 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
116 if (bus->resource[2]->flags & IORESOURCE_MEM) {
117 printk(" PREFETCH window: %08lx-%08lx\n",
118 region.start, region.end);
119 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
121 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
125 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
126 if (bus->resource[3]->flags & IORESOURCE_MEM) {
127 printk(" MEM window: %08lx-%08lx\n",
128 region.start, region.end);
129 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
131 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
136 /* Initialize bridges with base/limit values we have collected.
137 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
138 requires that if there is no I/O ports or memory behind the
139 bridge, corresponding range must be turned off by writing base
140 value greater than limit to the bridge's base/limit registers.
142 Note: care must be taken when updating I/O base/limit registers
143 of bridges which support 32-bit I/O. This update requires two
144 config space writes, so it's quite possible that an I/O window of
145 the bridge will have some undesirable address (e.g. 0) after the
146 first write. Ditto 64-bit prefetchable MMIO. */
147 static void __devinit
148 pci_setup_bridge(struct pci_bus *bus)
150 struct pci_dev *bridge = bus->self;
151 struct pci_bus_region region;
154 DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
155 bus->number, pci_name(bridge)));
157 /* Set up the top and bottom of the PCI I/O segment for this bus. */
158 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
159 if (bus->resource[0]->flags & IORESOURCE_IO) {
160 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
162 l |= (region.start >> 8) & 0x00f0;
163 l |= region.end & 0xf000;
164 /* Set up upper 16 bits of I/O base/limit. */
165 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
166 DBGC((KERN_INFO " IO window: %04lx-%04lx\n",
167 region.start, region.end));
170 /* Clear upper 16 bits of I/O base/limit. */
173 DBGC((KERN_INFO " IO window: disabled.\n"));
175 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
176 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
177 /* Update lower 16 bits of I/O base/limit. */
178 pci_write_config_dword(bridge, PCI_IO_BASE, l);
179 /* Update upper 16 bits of I/O base/limit. */
180 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
182 /* Set up the top and bottom of the PCI Memory segment
184 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
185 if (bus->resource[1]->flags & IORESOURCE_MEM) {
186 l = (region.start >> 16) & 0xfff0;
187 l |= region.end & 0xfff00000;
188 DBGC((KERN_INFO " MEM window: %08lx-%08lx\n",
189 region.start, region.end));
193 DBGC((KERN_INFO " MEM window: disabled.\n"));
195 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
197 /* Clear out the upper 32 bits of PREF limit.
198 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
199 disables PREF range, which is ok. */
200 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
202 /* Set up PREF base/limit. */
203 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
204 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
205 l = (region.start >> 16) & 0xfff0;
206 l |= region.end & 0xfff00000;
207 DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n",
208 region.start, region.end));
212 DBGC((KERN_INFO " PREFETCH window: disabled.\n"));
214 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
216 /* Clear out the upper 32 bits of PREF base. */
217 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
219 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
222 /* Check whether the bridge supports optional I/O and
223 prefetchable memory ranges. If not, the respective
224 base/limit registers must be read-only and read as 0. */
225 static void __devinit
226 pci_bridge_check_ranges(struct pci_bus *bus)
230 struct pci_dev *bridge = bus->self;
231 struct resource *b_res;
233 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
234 b_res[1].flags |= IORESOURCE_MEM;
236 pci_read_config_word(bridge, PCI_IO_BASE, &io);
238 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
239 pci_read_config_word(bridge, PCI_IO_BASE, &io);
240 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
243 b_res[0].flags |= IORESOURCE_IO;
244 /* DECchip 21050 pass 2 errata: the bridge may miss an address
245 disconnect boundary by one PCI data phase.
246 Workaround: do not use prefetching on this device. */
247 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
249 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
251 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
253 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
254 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
257 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
260 /* Helper function for sizing routines: find first available
261 bus resource of a given type. Note: we intentionally skip
262 the bus resources which have already been assigned (that is,
263 have non-NULL parent resource). */
264 static struct resource * __devinit
265 find_free_bus_resource(struct pci_bus *bus, unsigned long type)
269 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
272 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
273 r = bus->resource[i];
274 if (r && (r->flags & type_mask) == type && !r->parent)
280 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
281 since these windows have 4K granularity and the IO ranges
282 of non-bridge PCI devices are limited to 256 bytes.
283 We must be careful with the ISA aliasing though. */
284 static void __devinit
285 pbus_size_io(struct pci_bus *bus)
288 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
289 unsigned long size = 0, size1 = 0;
294 list_for_each_entry(dev, &bus->devices, bus_list) {
297 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
298 struct resource *r = &dev->resource[i];
299 unsigned long r_size;
301 if (r->parent || !(r->flags & IORESOURCE_IO))
303 r_size = r->end - r->start + 1;
306 /* Might be re-aligned for ISA */
312 /* To be fixed in 2.5: we should have sort of HAVE_ISA
313 flag in the struct pci_bus. */
314 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
315 size = (size & 0xff) + ((size & ~0xffUL) << 2);
317 size = ROUND_UP(size + size1, 4096);
322 /* Alignment of the IO window is always 4K */
324 b_res->end = b_res->start + size - 1;
327 /* Calculate the size of the bus and minimal alignment which
328 guarantees that all child resources fit in this size. */
330 pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
333 unsigned long min_align, align, size;
334 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
335 int order, max_order;
336 struct resource *b_res = find_free_bus_resource(bus, type);
341 memset(aligns, 0, sizeof(aligns));
345 list_for_each_entry(dev, &bus->devices, bus_list) {
348 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
349 struct resource *r = &dev->resource[i];
350 unsigned long r_size;
352 if (r->parent || (r->flags & mask) != type)
354 r_size = r->end - r->start + 1;
355 /* For bridges size != alignment */
356 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
357 order = __ffs(align) - 20;
359 printk(KERN_WARNING "PCI: region %s/%d "
360 "too large: %lx-%lx\n",
361 pci_name(dev), i, r->start, r->end);
368 /* Exclude ranges with size > align from
369 calculation of the alignment. */
371 aligns[order] += align;
372 if (order > max_order)
379 for (order = 0; order <= max_order; order++) {
380 unsigned long align1 = 1UL << (order + 20);
384 else if (ROUND_UP(align + min_align, min_align) < align1)
385 min_align = align1 >> 1;
386 align += aligns[order];
388 size = ROUND_UP(size, min_align);
393 b_res->start = min_align;
394 b_res->end = size + min_align - 1;
398 static void __devinit
399 pci_bus_size_cardbus(struct pci_bus *bus)
401 struct pci_dev *bridge = bus->self;
402 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
406 * Reserve some resources for CardBus. We reserve
407 * a fixed amount of bus space for CardBus bridges.
409 b_res[0].start = CARDBUS_IO_SIZE;
410 b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
411 b_res[0].flags |= IORESOURCE_IO;
413 b_res[1].start = CARDBUS_IO_SIZE;
414 b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
415 b_res[1].flags |= IORESOURCE_IO;
418 * Check whether prefetchable memory is supported
421 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
422 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
423 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
424 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
425 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
429 * If we have prefetchable memory support, allocate
430 * two regions. Otherwise, allocate one region of
433 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
434 b_res[2].start = CARDBUS_MEM_SIZE;
435 b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
436 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
438 b_res[3].start = CARDBUS_MEM_SIZE;
439 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
440 b_res[3].flags |= IORESOURCE_MEM;
442 b_res[3].start = CARDBUS_MEM_SIZE * 2;
443 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
444 b_res[3].flags |= IORESOURCE_MEM;
449 pci_bus_size_bridges(struct pci_bus *bus)
452 unsigned long mask, prefmask;
454 list_for_each_entry(dev, &bus->devices, bus_list) {
455 struct pci_bus *b = dev->subordinate;
459 switch (dev->class >> 8) {
460 case PCI_CLASS_BRIDGE_CARDBUS:
461 pci_bus_size_cardbus(b);
464 case PCI_CLASS_BRIDGE_PCI:
466 pci_bus_size_bridges(b);
475 switch (bus->self->class >> 8) {
476 case PCI_CLASS_BRIDGE_CARDBUS:
477 /* don't size cardbuses yet. */
480 case PCI_CLASS_BRIDGE_PCI:
481 pci_bridge_check_ranges(bus);
484 /* If the bridge supports prefetchable range, size it
485 separately. If it doesn't, or its prefetchable window
486 has already been allocated by arch code, try
487 non-prefetchable range for both types of PCI memory
489 mask = IORESOURCE_MEM;
490 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
491 if (pbus_size_mem(bus, prefmask, prefmask))
492 mask = prefmask; /* Success, size non-prefetch only. */
493 pbus_size_mem(bus, mask, IORESOURCE_MEM);
497 EXPORT_SYMBOL(pci_bus_size_bridges);
500 pci_bus_assign_resources(struct pci_bus *bus)
505 pbus_assign_resources_sorted(bus);
507 if (bus->bridge_ctl & PCI_BRIDGE_CTL_VGA) {
508 /* Propagate presence of the VGA to upstream bridges */
509 for (b = bus; b->parent; b = b->parent) {
510 b->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
513 list_for_each_entry(dev, &bus->devices, bus_list) {
514 b = dev->subordinate;
518 pci_bus_assign_resources(b);
520 switch (dev->class >> 8) {
521 case PCI_CLASS_BRIDGE_PCI:
525 case PCI_CLASS_BRIDGE_CARDBUS:
526 pci_setup_cardbus(b);
530 printk(KERN_INFO "PCI: not setting up bridge %s "
531 "for bus %d\n", pci_name(dev), b->number);
536 EXPORT_SYMBOL(pci_bus_assign_resources);
539 pci_assign_unassigned_resources(void)
543 /* Depth first, calculate sizes and alignments of all
544 subordinate buses. */
545 list_for_each_entry(bus, &pci_root_buses, node) {
546 pci_bus_size_bridges(bus);
548 /* Depth last, allocate resources and update the hardware. */
549 list_for_each_entry(bus, &pci_root_buses, node) {
550 pci_bus_assign_resources(bus);
551 pci_enable_bridges(bus);