1 /*======================================================================
3 Device driver for the PCMCIA control functionality of StrongARM
4 SA-1100 microprocessors.
6 The contents of this file are subject to the Mozilla Public
7 License Version 1.1 (the "License"); you may not use this file
8 except in compliance with the License. You may obtain a copy of
9 the License at http://www.mozilla.org/MPL/
11 Software distributed under the License is distributed on an "AS
12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
13 implied. See the License for the specific language governing
14 rights and limitations under the License.
16 The initial developer of the original code is John G. Dorsey
17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
20 Alternatively, the contents of this file may be used under the
21 terms of the GNU Public License version 2 (the "GPL"), in which
22 case the provisions of the GPL are applicable instead of the
23 above. If you wish to allow the use of your version of this file
24 only under the terms of the GPL and not to allow others to use
25 your version of this file under the MPL, indicate your decision
26 by deleting the provisions above and replace them with the notice
27 and other provisions required by the GPL. If you do not delete
28 the provisions above, a recipient may use your version of this
29 file under either the MPL or the GPL.
31 ======================================================================*/
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/config.h>
36 #include <linux/cpufreq.h>
37 #include <linux/ioport.h>
38 #include <linux/kernel.h>
39 #include <linux/notifier.h>
40 #include <linux/spinlock.h>
42 #include <asm/hardware.h>
45 #include <asm/system.h>
47 #include "soc_common.h"
48 #include "sa11xx_base.h"
52 * sa1100_pcmcia_default_mecr_timing
53 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
55 * Calculate MECR clock wait states for given CPU clock
56 * speed and command wait state. This function can be over-
57 * written by a board specific version.
59 * The default is to simply calculate the BS values as specified in
60 * the INTEL SA1100 development manual
61 * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
62 * that's section 10.2.5 in _my_ version of the manual ;)
65 sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt,
66 unsigned int cpu_speed,
67 unsigned int cmd_time)
69 return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed);
72 /* sa1100_pcmcia_set_mecr()
73 * ^^^^^^^^^^^^^^^^^^^^^^^^
75 * set MECR value for socket <sock> based on this sockets
76 * io, mem and attribute space access speed.
77 * Call board specific BS value calculation to allow boards
78 * to tweak the BS values.
81 sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock)
83 struct soc_pcmcia_timing timing;
86 unsigned int bs_io, bs_mem, bs_attr;
88 soc_common_pcmcia_get_timing(skt, &timing);
90 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
91 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
92 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
94 local_irq_save(flags);
96 old_mecr = mecr = MECR;
97 MECR_FAST_SET(mecr, skt->nr, 0);
98 MECR_BSIO_SET(mecr, skt->nr, bs_io);
99 MECR_BSA_SET(mecr, skt->nr, bs_attr);
100 MECR_BSM_SET(mecr, skt->nr, bs_mem);
101 if (old_mecr != mecr)
104 local_irq_restore(flags);
106 debug(skt, 2, "FAST %X BSM %X BSA %X BSIO %X\n",
107 MECR_FAST_GET(mecr, skt->nr),
108 MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr),
109 MECR_BSIO_GET(mecr, skt->nr));
115 sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
117 return sa1100_pcmcia_set_mecr(skt, cpufreq_get(0));
121 sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf)
123 struct soc_pcmcia_timing timing;
124 unsigned int clock = cpufreq_get(0);
125 unsigned long mecr = MECR;
128 soc_common_pcmcia_get_timing(skt, &timing);
130 p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
131 sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));
133 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
134 sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));
136 p+=sprintf(p, "common : %u (%u)\n", timing.mem,
137 sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));
142 int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops,
146 * set default MECR calculation if the board specific
147 * code did not specify one...
149 if (!ops->get_timing)
150 ops->get_timing = sa1100_pcmcia_default_mecr_timing;
152 /* Provide our SA11x0 specific timing routines. */
153 ops->set_timing = sa1100_pcmcia_set_timing;
154 ops->show_timing = sa1100_pcmcia_show_timing;
156 return soc_common_drv_pcmcia_probe(dev, ops, first, nr);
158 EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe);
160 #ifdef CONFIG_CPU_FREQ
162 /* sa1100_pcmcia_update_mecr()
163 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
164 * When sa1100_pcmcia_notifier() decides that a MECR adjustment (due
165 * to a core clock frequency change) is needed, this routine establishes
166 * new BS_xx values consistent with the clock speed `clock'.
168 static void sa1100_pcmcia_update_mecr(unsigned int clock)
170 struct soc_pcmcia_socket *skt;
172 down(&soc_pcmcia_sockets_lock);
173 list_for_each_entry(skt, &soc_pcmcia_sockets, node)
174 sa1100_pcmcia_set_mecr(skt, clock);
175 up(&soc_pcmcia_sockets_lock);
178 /* sa1100_pcmcia_notifier()
179 * ^^^^^^^^^^^^^^^^^^^^^^^^
180 * When changing the processor core clock frequency, it is necessary
181 * to adjust the MECR timings accordingly. We've recorded the timings
182 * requested by Card Services, so this is just a matter of finding
183 * out what our current speed is, and then recomputing the new MECR
186 * Returns: 0 on success, -1 on error
189 sa1100_pcmcia_notifier(struct notifier_block *nb, unsigned long val,
192 struct cpufreq_freqs *freqs = data;
195 case CPUFREQ_PRECHANGE:
196 if (freqs->new > freqs->old)
197 sa1100_pcmcia_update_mecr(freqs->new);
200 case CPUFREQ_POSTCHANGE:
201 if (freqs->new < freqs->old)
202 sa1100_pcmcia_update_mecr(freqs->new);
204 case CPUFREQ_RESUMECHANGE:
205 sa1100_pcmcia_update_mecr(freqs->new);
212 static struct notifier_block sa1100_pcmcia_notifier_block = {
213 .notifier_call = sa1100_pcmcia_notifier
216 static int __init sa11xx_pcmcia_init(void)
220 printk(KERN_INFO "SA11xx PCMCIA\n");
222 ret = cpufreq_register_notifier(&sa1100_pcmcia_notifier_block,
223 CPUFREQ_TRANSITION_NOTIFIER);
225 printk(KERN_ERR "Unable to register CPU frequency change "
226 "notifier (%d)\n", ret);
230 module_init(sa11xx_pcmcia_init);
232 static void __exit sa11xx_pcmcia_exit(void)
234 cpufreq_unregister_notifier(&sa1100_pcmcia_notifier_block, CPUFREQ_TRANSITION_NOTIFIER);
237 module_exit(sa11xx_pcmcia_exit);
240 MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>");
241 MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver");
242 MODULE_LICENSE("Dual MPL/GPL");