1 /* cpwatchdog.c - driver implementation for hardware watchdog
2 * timers found on Sun Microsystems CP1400 and CP1500 boards.
4 * This device supports both the generic Linux watchdog
5 * interface and Solaris-compatible ioctls as best it is
8 * NOTE: CP1400 systems appear to have a defective intr_mask
9 * register on the PLD, preventing the disabling of
10 * timer interrupts. We use a timer to periodically
11 * reset 'stopped' watchdogs on affected platforms.
13 * TODO: DevFS support (/dev/watchdogs/0 ... /dev/watchdogs/2)
15 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/errno.h>
22 #include <linux/major.h>
23 #include <linux/init.h>
24 #include <linux/miscdevice.h>
25 #include <linux/sched.h>
26 #include <linux/interrupt.h>
27 #include <linux/ioport.h>
28 #include <linux/timer.h>
31 #include <asm/oplib.h>
32 #include <asm/uaccess.h>
34 #include <asm/watchdog.h>
36 #define WD_OBPNAME "watchdog"
37 #define WD_BADMODEL "SUNW,501-5336"
38 #define WD_BTIMEOUT (jiffies + (HZ * 1000))
39 #define WD_BLIMIT 0xFFFF
41 #define WD0_DEVNAME "watchdog0"
42 #define WD1_DEVNAME "watchdog1"
43 #define WD2_DEVNAME "watchdog2"
50 /* Internal driver definitions
52 #define WD0_ID 0 /* Watchdog0 */
53 #define WD1_ID 1 /* Watchdog1 */
54 #define WD2_ID 2 /* Watchdog2 */
55 #define WD_NUMDEVS 3 /* Device contains 3 timers */
57 #define WD_INTR_OFF 0 /* Interrupt disable value */
58 #define WD_INTR_ON 1 /* Interrupt enable value */
60 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
61 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
62 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
64 /* Register value definitions
66 #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */
67 #define WD1_INTR_MASK 0x02
68 #define WD2_INTR_MASK 0x04
70 #define WD_S_RUNNING 0x01 /* Watchdog device status running */
71 #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */
73 /* Sun uses Altera PLD EPF8820ATC144-4
74 * providing three hardware watchdogs:
76 * 1) RIC - sends an interrupt when triggered
77 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
78 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
80 *** Timer register block definition (struct wd_timer_regblk)
82 * dcntr and limit registers (halfword access):
88 * dcntr - Current 16-bit downcounter value.
89 * When downcounter reaches '0' watchdog expires.
90 * Reading this register resets downcounter with 'limit' value.
91 * limit - 16-bit countdown value in 1/10th second increments.
92 * Writing this register begins countdown with input value.
93 * Reading from this register does not affect counter.
94 * NOTES: After watchdog reset, dcntr and limit contain '1'
96 * status register (byte access):
97 * ---------------------------
98 * | 7 | ... | 2 | 1 | 0 |
99 * --------------+------------
100 * |- UNUSED -| EXP | RUN |
101 * ---------------------------
102 * status- Bit 0 - Watchdog is running
103 * Bit 1 - Watchdog has expired
105 *** PLD register block definition (struct wd_pld_regblk)
107 * intr_mask register (byte access):
108 * ---------------------------------
109 * | 7 | ... | 3 | 2 | 1 | 0 |
110 * +-------------+------------------
111 * |- UNUSED -| WD3 | WD2 | WD1 |
112 * ---------------------------------
113 * WD3 - 1 == Interrupt disabled for watchdog 3
114 * WD2 - 1 == Interrupt disabled for watchdog 2
115 * WD1 - 1 == Interrupt disabled for watchdog 1
117 * pld_status register (byte access):
118 * UNKNOWN, MAGICAL MYSTERY REGISTER
121 struct wd_timer_regblk {
122 volatile __u16 dcntr; /* down counter - hw */
123 volatile __u16 dcntr_pad;
124 volatile __u16 limit; /* limit register - hw */
125 volatile __u16 limit_pad;
126 volatile __u8 status; /* status register - b */
127 volatile __u8 status_pad;
128 volatile __u16 status_pad2;
129 volatile __u32 pad32; /* yet more padding */
132 struct wd_pld_regblk {
133 volatile __u8 intr_mask; /* interrupt mask - b */
134 volatile __u8 intr_mask_pad;
135 volatile __u16 intr_mask_pad2;
136 volatile __u8 status; /* device status - b */
137 volatile __u8 status_pad;
138 volatile __u16 status_pad2;
142 volatile struct wd_timer_regblk wd0_regs;
143 volatile struct wd_timer_regblk wd1_regs;
144 volatile struct wd_timer_regblk wd2_regs;
145 volatile struct wd_pld_regblk pld_regs;
148 /* Individual timer structure
153 unsigned char runstatus;
154 volatile struct wd_timer_regblk* regs;
162 unsigned char isbaddoggie; /* defective PLD */
163 unsigned char opt_enable;
164 unsigned char opt_reboot;
165 unsigned short opt_timeout;
166 unsigned char initialized;
167 struct wd_timer watchdog[WD_NUMDEVS];
168 volatile struct wd_regblk* regs;
171 static struct wd_device wd_dev = {
172 0, SPIN_LOCK_UNLOCKED, 0, 0, 0, 0,
175 static struct timer_list wd_timer;
177 static int wd0_timeout = 0;
178 static int wd1_timeout = 0;
179 static int wd2_timeout = 0;
182 MODULE_PARM (wd0_timeout, "i");
183 MODULE_PARM_DESC(wd0_timeout, "Default watchdog0 timeout in 1/10secs");
184 MODULE_PARM (wd1_timeout, "i");
185 MODULE_PARM_DESC(wd1_timeout, "Default watchdog1 timeout in 1/10secs");
186 MODULE_PARM (wd2_timeout, "i");
187 MODULE_PARM_DESC(wd2_timeout, "Default watchdog2 timeout in 1/10secs");
190 ("Eric Brower <ebrower@usa.net>");
192 ("Hardware watchdog driver for Sun Microsystems CP1400/1500");
193 MODULE_LICENSE("GPL");
194 MODULE_SUPPORTED_DEVICE
196 #endif /* ifdef MODULE */
198 /* Forward declarations of internal methods
201 static void wd_dumpregs(void);
203 static irqreturn_t wd_interrupt(int irq, void *dev_id, struct pt_regs *regs);
204 static void wd_toggleintr(struct wd_timer* pTimer, int enable);
205 static void wd_pingtimer(struct wd_timer* pTimer);
206 static void wd_starttimer(struct wd_timer* pTimer);
207 static void wd_resetbrokentimer(struct wd_timer* pTimer);
208 static void wd_stoptimer(struct wd_timer* pTimer);
209 static void wd_brokentimer(unsigned long data);
210 static int wd_getstatus(struct wd_timer* pTimer);
212 /* PLD expects words to be written in LSB format,
213 * so we must flip all words prior to writing them to regs
215 static inline unsigned short flip_word(unsigned short word)
217 return ((word & 0xff) << 8) | ((word >> 8) & 0xff);
220 #define wd_writew(val, addr) (writew(flip_word(val), addr))
221 #define wd_readw(addr) (flip_word(readw(addr)))
222 #define wd_writeb(val, addr) (writeb(val, addr))
223 #define wd_readb(addr) (readb(addr))
226 /* CP1400s seem to have broken PLD implementations--
227 * the interrupt_mask register cannot be written, so
228 * no timer interrupts can be masked within the PLD.
230 static inline int wd_isbroken(void)
232 /* we could test this by read/write/read/restore
233 * on the interrupt mask register only if OBP
234 * 'watchdog-enable?' == FALSE, but it seems
235 * ubiquitous on CP1400s
238 prom_getproperty(prom_root_node, "model", val, sizeof(val));
239 return((!strcmp(val, WD_BADMODEL)) ? 1 : 0);
242 /* Retrieve watchdog-enable? option from OBP
243 * Returns 0 if false, 1 if true
245 static inline int wd_opt_enable(void)
249 opt_node = prom_getchild(prom_root_node);
250 opt_node = prom_searchsiblings(opt_node, "options");
251 return((-1 == prom_getint(opt_node, "watchdog-enable?")) ? 0 : 1);
254 /* Retrieve watchdog-reboot? option from OBP
255 * Returns 0 if false, 1 if true
257 static inline int wd_opt_reboot(void)
261 opt_node = prom_getchild(prom_root_node);
262 opt_node = prom_searchsiblings(opt_node, "options");
263 return((-1 == prom_getint(opt_node, "watchdog-reboot?")) ? 0 : 1);
266 /* Retrieve watchdog-timeout option from OBP
267 * Returns OBP value, or 0 if not located
269 static inline int wd_opt_timeout(void)
275 opt_node = prom_getchild(prom_root_node);
276 opt_node = prom_searchsiblings(opt_node, "options");
277 opt_node = prom_getproperty(opt_node,
282 /* atoi implementation */
283 for(opt_node = 0; /* nop */; p++) {
284 if(*p >= '0' && *p <= '9') {
285 opt_node = (10*opt_node)+(*p-'0');
292 return((-1 == opt_node) ? (0) : (opt_node));
295 static int wd_open(struct inode *inode, struct file *f)
297 switch(iminor(inode))
300 f->private_data = &wd_dev.watchdog[WD0_ID];
303 f->private_data = &wd_dev.watchdog[WD1_ID];
306 f->private_data = &wd_dev.watchdog[WD2_ID];
312 /* Register IRQ on first open of device */
313 if(0 == wd_dev.initialized)
315 if (request_irq(wd_dev.irq,
319 (void *)wd_dev.regs)) {
320 printk("%s: Cannot register IRQ %s\n",
321 WD_OBPNAME, __irq_itoa(wd_dev.irq));
324 wd_dev.initialized = 1;
330 static int wd_release(struct inode *inode, struct file *file)
335 static int wd_ioctl(struct inode *inode, struct file *file,
336 unsigned int cmd, unsigned long arg)
339 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
340 void __user *argp = (void __user *)arg;
341 struct watchdog_info info = {
344 "Altera EPF8820ATC144-4"
353 /* Generic Linux IOCTLs */
354 case WDIOC_GETSUPPORT:
355 if(copy_to_user(argp, &info, sizeof(struct watchdog_info))) {
359 case WDIOC_GETSTATUS:
360 case WDIOC_GETBOOTSTATUS:
361 if (put_user(0, (int __user *)argp))
364 case WDIOC_KEEPALIVE:
365 wd_pingtimer(pTimer);
367 case WDIOC_SETOPTIONS:
368 if(copy_from_user(&setopt, argp, sizeof(unsigned int))) {
371 if(setopt & WDIOS_DISABLECARD) {
372 if(wd_dev.opt_enable) {
374 "%s: cannot disable watchdog in ENABLED mode\n",
378 wd_stoptimer(pTimer);
380 else if(setopt & WDIOS_ENABLECARD) {
381 wd_starttimer(pTimer);
387 /* Solaris-compatible IOCTLs */
389 setopt = wd_getstatus(pTimer);
390 if(copy_to_user(argp, &setopt, sizeof(unsigned int))) {
395 wd_starttimer(pTimer);
398 if(wd_dev.opt_enable) {
399 printk("%s: cannot disable watchdog in ENABLED mode\n",
403 wd_stoptimer(pTimer);
411 static ssize_t wd_write(struct file *file,
412 const char __user *buf,
416 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
422 if (ppos != &file->f_pos)
426 wd_pingtimer(pTimer);
432 static ssize_t wd_read(struct file * file, char __user *buffer,
433 size_t count, loff_t *ppos)
440 #endif /* ifdef WD_DEBUG */
443 static irqreturn_t wd_interrupt(int irq, void *dev_id, struct pt_regs *regs)
445 /* Only WD0 will interrupt-- others are NMI and we won't
448 spin_lock_irq(&wd_dev.lock);
449 if((unsigned long)wd_dev.regs == (unsigned long)dev_id)
451 wd_stoptimer(&wd_dev.watchdog[WD0_ID]);
452 wd_dev.watchdog[WD0_ID].runstatus |= WD_STAT_SVCD;
454 spin_unlock_irq(&wd_dev.lock);
458 static struct file_operations wd_fops = {
459 .owner = THIS_MODULE,
464 .release = wd_release,
467 static struct miscdevice wd0_miscdev = { WD0_MINOR, WD0_DEVNAME, &wd_fops };
468 static struct miscdevice wd1_miscdev = { WD1_MINOR, WD1_DEVNAME, &wd_fops };
469 static struct miscdevice wd2_miscdev = { WD2_MINOR, WD2_DEVNAME, &wd_fops };
472 static void wd_dumpregs(void)
474 /* Reading from downcounters initiates watchdog countdown--
475 * Example is included below for illustration purposes.
478 printk("%s: dumping register values\n", WD_OBPNAME);
479 for(i = WD0_ID; i < WD_NUMDEVS; ++i) {
480 /* printk("\t%s%i: dcntr at 0x%lx: 0x%x\n",
483 * (unsigned long)(&wd_dev.watchdog[i].regs->dcntr),
484 * readw(&wd_dev.watchdog[i].regs->dcntr));
486 printk("\t%s%i: limit at 0x%lx: 0x%x\n",
489 (unsigned long)(&wd_dev.watchdog[i].regs->limit),
490 readw(&wd_dev.watchdog[i].regs->limit));
491 printk("\t%s%i: status at 0x%lx: 0x%x\n",
494 (unsigned long)(&wd_dev.watchdog[i].regs->status),
495 readb(&wd_dev.watchdog[i].regs->status));
496 printk("\t%s%i: driver status: 0x%x\n",
499 wd_getstatus(&wd_dev.watchdog[i]));
501 printk("\tintr_mask at 0x%lx: 0x%x\n",
502 (unsigned long)(&wd_dev.regs->pld_regs.intr_mask),
503 readb(&wd_dev.regs->pld_regs.intr_mask));
504 printk("\tpld_status at 0x%lx: 0x%x\n",
505 (unsigned long)(&wd_dev.regs->pld_regs.status),
506 readb(&wd_dev.regs->pld_regs.status));
510 /* Enable or disable watchdog interrupts
511 * Because of the CP1400 defect this should only be
512 * called during initialzation or by wd_[start|stop]timer()
514 * pTimer - pointer to timer device, or NULL to indicate all timers
515 * enable - non-zero to enable interrupts, zero to disable
517 static void wd_toggleintr(struct wd_timer* pTimer, int enable)
519 unsigned char curregs = wd_readb(&wd_dev.regs->pld_regs.intr_mask);
520 unsigned char setregs =
522 (WD0_INTR_MASK | WD1_INTR_MASK | WD2_INTR_MASK) :
525 (WD_INTR_ON == enable) ?
526 (curregs &= ~setregs):
527 (curregs |= setregs);
529 wd_writeb(curregs, &wd_dev.regs->pld_regs.intr_mask);
533 /* Reset countdown timer with 'limit' value and continue countdown.
534 * This will not start a stopped timer.
536 * pTimer - pointer to timer device
538 static void wd_pingtimer(struct wd_timer* pTimer)
540 if(wd_readb(&pTimer->regs->status) & WD_S_RUNNING) {
541 wd_readw(&pTimer->regs->dcntr);
545 /* Stop a running watchdog timer-- the timer actually keeps
546 * running, but the interrupt is masked so that no action is
547 * taken upon expiration.
549 * pTimer - pointer to timer device
551 static void wd_stoptimer(struct wd_timer* pTimer)
553 if(wd_readb(&pTimer->regs->status) & WD_S_RUNNING) {
554 wd_toggleintr(pTimer, WD_INTR_OFF);
556 if(wd_dev.isbaddoggie) {
557 pTimer->runstatus |= WD_STAT_BSTOP;
558 wd_brokentimer((unsigned long)&wd_dev);
563 /* Start a watchdog timer with the specified limit value
564 * If the watchdog is running, it will be restarted with
565 * the provided limit value.
567 * This function will enable interrupts on the specified
570 * pTimer - pointer to timer device
571 * limit - limit (countdown) value in 1/10th seconds
573 static void wd_starttimer(struct wd_timer* pTimer)
575 if(wd_dev.isbaddoggie) {
576 pTimer->runstatus &= ~WD_STAT_BSTOP;
578 pTimer->runstatus &= ~WD_STAT_SVCD;
580 wd_writew(pTimer->timeout, &pTimer->regs->limit);
581 wd_toggleintr(pTimer, WD_INTR_ON);
584 /* Restarts timer with maximum limit value and
585 * does not unset 'brokenstop' value.
587 static void wd_resetbrokentimer(struct wd_timer* pTimer)
589 wd_toggleintr(pTimer, WD_INTR_ON);
590 wd_writew(WD_BLIMIT, &pTimer->regs->limit);
593 /* Timer device initialization helper.
594 * Returns 0 on success, other on failure
596 static int wd_inittimer(int whichdog)
598 struct miscdevice *whichmisc;
599 volatile struct wd_timer_regblk *whichregs;
607 whichmisc = &wd0_miscdev;
608 strcpy(whichident, "RIC");
609 whichregs = &wd_dev.regs->wd0_regs;
610 whichmask = WD0_INTR_MASK;
611 whichlimit= (0 == wd0_timeout) ?
612 (wd_dev.opt_timeout):
616 whichmisc = &wd1_miscdev;
617 strcpy(whichident, "XIR");
618 whichregs = &wd_dev.regs->wd1_regs;
619 whichmask = WD1_INTR_MASK;
620 whichlimit= (0 == wd1_timeout) ?
621 (wd_dev.opt_timeout):
625 whichmisc = &wd2_miscdev;
626 strcpy(whichident, "POR");
627 whichregs = &wd_dev.regs->wd2_regs;
628 whichmask = WD2_INTR_MASK;
629 whichlimit= (0 == wd2_timeout) ?
630 (wd_dev.opt_timeout):
634 printk("%s: %s: invalid watchdog id: %i\n",
635 WD_OBPNAME, __FUNCTION__, whichdog);
638 if(0 != misc_register(whichmisc))
642 wd_dev.watchdog[whichdog].regs = whichregs;
643 wd_dev.watchdog[whichdog].timeout = whichlimit;
644 wd_dev.watchdog[whichdog].intr_mask = whichmask;
645 wd_dev.watchdog[whichdog].runstatus &= ~WD_STAT_BSTOP;
646 wd_dev.watchdog[whichdog].runstatus |= WD_STAT_INIT;
648 printk("%s%i: %s hardware watchdog [%01i.%i sec] %s\n",
652 wd_dev.watchdog[whichdog].timeout / 10,
653 wd_dev.watchdog[whichdog].timeout % 10,
654 (0 != wd_dev.opt_enable) ? "in ENABLED mode" : "");
658 /* Timer method called to reset stopped watchdogs--
659 * because of the PLD bug on CP1400, we cannot mask
660 * interrupts within the PLD so me must continually
661 * reset the timers ad infinitum.
663 static void wd_brokentimer(unsigned long data)
665 struct wd_device* pDev = (struct wd_device*)data;
668 /* kill a running timer instance, in case we
669 * were called directly instead of by kernel timer
671 if(timer_pending(&wd_timer)) {
672 del_timer(&wd_timer);
675 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
676 if(pDev->watchdog[id].runstatus & WD_STAT_BSTOP) {
678 wd_resetbrokentimer(&pDev->watchdog[id]);
683 /* there is at least one timer brokenstopped-- reschedule */
684 init_timer(&wd_timer);
685 wd_timer.expires = WD_BTIMEOUT;
686 add_timer(&wd_timer);
690 static int wd_getstatus(struct wd_timer* pTimer)
692 unsigned char stat = wd_readb(&pTimer->regs->status);
693 unsigned char intr = wd_readb(&wd_dev.regs->pld_regs.intr_mask);
694 unsigned char ret = WD_STOPPED;
696 /* determine STOPPED */
700 /* determine EXPIRED vs FREERUN vs RUNNING */
701 else if(WD_S_EXPIRED & stat) {
704 else if(WD_S_RUNNING & stat) {
705 if(intr & pTimer->intr_mask) {
709 /* Fudge WD_EXPIRED status for defective CP1400--
710 * IF timer is running
711 * AND brokenstop is set
712 * AND an interrupt has been serviced
715 * IF timer is running
716 * AND brokenstop is set
717 * AND no interrupt has been serviced
720 if(wd_dev.isbaddoggie && (pTimer->runstatus & WD_STAT_BSTOP)) {
721 if(pTimer->runstatus & WD_STAT_SVCD) {
725 /* we could as well pretend we are expired */
735 /* determine SERVICED */
736 if(pTimer->runstatus & WD_STAT_SVCD) {
743 static int __init wd_init(void)
746 struct linux_ebus *ebus = NULL;
747 struct linux_ebus_device *edev = NULL;
749 for_each_ebus(ebus) {
750 for_each_ebusdev(edev, ebus) {
751 if (!strcmp(edev->prom_name, WD_OBPNAME))
758 printk("%s: unable to locate device\n", WD_OBPNAME);
763 ioremap(edev->resource[0].start, sizeof(struct wd_regblk));
765 if(NULL == wd_dev.regs) {
766 printk("%s: unable to map registers\n", WD_OBPNAME);
770 /* initialize device structure from OBP parameters */
771 wd_dev.irq = edev->irqs[0];
772 wd_dev.opt_enable = wd_opt_enable();
773 wd_dev.opt_reboot = wd_opt_reboot();
774 wd_dev.opt_timeout = wd_opt_timeout();
775 wd_dev.isbaddoggie = wd_isbroken();
777 /* disable all interrupts unless watchdog-enabled? == true */
778 if(! wd_dev.opt_enable) {
779 wd_toggleintr(NULL, WD_INTR_OFF);
782 /* register miscellaneous devices */
783 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
784 if(0 != wd_inittimer(id)) {
785 printk("%s%i: unable to initialize\n", WD_OBPNAME, id);
789 /* warn about possible defective PLD */
790 if(wd_dev.isbaddoggie) {
791 init_timer(&wd_timer);
792 wd_timer.function = wd_brokentimer;
793 wd_timer.data = (unsigned long)&wd_dev;
794 wd_timer.expires = WD_BTIMEOUT;
796 printk("%s: PLD defect workaround enabled for model %s\n",
797 WD_OBPNAME, WD_BADMODEL);
802 static void __exit wd_cleanup(void)
806 /* if 'watchdog-enable?' == TRUE, timers are not stopped
807 * when module is unloaded. All brokenstopped timers will
808 * also now eventually trip.
810 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
811 if(WD_S_RUNNING == wd_readb(&wd_dev.watchdog[id].regs->status)) {
812 if(wd_dev.opt_enable) {
813 printk(KERN_WARNING "%s%i: timer not stopped at release\n",
817 wd_stoptimer(&wd_dev.watchdog[id]);
818 if(wd_dev.watchdog[id].runstatus & WD_STAT_BSTOP) {
819 wd_resetbrokentimer(&wd_dev.watchdog[id]);
821 "%s%i: defect workaround disabled at release, "\
822 "timer expires in ~%01i sec\n",
824 wd_readw(&wd_dev.watchdog[id].regs->limit) / 10);
830 if(wd_dev.isbaddoggie && timer_pending(&wd_timer)) {
831 del_timer(&wd_timer);
833 if(0 != (wd_dev.watchdog[WD0_ID].runstatus & WD_STAT_INIT)) {
834 misc_deregister(&wd0_miscdev);
836 if(0 != (wd_dev.watchdog[WD1_ID].runstatus & WD_STAT_INIT)) {
837 misc_deregister(&wd1_miscdev);
839 if(0 != (wd_dev.watchdog[WD2_ID].runstatus & WD_STAT_INIT)) {
840 misc_deregister(&wd2_miscdev);
842 if(0 != wd_dev.initialized) {
843 free_irq(wd_dev.irq, (void *)wd_dev.regs);
845 iounmap(wd_dev.regs);
848 module_init(wd_init);
849 module_exit(wd_cleanup);