1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
11 #include <linux/interrupt.h>
15 #if defined(CONFIG_53C700_MEM_MAPPED) && defined(CONFIG_53C700_IO_MAPPED)
16 #define CONFIG_53C700_BOTH_MAPPED
19 /* Turn on for general debugging---too verbose for normal use */
21 /* Debug the tag queues, checking hash queue allocation and deallocation
22 * and search for duplicate tags */
23 #undef NCR_700_TAG_DEBUG
26 #define DEBUG(x) printk x
31 /* The number of available command slots */
32 #define NCR_700_COMMAND_SLOTS_PER_HOST 64
33 /* The maximum number of Scatter Gathers we allow */
34 #define NCR_700_SG_SEGMENTS 32
35 /* The maximum number of luns (make this of the form 2^n) */
36 #define NCR_700_MAX_LUNS 32
37 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
38 /* Maximum number of tags the driver ever allows per device */
39 #define NCR_700_MAX_TAGS 16
40 /* Tag depth the driver starts out with (can be altered in sysfs) */
41 #define NCR_700_DEFAULT_TAGS 4
42 /* This is the default number of commands per LUN in the untagged case.
43 * two is a good value because it means we can have one command active and
44 * one command fully prepared and waiting
46 #define NCR_700_CMD_PER_LUN 2
47 /* magic byte identifying an internally generated REQUEST_SENSE command */
48 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42
50 /* WARNING: Leave this in for now: the dependency preprocessor doesn't
51 * pick up file specific flags, so must define here if they are not
53 #if !defined(CONFIG_53C700_IO_MAPPED) && !defined(CONFIG_53C700_MEM_MAPPED)
54 #error "Config.in must define either CONFIG_53C700_IO_MAPPED or CONFIG_53C700_MEM_MAPPED to use this scsi core."
57 struct NCR_700_Host_Parameters;
59 /* These are the externally used routines */
60 struct Scsi_Host *NCR_700_detect(Scsi_Host_Template *, struct NCR_700_Host_Parameters *);
61 int NCR_700_release(struct Scsi_Host *host);
62 irqreturn_t NCR_700_intr(int, void *, struct pt_regs *);
65 enum NCR_700_Host_State {
70 struct NCR_700_SG_List {
71 /* The following is a script fragment to move the buffer onto the
72 * bus and then link the next fragment or return */
73 #define SCRIPT_MOVE_DATA_IN 0x09000000
74 #define SCRIPT_MOVE_DATA_OUT 0x08000000
77 #define SCRIPT_NOP 0x80000000
78 #define SCRIPT_RETURN 0x90080000
81 /* We use device->hostdata to store negotiated parameters. This is
82 * supposed to be a pointer to a device private area, but we cannot
83 * really use it as such since it will never be freed, so just use the
84 * 32 bits to cram the information. The SYNC negotiation sequence looks
87 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
88 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
89 * If we get an SDTR reply, work out the SXFER parameters, squirrel
90 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
91 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
94 * 0:7 SXFER_REG negotiated value for this device
95 * 8:15 Current queue depth
96 * 16 negotiated SYNC flag
97 * 17 begin SYNC negotiation flag
98 * 18 device supports tag queueing */
99 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
100 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
101 #define NCR_700_DEV_BEGIN_TAG_QUEUEING (1<<18)
102 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
105 NCR_700_set_depth(Scsi_Device *SDp, __u8 depth)
107 long l = (long)SDp->hostdata;
110 l |= 0xff00 & (depth << 8);
111 SDp->hostdata = (void *)l;
114 NCR_700_get_depth(Scsi_Device *SDp)
116 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8);
119 NCR_700_is_flag_set(Scsi_Device *SDp, __u32 flag)
121 return (((unsigned long)SDp->hostdata) & flag) == flag;
124 NCR_700_is_flag_clear(Scsi_Device *SDp, __u32 flag)
126 return (((unsigned long)SDp->hostdata) & flag) == 0;
129 NCR_700_set_flag(Scsi_Device *SDp, __u32 flag)
131 SDp->hostdata = (void *)((long)SDp->hostdata | (flag & 0xffff0000));
134 NCR_700_clear_flag(Scsi_Device *SDp, __u32 flag)
136 SDp->hostdata = (void *)((long)SDp->hostdata & ~(flag & 0xffff0000));
139 struct NCR_700_command_slot {
140 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
141 struct NCR_700_SG_List *pSG;
142 #define NCR_700_SLOT_MASK 0xFC
143 #define NCR_700_SLOT_MAGIC 0xb8
144 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
145 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
146 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
151 /* The pci_mapped address of the actual command in cmnd */
154 /* if this command is a pci_single mapping, holds the dma address
155 * for later unmapping in the done routine */
156 dma_addr_t dma_handle;
157 /* historical remnant, now used to link free commands */
158 struct NCR_700_command_slot *ITL_forw;
161 struct NCR_700_Host_Parameters {
162 /* These must be filled in by the calling driver */
163 int clock; /* board clock speed in MHz */
164 unsigned long base; /* the base for the port (copied to host) */
166 __u32 dmode_extra; /* adjustable bus settings */
167 __u32 differential:1; /* if we are differential */
168 #ifdef CONFIG_53C700_LE_ON_BE
169 /* This option is for HP only. Set it if your chip is wired for
170 * little endian on this platform (which is big endian) */
171 __u32 force_le_on_be:1;
173 __u32 chip710:1; /* set if really a 710 not 700 */
174 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */
176 /* NOTHING BELOW HERE NEEDS ALTERING */
177 __u32 fast:1; /* if we can alter the SCSI bus clock
178 speed (so can negiotiate sync) */
179 #ifdef CONFIG_53C700_BOTH_MAPPED
180 __u32 mem_mapped; /* set if memory mapped */
182 int sync_clock; /* The speed of the SYNC core */
184 __u32 *script; /* pointer to script location */
185 __u32 pScript; /* physical mem addr of script */
187 enum NCR_700_Host_State state; /* protected by state lock */
189 /* Note: pScript contains the single consistent block of
190 * memory. All the msgin, msgout and status are allocated in
191 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
192 * represents the total size of this area */
193 #define MSG_ARRAY_SIZE 8
194 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
196 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
198 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
200 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
201 struct NCR_700_command_slot *slots;
202 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
203 int saved_slot_position;
204 int command_slot_count; /* protected by state lock */
210 /* Free list, singly linked by ITL_forw elements */
211 struct NCR_700_command_slot *free_list;
212 /* Completion for waited for ops, like reset, abort or
215 * NOTE: relies on single threading in the error handler to
216 * have only one outstanding at once */
217 struct completion *eh_complete;
221 * 53C700 Register Interface - the offset from the Selected base
223 #ifdef CONFIG_53C700_LE_ON_BE
224 #define bE (hostdata->force_le_on_be ? 0 : 3)
225 #define bSWAP (hostdata->force_le_on_be)
226 #elif defined(__BIG_ENDIAN)
229 #elif defined(__LITTLE_ENDIAN)
233 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
235 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
236 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
238 /* NOTE: These registers are in the LE register space only, the required byte
239 * swapping is done by the NCR_700_{read|write}[b] functions */
240 #define SCNTL0_REG 0x00
241 #define FULL_ARBITRATION 0xc0
243 #define ENABLE_PARITY 0x04
244 #define AUTO_ATN 0x02
245 #define SCNTL1_REG 0x01
246 #define SLOW_BUS 0x80
247 #define ENABLE_SELECT 0x20
248 #define ASSERT_RST 0x08
249 #define ASSERT_EVEN_PARITY 0x04
250 #define SDID_REG 0x02
251 #define SIEN_REG 0x03
252 #define PHASE_MM_INT 0x80
253 #define FUNC_COMP_INT 0x40
254 #define SEL_TIMEOUT_INT 0x20
255 #define SELECT_INT 0x10
256 #define GROSS_ERR_INT 0x08
257 #define UX_DISC_INT 0x04
259 #define PAR_ERR_INT 0x01
260 #define SCID_REG 0x04
261 #define SXFER_REG 0x05
262 #define ASYNC_OPERATION 0x00
263 #define SODL_REG 0x06
264 #define SOCL_REG 0x07
265 #define SFBR_REG 0x08
266 #define SIDL_REG 0x09
267 #define SBDL_REG 0x0A
268 #define SBCL_REG 0x0B
272 #define SYNC_DIV_AS_ASYNC 0x00
273 #define SYNC_DIV_1_0 0x01
274 #define SYNC_DIV_1_5 0x02
275 #define SYNC_DIV_2_0 0x03
276 #define DSTAT_REG 0x0C
277 #define ILGL_INST_DETECTED 0x01
278 #define WATCH_DOG_INTERRUPT 0x02
279 #define SCRIPT_INT_RECEIVED 0x04
281 #define SSTAT0_REG 0x0D
282 #define PARITY_ERROR 0x01
283 #define SCSI_RESET_DETECTED 0x02
284 #define UNEXPECTED_DISCONNECT 0x04
285 #define SCSI_GROSS_ERROR 0x08
286 #define SELECTED 0x10
287 #define SELECTION_TIMEOUT 0x20
288 #define FUNCTION_COMPLETE 0x40
289 #define PHASE_MISMATCH 0x80
290 #define SSTAT1_REG 0x0E
291 #define SIDL_REG_FULL 0x80
292 #define SODR_REG_FULL 0x40
293 #define SODL_REG_FULL 0x20
294 #define SSTAT2_REG 0x0F
295 #define CTEST0_REG 0x14
296 #define BTB_TIMER_DISABLE 0x40
297 #define CTEST1_REG 0x15
298 #define CTEST2_REG 0x16
299 #define CTEST3_REG 0x17
300 #define CTEST4_REG 0x18
301 #define DISABLE_FIFO 0x00
304 #define BYTE_LANE0 0x04
305 #define BYTE_LANE1 0x05
306 #define BYTE_LANE2 0x06
307 #define BYTE_LANE3 0x07
308 #define SCSI_ZMODE 0x20
310 #define CTEST5_REG 0x19
311 #define MASTER_CONTROL 0x10
312 #define DMA_DIRECTION 0x08
313 #define CTEST7_REG 0x1B
314 #define BURST_DISABLE 0x80 /* 710 only */
315 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
319 #define CTEST6_REG 0x1A
320 #define TEMP_REG 0x1C
321 #define DFIFO_REG 0x20
322 #define FLUSH_DMA_FIFO 0x80
323 #define CLR_FIFO 0x40
324 #define ISTAT_REG 0x21
325 #define ABORT_OPERATION 0x80
326 #define SOFTWARE_RESET_710 0x40
327 #define DMA_INT_PENDING 0x01
328 #define SCSI_INT_PENDING 0x02
329 #define CONNECTED 0x08
330 #define CTEST8_REG 0x22
331 #define LAST_DIS_ENBL 0x01
332 #define SHORTEN_FILTERING 0x04
333 #define ENABLE_ACTIVE_NEGATION 0x10
334 #define GENERATE_RECEIVE_PARITY 0x20
335 #define CLR_FIFO_710 0x04
336 #define FLUSH_DMA_FIFO_710 0x08
337 #define CTEST9_REG 0x23
339 #define DCMD_REG 0x27
340 #define DNAD_REG 0x28
341 #define DIEN_REG 0x39
342 #define BUS_FAULT 0x20
343 #define ABORT_INT 0x10
344 #define INT_INST_INT 0x04
346 #define ILGL_INST_INT 0x01
347 #define DCNTL_REG 0x3B
348 #define SOFTWARE_RESET 0x01
349 #define COMPAT_700_MODE 0x01
350 #define SCRPTS_16BITS 0x20
351 #define ASYNC_DIV_2_0 0x00
352 #define ASYNC_DIV_1_5 0x40
353 #define ASYNC_DIV_1_0 0x80
354 #define ASYNC_DIV_3_0 0xc0
355 #define DMODE_710_REG 0x38
356 #define DMODE_700_REG 0x34
357 #define BURST_LENGTH_1 0x00
358 #define BURST_LENGTH_2 0x40
359 #define BURST_LENGTH_4 0x80
360 #define BURST_LENGTH_8 0xC0
361 #define DMODE_FC1 0x10
362 #define DMODE_FC2 0x20
369 #define DSPS_REG 0x30
371 /* Parameters to begin SDTR negotiations. Empirically, I find that
372 * the 53c700-66 cannot handle an offset >8, so don't change this */
373 #define NCR_700_MAX_OFFSET 8
374 /* Was hoping the max offset would be greater for the 710, but
375 * empirically it seems to be 8 also */
376 #define NCR_710_MAX_OFFSET 8
377 #define NCR_700_MIN_XFERP 1
378 #define NCR_710_MIN_XFERP 0
379 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
381 #define script_patch_32(script, symbol, value) \
384 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
385 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
386 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
387 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
388 DEBUG((" script, patching %s at %d to 0x%lx\n", \
389 #symbol, A_##symbol##_used[i], (value))); \
393 #define script_patch_32_abs(script, symbol, value) \
396 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
397 (script)[A_##symbol##_used[i]] = bS_to_host(value); \
398 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
399 DEBUG((" script, patching %s at %d to 0x%lx\n", \
400 #symbol, A_##symbol##_used[i], (value))); \
404 /* Used for patching the SCSI ID in the SELECT instruction */
405 #define script_patch_ID(script, symbol, value) \
408 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
409 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
411 val |= ((value) & 0xff) << 16; \
412 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
413 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
414 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
415 #symbol, A_##symbol##_used[i], val)); \
419 #define script_patch_16(script, symbol, value) \
422 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
423 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
425 val |= ((value) & 0xffff); \
426 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
427 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
428 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
429 #symbol, A_##symbol##_used[i], val)); \
435 NCR_700_mem_readb(struct Scsi_Host *host, __u32 reg)
437 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
438 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
440 return readb(host->base + (reg^bE));
444 NCR_700_mem_readl(struct Scsi_Host *host, __u32 reg)
446 __u32 value = __raw_readl(host->base + reg);
447 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
448 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
450 /* sanity check the register */
455 return bS_to_cpu(value);
459 NCR_700_mem_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
461 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
462 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
464 writeb(value, host->base + (reg^bE));
468 NCR_700_mem_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
470 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
471 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
474 /* sanity check the register */
479 __raw_writel(bS_to_host(value), host->base + reg);
483 NCR_700_io_readb(struct Scsi_Host *host, __u32 reg)
485 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
486 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
488 return inb(host->base + (reg^bE));
492 NCR_700_io_readl(struct Scsi_Host *host, __u32 reg)
494 __u32 value = inl(host->base + reg);
495 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
496 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
499 /* sanity check the register */
504 return bS_to_cpu(value);
508 NCR_700_io_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
510 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
511 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
513 outb(value, host->base + (reg^bE));
517 NCR_700_io_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
519 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
520 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
523 /* sanity check the register */
528 outl(bS_to_host(value), host->base + reg);
531 #ifdef CONFIG_53C700_BOTH_MAPPED
534 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
538 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
539 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
541 if(hostdata->mem_mapped)
542 val = NCR_700_mem_readb(host, reg);
544 val = NCR_700_io_readb(host, reg);
550 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
554 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
555 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
557 if(hostdata->mem_mapped)
558 val = NCR_700_mem_readl(host, reg);
560 val = NCR_700_io_readl(host, reg);
566 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
568 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
569 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
571 if(hostdata->mem_mapped)
572 NCR_700_mem_writeb(value, host, reg);
574 NCR_700_io_writeb(value, host, reg);
578 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
580 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
581 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
583 if(hostdata->mem_mapped)
584 NCR_700_mem_writel(value, host, reg);
586 NCR_700_io_writel(value, host, reg);
590 NCR_700_set_mem_mapped(struct NCR_700_Host_Parameters *hostdata)
592 hostdata->mem_mapped = 1;
596 NCR_700_set_io_mapped(struct NCR_700_Host_Parameters *hostdata)
598 hostdata->mem_mapped = 0;
602 #elif defined(CONFIG_53C700_IO_MAPPED)
604 #define NCR_700_readb NCR_700_io_readb
605 #define NCR_700_readl NCR_700_io_readl
606 #define NCR_700_writeb NCR_700_io_writeb
607 #define NCR_700_writel NCR_700_io_writel
609 #define NCR_700_set_io_mapped(x)
610 #define NCR_700_set_mem_mapped(x) error I/O mapped only
612 #elif defined(CONFIG_53C700_MEM_MAPPED)
614 #define NCR_700_readb NCR_700_mem_readb
615 #define NCR_700_readl NCR_700_mem_readl
616 #define NCR_700_writeb NCR_700_mem_writeb
617 #define NCR_700_writel NCR_700_mem_writel
619 #define NCR_700_set_io_mapped(x) error MEM mapped only
620 #define NCR_700_set_mem_mapped(x)
623 #error neither CONFIG_53C700_MEM_MAPPED nor CONFIG_53C700_IO_MAPPED is set