1 #define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that redistributions of source
12 * code retain the above copyright notice and this comment without
15 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
16 * changed its name to ConnectCom Solutions, Inc.
18 * There is an AdvanSys Linux WWW page at:
19 * http://www.connectcom.net/downloads/software/os/linux.html
20 * http://www.advansys.com/linux.html
22 * The latest released version of the AdvanSys driver is available at:
23 * ftp://ftp.advansys.com/pub/linux/linux.tgz
24 * ftp://ftp.connectcom.net/pub/linux/linux.tgz
26 * Please send questions, comments, bug reports to:
27 * support@connectcom.net
32 Documentation for the AdvanSys Driver
34 A. Linux Kernels Supported by this Driver
35 B. Adapters Supported by this Driver
36 C. Linux source files modified by AdvanSys Driver
38 E. Driver Compile Time Options and Debugging
40 G. Tests to run before releasing new driver
42 I. Known Problems/Fix List
43 J. Credits (Chronological Order)
44 K. ConnectCom (AdvanSys) Contact Information
46 A. Linux Kernels Supported by this Driver
48 This driver has been tested in the following Linux kernels: v2.2.18
49 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
50 alpha, and PowerPC platforms.
52 B. Adapters Supported by this Driver
54 AdvanSys (Advanced System Products, Inc.) manufactures the following
55 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
56 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
57 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
58 transfer) SCSI Host Adapters for the PCI bus.
60 The CDB counts below indicate the number of SCSI CDB (Command
61 Descriptor Block) requests that can be stored in the RISC chip
62 cache and board LRAM. A CDB is a single SCSI command. The driver
63 detect routine will display the number of CDBs available for each
64 adapter detected. The number of CDBs used by the driver can be
65 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
68 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
70 Connectivity Products:
71 ABP510/5150 - Bus-Master ISA (240 CDB)
72 ABP5140 - Bus-Master ISA PnP (16 CDB)
73 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
74 ABP902/3902 - Bus-Master PCI (16 CDB)
75 ABP3905 - Bus-Master PCI (16 CDB)
76 ABP915 - Bus-Master PCI (16 CDB)
77 ABP920 - Bus-Master PCI (16 CDB)
78 ABP3922 - Bus-Master PCI (16 CDB)
79 ABP3925 - Bus-Master PCI (16 CDB)
80 ABP930 - Bus-Master PCI (16 CDB)
81 ABP930U - Bus-Master PCI Ultra (16 CDB)
82 ABP930UA - Bus-Master PCI Ultra (16 CDB)
83 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
84 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
86 Single Channel Products:
87 ABP542 - Bus-Master ISA with floppy (240 CDB)
88 ABP742 - Bus-Master EISA (240 CDB)
89 ABP842 - Bus-Master VL (240 CDB)
90 ABP940 - Bus-Master PCI (240 CDB)
91 ABP940U - Bus-Master PCI Ultra (240 CDB)
92 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
93 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
94 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
95 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
96 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
97 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
98 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
100 Multi-Channel Products:
101 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
102 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
103 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
104 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
105 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
106 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
107 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
108 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
109 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
111 C. Linux source files modified by AdvanSys Driver
113 This section for historical purposes documents the changes
114 originally made to the Linux kernel source to add the advansys
115 driver. As Linux has changed some of these files have also
118 1. linux/arch/i386/config.in:
120 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
122 2. linux/drivers/scsi/hosts.c:
124 #ifdef CONFIG_SCSI_ADVANSYS
125 #include "advansys.h"
128 and after "static Scsi_Host_Template builtin_scsi_hosts[] =":
130 #ifdef CONFIG_SCSI_ADVANSYS
134 3. linux/drivers/scsi/Makefile:
136 ifdef CONFIG_SCSI_ADVANSYS
137 SCSI_SRCS := $(SCSI_SRCS) advansys.c
138 SCSI_OBJS := $(SCSI_OBJS) advansys.o
140 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
143 4. linux/init/main.c:
145 extern void advansys_setup(char *str, int *ints);
147 and add the following lines to the bootsetups[] array.
149 #ifdef CONFIG_SCSI_ADVANSYS
150 { "advansys=", advansys_setup },
155 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
157 2. This driver should be maintained in multiple files. But to make
158 it easier to include with Linux and to follow Linux conventions,
159 the whole driver is maintained in the source files advansys.h and
160 advansys.c. In this file logical sections of the driver begin with
161 a comment that contains '---'. The following are the logical sections
165 --- Linux Include File
168 --- Asc Library Constants and Macros
169 --- Adv Library Constants and Macros
170 --- Driver Constants and Macros
171 --- Driver Structures
173 --- Driver Function Prototypes
174 --- Linux 'Scsi_Host_Template' and advansys_setup() Functions
175 --- Loadable Driver Support
176 --- Miscellaneous Driver Functions
177 --- Functions Required by the Asc Library
178 --- Functions Required by the Adv Library
179 --- Tracing and Debugging Functions
180 --- Asc Library Functions
181 --- Adv Library Functions
183 3. The string 'XXX' is used to flag code that needs to be re-written
184 or that contains a problem that needs to be addressed.
186 4. I have stripped comments from and reformatted the source for the
187 Asc Library and Adv Library to reduce the size of this file. This
188 source can be found under the following headings. The Asc Library
189 is used to support Narrow Boards. The Adv Library is used to
192 --- Asc Library Constants and Macros
193 --- Adv Library Constants and Macros
194 --- Asc Library Functions
195 --- Adv Library Functions
197 E. Driver Compile Time Options and Debugging
199 In this source file the following constants can be defined. They are
200 defined in the source below. Both of these options are enabled by
203 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
205 Enabling this option adds assertion logic statements to the
206 driver. If an assertion fails a message will be displayed to
207 the console, but the system will continue to operate. Any
208 assertions encountered should be reported to the person
209 responsible for the driver. Assertion statements may proactively
210 detect problems with the driver and facilitate fixing these
211 problems. Enabling assertions will add a small overhead to the
212 execution of the driver.
214 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
216 Enabling this option adds tracing functions to the driver and
217 the ability to set a driver tracing level at boot time. This
218 option will also export symbols not required outside the driver to
219 the kernel name space. This option is very useful for debugging
220 the driver, but it will add to the size of the driver execution
221 image and add overhead to the execution of the driver.
223 The amount of debugging output can be controlled with the global
224 variable 'asc_dbglvl'. The higher the number the more output. By
225 default the debug level is 0.
227 If the driver is loaded at boot time and the LILO Driver Option
228 is included in the system, the debug level can be changed by
229 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
230 first three hex digits of the pseudo I/O Port must be set to
231 'deb' and the fourth hex digit specifies the debug level: 0 - F.
232 The following command line will look for an adapter at 0x330
233 and set the debug level to 2.
235 linux advansys=0x330,0,0,0,0xdeb2
237 If the driver is built as a loadable module this variable can be
238 defined when the driver is loaded. The following insmod command
239 will set the debug level to one.
241 insmod advansys.o asc_dbglvl=1
243 Debugging Message Levels:
245 1: High-Level Tracing
248 To enable debug output to console, please make sure that:
250 a. System and kernel logging is enabled (syslogd, klogd running).
251 b. Kernel messages are routed to console output. Check
252 /etc/syslog.conf for an entry similar to this:
256 c. klogd is started with the appropriate -c parameter
259 This will cause printk() messages to be be displayed on the
260 current console. Refer to the klogd(8) and syslogd(8) man pages
263 Alternatively you can enable printk() to console with this
264 program. However, this is not the 'official' way to do this.
265 Debug output is logged in /var/log/messages.
269 syscall(103, 7, 0, 0);
272 Increasing LOG_BUF_LEN in kernel/printk.c to something like
273 40960 allows more debug messages to be buffered in the kernel
274 and written to the console or log file.
276 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
278 Enabling this option adds statistics collection and display
279 through /proc to the driver. The information is useful for
280 monitoring driver and device performance. It will add to the
281 size of the driver execution image and add minor overhead to
282 the execution of the driver.
284 Statistics are maintained on a per adapter basis. Driver entry
285 point call counts and transfer size counts are maintained.
286 Statistics are only available for kernels greater than or equal
287 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
289 AdvanSys SCSI adapter files have the following path name format:
291 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
293 This information can be displayed with cat. For example:
295 cat /proc/scsi/advansys/0
297 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
298 contain adapter and device configuration information.
300 F. Driver LILO Option
302 If init/main.c is modified as described in the 'Directions for Adding
303 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
304 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
305 This option can be used to either disable I/O port scanning or to limit
306 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
307 PCI boards will still be searched for and detected. This option only
308 affects searching for ISA and VL boards.
311 1. Eliminate I/O port scanning:
312 boot: linux advansys=
314 boot: linux advansys=0x0
315 2. Limit I/O port scanning to one I/O port:
316 boot: linux advansys=0x110
317 3. Limit I/O port scanning to four I/O ports:
318 boot: linux advansys=0x110,0x210,0x230,0x330
320 For a loadable module the same effect can be achieved by setting
321 the 'asc_iopflag' variable and 'asc_ioport' array when loading
324 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
326 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
327 I/O Port may be added to specify the driver debug level. Refer to
328 the 'Driver Compile Time Options and Debugging' section above for
331 G. Tests to run before releasing new driver
333 1. In the supported kernels verify there are no warning or compile
334 errors when the kernel is built as both a driver and as a module
335 and with the following options:
337 ADVANSYS_DEBUG - enabled and disabled
338 CONFIG_SMP - enabled and disabled
339 CONFIG_PROC_FS - enabled and disabled
341 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
342 card and one wide card attached to a hard disk and CD-ROM drive:
343 fdisk, mkfs, fsck, bonnie, copy/compare test from the
344 CD-ROM to the hard drive.
352 1. Prevent advansys_detect() from being called twice.
353 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
356 1. Prevent re-entrancy in the interrupt handler which
357 resulted in the driver hanging Linux.
358 2. Fix problem that prevented ABP-940 cards from being
359 recognized on some PCI motherboards.
360 3. Add support for the ABP-5140 PnP ISA card.
361 4. Fix check condition return status.
362 5. Add conditionally compiled code for Linux v1.3.X.
365 1. Fix problem in advansys_biosparam() that resulted in the
366 wrong drive geometry being returned for drives > 1GB with
367 extended translation enabled.
368 2. Add additional tracing during device initialization.
369 3. Change code that only applies to ISA PnP adapter.
370 4. Eliminate 'make dep' warning.
371 5. Try to fix problem with handling resets by increasing their
375 1. Change definitions to eliminate conflicts with other subsystems.
376 2. Add versioning code for the shared interrupt changes.
377 3. Eliminate problem in asc_rmqueue() with iterating after removing
379 4. Remove reset request loop problem from the "Known Problems or
380 Issues" section. This problem was isolated and fixed in the
381 mid-level SCSI driver.
384 1. Add support for ABP-940U (PCI Ultra) adapter.
385 2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
386 request_irq and supplying a dev_id pointer to both request_irq()
388 3. In AscSearchIOPortAddr11() restore a call to check_region() which
389 should be used before I/O port probing.
390 4. Fix bug in asc_prt_hex() which resulted in the displaying
392 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
393 6. Change driver versioning to be specific to each Linux sub-level.
394 7. Change statistics gathering to be per adapter instead of global
396 8. Add more information and statistics to the adapter /proc file:
397 /proc/scsi/advansys[0...].
398 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
399 This problem has been addressed with the SCSI mid-level changes
400 made in v1.3.89. The advansys_select_queue_depths() function
401 was added for the v1.3.89 changes.
404 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
407 1. Enable clustering and optimize the setting of the maximum number
408 of scatter gather elements for any particular board. Clustering
409 increases CPU utilization, but results in a relatively larger
410 increase in I/O throughput.
411 2. Improve the performance of the request queuing functions by
412 adding a last pointer to the queue structure.
413 3. Correct problems with reset and abort request handling that
414 could have hung or crashed Linux.
415 4. Add more information to the adapter /proc file:
416 /proc/scsi/advansys[0...].
417 5. Remove the request timeout issue form the driver issues list.
418 6. Miscellaneous documentation additions and changes.
421 1. Make changes to handle the new v2.1.0 kernel memory mapping
422 in which a kernel virtual address may not be equivalent to its
423 bus or DMA memory address.
424 2. Change abort and reset request handling to make it yet even
426 3. Try to mitigate request starvation by sending ordered requests
427 to heavily loaded, tag queuing enabled devices.
428 4. Maintain statistics on request response time.
429 5. Add request response time statistics and other information to
430 the adapter /proc file: /proc/scsi/advansys[0...].
433 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
434 make use of mid-level SCSI driver device queue depth flow
435 control mechanism. This will eliminate aborts caused by a
436 device being unable to keep up with requests and eliminate
437 repeat busy or QUEUE FULL status returned by a device.
438 2. Incorporate miscellaneous Asc Library bug fixes.
439 3. To allow the driver to work in kernels with broken module
440 support set 'cmd_per_lun' if the driver is compiled as a
441 module. This change affects kernels v1.3.89 to present.
442 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
443 is relocated by the motherboard BIOS and its new address can
444 not be determined by the driver.
445 5. Add mid-level SCSI queue depth information to the adapter
446 /proc file: /proc/scsi/advansys[0...].
449 1. Change allocation of global structures used for device
450 initialization to guarantee they are in DMA-able memory.
451 Previously when the driver was loaded as a module these
452 structures might not have been in DMA-able memory, causing
453 device initialization to fail.
456 1. In advansys_reset(), if the request is a synchronous reset
457 request, even if the request serial number has changed, then
458 complete the request.
459 2. Add Asc Library bug fixes including new microcode.
460 3. Clear inquiry buffer before using it.
461 4. Correct ifdef typo.
464 1. Add Asc Library bug fixes including new microcode.
465 2. Add synchronous data transfer rate information to the
466 adapter /proc file: /proc/scsi/advansys[0...].
467 3. Change ADVANSYS_DEBUG to be disabled by default. This
468 will reduce the size of the driver image, eliminate execution
469 overhead, and remove unneeded symbols from the kernel symbol
470 space that were previously added by the driver.
471 4. Add new compile-time option ADVANSYS_ASSERT for assertion
472 code that used to be defined within ADVANSYS_DEBUG. This
473 option is enabled by default.
476 1. Change version number to 2.8 to synchronize the Linux driver
477 version numbering with other AdvanSys drivers.
478 2. Reformat source files without tabs to present the same view
479 of the file to everyone regardless of the editor tab setting
481 3. Add Asc Library bug fixes.
484 1. Change version number to 3.1 to indicate that support for
485 Ultra-Wide adapters (ABP-940UW) is included in this release.
486 2. Add Asc Library (Narrow Board) bug fixes.
487 3. Report an underrun condition with the host status byte set
488 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
489 causes the underrun condition to be ignored. When Linux defines
490 its own DID_UNDERRUN the constant defined in this file can be
492 4. Add patch to AscWaitTixISRDone().
493 5. Add support for up to 16 different AdvanSys host adapter SCSI
494 channels in one system. This allows four cards with four channels
495 to be used in one system.
498 1. Handle that PCI register base addresses are not always page
499 aligned even though ioremap() requires that the address argument
503 1. Update latest BIOS version checked for from the /proc file.
504 2. Don't set microcode SDTR variable at initialization. Instead
505 wait until device capabilities have been detected from an Inquiry
509 1. Improve performance when the driver is compiled as module by
510 allowing up to 64 scatter-gather elements instead of 8.
513 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
514 2. Include SMP locking changes.
515 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
517 4. Update board serial number printing.
518 5. Try allocating an IRQ both with and without the SA_INTERRUPT
519 flag set to allow IRQ sharing with drivers that do not set
520 the SA_INTERRUPT flag. Also display a more descriptive error
521 message if request_irq() fails.
522 6. Update to latest Asc and Adv Libraries.
525 1. Update Adv Library to 4.16 which includes support for
526 the ASC38C0800 (Ultra2/LVD) IC.
529 1. Correct PCI compile time option for v2.1.93 and greater
530 kernels, advansys_info() string, and debug compile time
532 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
533 kernels. This caused an LVD detection/BIST problem problem
535 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
536 to be consistent with the BIOS.
537 4. Update to Asc Library S121 and Adv Library 5.2.
540 1. Correct PCI card detection bug introduced in 3.2B that
541 prevented PCI cards from being detected in kernels older
545 1. Correct /proc device synchronous speed information display.
546 Also when re-negotiation is pending for a target device
547 note this condition with an * and footnote.
548 2. Correct initialization problem with Ultra-Wide cards that
549 have a pre-3.2 BIOS. A microcode variable changed locations
550 in 3.2 and greater BIOSes which caused WDTR to be attempted
551 erroneously with drives that don't support WDTR.
554 1. Fix compile error caused by v2.3.13 PCI structure change.
555 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
556 checksum error for ISA cards.
557 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
558 SCSI changes that it depended on were never included in Linux.
561 1. Handle new initial function code added in v2.3.16 for all
565 1. Fix PCI board detection in v2.3.13 and greater kernels.
566 2. Fix comiple errors in v2.3.X with debugging enabled.
569 1. Add 64-bit address, long support for Alpha and UltraSPARC.
570 The driver has been verified to work on an Alpha system.
571 2. Add partial byte order handling support for Power PC and
572 other big-endian platforms. This support has not yet been
573 completed or verified.
574 3. For wide boards replace block zeroing of request and
575 scatter-gather structures with individual field initialization
576 to improve performance.
577 4. Correct and clarify ROM BIOS version detection.
580 1. Update to Adv Library 5.4.
581 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
582 adv_isr_callback(). Remove DID_UNDERRUN constant and other
583 no longer needed code that previously documented the lack
584 of underrun handling.
587 1. Eliminate compile errors for v2.0 and earlier kernels.
590 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
591 2. Update Adv Library to 5.5.
592 3. Add ifdef handling for /proc changes added in v2.3.28.
593 4. Increase Wide board scatter-gather list maximum length to
594 255 when the driver is compiled into the kernel.
597 1. Fix bug in adv_get_sglist() that caused an assertion failure
598 at line 7475. The reqp->sgblkp pointer must be initialized
599 to NULL in adv_get_sglist().
602 1. Really fix bug in adv_get_sglist().
603 2. Incorporate v2.3.29 changes into driver.
606 1. Add CONFIG_ISA ifdef code.
607 2. Include advansys_interrupts_enabled name change patch.
608 3. For >= v2.3.28 use new SCSI error handling with new function
609 advansys_eh_bus_reset(). Don't include an abort function
610 because of base library limitations.
611 4. For >= v2.3.28 use per board lock instead of io_request_lock.
612 5. For >= v2.3.28 eliminate advansys_command() and
613 advansys_command_done().
614 6. Add some changes for PowerPC (Big Endian) support, but it isn't
616 7. Fix "nonexistent resource free" problem that occurred on a module
617 unload for boards with an I/O space >= 255. The 'n_io_port' field
618 is only one byte and can not be used to hold an ioport length more
622 1. Update to Adv Library 5.8.
623 2. For wide cards add support for CDBs up to 16 bytes.
624 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
627 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
629 2. Change bitfields to shift and mask access for endian
633 1. Update for latest 2.4 kernel.
634 2. Test ABP-480 CardBus support in 2.4 kernel - works!
635 3. Update to Asc Library S123.
636 4. Update to Adv Library 5.12.
639 1. Update for latest 2.4 kernel.
640 2. Create patches for 2.2 and 2.4 kernels.
643 1. Now that 2.4 is released remove ifdef code for kernel versions
644 less than 2.2. The driver is now only supported in kernels 2.2,
646 2. Add code to release and acquire the io_request_lock in
647 the driver entrypoint functions: advansys_detect and
648 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
649 still holds the io_request_lock on entry to SCSI low-level drivers.
650 This was supposed to be removed before 2.4 was released but never
651 happened. When the mid-level SCSI driver is changed all references
652 to the io_request_lock should be removed from the driver.
653 3. Simplify error handling by removing advansys_abort(),
654 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
655 now handled by resetting the SCSI bus and fully re-initializing
656 the chip. This simple method of error recovery has proven to work
657 most reliably after attempts at different methods. Also now only
658 support the "new" error handling method and remove the obsolete
659 error handling interface.
660 4. Fix debug build errors.
663 1. Merge with ConnectCom version from Andy Kellner which
664 updates Adv Library to 5.14.
665 2. Make PowerPC (Big Endian) work for narrow cards and
666 fix problems writing EEPROM for wide cards.
667 3. Remove interrupts_enabled assertion function.
670 1. Return an error from narrow boards if passed a 16 byte
671 CDB. The wide board can already handle 16 byte CDBs.
674 1. hacks for lk 2.5 series (D. Gilbert)
677 1. change select_queue_depths to slave_configure
678 2. make cmd_per_lun be sane again
681 1. continuing cleanup for lk 2.6 series
682 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
683 3. Fix problem that oopsed ISA cards
685 I. Known Problems/Fix List (XXX)
687 1. Need to add memory mapping workaround. Test the memory mapping.
688 If it doesn't work revert to I/O port access. Can a test be done
690 2. Handle an interrupt not working. Keep an interrupt counter in
691 the interrupt handler. In the timeout function if the interrupt
692 has not occurred then print a message and run in polled mode.
693 3. Allow bus type scanning order to be changed.
694 4. Need to add support for target mode commands, cf. CAM XPT.
696 J. Credits (Chronological Order)
698 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
699 and maintained it up to 3.3F. He continues to answer questions
700 and help maintain the driver.
702 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
703 basis for the Linux v1.3.X changes which were included in the
706 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
707 in advansys_biosparam() which was fixed in the 1.3 release.
709 Erik Ratcliffe <erik@caldera.com> has done testing of the
710 AdvanSys driver in the Caldera releases.
712 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
713 AscWaitTixISRDone() which he found necessary to make the
714 driver work with a SCSI-1 disk.
716 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
717 support in the 3.1A driver.
719 Doug Gilbert <dgilbert@interlog.com> has made changes and
720 suggestions to improve the driver and done a lot of testing.
722 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
725 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
726 patch and helped with PowerPC wide and narrow board support.
728 Philip Blundell <philip.blundell@pobox.com> provided an
729 advansys_interrupts_enabled patch.
731 Dave Jones <dave@denial.force9.co.uk> reported the compiler
732 warnings generated when CONFIG_PROC_FS was not defined in
735 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
736 problems) for wide cards.
738 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
741 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
742 board support and fixed a bug in AscGetEEPConfig().
744 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
745 save_flags/restore_flags changes.
747 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
748 driver development for ConnectCom (Version > 3.3F).
750 K. ConnectCom (AdvanSys) Contact Information
752 Mail: ConnectCom Solutions, Inc.
755 Operator/Sales: 1-408-383-9400
757 Tech Support: 1-408-467-2930
758 Tech Support E-Mail: linux@connectcom.net
759 FTP Site: ftp.connectcom.net (login: anonymous)
760 Web Site: http://www.connectcom.net
765 * --- Linux Include Files
768 #include <linux/config.h>
769 #include <linux/module.h>
771 #if defined(CONFIG_X86) && !defined(CONFIG_ISA)
773 #endif /* CONFIG_X86 && !CONFIG_ISA */
775 #include <linux/string.h>
776 #include <linux/kernel.h>
777 #include <linux/types.h>
778 #include <linux/ioport.h>
779 #include <linux/interrupt.h>
780 #include <linux/delay.h>
781 #include <linux/slab.h>
782 #include <linux/mm.h>
783 #include <linux/proc_fs.h>
784 #include <linux/init.h>
785 #include <linux/blkdev.h>
786 #include <linux/stat.h>
787 #include <linux/spinlock.h>
788 #include <linux/dma-mapping.h>
791 #include <asm/system.h>
794 /* FIXME: (by jejb@steeleye.com) This warning is present for two
797 * 1) This driver badly needs converting to the correct driver model
800 * 2) Although all of the necessary command mapping places have the
801 * appropriate dma_map.. APIs, the driver still processes its internal
802 * queue using bus_to_virt() and virt_to_bus() which are illegal under
803 * the API. The entire queue processing structure will need to be
804 * altered to fix this.
806 #warning this driver is still not properly converted to the DMA API
808 #include <scsi/scsi_cmnd.h>
809 #include <scsi/scsi_device.h>
810 #include <scsi/scsi.h>
811 #include <scsi/scsi_host.h>
812 #include "advansys.h"
814 #include <linux/pci.h>
815 #endif /* CONFIG_PCI */
822 /* Enable driver assertions. */
823 #define ADVANSYS_ASSERT
825 /* Enable driver /proc statistics. */
826 #define ADVANSYS_STATS
828 /* Enable driver tracing. */
829 /* #define ADVANSYS_DEBUG */
833 * --- Debugging Header
836 #ifdef ADVANSYS_DEBUG
838 #else /* ADVANSYS_DEBUG */
839 #define STATIC static
840 #endif /* ADVANSYS_DEBUG */
844 * --- Asc Library Constants and Macros
847 #define ASC_LIB_VERSION_MAJOR 1
848 #define ASC_LIB_VERSION_MINOR 24
849 #define ASC_LIB_SERIAL_NUMBER 123
852 * Portable Data Types
854 * Any instance where a 32-bit long or pointer type is assumed
855 * for precision or HW defined structures, the following define
856 * types must be used. In Linux the char, short, and int types
857 * are all consistent at 8, 16, and 32 bits respectively. Pointers
858 * and long types are 64 bits on Alpha and UltraSPARC.
860 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
861 #define ASC_VADDR __u32 /* Virtual address data type. */
862 #define ASC_DCNT __u32 /* Unsigned Data count type. */
863 #define ASC_SDCNT __s32 /* Signed Data count type. */
866 * These macros are used to convert a virtual address to a
867 * 32-bit value. This currently can be used on Linux Alpha
868 * which uses 64-bit virtual address but a 32-bit bus address.
869 * This is likely to break in the future, but doing this now
870 * will give us time to change the HW and FW to handle 64-bit
873 #define ASC_VADDR_TO_U32 virt_to_bus
874 #define ASC_U32_TO_VADDR bus_to_virt
876 typedef unsigned char uchar;
887 #define UW_ERR (uint)(0xFFFF)
888 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
889 #define AscPCIConfigVendorIDRegister 0x0000
890 #define AscPCIConfigDeviceIDRegister 0x0002
891 #define AscPCIConfigCommandRegister 0x0004
892 #define AscPCIConfigStatusRegister 0x0006
893 #define AscPCIConfigRevisionIDRegister 0x0008
894 #define AscPCIConfigCacheSize 0x000C
895 #define AscPCIConfigLatencyTimer 0x000D
896 #define AscPCIIOBaseRegister 0x0010
897 #define AscPCICmdRegBits_IOMemBusMaster 0x0007
898 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
899 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
900 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
901 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
902 #define ASC_PCI_VENDORID 0x10CD
903 #define ASC_PCI_DEVICEID_1200A 0x1100
904 #define ASC_PCI_DEVICEID_1200B 0x1200
905 #define ASC_PCI_DEVICEID_ULTRA 0x1300
906 #define ASC_PCI_REVISION_3150 0x02
907 #define ASC_PCI_REVISION_3050 0x03
909 #define ASC_DVCLIB_CALL_DONE (1)
910 #define ASC_DVCLIB_CALL_FAILED (0)
911 #define ASC_DVCLIB_CALL_ERROR (-1)
914 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
915 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
916 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
919 #define CC_VERY_LONG_SG_LIST 0
920 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
922 #define PortAddr unsigned short /* port address size */
923 #define inp(port) inb(port)
924 #define outp(port, byte) outb((byte), (port))
926 #define inpw(port) inw(port)
927 #define outpw(port, word) outw((word), (port))
929 #define ASC_MAX_SG_QUEUE 7
930 #define ASC_MAX_SG_LIST 255
932 #define ASC_CS_TYPE unsigned short
934 #define ASC_IS_ISA (0x0001)
935 #define ASC_IS_ISAPNP (0x0081)
936 #define ASC_IS_EISA (0x0002)
937 #define ASC_IS_PCI (0x0004)
938 #define ASC_IS_PCI_ULTRA (0x0104)
939 #define ASC_IS_PCMCIA (0x0008)
940 #define ASC_IS_MCA (0x0020)
941 #define ASC_IS_VL (0x0040)
942 #define ASC_ISA_PNP_PORT_ADDR (0x279)
943 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
944 #define ASC_IS_WIDESCSI_16 (0x0100)
945 #define ASC_IS_WIDESCSI_32 (0x0200)
946 #define ASC_IS_BIG_ENDIAN (0x8000)
947 #define ASC_CHIP_MIN_VER_VL (0x01)
948 #define ASC_CHIP_MAX_VER_VL (0x07)
949 #define ASC_CHIP_MIN_VER_PCI (0x09)
950 #define ASC_CHIP_MAX_VER_PCI (0x0F)
951 #define ASC_CHIP_VER_PCI_BIT (0x08)
952 #define ASC_CHIP_MIN_VER_ISA (0x11)
953 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
954 #define ASC_CHIP_MAX_VER_ISA (0x27)
955 #define ASC_CHIP_VER_ISA_BIT (0x30)
956 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
957 #define ASC_CHIP_VER_ASYN_BUG (0x21)
958 #define ASC_CHIP_VER_PCI 0x08
959 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
960 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
961 #define ASC_CHIP_MIN_VER_EISA (0x41)
962 #define ASC_CHIP_MAX_VER_EISA (0x47)
963 #define ASC_CHIP_VER_EISA_BIT (0x40)
964 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
965 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
966 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
967 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
968 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
969 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
970 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
971 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
972 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
973 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
974 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
976 #define ASC_SCSI_ID_BITS 3
977 #define ASC_SCSI_TIX_TYPE uchar
978 #define ASC_ALL_DEVICE_BIT_SET 0xFF
979 #define ASC_SCSI_BIT_ID_TYPE uchar
980 #define ASC_MAX_TID 7
981 #define ASC_MAX_LUN 7
982 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
983 #define ASC_MAX_SENSE_LEN 32
984 #define ASC_MIN_SENSE_LEN 14
985 #define ASC_MAX_CDB_LEN 12
986 #define ASC_SCSI_RESET_HOLD_TIME_US 60
988 #define ADV_INQ_CLOCKING_ST_ONLY 0x0
989 #define ADV_INQ_CLOCKING_DT_ONLY 0x1
990 #define ADV_INQ_CLOCKING_ST_AND_DT 0x3
993 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
994 * and CmdDt (Command Support Data) field bit definitions.
996 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
997 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
998 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
999 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
1001 #define ASC_SCSIDIR_NOCHK 0x00
1002 #define ASC_SCSIDIR_T2H 0x08
1003 #define ASC_SCSIDIR_H2T 0x10
1004 #define ASC_SCSIDIR_NODATA 0x18
1005 #define SCSI_ASC_NOMEDIA 0x3A
1006 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
1007 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
1008 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
1009 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
1010 #define MS_CMD_DONE 0x00
1011 #define MS_EXTEND 0x01
1012 #define MS_SDTR_LEN 0x03
1013 #define MS_SDTR_CODE 0x01
1014 #define MS_WDTR_LEN 0x02
1015 #define MS_WDTR_CODE 0x03
1016 #define MS_MDP_LEN 0x05
1017 #define MS_MDP_CODE 0x00
1020 * Inquiry data structure and bitfield macros
1022 * Only quantities of more than 1 bit are shifted, since the others are
1023 * just tested for true or false. C bitfields aren't portable between big
1024 * and little-endian platforms so they are not used.
1027 #define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1028 #define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1029 #define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1030 #define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1031 #define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1032 #define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1033 #define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1034 #define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1035 #define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1036 #define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1037 #define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1038 #define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1039 #define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1040 #define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1041 #define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1042 #define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1043 #define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1044 #define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1045 #define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1046 #define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1058 uchar product_id[16];
1059 uchar product_rev_level[4];
1062 #define ASC_SG_LIST_PER_Q 7
1063 #define QS_FREE 0x00
1064 #define QS_READY 0x01
1065 #define QS_DISC1 0x02
1066 #define QS_DISC2 0x04
1067 #define QS_BUSY 0x08
1068 #define QS_ABORTED 0x40
1069 #define QS_DONE 0x80
1070 #define QC_NO_CALLBACK 0x01
1071 #define QC_SG_SWAP_QUEUE 0x02
1072 #define QC_SG_HEAD 0x04
1073 #define QC_DATA_IN 0x08
1074 #define QC_DATA_OUT 0x10
1075 #define QC_URGENT 0x20
1076 #define QC_MSG_OUT 0x40
1077 #define QC_REQ_SENSE 0x80
1078 #define QCSG_SG_XFER_LIST 0x02
1079 #define QCSG_SG_XFER_MORE 0x04
1080 #define QCSG_SG_XFER_END 0x08
1081 #define QD_IN_PROGRESS 0x00
1082 #define QD_NO_ERROR 0x01
1083 #define QD_ABORTED_BY_HOST 0x02
1084 #define QD_WITH_ERROR 0x04
1085 #define QD_INVALID_REQUEST 0x80
1086 #define QD_INVALID_HOST_NUM 0x81
1087 #define QD_INVALID_DEVICE 0x82
1088 #define QD_ERR_INTERNAL 0xFF
1089 #define QHSTA_NO_ERROR 0x00
1090 #define QHSTA_M_SEL_TIMEOUT 0x11
1091 #define QHSTA_M_DATA_OVER_RUN 0x12
1092 #define QHSTA_M_DATA_UNDER_RUN 0x12
1093 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1094 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1095 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1096 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1097 #define QHSTA_D_HOST_ABORT_FAILED 0x23
1098 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1099 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1100 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1101 #define QHSTA_M_WTM_TIMEOUT 0x41
1102 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1103 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1104 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1105 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
1106 #define QHSTA_M_BAD_TAG_CODE 0x46
1107 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1108 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1109 #define QHSTA_D_LRAM_CMP_ERROR 0x81
1110 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1111 #define ASC_FLAG_SCSIQ_REQ 0x01
1112 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1113 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
1114 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1115 #define ASC_FLAG_WIN16 0x10
1116 #define ASC_FLAG_WIN32 0x20
1117 #define ASC_FLAG_ISA_OVER_16MB 0x40
1118 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
1119 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1120 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1121 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1122 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1123 #define ASC_SCSIQ_CPY_BEG 4
1124 #define ASC_SCSIQ_SGHD_CPY_BEG 2
1125 #define ASC_SCSIQ_B_FWD 0
1126 #define ASC_SCSIQ_B_BWD 1
1127 #define ASC_SCSIQ_B_STATUS 2
1128 #define ASC_SCSIQ_B_QNO 3
1129 #define ASC_SCSIQ_B_CNTL 4
1130 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1131 #define ASC_SCSIQ_D_DATA_ADDR 8
1132 #define ASC_SCSIQ_D_DATA_CNT 12
1133 #define ASC_SCSIQ_B_SENSE_LEN 20
1134 #define ASC_SCSIQ_DONE_INFO_BEG 22
1135 #define ASC_SCSIQ_D_SRBPTR 22
1136 #define ASC_SCSIQ_B_TARGET_IX 26
1137 #define ASC_SCSIQ_B_CDB_LEN 28
1138 #define ASC_SCSIQ_B_TAG_CODE 29
1139 #define ASC_SCSIQ_W_VM_ID 30
1140 #define ASC_SCSIQ_DONE_STATUS 32
1141 #define ASC_SCSIQ_HOST_STATUS 33
1142 #define ASC_SCSIQ_SCSI_STATUS 34
1143 #define ASC_SCSIQ_CDB_BEG 36
1144 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1145 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1146 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1147 #define ASC_SCSIQ_B_SG_WK_QP 49
1148 #define ASC_SCSIQ_B_SG_WK_IX 50
1149 #define ASC_SCSIQ_W_ALT_DC1 52
1150 #define ASC_SCSIQ_B_LIST_CNT 6
1151 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
1152 #define ASC_SGQ_B_SG_CNTL 4
1153 #define ASC_SGQ_B_SG_HEAD_QP 5
1154 #define ASC_SGQ_B_SG_LIST_CNT 6
1155 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1156 #define ASC_SGQ_LIST_BEG 8
1157 #define ASC_DEF_SCSI1_QNG 4
1158 #define ASC_MAX_SCSI1_QNG 4
1159 #define ASC_DEF_SCSI2_QNG 16
1160 #define ASC_MAX_SCSI2_QNG 32
1161 #define ASC_TAG_CODE_MASK 0x23
1162 #define ASC_STOP_REQ_RISC_STOP 0x01
1163 #define ASC_STOP_ACK_RISC_STOP 0x03
1164 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1165 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1166 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1167 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1168 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1169 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1170 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1171 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1172 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1173 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1175 typedef struct asc_scsiq_1 {
1182 ASC_PADDR data_addr;
1184 ASC_PADDR sense_addr;
1189 typedef struct asc_scsiq_2 {
1198 typedef struct asc_scsiq_3 {
1205 typedef struct asc_scsiq_4 {
1206 uchar cdb[ASC_MAX_CDB_LEN];
1207 uchar y_first_sg_list_qp;
1208 uchar y_working_sg_qp;
1209 uchar y_working_sg_ix;
1212 ushort x_reconnect_rtn;
1213 ASC_PADDR x_saved_data_addr;
1214 ASC_DCNT x_saved_data_cnt;
1217 typedef struct asc_q_done_info {
1226 ASC_DCNT remain_bytes;
1229 typedef struct asc_sg_list {
1234 typedef struct asc_sg_head {
1237 ushort entry_to_copy;
1239 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1242 #define ASC_MIN_SG_LIST 2
1244 typedef struct asc_min_sg_head {
1247 ushort entry_to_copy;
1249 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1252 #define QCX_SORT (0x0001)
1253 #define QCX_COALEASE (0x0002)
1255 typedef struct asc_scsi_q {
1259 ASC_SG_HEAD *sg_head;
1260 ushort remain_sg_entry_cnt;
1261 ushort next_sg_index;
1264 typedef struct asc_scsi_req_q {
1268 ASC_SG_HEAD *sg_head;
1271 uchar cdb[ASC_MAX_CDB_LEN];
1272 uchar sense[ASC_MIN_SENSE_LEN];
1275 typedef struct asc_scsi_bios_req_q {
1279 ASC_SG_HEAD *sg_head;
1282 uchar cdb[ASC_MAX_CDB_LEN];
1283 uchar sense[ASC_MIN_SENSE_LEN];
1284 } ASC_SCSI_BIOS_REQ_Q;
1286 typedef struct asc_risc_q {
1295 typedef struct asc_sg_list_q {
1301 uchar sg_cur_list_cnt;
1304 typedef struct asc_risc_sg_list_q {
1308 ASC_SG_LIST sg_list[7];
1309 } ASC_RISC_SG_LIST_Q;
1311 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1312 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1313 #define ASCQ_ERR_NO_ERROR 0
1314 #define ASCQ_ERR_IO_NOT_FOUND 1
1315 #define ASCQ_ERR_LOCAL_MEM 2
1316 #define ASCQ_ERR_CHKSUM 3
1317 #define ASCQ_ERR_START_CHIP 4
1318 #define ASCQ_ERR_INT_TARGET_ID 5
1319 #define ASCQ_ERR_INT_LOCAL_MEM 6
1320 #define ASCQ_ERR_HALT_RISC 7
1321 #define ASCQ_ERR_GET_ASPI_ENTRY 8
1322 #define ASCQ_ERR_CLOSE_ASPI 9
1323 #define ASCQ_ERR_HOST_INQUIRY 0x0A
1324 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1325 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1326 #define ASCQ_ERR_Q_STATUS 0x0D
1327 #define ASCQ_ERR_WR_SCSIQ 0x0E
1328 #define ASCQ_ERR_PC_ADDR 0x0F
1329 #define ASCQ_ERR_SYN_OFFSET 0x10
1330 #define ASCQ_ERR_SYN_XFER_TIME 0x11
1331 #define ASCQ_ERR_LOCK_DMA 0x12
1332 #define ASCQ_ERR_UNLOCK_DMA 0x13
1333 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1334 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
1335 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
1336 #define ASCQ_ERR_CUR_QNG 0x17
1337 #define ASCQ_ERR_SG_Q_LINKS 0x18
1338 #define ASCQ_ERR_SCSIQ_PTR 0x19
1339 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1340 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1341 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1342 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1343 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1344 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1345 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1346 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1347 #define ASCQ_ERR_SEND_SCSI_Q 0x22
1348 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1349 #define ASCQ_ERR_RESET_SDTR 0x24
1352 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1354 #define ASC_WARN_NO_ERROR 0x0000
1355 #define ASC_WARN_IO_PORT_ROTATE 0x0001
1356 #define ASC_WARN_EEPROM_CHKSUM 0x0002
1357 #define ASC_WARN_IRQ_MODIFIED 0x0004
1358 #define ASC_WARN_AUTO_CONFIG 0x0008
1359 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1360 #define ASC_WARN_EEPROM_RECOVER 0x0020
1361 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
1362 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1365 * Error code values are set in ASC_DVC_VAR 'err_code'.
1367 #define ASC_IERR_WRITE_EEPROM 0x0001
1368 #define ASC_IERR_MCODE_CHKSUM 0x0002
1369 #define ASC_IERR_SET_PC_ADDR 0x0004
1370 #define ASC_IERR_START_STOP_CHIP 0x0008
1371 #define ASC_IERR_IRQ_NO 0x0010
1372 #define ASC_IERR_SET_IRQ_NO 0x0020
1373 #define ASC_IERR_CHIP_VERSION 0x0040
1374 #define ASC_IERR_SET_SCSI_ID 0x0080
1375 #define ASC_IERR_GET_PHY_ADDR 0x0100
1376 #define ASC_IERR_BAD_SIGNATURE 0x0200
1377 #define ASC_IERR_NO_BUS_TYPE 0x0400
1378 #define ASC_IERR_SCAM 0x0800
1379 #define ASC_IERR_SET_SDTR 0x1000
1380 #define ASC_IERR_RW_LRAM 0x8000
1382 #define ASC_DEF_IRQ_NO 10
1383 #define ASC_MAX_IRQ_NO 15
1384 #define ASC_MIN_IRQ_NO 10
1385 #define ASC_MIN_REMAIN_Q (0x02)
1386 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1387 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
1388 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
1389 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1390 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1391 #define ASC_MAX_TOTAL_QNG 240
1392 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1393 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1394 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1395 #define ASC_MAX_INRAM_TAG_QNG 16
1396 #define ASC_IOADR_TABLE_MAX_IX 11
1397 #define ASC_IOADR_GAP 0x10
1398 #define ASC_SEARCH_IOP_GAP 0x10
1399 #define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1400 #define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1401 #define ASC_IOADR_1 (PortAddr)0x0110
1402 #define ASC_IOADR_2 (PortAddr)0x0130
1403 #define ASC_IOADR_3 (PortAddr)0x0150
1404 #define ASC_IOADR_4 (PortAddr)0x0190
1405 #define ASC_IOADR_5 (PortAddr)0x0210
1406 #define ASC_IOADR_6 (PortAddr)0x0230
1407 #define ASC_IOADR_7 (PortAddr)0x0250
1408 #define ASC_IOADR_8 (PortAddr)0x0330
1409 #define ASC_IOADR_DEF ASC_IOADR_8
1410 #define ASC_LIB_SCSIQ_WK_SP 256
1411 #define ASC_MAX_SYN_XFER_NO 16
1412 #define ASC_SYN_MAX_OFFSET 0x0F
1413 #define ASC_DEF_SDTR_OFFSET 0x0F
1414 #define ASC_DEF_SDTR_INDEX 0x00
1415 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1416 #define SYN_XFER_NS_0 25
1417 #define SYN_XFER_NS_1 30
1418 #define SYN_XFER_NS_2 35
1419 #define SYN_XFER_NS_3 40
1420 #define SYN_XFER_NS_4 50
1421 #define SYN_XFER_NS_5 60
1422 #define SYN_XFER_NS_6 70
1423 #define SYN_XFER_NS_7 85
1424 #define SYN_ULTRA_XFER_NS_0 12
1425 #define SYN_ULTRA_XFER_NS_1 19
1426 #define SYN_ULTRA_XFER_NS_2 25
1427 #define SYN_ULTRA_XFER_NS_3 32
1428 #define SYN_ULTRA_XFER_NS_4 38
1429 #define SYN_ULTRA_XFER_NS_5 44
1430 #define SYN_ULTRA_XFER_NS_6 50
1431 #define SYN_ULTRA_XFER_NS_7 57
1432 #define SYN_ULTRA_XFER_NS_8 63
1433 #define SYN_ULTRA_XFER_NS_9 69
1434 #define SYN_ULTRA_XFER_NS_10 75
1435 #define SYN_ULTRA_XFER_NS_11 82
1436 #define SYN_ULTRA_XFER_NS_12 88
1437 #define SYN_ULTRA_XFER_NS_13 94
1438 #define SYN_ULTRA_XFER_NS_14 100
1439 #define SYN_ULTRA_XFER_NS_15 107
1441 typedef struct ext_msg {
1447 uchar sdtr_xfer_period;
1448 uchar sdtr_req_ack_offset;
1463 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1464 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1465 #define wdtr_width u_ext_msg.wdtr.wdtr_width
1466 #define mdp_b3 u_ext_msg.mdp_b3
1467 #define mdp_b2 u_ext_msg.mdp_b2
1468 #define mdp_b1 u_ext_msg.mdp_b1
1469 #define mdp_b0 u_ext_msg.mdp_b0
1471 typedef struct asc_dvc_cfg {
1472 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1473 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1474 ASC_SCSI_BIT_ID_TYPE disc_enable;
1475 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1477 uchar isa_dma_speed;
1478 uchar isa_dma_channel;
1480 ushort lib_serial_no;
1483 ushort mcode_version;
1484 uchar max_tag_qng[ASC_MAX_TID + 1];
1486 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1487 ushort pci_slot_info;
1488 uchar adapter_info[6];
1492 #define ASC_DEF_DVC_CNTL 0xFFFF
1493 #define ASC_DEF_CHIP_SCSI_ID 7
1494 #define ASC_DEF_ISA_DMA_SPEED 4
1495 #define ASC_INIT_STATE_NULL 0x0000
1496 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1497 #define ASC_INIT_STATE_END_GET_CFG 0x0002
1498 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1499 #define ASC_INIT_STATE_END_SET_CFG 0x0008
1500 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1501 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
1502 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1503 #define ASC_INIT_STATE_END_INQUIRY 0x0080
1504 #define ASC_INIT_RESET_SCSI_DONE 0x0100
1505 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1506 #define ASC_PCI_DEVICE_ID_REV_A 0x1100
1507 #define ASC_PCI_DEVICE_ID_REV_B 0x1200
1508 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1509 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1510 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1511 #define ASC_MIN_TAGGED_CMD 7
1512 #define ASC_MAX_SCSI_RESET_WAIT 30
1514 struct asc_dvc_var; /* Forward Declaration. */
1516 typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
1517 typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
1519 typedef struct asc_dvc_var {
1523 ushort bug_fix_cntl;
1525 ASC_ISR_CALLBACK isr_callback;
1526 ASC_EXE_CALLBACK exe_callback;
1527 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1528 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1529 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1530 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1531 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1532 ASC_SCSI_BIT_ID_TYPE start_motor;
1533 uchar scsi_reset_wait;
1536 uchar max_total_qng;
1537 uchar cur_total_qng;
1538 uchar in_critical_cnt;
1540 uchar last_q_shortage;
1542 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1543 uchar max_dvc_qng[ASC_MAX_TID + 1];
1544 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1545 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1546 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1548 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1551 uchar dos_int13_table[ASC_MAX_TID + 1];
1552 ASC_DCNT max_dma_count;
1553 ASC_SCSI_BIT_ID_TYPE no_scam;
1554 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1555 uchar max_sdtr_index;
1556 uchar host_init_sdtr_index;
1557 struct asc_board *drv_ptr;
1561 typedef struct asc_dvc_inq_info {
1562 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1565 typedef struct asc_cap_info {
1570 typedef struct asc_cap_info_array {
1571 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1572 } ASC_CAP_INFO_ARRAY;
1574 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1575 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1576 #define ASC_CNTL_INITIATOR (ushort)0x0001
1577 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1578 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1579 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1580 #define ASC_CNTL_NO_SCAM (ushort)0x0010
1581 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1582 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1583 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1584 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
1585 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1586 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1587 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1588 #define ASC_CNTL_BURST_MODE (ushort)0x2000
1589 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1590 #define ASC_EEP_DVC_CFG_BEG_VL 2
1591 #define ASC_EEP_MAX_DVC_ADDR_VL 15
1592 #define ASC_EEP_DVC_CFG_BEG 32
1593 #define ASC_EEP_MAX_DVC_ADDR 45
1594 #define ASC_EEP_DEFINED_WORDS 10
1595 #define ASC_EEP_MAX_ADDR 63
1596 #define ASC_EEP_RES_WORDS 0
1597 #define ASC_EEP_MAX_RETRY 20
1598 #define ASC_MAX_INIT_BUSY_RETRY 8
1599 #define ASC_EEP_ISA_PNP_WSIZE 16
1602 * These macros keep the chip SCSI id and ISA DMA speed
1603 * bitfields in board order. C bitfields aren't portable
1604 * between big and little-endian platforms so they are
1608 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1609 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1610 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1611 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1612 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1613 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1615 typedef struct asceep_config {
1622 uchar max_total_qng;
1625 uchar power_up_wait;
1627 uchar id_speed; /* low order 4 bits is chip scsi id */
1628 /* high order 4 bits is isa dma speed */
1629 uchar dos_int13_table[ASC_MAX_TID + 1];
1630 uchar adapter_info[6];
1635 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1636 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1637 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1639 #define ASC_EEP_CMD_READ 0x80
1640 #define ASC_EEP_CMD_WRITE 0x40
1641 #define ASC_EEP_CMD_WRITE_ABLE 0x30
1642 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1643 #define ASC_OVERRUN_BSIZE 0x00000048UL
1644 #define ASC_CTRL_BREAK_ONCE 0x0001
1645 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1646 #define ASCV_MSGOUT_BEG 0x0000
1647 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1648 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1649 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1650 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1651 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1652 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1653 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1654 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1655 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1656 #define ASCV_BREAK_ADDR (ushort)0x0028
1657 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1658 #define ASCV_BREAK_CONTROL (ushort)0x002C
1659 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1661 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1662 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1663 #define ASCV_MCODE_SIZE_W (ushort)0x0034
1664 #define ASCV_STOP_CODE_B (ushort)0x0036
1665 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1666 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1667 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1668 #define ASCV_HALTCODE_W (ushort)0x0040
1669 #define ASCV_CHKSUM_W (ushort)0x0042
1670 #define ASCV_MC_DATE_W (ushort)0x0044
1671 #define ASCV_MC_VER_W (ushort)0x0046
1672 #define ASCV_NEXTRDY_B (ushort)0x0048
1673 #define ASCV_DONENEXT_B (ushort)0x0049
1674 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1675 #define ASCV_SCSIBUSY_B (ushort)0x004B
1676 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1677 #define ASCV_CURCDB_B (ushort)0x004D
1678 #define ASCV_RCLUN_B (ushort)0x004E
1679 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
1680 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
1681 #define ASCV_DISC_ENABLE_B (ushort)0x0052
1682 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1683 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1684 #define ASCV_MCODE_CNTL_B (ushort)0x0056
1685 #define ASCV_NULL_TARGET_B (ushort)0x0057
1686 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1687 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1688 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1689 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1690 #define ASCV_HOST_FLAG_B (ushort)0x005D
1691 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1692 #define ASCV_VER_SERIAL_B (ushort)0x0065
1693 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1694 #define ASCV_WTM_FLAG_B (ushort)0x0068
1695 #define ASCV_RISC_FLAG_B (ushort)0x006A
1696 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1697 #define ASC_HOST_FLAG_IN_ISR 0x01
1698 #define ASC_HOST_FLAG_ACK_INT 0x02
1699 #define ASC_RISC_FLAG_GEN_INT 0x01
1700 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1701 #define IOP_CTRL (0x0F)
1702 #define IOP_STATUS (0x0E)
1703 #define IOP_INT_ACK IOP_STATUS
1704 #define IOP_REG_IFC (0x0D)
1705 #define IOP_SYN_OFFSET (0x0B)
1706 #define IOP_EXTRA_CONTROL (0x0D)
1707 #define IOP_REG_PC (0x0C)
1708 #define IOP_RAM_ADDR (0x0A)
1709 #define IOP_RAM_DATA (0x08)
1710 #define IOP_EEP_DATA (0x06)
1711 #define IOP_EEP_CMD (0x07)
1712 #define IOP_VERSION (0x03)
1713 #define IOP_CONFIG_HIGH (0x04)
1714 #define IOP_CONFIG_LOW (0x02)
1715 #define IOP_SIG_BYTE (0x01)
1716 #define IOP_SIG_WORD (0x00)
1717 #define IOP_REG_DC1 (0x0E)
1718 #define IOP_REG_DC0 (0x0C)
1719 #define IOP_REG_SB (0x0B)
1720 #define IOP_REG_DA1 (0x0A)
1721 #define IOP_REG_DA0 (0x08)
1722 #define IOP_REG_SC (0x09)
1723 #define IOP_DMA_SPEED (0x07)
1724 #define IOP_REG_FLAG (0x07)
1725 #define IOP_FIFO_H (0x06)
1726 #define IOP_FIFO_L (0x04)
1727 #define IOP_REG_ID (0x05)
1728 #define IOP_REG_QP (0x03)
1729 #define IOP_REG_IH (0x02)
1730 #define IOP_REG_IX (0x01)
1731 #define IOP_REG_AX (0x00)
1732 #define IFC_REG_LOCK (0x00)
1733 #define IFC_REG_UNLOCK (0x09)
1734 #define IFC_WR_EN_FILTER (0x10)
1735 #define IFC_RD_NO_EEPROM (0x10)
1736 #define IFC_SLEW_RATE (0x20)
1737 #define IFC_ACT_NEG (0x40)
1738 #define IFC_INP_FILTER (0x80)
1739 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1740 #define SC_SEL (uchar)(0x80)
1741 #define SC_BSY (uchar)(0x40)
1742 #define SC_ACK (uchar)(0x20)
1743 #define SC_REQ (uchar)(0x10)
1744 #define SC_ATN (uchar)(0x08)
1745 #define SC_IO (uchar)(0x04)
1746 #define SC_CD (uchar)(0x02)
1747 #define SC_MSG (uchar)(0x01)
1748 #define SEC_SCSI_CTL (uchar)(0x80)
1749 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
1750 #define SEC_SLEW_RATE (uchar)(0x20)
1751 #define SEC_ENABLE_FILTER (uchar)(0x10)
1752 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
1753 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
1754 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1755 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1756 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1757 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1758 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1759 #define ASC_MAX_QNO 0xF8
1760 #define ASC_DATA_SEC_BEG (ushort)0x0080
1761 #define ASC_DATA_SEC_END (ushort)0x0080
1762 #define ASC_CODE_SEC_BEG (ushort)0x0080
1763 #define ASC_CODE_SEC_END (ushort)0x0080
1764 #define ASC_QADR_BEG (0x4000)
1765 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1766 #define ASC_QADR_END (ushort)0x7FFF
1767 #define ASC_QLAST_ADR (ushort)0x7FC0
1768 #define ASC_QBLK_SIZE 0x40
1769 #define ASC_BIOS_DATA_QBEG 0xF8
1770 #define ASC_MIN_ACTIVE_QNO 0x01
1771 #define ASC_QLINK_END 0xFF
1772 #define ASC_EEPROM_WORDS 0x10
1773 #define ASC_MAX_MGS_LEN 0x10
1774 #define ASC_BIOS_ADDR_DEF 0xDC00
1775 #define ASC_BIOS_SIZE 0x3800
1776 #define ASC_BIOS_RAM_OFF 0x3800
1777 #define ASC_BIOS_RAM_SIZE 0x800
1778 #define ASC_BIOS_MIN_ADDR 0xC000
1779 #define ASC_BIOS_MAX_ADDR 0xEC00
1780 #define ASC_BIOS_BANK_SIZE 0x0400
1781 #define ASC_MCODE_START_ADDR 0x0080
1782 #define ASC_CFG0_HOST_INT_ON 0x0020
1783 #define ASC_CFG0_BIOS_ON 0x0040
1784 #define ASC_CFG0_VERA_BURST_ON 0x0080
1785 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1786 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1787 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1788 #define ASC_CFG_MSW_CLR_MASK 0x3080
1789 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
1790 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1791 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1792 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1793 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1794 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
1795 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
1796 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1797 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1798 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1799 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1800 #define CSW_HALTED (ASC_CS_TYPE)0x0010
1801 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1802 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1803 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1804 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1805 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1806 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1807 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
1808 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
1809 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1810 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1811 #define CC_CHIP_RESET (uchar)0x80
1812 #define CC_SCSI_RESET (uchar)0x40
1813 #define CC_HALT (uchar)0x20
1814 #define CC_SINGLE_STEP (uchar)0x10
1815 #define CC_DMA_ABLE (uchar)0x08
1816 #define CC_TEST (uchar)0x04
1817 #define CC_BANK_ONE (uchar)0x02
1818 #define CC_DIAG (uchar)0x01
1819 #define ASC_1000_ID0W 0x04C1
1820 #define ASC_1000_ID0W_FIX 0x00C1
1821 #define ASC_1000_ID1B 0x25
1822 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1823 #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1824 #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1825 #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1826 #define ASC_EISA_REV_IOP_MASK (0x0C83)
1827 #define ASC_EISA_PID_IOP_MASK (0x0C80)
1828 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1829 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1830 #define ASC_EISA_ID_740 0x01745004UL
1831 #define ASC_EISA_ID_750 0x01755004UL
1832 #define INS_HALTINT (ushort)0x6281
1833 #define INS_HALT (ushort)0x6280
1834 #define INS_SINT (ushort)0x6200
1835 #define INS_RFLAG_WTM (ushort)0x7380
1836 #define ASC_MC_SAVE_CODE_WSIZE 0x500
1837 #define ASC_MC_SAVE_DATA_WSIZE 0x40
1839 typedef struct asc_mc_saved {
1840 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1841 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1844 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1845 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1846 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1847 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1848 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1849 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1850 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1851 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1852 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1853 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1854 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1855 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1856 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1857 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1858 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1859 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1860 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1861 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1862 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1863 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1864 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1865 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1866 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1867 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1868 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1869 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1870 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1871 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1872 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1873 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1874 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1875 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1876 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1877 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1878 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1879 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1880 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1881 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1882 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1883 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1884 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1885 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1886 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1887 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1888 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1889 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1890 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1891 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1892 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1893 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1894 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1895 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1896 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1897 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1898 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1899 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1900 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1901 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1902 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1903 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1904 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1905 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1906 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1907 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1908 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1909 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1910 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1911 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1913 STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1914 STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1915 STATIC void AscWaitEEPRead(void);
1916 STATIC void AscWaitEEPWrite(void);
1917 STATIC ushort AscReadEEPWord(PortAddr, uchar);
1918 STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1919 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1920 STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1921 STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1922 STATIC int AscStartChip(PortAddr);
1923 STATIC int AscStopChip(PortAddr);
1924 STATIC void AscSetChipIH(PortAddr, ushort);
1925 STATIC int AscIsChipHalted(PortAddr);
1926 STATIC void AscAckInterrupt(PortAddr);
1927 STATIC void AscDisableInterrupt(PortAddr);
1928 STATIC void AscEnableInterrupt(PortAddr);
1929 STATIC void AscSetBank(PortAddr, uchar);
1930 STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1932 STATIC ushort AscGetIsaDmaChannel(PortAddr);
1933 STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
1934 STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1935 STATIC uchar AscGetIsaDmaSpeed(PortAddr);
1936 #endif /* CONFIG_ISA */
1937 STATIC uchar AscReadLramByte(PortAddr, ushort);
1938 STATIC ushort AscReadLramWord(PortAddr, ushort);
1939 #if CC_VERY_LONG_SG_LIST
1940 STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1941 #endif /* CC_VERY_LONG_SG_LIST */
1942 STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
1943 STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
1944 STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1945 STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1946 STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1947 STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1948 STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1949 STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1950 STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
1951 STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1952 STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1953 STATIC int AscTestExternalLram(ASC_DVC_VAR *);
1954 STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1955 STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1956 STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
1957 STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1958 STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
1959 STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1960 STATIC int AscHostReqRiscHalt(PortAddr);
1961 STATIC int AscStopQueueExe(PortAddr);
1962 STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
1964 uchar n_q_required);
1965 STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
1966 ASC_SCSI_Q *, uchar);
1967 STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
1968 ASC_SCSI_Q *, uchar);
1969 STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1970 STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1971 STATIC ushort AscInitLram(ASC_DVC_VAR *);
1972 STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
1973 STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1974 STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
1975 STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1976 ASC_QDONE_INFO *, ASC_DCNT);
1977 STATIC int AscIsrQDone(ASC_DVC_VAR *);
1978 STATIC int AscCompareString(uchar *, uchar *, int);
1980 STATIC ushort AscGetEisaChipCfg(PortAddr);
1981 STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
1982 STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
1983 STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
1984 STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1985 STATIC void AscSetISAPNPWaitForKey(void);
1986 #endif /* CONFIG_ISA */
1987 STATIC uchar AscGetChipScsiCtrl(PortAddr);
1988 STATIC uchar AscSetChipScsiID(PortAddr, uchar);
1989 STATIC uchar AscGetChipVersion(PortAddr, ushort);
1990 STATIC ushort AscGetChipBusType(PortAddr);
1991 STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1992 STATIC int AscFindSignature(PortAddr);
1993 STATIC void AscToggleIRQAct(PortAddr);
1994 STATIC uchar AscGetChipIRQ(PortAddr, ushort);
1995 STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1996 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1997 STATIC inline ulong DvcEnterCritical(void);
1998 STATIC inline void DvcLeaveCritical(ulong);
2000 STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
2001 STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
2003 #endif /* CONFIG_PCI */
2004 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
2005 STATIC void DvcSleepMilliSecond(ASC_DCNT);
2006 STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
2007 STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
2008 STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
2009 STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
2010 STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
2011 STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
2012 STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
2013 ASC_SCSI_INQUIRY *);
2014 STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
2015 STATIC void AscInquiryHandling(ASC_DVC_VAR *,
2016 uchar, ASC_SCSI_INQUIRY *);
2017 STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
2018 STATIC int AscISR(ASC_DVC_VAR *);
2019 STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
2021 STATIC int AscSgListToQueue(int);
2023 STATIC void AscEnableIsaDma(uchar);
2024 #endif /* CONFIG_ISA */
2025 STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
2029 * --- Adv Library Constants and Macros
2032 #define ADV_LIB_VERSION_MAJOR 5
2033 #define ADV_LIB_VERSION_MINOR 14
2036 #define ADV_OS_LINUX
2039 * Define Adv Library required special types.
2043 * Portable Data Types
2045 * Any instance where a 32-bit long or pointer type is assumed
2046 * for precision or HW defined structures, the following define
2047 * types must be used. In Linux the char, short, and int types
2048 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2049 * and long types are 64 bits on Alpha and UltraSPARC.
2051 #define ADV_PADDR __u32 /* Physical address data type. */
2052 #define ADV_VADDR __u32 /* Virtual address data type. */
2053 #define ADV_DCNT __u32 /* Unsigned Data count type. */
2054 #define ADV_SDCNT __s32 /* Signed Data count type. */
2057 * These macros are used to convert a virtual address to a
2058 * 32-bit value. This currently can be used on Linux Alpha
2059 * which uses 64-bit virtual address but a 32-bit bus address.
2060 * This is likely to break in the future, but doing this now
2061 * will give us time to change the HW and FW to handle 64-bit
2064 #define ADV_VADDR_TO_U32 virt_to_bus
2065 #define ADV_U32_TO_VADDR bus_to_virt
2067 #define AdvPortAddr ulong /* Virtual memory address size */
2070 * Define Adv Library required memory access macros.
2072 #define ADV_MEM_READB(addr) readb(addr)
2073 #define ADV_MEM_READW(addr) readw(addr)
2074 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2075 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2076 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2078 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2081 * For wide boards a CDB length maximum of 16 bytes
2084 #define ADV_MAX_CDB_LEN 16
2087 * Define total number of simultaneous maximum element scatter-gather
2088 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2089 * maximum number of outstanding commands per wide host adapter. Each
2090 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2091 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2092 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2093 * structures or 255 scatter-gather elements.
2096 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2099 * Define Adv Library required maximum number of scatter-gather
2100 * elements per request.
2102 #define ADV_MAX_SG_LIST 255
2104 /* Number of SG blocks needed. */
2105 #define ADV_NUM_SG_BLOCK \
2106 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2108 /* Total contiguous memory needed for SG blocks. */
2109 #define ADV_SG_TOTAL_MEM_SIZE \
2110 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2112 #define ADV_PAGE_SIZE PAGE_SIZE
2114 #define ADV_NUM_PAGE_CROSSING \
2115 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2118 #define ADV_PCI_VENDOR_ID 0x10CD
2119 #define ADV_PCI_DEVICE_ID_REV_A 0x2300
2120 #define ADV_PCI_DEVID_38C0800_REV1 0x2500
2121 #define ADV_PCI_DEVID_38C1600_REV1 0x2700
2123 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
2124 #define ADV_EEP_DVC_CFG_END (0x15)
2125 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2126 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
2128 #define ADV_EEP_DELAY_MS 100
2130 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2131 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2133 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2134 * For later ICs Bit 13 controls whether the CIS (Card Information
2135 * Service Section) is loaded from EEPROM.
2137 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2138 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2142 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2143 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2144 * Function 0 will specify INT B.
2146 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2147 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2148 * Function 1 will specify INT A.
2150 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2152 typedef struct adveep_3550_config
2154 /* Word Offset, Description */
2156 ushort cfg_lsw; /* 00 power up initialization */
2157 /* bit 13 set - Term Polarity Control */
2158 /* bit 14 set - BIOS Enable */
2159 /* bit 15 set - Big Endian Mode */
2160 ushort cfg_msw; /* 01 unused */
2161 ushort disc_enable; /* 02 disconnect enable */
2162 ushort wdtr_able; /* 03 Wide DTR able */
2163 ushort sdtr_able; /* 04 Synchronous DTR able */
2164 ushort start_motor; /* 05 send start up motor */
2165 ushort tagqng_able; /* 06 tag queuing able */
2166 ushort bios_scan; /* 07 BIOS device control */
2167 ushort scam_tolerant; /* 08 no scam */
2169 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2170 uchar bios_boot_delay; /* power up wait */
2172 uchar scsi_reset_delay; /* 10 reset delay */
2173 uchar bios_id_lun; /* first boot device scsi id & lun */
2174 /* high nibble is lun */
2175 /* low nibble is scsi id */
2177 uchar termination; /* 11 0 - automatic */
2178 /* 1 - low off / high off */
2179 /* 2 - low off / high on */
2180 /* 3 - low on / high on */
2181 /* There is no low on / high off */
2183 uchar reserved1; /* reserved byte (not used) */
2185 ushort bios_ctrl; /* 12 BIOS control bits */
2186 /* bit 0 BIOS don't act as initiator. */
2187 /* bit 1 BIOS > 1 GB support */
2188 /* bit 2 BIOS > 2 Disk Support */
2189 /* bit 3 BIOS don't support removables */
2190 /* bit 4 BIOS support bootable CD */
2191 /* bit 5 BIOS scan enabled */
2192 /* bit 6 BIOS support multiple LUNs */
2193 /* bit 7 BIOS display of message */
2194 /* bit 8 SCAM disabled */
2195 /* bit 9 Reset SCSI bus during init. */
2197 /* bit 11 No verbose initialization. */
2198 /* bit 12 SCSI parity enabled */
2202 ushort ultra_able; /* 13 ULTRA speed able */
2203 ushort reserved2; /* 14 reserved */
2204 uchar max_host_qng; /* 15 maximum host queuing */
2205 uchar max_dvc_qng; /* maximum per device queuing */
2206 ushort dvc_cntl; /* 16 control bit for driver */
2207 ushort bug_fix; /* 17 control bit for bug fix */
2208 ushort serial_number_word1; /* 18 Board serial number word 1 */
2209 ushort serial_number_word2; /* 19 Board serial number word 2 */
2210 ushort serial_number_word3; /* 20 Board serial number word 3 */
2211 ushort check_sum; /* 21 EEP check sum */
2212 uchar oem_name[16]; /* 22 OEM name */
2213 ushort dvc_err_code; /* 30 last device driver error code */
2214 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2215 ushort adv_err_addr; /* 32 last uc error address */
2216 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2217 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2218 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2219 ushort num_of_err; /* 36 number of error */
2220 } ADVEEP_3550_CONFIG;
2222 typedef struct adveep_38C0800_config
2224 /* Word Offset, Description */
2226 ushort cfg_lsw; /* 00 power up initialization */
2227 /* bit 13 set - Load CIS */
2228 /* bit 14 set - BIOS Enable */
2229 /* bit 15 set - Big Endian Mode */
2230 ushort cfg_msw; /* 01 unused */
2231 ushort disc_enable; /* 02 disconnect enable */
2232 ushort wdtr_able; /* 03 Wide DTR able */
2233 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2234 ushort start_motor; /* 05 send start up motor */
2235 ushort tagqng_able; /* 06 tag queuing able */
2236 ushort bios_scan; /* 07 BIOS device control */
2237 ushort scam_tolerant; /* 08 no scam */
2239 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2240 uchar bios_boot_delay; /* power up wait */
2242 uchar scsi_reset_delay; /* 10 reset delay */
2243 uchar bios_id_lun; /* first boot device scsi id & lun */
2244 /* high nibble is lun */
2245 /* low nibble is scsi id */
2247 uchar termination_se; /* 11 0 - automatic */
2248 /* 1 - low off / high off */
2249 /* 2 - low off / high on */
2250 /* 3 - low on / high on */
2251 /* There is no low on / high off */
2253 uchar termination_lvd; /* 11 0 - automatic */
2254 /* 1 - low off / high off */
2255 /* 2 - low off / high on */
2256 /* 3 - low on / high on */
2257 /* There is no low on / high off */
2259 ushort bios_ctrl; /* 12 BIOS control bits */
2260 /* bit 0 BIOS don't act as initiator. */
2261 /* bit 1 BIOS > 1 GB support */
2262 /* bit 2 BIOS > 2 Disk Support */
2263 /* bit 3 BIOS don't support removables */
2264 /* bit 4 BIOS support bootable CD */
2265 /* bit 5 BIOS scan enabled */
2266 /* bit 6 BIOS support multiple LUNs */
2267 /* bit 7 BIOS display of message */
2268 /* bit 8 SCAM disabled */
2269 /* bit 9 Reset SCSI bus during init. */
2271 /* bit 11 No verbose initialization. */
2272 /* bit 12 SCSI parity enabled */
2276 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2277 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2278 uchar max_host_qng; /* 15 maximum host queueing */
2279 uchar max_dvc_qng; /* maximum per device queuing */
2280 ushort dvc_cntl; /* 16 control bit for driver */
2281 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2282 ushort serial_number_word1; /* 18 Board serial number word 1 */
2283 ushort serial_number_word2; /* 19 Board serial number word 2 */
2284 ushort serial_number_word3; /* 20 Board serial number word 3 */
2285 ushort check_sum; /* 21 EEP check sum */
2286 uchar oem_name[16]; /* 22 OEM name */
2287 ushort dvc_err_code; /* 30 last device driver error code */
2288 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2289 ushort adv_err_addr; /* 32 last uc error address */
2290 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2291 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2292 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2293 ushort reserved36; /* 36 reserved */
2294 ushort reserved37; /* 37 reserved */
2295 ushort reserved38; /* 38 reserved */
2296 ushort reserved39; /* 39 reserved */
2297 ushort reserved40; /* 40 reserved */
2298 ushort reserved41; /* 41 reserved */
2299 ushort reserved42; /* 42 reserved */
2300 ushort reserved43; /* 43 reserved */
2301 ushort reserved44; /* 44 reserved */
2302 ushort reserved45; /* 45 reserved */
2303 ushort reserved46; /* 46 reserved */
2304 ushort reserved47; /* 47 reserved */
2305 ushort reserved48; /* 48 reserved */
2306 ushort reserved49; /* 49 reserved */
2307 ushort reserved50; /* 50 reserved */
2308 ushort reserved51; /* 51 reserved */
2309 ushort reserved52; /* 52 reserved */
2310 ushort reserved53; /* 53 reserved */
2311 ushort reserved54; /* 54 reserved */
2312 ushort reserved55; /* 55 reserved */
2313 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2314 ushort cisprt_msw; /* 57 CIS PTR MSW */
2315 ushort subsysvid; /* 58 SubSystem Vendor ID */
2316 ushort subsysid; /* 59 SubSystem ID */
2317 ushort reserved60; /* 60 reserved */
2318 ushort reserved61; /* 61 reserved */
2319 ushort reserved62; /* 62 reserved */
2320 ushort reserved63; /* 63 reserved */
2321 } ADVEEP_38C0800_CONFIG;
2323 typedef struct adveep_38C1600_config
2325 /* Word Offset, Description */
2327 ushort cfg_lsw; /* 00 power up initialization */
2328 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2329 /* clear - Func. 0 INTA, Func. 1 INTB */
2330 /* bit 13 set - Load CIS */
2331 /* bit 14 set - BIOS Enable */
2332 /* bit 15 set - Big Endian Mode */
2333 ushort cfg_msw; /* 01 unused */
2334 ushort disc_enable; /* 02 disconnect enable */
2335 ushort wdtr_able; /* 03 Wide DTR able */
2336 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2337 ushort start_motor; /* 05 send start up motor */
2338 ushort tagqng_able; /* 06 tag queuing able */
2339 ushort bios_scan; /* 07 BIOS device control */
2340 ushort scam_tolerant; /* 08 no scam */
2342 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2343 uchar bios_boot_delay; /* power up wait */
2345 uchar scsi_reset_delay; /* 10 reset delay */
2346 uchar bios_id_lun; /* first boot device scsi id & lun */
2347 /* high nibble is lun */
2348 /* low nibble is scsi id */
2350 uchar termination_se; /* 11 0 - automatic */
2351 /* 1 - low off / high off */
2352 /* 2 - low off / high on */
2353 /* 3 - low on / high on */
2354 /* There is no low on / high off */
2356 uchar termination_lvd; /* 11 0 - automatic */
2357 /* 1 - low off / high off */
2358 /* 2 - low off / high on */
2359 /* 3 - low on / high on */
2360 /* There is no low on / high off */
2362 ushort bios_ctrl; /* 12 BIOS control bits */
2363 /* bit 0 BIOS don't act as initiator. */
2364 /* bit 1 BIOS > 1 GB support */
2365 /* bit 2 BIOS > 2 Disk Support */
2366 /* bit 3 BIOS don't support removables */
2367 /* bit 4 BIOS support bootable CD */
2368 /* bit 5 BIOS scan enabled */
2369 /* bit 6 BIOS support multiple LUNs */
2370 /* bit 7 BIOS display of message */
2371 /* bit 8 SCAM disabled */
2372 /* bit 9 Reset SCSI bus during init. */
2373 /* bit 10 Basic Integrity Checking disabled */
2374 /* bit 11 No verbose initialization. */
2375 /* bit 12 SCSI parity enabled */
2376 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2379 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2380 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2381 uchar max_host_qng; /* 15 maximum host queueing */
2382 uchar max_dvc_qng; /* maximum per device queuing */
2383 ushort dvc_cntl; /* 16 control bit for driver */
2384 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2385 ushort serial_number_word1; /* 18 Board serial number word 1 */
2386 ushort serial_number_word2; /* 19 Board serial number word 2 */
2387 ushort serial_number_word3; /* 20 Board serial number word 3 */
2388 ushort check_sum; /* 21 EEP check sum */
2389 uchar oem_name[16]; /* 22 OEM name */
2390 ushort dvc_err_code; /* 30 last device driver error code */
2391 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2392 ushort adv_err_addr; /* 32 last uc error address */
2393 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2394 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2395 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2396 ushort reserved36; /* 36 reserved */
2397 ushort reserved37; /* 37 reserved */
2398 ushort reserved38; /* 38 reserved */
2399 ushort reserved39; /* 39 reserved */
2400 ushort reserved40; /* 40 reserved */
2401 ushort reserved41; /* 41 reserved */
2402 ushort reserved42; /* 42 reserved */
2403 ushort reserved43; /* 43 reserved */
2404 ushort reserved44; /* 44 reserved */
2405 ushort reserved45; /* 45 reserved */
2406 ushort reserved46; /* 46 reserved */
2407 ushort reserved47; /* 47 reserved */
2408 ushort reserved48; /* 48 reserved */
2409 ushort reserved49; /* 49 reserved */
2410 ushort reserved50; /* 50 reserved */
2411 ushort reserved51; /* 51 reserved */
2412 ushort reserved52; /* 52 reserved */
2413 ushort reserved53; /* 53 reserved */
2414 ushort reserved54; /* 54 reserved */
2415 ushort reserved55; /* 55 reserved */
2416 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2417 ushort cisprt_msw; /* 57 CIS PTR MSW */
2418 ushort subsysvid; /* 58 SubSystem Vendor ID */
2419 ushort subsysid; /* 59 SubSystem ID */
2420 ushort reserved60; /* 60 reserved */
2421 ushort reserved61; /* 61 reserved */
2422 ushort reserved62; /* 62 reserved */
2423 ushort reserved63; /* 63 reserved */
2424 } ADVEEP_38C1600_CONFIG;
2429 #define ASC_EEP_CMD_DONE 0x0200
2430 #define ASC_EEP_CMD_DONE_ERR 0x0001
2433 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2436 #define BIOS_CTRL_BIOS 0x0001
2437 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
2438 #define BIOS_CTRL_GT_2_DISK 0x0004
2439 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2440 #define BIOS_CTRL_BOOTABLE_CD 0x0010
2441 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
2442 #define BIOS_CTRL_DISPLAY_MSG 0x0080
2443 #define BIOS_CTRL_NO_SCAM 0x0100
2444 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2445 #define BIOS_CTRL_INIT_VERBOSE 0x0800
2446 #define BIOS_CTRL_SCSI_PARITY 0x1000
2447 #define BIOS_CTRL_AIPP_DIS 0x2000
2449 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2450 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2452 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2453 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2456 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2457 * a special 16K Adv Library and Microcode version. After the issue is
2458 * resolved, should restore 32K support.
2460 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2462 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2463 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2464 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2467 * Byte I/O register address from base of 'iop_base'.
2469 #define IOPB_INTR_STATUS_REG 0x00
2470 #define IOPB_CHIP_ID_1 0x01
2471 #define IOPB_INTR_ENABLES 0x02
2472 #define IOPB_CHIP_TYPE_REV 0x03
2473 #define IOPB_RES_ADDR_4 0x04
2474 #define IOPB_RES_ADDR_5 0x05
2475 #define IOPB_RAM_DATA 0x06
2476 #define IOPB_RES_ADDR_7 0x07
2477 #define IOPB_FLAG_REG 0x08
2478 #define IOPB_RES_ADDR_9 0x09
2479 #define IOPB_RISC_CSR 0x0A
2480 #define IOPB_RES_ADDR_B 0x0B
2481 #define IOPB_RES_ADDR_C 0x0C
2482 #define IOPB_RES_ADDR_D 0x0D
2483 #define IOPB_SOFT_OVER_WR 0x0E
2484 #define IOPB_RES_ADDR_F 0x0F
2485 #define IOPB_MEM_CFG 0x10
2486 #define IOPB_RES_ADDR_11 0x11
2487 #define IOPB_GPIO_DATA 0x12
2488 #define IOPB_RES_ADDR_13 0x13
2489 #define IOPB_FLASH_PAGE 0x14
2490 #define IOPB_RES_ADDR_15 0x15
2491 #define IOPB_GPIO_CNTL 0x16
2492 #define IOPB_RES_ADDR_17 0x17
2493 #define IOPB_FLASH_DATA 0x18
2494 #define IOPB_RES_ADDR_19 0x19
2495 #define IOPB_RES_ADDR_1A 0x1A
2496 #define IOPB_RES_ADDR_1B 0x1B
2497 #define IOPB_RES_ADDR_1C 0x1C
2498 #define IOPB_RES_ADDR_1D 0x1D
2499 #define IOPB_RES_ADDR_1E 0x1E
2500 #define IOPB_RES_ADDR_1F 0x1F
2501 #define IOPB_DMA_CFG0 0x20
2502 #define IOPB_DMA_CFG1 0x21
2503 #define IOPB_TICKLE 0x22
2504 #define IOPB_DMA_REG_WR 0x23
2505 #define IOPB_SDMA_STATUS 0x24
2506 #define IOPB_SCSI_BYTE_CNT 0x25
2507 #define IOPB_HOST_BYTE_CNT 0x26
2508 #define IOPB_BYTE_LEFT_TO_XFER 0x27
2509 #define IOPB_BYTE_TO_XFER_0 0x28
2510 #define IOPB_BYTE_TO_XFER_1 0x29
2511 #define IOPB_BYTE_TO_XFER_2 0x2A
2512 #define IOPB_BYTE_TO_XFER_3 0x2B
2513 #define IOPB_ACC_GRP 0x2C
2514 #define IOPB_RES_ADDR_2D 0x2D
2515 #define IOPB_DEV_ID 0x2E
2516 #define IOPB_RES_ADDR_2F 0x2F
2517 #define IOPB_SCSI_DATA 0x30
2518 #define IOPB_RES_ADDR_31 0x31
2519 #define IOPB_RES_ADDR_32 0x32
2520 #define IOPB_SCSI_DATA_HSHK 0x33
2521 #define IOPB_SCSI_CTRL 0x34
2522 #define IOPB_RES_ADDR_35 0x35
2523 #define IOPB_RES_ADDR_36 0x36
2524 #define IOPB_RES_ADDR_37 0x37
2525 #define IOPB_RAM_BIST 0x38
2526 #define IOPB_PLL_TEST 0x39
2527 #define IOPB_PCI_INT_CFG 0x3A
2528 #define IOPB_RES_ADDR_3B 0x3B
2529 #define IOPB_RFIFO_CNT 0x3C
2530 #define IOPB_RES_ADDR_3D 0x3D
2531 #define IOPB_RES_ADDR_3E 0x3E
2532 #define IOPB_RES_ADDR_3F 0x3F
2535 * Word I/O register address from base of 'iop_base'.
2537 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
2538 #define IOPW_CTRL_REG 0x02 /* CC */
2539 #define IOPW_RAM_ADDR 0x04 /* LA */
2540 #define IOPW_RAM_DATA 0x06 /* LD */
2541 #define IOPW_RES_ADDR_08 0x08
2542 #define IOPW_RISC_CSR 0x0A /* CSR */
2543 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2544 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2545 #define IOPW_RES_ADDR_10 0x10
2546 #define IOPW_SEL_MASK 0x12 /* SM */
2547 #define IOPW_RES_ADDR_14 0x14
2548 #define IOPW_FLASH_ADDR 0x16 /* FA */
2549 #define IOPW_RES_ADDR_18 0x18
2550 #define IOPW_EE_CMD 0x1A /* EC */
2551 #define IOPW_EE_DATA 0x1C /* ED */
2552 #define IOPW_SFIFO_CNT 0x1E /* SFC */
2553 #define IOPW_RES_ADDR_20 0x20
2554 #define IOPW_Q_BASE 0x22 /* QB */
2555 #define IOPW_QP 0x24 /* QP */
2556 #define IOPW_IX 0x26 /* IX */
2557 #define IOPW_SP 0x28 /* SP */
2558 #define IOPW_PC 0x2A /* PC */
2559 #define IOPW_RES_ADDR_2C 0x2C
2560 #define IOPW_RES_ADDR_2E 0x2E
2561 #define IOPW_SCSI_DATA 0x30 /* SD */
2562 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2563 #define IOPW_SCSI_CTRL 0x34 /* SC */
2564 #define IOPW_HSHK_CFG 0x36 /* HCFG */
2565 #define IOPW_SXFR_STATUS 0x36 /* SXS */
2566 #define IOPW_SXFR_CNTL 0x38 /* SXL */
2567 #define IOPW_SXFR_CNTH 0x3A /* SXH */
2568 #define IOPW_RES_ADDR_3C 0x3C
2569 #define IOPW_RFIFO_DATA 0x3E /* RFD */
2572 * Doubleword I/O register address from base of 'iop_base'.
2574 #define IOPDW_RES_ADDR_0 0x00
2575 #define IOPDW_RAM_DATA 0x04
2576 #define IOPDW_RES_ADDR_8 0x08
2577 #define IOPDW_RES_ADDR_C 0x0C
2578 #define IOPDW_RES_ADDR_10 0x10
2579 #define IOPDW_COMMA 0x14
2580 #define IOPDW_COMMB 0x18
2581 #define IOPDW_RES_ADDR_1C 0x1C
2582 #define IOPDW_SDMA_ADDR0 0x20
2583 #define IOPDW_SDMA_ADDR1 0x24
2584 #define IOPDW_SDMA_COUNT 0x28
2585 #define IOPDW_SDMA_ERROR 0x2C
2586 #define IOPDW_RDMA_ADDR0 0x30
2587 #define IOPDW_RDMA_ADDR1 0x34
2588 #define IOPDW_RDMA_COUNT 0x38
2589 #define IOPDW_RDMA_ERROR 0x3C
2591 #define ADV_CHIP_ID_BYTE 0x25
2592 #define ADV_CHIP_ID_WORD 0x04C1
2594 #define ADV_SC_SCSI_BUS_RESET 0x2000
2596 #define ADV_INTR_ENABLE_HOST_INTR 0x01
2597 #define ADV_INTR_ENABLE_SEL_INTR 0x02
2598 #define ADV_INTR_ENABLE_DPR_INTR 0x04
2599 #define ADV_INTR_ENABLE_RTA_INTR 0x08
2600 #define ADV_INTR_ENABLE_RMA_INTR 0x10
2601 #define ADV_INTR_ENABLE_RST_INTR 0x20
2602 #define ADV_INTR_ENABLE_DPE_INTR 0x40
2603 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2605 #define ADV_INTR_STATUS_INTRA 0x01
2606 #define ADV_INTR_STATUS_INTRB 0x02
2607 #define ADV_INTR_STATUS_INTRC 0x04
2609 #define ADV_RISC_CSR_STOP (0x0000)
2610 #define ADV_RISC_TEST_COND (0x2000)
2611 #define ADV_RISC_CSR_RUN (0x4000)
2612 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2614 #define ADV_CTRL_REG_HOST_INTR 0x0100
2615 #define ADV_CTRL_REG_SEL_INTR 0x0200
2616 #define ADV_CTRL_REG_DPR_INTR 0x0400
2617 #define ADV_CTRL_REG_RTA_INTR 0x0800
2618 #define ADV_CTRL_REG_RMA_INTR 0x1000
2619 #define ADV_CTRL_REG_RES_BIT14 0x2000
2620 #define ADV_CTRL_REG_DPE_INTR 0x4000
2621 #define ADV_CTRL_REG_POWER_DONE 0x8000
2622 #define ADV_CTRL_REG_ANY_INTR 0xFF00
2624 #define ADV_CTRL_REG_CMD_RESET 0x00C6
2625 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2626 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2627 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2628 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2630 #define ADV_TICKLE_NOP 0x00
2631 #define ADV_TICKLE_A 0x01
2632 #define ADV_TICKLE_B 0x02
2633 #define ADV_TICKLE_C 0x03
2635 #define ADV_SCSI_CTRL_RSTOUT 0x2000
2637 #define AdvIsIntPending(port) \
2638 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2641 * SCSI_CFG0 Register bit definitions
2643 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2644 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2645 #define EVEN_PARITY 0x1000 /* Select Even Parity */
2646 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2647 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2648 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2649 #define SCAM_EN 0x0080 /* Enable SCAM selection */
2650 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2651 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2652 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2653 #define OUR_ID 0x000F /* SCSI ID */
2656 * SCSI_CFG1 Register bit definitions
2658 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2659 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2660 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2661 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
2662 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2663 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2664 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2665 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2666 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2667 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2668 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2669 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2670 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2671 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2672 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2675 * Addendum for ASC-38C0800 Chip
2677 * The ASC-38C1600 Chip uses the same definitions except that the
2678 * bus mode override bits [12:10] have been moved to byte register
2679 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2680 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2681 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2682 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2683 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2685 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2686 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2687 #define HVD 0x1000 /* HVD Device Detect */
2688 #define LVD 0x0800 /* LVD Device Detect */
2689 #define SE 0x0400 /* SE Device Detect */
2690 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
2691 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2692 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2693 #define TERM_SE 0x0030 /* SE Termination Bits */
2694 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2695 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2696 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2697 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2698 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2699 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2700 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2701 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2704 #define CABLE_ILLEGAL_A 0x7
2705 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2707 #define CABLE_ILLEGAL_B 0xB
2708 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2711 * MEM_CFG Register bit definitions
2713 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2714 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2715 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2716 #define RAM_SZ_2KB 0x00 /* 2 KB */
2717 #define RAM_SZ_4KB 0x04 /* 4 KB */
2718 #define RAM_SZ_8KB 0x08 /* 8 KB */
2719 #define RAM_SZ_16KB 0x0C /* 16 KB */
2720 #define RAM_SZ_32KB 0x10 /* 32 KB */
2721 #define RAM_SZ_64KB 0x14 /* 64 KB */
2724 * DMA_CFG0 Register bit definitions
2726 * This register is only accessible to the host.
2728 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2729 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2730 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
2731 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
2732 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
2733 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
2734 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2735 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
2736 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
2737 #define START_CTL 0x0C /* DMA start conditions */
2738 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
2739 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2740 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2741 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2742 #define READ_CMD 0x03 /* Memory Read Method */
2743 #define READ_CMD_MR 0x00 /* Memory Read */
2744 #define READ_CMD_MRL 0x02 /* Memory Read Long */
2745 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2748 * ASC-38C0800 RAM BIST Register bit definitions
2750 #define RAM_TEST_MODE 0x80
2751 #define PRE_TEST_MODE 0x40
2752 #define NORMAL_MODE 0x00
2753 #define RAM_TEST_DONE 0x10
2754 #define RAM_TEST_STATUS 0x0F
2755 #define RAM_TEST_HOST_ERROR 0x08
2756 #define RAM_TEST_INTRAM_ERROR 0x04
2757 #define RAM_TEST_RISC_ERROR 0x02
2758 #define RAM_TEST_SCSI_ERROR 0x01
2759 #define RAM_TEST_SUCCESS 0x00
2760 #define PRE_TEST_VALUE 0x05
2761 #define NORMAL_VALUE 0x00
2764 * ASC38C1600 Definitions
2766 * IOPB_PCI_INT_CFG Bit Field Definitions
2769 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2772 * Bit 1 can be set to change the interrupt for the Function to operate in
2773 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2774 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2775 * mode, otherwise the operating mode is undefined.
2777 #define TOTEMPOLE 0x02
2780 * Bit 0 can be used to change the Int Pin for the Function. The value is
2781 * 0 by default for both Functions with Function 0 using INT A and Function
2782 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2785 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2786 * value specified in the PCI Configuration Space.
2793 * Adv Library Status Definitions
2797 #define ADV_NOERROR 1
2798 #define ADV_SUCCESS 1
2800 #define ADV_ERROR (-1)
2804 * ADV_DVC_VAR 'warn_code' values
2806 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2807 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2808 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2809 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2810 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2812 #define ADV_MAX_TID 15 /* max. target identifier */
2813 #define ADV_MAX_LUN 7 /* max. logical unit number */
2816 * Error code values are set in ADV_DVC_VAR 'err_code'.
2818 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2819 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2820 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2821 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2822 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2823 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2824 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2825 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2826 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2827 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2828 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2829 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2830 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2831 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2834 * Fixed locations of microcode operating variables.
2836 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2837 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2838 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2839 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2840 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2841 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2842 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2843 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2844 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2845 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2846 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2847 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2848 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2849 #define ASC_MC_CHIP_TYPE 0x009A
2850 #define ASC_MC_INTRB_CODE 0x009B
2851 #define ASC_MC_WDTR_ABLE 0x009C
2852 #define ASC_MC_SDTR_ABLE 0x009E
2853 #define ASC_MC_TAGQNG_ABLE 0x00A0
2854 #define ASC_MC_DISC_ENABLE 0x00A2
2855 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
2856 #define ASC_MC_IDLE_CMD 0x00A6
2857 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2858 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2859 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2860 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2861 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2862 #define ASC_MC_SDTR_DONE 0x00B6
2863 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2864 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2865 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2866 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2867 #define ASC_MC_WDTR_DONE 0x0124
2868 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2869 #define ASC_MC_ICQ 0x0160
2870 #define ASC_MC_IRQ 0x0164
2871 #define ASC_MC_PPR_ABLE 0x017A
2874 * BIOS LRAM variable absolute offsets.
2876 #define BIOS_CODESEG 0x54
2877 #define BIOS_CODELEN 0x56
2878 #define BIOS_SIGNATURE 0x58
2879 #define BIOS_VERSION 0x5A
2882 * Microcode Control Flags
2884 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2885 * and handled by the microcode.
2887 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2888 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2891 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2893 #define HSHK_CFG_WIDE_XFR 0x8000
2894 #define HSHK_CFG_RATE 0x0F00
2895 #define HSHK_CFG_OFFSET 0x001F
2897 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2898 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2899 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2900 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2902 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2903 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2904 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2905 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2906 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2908 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2909 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2910 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2911 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2912 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2914 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2915 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2917 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2918 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2921 * All fields here are accessed by the board microcode and need to be
2924 typedef struct adv_carr_t
2926 ADV_VADDR carr_va; /* Carrier Virtual Address */
2927 ADV_PADDR carr_pa; /* Carrier Physical Address */
2928 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2930 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2932 * next_vpa [3:1] Reserved Bits
2933 * next_vpa [0] Done Flag set in Response Queue.
2939 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2941 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2943 #define ASC_RQ_DONE 0x00000001
2944 #define ASC_RQ_GOOD 0x00000002
2945 #define ASC_CQ_STOPPER 0x00000000
2947 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2949 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2950 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2951 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2953 #define ADV_CARRIER_BUFSIZE \
2954 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2957 * ASC_SCSI_REQ_Q 'a_flag' definitions
2959 * The Adv Library should limit use to the lower nibble (4 bits) of
2960 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2962 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2963 #define ADV_SCSIQ_DONE 0x02 /* request done */
2964 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2966 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2967 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2968 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2971 * Adapter temporary configuration structure
2973 * This structure can be discarded after initialization. Don't add
2974 * fields here needed after initialization.
2976 * Field naming convention:
2978 * *_enable indicates the field enables or disables a feature. The
2979 * value of the field is never reset.
2981 typedef struct adv_dvc_cfg {
2982 ushort disc_enable; /* enable disconnection */
2983 uchar chip_version; /* chip version */
2984 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2985 ushort lib_version; /* Adv Library version number */
2986 ushort control_flag; /* Microcode Control Flag */
2987 ushort mcode_date; /* Microcode date */
2988 ushort mcode_version; /* Microcode version */
2989 ushort pci_slot_info; /* high byte device/function number */
2990 /* bits 7-3 device num., bits 2-0 function num. */
2991 /* low byte bus num. */
2992 ushort serial1; /* EEPROM serial number word 1 */
2993 ushort serial2; /* EEPROM serial number word 2 */
2994 ushort serial3; /* EEPROM serial number word 3 */
2995 struct device *dev; /* pointer to the pci dev structure for this board */
2999 struct adv_scsi_req_q;
3001 typedef void (* ADV_ISR_CALLBACK)
3002 (struct adv_dvc_var *, struct adv_scsi_req_q *);
3004 typedef void (* ADV_ASYNC_CALLBACK)
3005 (struct adv_dvc_var *, uchar);
3008 * Adapter operation variable structure.
3010 * One structure is required per host adapter.
3012 * Field naming convention:
3014 * *_able indicates both whether a feature should be enabled or disabled
3015 * and whether a device isi capable of the feature. At initialization
3016 * this field may be set, but later if a device is found to be incapable
3017 * of the feature, the field is cleared.
3019 typedef struct adv_dvc_var {
3020 AdvPortAddr iop_base; /* I/O port address */
3021 ushort err_code; /* fatal error code */
3022 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
3023 ADV_ISR_CALLBACK isr_callback;
3024 ADV_ASYNC_CALLBACK async_callback;
3025 ushort wdtr_able; /* try WDTR for a device */
3026 ushort sdtr_able; /* try SDTR for a device */
3027 ushort ultra_able; /* try SDTR Ultra speed for a device */
3028 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
3029 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
3030 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
3031 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
3032 ushort tagqng_able; /* try tagged queuing with a device */
3033 ushort ppr_able; /* PPR message capable per TID bitmask. */
3034 uchar max_dvc_qng; /* maximum number of tagged commands per device */
3035 ushort start_motor; /* start motor command allowed */
3036 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
3037 uchar chip_no; /* should be assigned by caller */
3038 uchar max_host_qng; /* maximum number of Q'ed command allowed */
3039 uchar irq_no; /* IRQ number */
3040 ushort no_scam; /* scam_tolerant of EEPROM */
3041 struct asc_board *drv_ptr; /* driver pointer to private structure */
3042 uchar chip_scsi_id; /* chip SCSI target ID */
3044 uchar bist_err_code;
3045 ADV_CARR_T *carrier_buf;
3046 ADV_CARR_T *carr_freelist; /* Carrier free list. */
3047 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
3048 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
3049 ushort carr_pending_cnt; /* Count of pending carriers. */
3051 * Note: The following fields will not be used after initialization. The
3052 * driver may discard the buffer after initialization is done.
3054 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3057 #define NO_OF_SG_PER_BLOCK 15
3059 typedef struct asc_sg_block {
3063 uchar sg_cnt; /* Valid entries in block. */
3064 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3066 ADV_PADDR sg_addr; /* SG element address. */
3067 ADV_DCNT sg_count; /* SG element count. */
3068 } sg_list[NO_OF_SG_PER_BLOCK];
3072 * ADV_SCSI_REQ_Q - microcode request structure
3074 * All fields in this structure up to byte 60 are used by the microcode.
3075 * The microcode makes assumptions about the size and ordering of fields
3076 * in this structure. Do not change the structure definition here without
3077 * coordinating the change with the microcode.
3079 * All fields accessed by microcode must be maintained in little_endian
3082 typedef struct adv_scsi_req_q {
3083 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3085 uchar target_id; /* Device target identifier. */
3086 uchar target_lun; /* Device target logical unit number. */
3087 ADV_PADDR data_addr; /* Data buffer physical address. */
3088 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3089 ADV_PADDR sense_addr;
3093 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3095 uchar done_status; /* Completion status. */
3096 uchar scsi_status; /* SCSI status byte. */
3097 uchar host_status; /* Ucode host status. */
3098 uchar sg_working_ix;
3099 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3100 ADV_PADDR sg_real_addr; /* SG list physical address. */
3101 ADV_PADDR scsiq_rptr;
3102 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3103 ADV_VADDR scsiq_ptr;
3106 * End of microcode structure - 60 bytes. The rest of the structure
3107 * is used by the Adv Library and ignored by the microcode.
3110 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3111 char *vdata_addr; /* Data buffer virtual address. */
3113 uchar pad[2]; /* Pad out to a word boundary. */
3117 * Microcode idle loop commands
3119 #define IDLE_CMD_COMPLETED 0
3120 #define IDLE_CMD_STOP_CHIP 0x0001
3121 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3122 #define IDLE_CMD_SEND_INT 0x0004
3123 #define IDLE_CMD_ABORT 0x0008
3124 #define IDLE_CMD_DEVICE_RESET 0x0010
3125 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3126 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3127 #define IDLE_CMD_SCSIREQ 0x0080
3129 #define IDLE_CMD_STATUS_SUCCESS 0x0001
3130 #define IDLE_CMD_STATUS_FAILURE 0x0002
3133 * AdvSendIdleCmd() flag definitions.
3135 #define ADV_NOWAIT 0x01
3138 * Wait loop time out values.
3140 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3141 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3142 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3143 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3144 #define SCSI_MAX_RETRY 10 /* retry count */
3146 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3147 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3148 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3149 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3152 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3155 * Device drivers must define the following functions.
3157 STATIC inline ulong DvcEnterCritical(void);
3158 STATIC inline void DvcLeaveCritical(ulong);
3159 STATIC void DvcSleepMilliSecond(ADV_DCNT);
3160 STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3161 STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3162 STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3163 uchar *, ASC_SDCNT *, int);
3164 STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3167 * Adv Library functions available to drivers.
3169 STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3170 STATIC int AdvISR(ADV_DVC_VAR *);
3171 STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
3172 STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3173 STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3174 STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3175 STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
3176 STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3179 * Internal Adv Library functions.
3181 STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3182 STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3183 STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3184 STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3185 STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3186 STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3187 STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3188 STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3189 STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3190 STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3191 STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3192 STATIC void AdvWaitEEPCmd(AdvPortAddr);
3193 STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
3196 * PCI Bus Definitions
3198 #define AscPCICmdRegBits_BusMastering 0x0007
3199 #define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3201 /* Read byte from a register. */
3202 #define AdvReadByteRegister(iop_base, reg_off) \
3203 (ADV_MEM_READB((iop_base) + (reg_off)))
3205 /* Write byte to a register. */
3206 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
3207 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3209 /* Read word (2 bytes) from a register. */
3210 #define AdvReadWordRegister(iop_base, reg_off) \
3211 (ADV_MEM_READW((iop_base) + (reg_off)))
3213 /* Write word (2 bytes) to a register. */
3214 #define AdvWriteWordRegister(iop_base, reg_off, word) \
3215 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3217 /* Write dword (4 bytes) to a register. */
3218 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3219 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3221 /* Read byte from LRAM. */
3222 #define AdvReadByteLram(iop_base, addr, byte) \
3224 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3225 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3228 /* Write byte to LRAM. */
3229 #define AdvWriteByteLram(iop_base, addr, byte) \
3230 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3231 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3233 /* Read word (2 bytes) from LRAM. */
3234 #define AdvReadWordLram(iop_base, addr, word) \
3236 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3237 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3240 /* Write word (2 bytes) to LRAM. */
3241 #define AdvWriteWordLram(iop_base, addr, word) \
3242 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3243 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3245 /* Write little-endian double word (4 bytes) to LRAM */
3246 /* Because of unspecified C language ordering don't use auto-increment. */
3247 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3248 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3249 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3250 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3251 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3252 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3253 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3255 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
3256 #define AdvReadWordAutoIncLram(iop_base) \
3257 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3259 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
3260 #define AdvWriteWordAutoIncLram(iop_base, word) \
3261 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3265 * Define macro to check for Condor signature.
3267 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3268 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3270 #define AdvFindSignature(iop_base) \
3271 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3272 ADV_CHIP_ID_BYTE) && \
3273 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3274 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3277 * Define macro to Return the version number of the chip at 'iop_base'.
3279 * The second parameter 'bus_type' is currently unused.
3281 #define AdvGetChipVersion(iop_base, bus_type) \
3282 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3285 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3286 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3288 * If the request has not yet been sent to the device it will simply be
3289 * aborted from RISC memory. If the request is disconnected it will be
3290 * aborted on reselection by sending an Abort Message to the target ID.
3293 * ADV_TRUE(1) - Queue was successfully aborted.
3294 * ADV_FALSE(0) - Queue was not found on the active queue list.
3296 #define AdvAbortQueue(asc_dvc, scsiq) \
3297 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3301 * Send a Bus Device Reset Message to the specified target ID.
3303 * All outstanding commands will be purged if sending the
3304 * Bus Device Reset Message is successful.
3307 * ADV_TRUE(1) - All requests on the target are purged.
3308 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3311 #define AdvResetDevice(asc_dvc, target_id) \
3312 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3313 (ADV_DCNT) (target_id))
3316 * SCSI Wide Type definition.
3318 #define ADV_SCSI_BIT_ID_TYPE ushort
3321 * AdvInitScsiTarget() 'cntl_flag' options.
3323 #define ADV_SCAN_LUN 0x01
3324 #define ADV_CAPINFO_NOLUN 0x02
3327 * Convert target id to target id bit mask.
3329 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3332 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3335 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
3336 #define QD_NO_ERROR 0x01
3337 #define QD_ABORTED_BY_HOST 0x02
3338 #define QD_WITH_ERROR 0x04
3340 #define QHSTA_NO_ERROR 0x00
3341 #define QHSTA_M_SEL_TIMEOUT 0x11
3342 #define QHSTA_M_DATA_OVER_RUN 0x12
3343 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3344 #define QHSTA_M_QUEUE_ABORTED 0x15
3345 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3346 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3347 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3348 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3349 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3350 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3351 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3352 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3353 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3354 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3355 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3356 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3357 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3358 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3359 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3360 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3361 #define QHSTA_M_WTM_TIMEOUT 0x41
3362 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3363 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3364 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3365 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3366 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3367 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3371 * Default EEPROM Configuration structure defined in a_init.c.
3373 extern ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3374 extern ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3375 extern ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3378 * DvcGetPhyAddr() flag arguments
3380 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3381 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3382 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3383 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3384 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3385 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3387 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
3388 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3389 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3390 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3393 * Total contiguous memory needed for driver SG blocks.
3395 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3396 * number of scatter-gather elements the driver supports in a
3400 #define ADV_SG_LIST_MAX_BYTE_SIZE \
3401 (sizeof(ADV_SG_BLOCK) * \
3402 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3405 * Inquiry data structure and bitfield macros
3407 * Using bitfields to access the subchar data isn't portable across
3408 * endianness, so instead mask and shift. Only quantities of more
3409 * than 1 bit are shifted, since the others are just tested for true
3413 #define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3414 #define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3415 #define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3416 #define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3417 #define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3418 #define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3419 #define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3420 #define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3421 #define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3422 #define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3423 #define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3424 #define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3425 #define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3426 #define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3427 #define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3428 #define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3429 #define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3430 #define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3431 #define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3432 #define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3435 uchar periph; /* peripheral device type [0:4] */
3436 /* peripheral qualifier [5:7] */
3437 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3438 /* RMB - removable medium bit [7] */
3439 uchar ver; /* ANSI approved version [0:2] */
3440 /* ECMA version [3:5] */
3441 /* ISO version [6:7] */
3442 uchar byte3; /* response data format [0:3] */
3447 /* reserved [4:5] */
3448 /* terminate I/O process bit (see 5.6.22) [6] */
3449 /* asynch. event notification (processor) [7] */
3450 uchar add_len; /* additional length */
3451 uchar res1; /* reserved */
3452 uchar res2; /* reserved */
3453 uchar flags; /* soft reset implemented [0] */
3454 /* command queuing [1] */
3456 /* linked command for this logical unit [3] */
3457 /* synchronous data transfer [4] */
3458 /* wide bus 16 bit data transfer [5] */
3459 /* wide bus 32 bit data transfer [6] */
3460 /* relative addressing mode [7] */
3461 uchar vendor_id[8]; /* vendor identification */
3462 uchar product_id[16]; /* product identification */
3463 uchar product_rev_level[4]; /* product revision level */
3464 uchar vendor_specific[20]; /* vendor specific */
3465 uchar info; /* information unit supported [0] */
3466 /* quick arbitrate supported [1] */
3467 /* clocking field [2:3] */
3468 /* reserved [4:7] */
3469 uchar res3; /* reserved */
3470 } ADV_SCSI_INQUIRY; /* 58 bytes */
3474 * --- Driver Constants and Macros
3477 #define ASC_NUM_BOARD_SUPPORTED 16
3478 #define ASC_NUM_IOPORT_PROBE 4
3479 #define ASC_NUM_BUS 4
3481 /* Reference Scsi_Host hostdata */
3482 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3484 /* asc_board_t flags */
3485 #define ASC_HOST_IN_RESET 0x01
3486 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3487 #define ASC_SELECT_QUEUE_DEPTHS 0x08
3489 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3490 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3492 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3494 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
3496 #ifdef CONFIG_PROC_FS
3497 /* /proc/scsi/advansys/[0...] related definitions */
3498 #define ASC_PRTBUF_SIZE 2048
3499 #define ASC_PRTLINE_SIZE 160
3501 #define ASC_PRT_NEXT() \
3505 if (leftlen == 0) { \
3510 #endif /* CONFIG_PROC_FS */
3512 /* Asc Library return codes */
3515 #define ASC_NOERROR 1
3517 #define ASC_ERROR (-1)
3519 /* struct scsi_cmnd function return codes */
3520 #define STATUS_BYTE(byte) (byte)
3521 #define MSG_BYTE(byte) ((byte) << 8)
3522 #define HOST_BYTE(byte) ((byte) << 16)
3523 #define DRIVER_BYTE(byte) ((byte) << 24)
3526 * The following definitions and macros are OS independent interfaces to
3527 * the queue functions:
3528 * REQ - SCSI request structure
3529 * REQP - pointer to SCSI request structure
3530 * REQPTID(reqp) - reqp's target id
3531 * REQPNEXT(reqp) - reqp's next pointer
3532 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3533 * REQPTIME(reqp) - reqp's time stamp value
3534 * REQTIMESTAMP() - system time stamp value
3536 typedef struct scsi_cmnd REQ, *REQP;
3537 #define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3538 #define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3539 #define REQPTID(reqp) ((reqp)->device->id)
3540 #define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3541 #define REQTIMESTAMP() (jiffies)
3543 #define REQTIMESTAT(function, ascq, reqp, tid) \
3546 * If the request time stamp is less than the system time stamp, then \
3547 * maybe the system time stamp wrapped. Set the request time to zero.\
3549 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3550 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3552 /* Indicate an error occurred with the assertion. */ \
3553 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3554 REQPTIME(reqp) = 0; \
3556 /* Handle first minimum time case without external initialization. */ \
3557 if (((ascq)->q_tot_cnt[tid] == 1) || \
3558 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3559 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3560 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3561 (function), (tid), (ascq)->q_min_tim[tid]); \
3563 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3564 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3565 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3566 (function), tid, (ascq)->q_max_tim[tid]); \
3568 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3569 /* Reset the time stamp field. */ \
3570 REQPTIME(reqp) = 0; \
3573 /* asc_enqueue() flags */
3577 /* asc_dequeue_list() argument */
3578 #define ASC_TID_ALL (-1)
3580 /* Return non-zero, if the queue is empty. */
3581 #define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3583 #define PCI_MAX_SLOT 0x1F
3584 #define PCI_MAX_BUS 0xFF
3585 #define PCI_IOADDRESS_MASK 0xFFFE
3586 #define ASC_PCI_VENDORID 0x10CD
3587 #define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3588 #define ASC_PCI_DEVICE_ID_1100 0x1100
3589 #define ASC_PCI_DEVICE_ID_1200 0x1200
3590 #define ASC_PCI_DEVICE_ID_1300 0x1300
3591 #define ASC_PCI_DEVICE_ID_2300 0x2300 /* ASC-3550 */
3592 #define ASC_PCI_DEVICE_ID_2500 0x2500 /* ASC-38C0800 */
3593 #define ASC_PCI_DEVICE_ID_2700 0x2700 /* ASC-38C1600 */
3595 #ifndef ADVANSYS_STATS
3596 #define ASC_STATS(shp, counter)
3597 #define ASC_STATS_ADD(shp, counter, count)
3598 #else /* ADVANSYS_STATS */
3599 #define ASC_STATS(shp, counter) \
3600 (ASC_BOARDP(shp)->asc_stats.counter++)
3602 #define ASC_STATS_ADD(shp, counter, count) \
3603 (ASC_BOARDP(shp)->asc_stats.counter += (count))
3604 #endif /* ADVANSYS_STATS */
3606 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3608 /* If the result wraps when calculating tenths, return 0. */
3609 #define ASC_TENTHS(num, den) \
3610 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3611 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3614 * Display a message to the console.
3616 #define ASC_PRINT(s) \
3618 printk("advansys: "); \
3622 #define ASC_PRINT1(s, a1) \
3624 printk("advansys: "); \
3625 printk((s), (a1)); \
3628 #define ASC_PRINT2(s, a1, a2) \
3630 printk("advansys: "); \
3631 printk((s), (a1), (a2)); \
3634 #define ASC_PRINT3(s, a1, a2, a3) \
3636 printk("advansys: "); \
3637 printk((s), (a1), (a2), (a3)); \
3640 #define ASC_PRINT4(s, a1, a2, a3, a4) \
3642 printk("advansys: "); \
3643 printk((s), (a1), (a2), (a3), (a4)); \
3647 #ifndef ADVANSYS_DEBUG
3649 #define ASC_DBG(lvl, s)
3650 #define ASC_DBG1(lvl, s, a1)
3651 #define ASC_DBG2(lvl, s, a1, a2)
3652 #define ASC_DBG3(lvl, s, a1, a2, a3)
3653 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3654 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3655 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3656 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3657 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3658 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3659 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3660 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
3661 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
3662 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
3663 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3665 #else /* ADVANSYS_DEBUG */
3668 * Debugging Message Levels:
3670 * 1: High-Level Tracing
3671 * 2-N: Verbose Tracing
3674 #define ASC_DBG(lvl, s) \
3676 if (asc_dbglvl >= (lvl)) { \
3681 #define ASC_DBG1(lvl, s, a1) \
3683 if (asc_dbglvl >= (lvl)) { \
3684 printk((s), (a1)); \
3688 #define ASC_DBG2(lvl, s, a1, a2) \
3690 if (asc_dbglvl >= (lvl)) { \
3691 printk((s), (a1), (a2)); \
3695 #define ASC_DBG3(lvl, s, a1, a2, a3) \
3697 if (asc_dbglvl >= (lvl)) { \
3698 printk((s), (a1), (a2), (a3)); \
3702 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3704 if (asc_dbglvl >= (lvl)) { \
3705 printk((s), (a1), (a2), (a3), (a4)); \
3709 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3711 if (asc_dbglvl >= (lvl)) { \
3712 asc_prt_scsi_host(s); \
3716 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3718 if (asc_dbglvl >= (lvl)) { \
3719 asc_prt_scsi_cmnd(s); \
3723 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3725 if (asc_dbglvl >= (lvl)) { \
3726 asc_prt_asc_scsi_q(scsiqp); \
3730 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3732 if (asc_dbglvl >= (lvl)) { \
3733 asc_prt_asc_qdone_info(qdone); \
3737 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3739 if (asc_dbglvl >= (lvl)) { \
3740 asc_prt_adv_scsi_req_q(scsiqp); \
3744 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3746 if (asc_dbglvl >= (lvl)) { \
3747 asc_prt_hex((name), (start), (length)); \
3751 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3752 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3754 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3755 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3757 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3758 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3759 #endif /* ADVANSYS_DEBUG */
3761 #ifndef ADVANSYS_ASSERT
3762 #define ASC_ASSERT(a)
3763 #else /* ADVANSYS_ASSERT */
3765 #define ASC_ASSERT(a) \
3768 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3769 __FILE__, __LINE__); \
3773 #endif /* ADVANSYS_ASSERT */
3777 * --- Driver Structures
3780 #ifdef ADVANSYS_STATS
3782 /* Per board statistics structure */
3784 /* Driver Entrypoint Statistics */
3785 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3786 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3787 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3788 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3789 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3790 ADV_DCNT done; /* # calls to request's scsi_done function */
3791 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3792 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3793 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3794 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3795 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3796 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3797 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3798 ADV_DCNT exe_unknown; /* # unknown returns. */
3799 /* Data Transfer Statistics */
3800 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3801 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3802 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3803 ADV_DCNT sg_elem; /* # scatter-gather elements */
3804 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3806 #endif /* ADVANSYS_STATS */
3809 * Request queuing structure
3811 typedef struct asc_queue {
3812 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3813 REQP q_first[ADV_MAX_TID+1]; /* first queued request */
3814 REQP q_last[ADV_MAX_TID+1]; /* last queued request */
3815 #ifdef ADVANSYS_STATS
3816 short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
3817 short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
3818 ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
3819 ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
3820 ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
3821 ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
3822 #endif /* ADVANSYS_STATS */
3826 * Adv Library Request Structures
3828 * The following two structures are used to process Wide Board requests.
3830 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3831 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3832 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3833 * Mid-Level SCSI request structure.
3835 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3836 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3837 * up to 255 scatter-gather elements may be used per request or
3840 * Both structures must be 32 byte aligned.
3842 typedef struct adv_sgblk {
3843 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3844 uchar align[32]; /* Sgblock structure padding. */
3845 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3848 typedef struct adv_req {
3849 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3850 uchar align[32]; /* Request structure padding. */
3851 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3852 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3853 struct adv_req *next_reqp; /* Next Request Structure. */
3857 * Structure allocated for each board.
3859 * This structure is allocated by scsi_register() at the end
3860 * of the 'Scsi_Host' structure starting at the 'hostdata'
3861 * field. It is guaranteed to be allocated from DMA-able memory.
3863 typedef struct asc_board {
3864 int id; /* Board Id */
3865 uint flags; /* Board flags */
3867 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3868 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3871 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3872 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3874 ushort asc_n_io_port; /* Number I/O ports. */
3875 asc_queue_t active; /* Active command queue */
3876 asc_queue_t waiting; /* Waiting command queue */
3877 asc_queue_t done; /* Done command queue */
3878 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3879 struct scsi_device *device[ADV_MAX_TID+1]; /* Mid-Level Scsi Device */
3880 ushort reqcnt[ADV_MAX_TID+1]; /* Starvation request count */
3881 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3882 ushort queue_full_cnt[ADV_MAX_TID+1]; /* Queue full count */
3884 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3885 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3886 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3887 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3889 ulong last_reset; /* Saved last reset time */
3890 spinlock_t lock; /* Board spinlock */
3891 #ifdef CONFIG_PROC_FS
3892 /* /proc/scsi/advansys/[0...] */
3893 char *prtbuf; /* /proc print buffer */
3894 #endif /* CONFIG_PROC_FS */
3895 #ifdef ADVANSYS_STATS
3896 struct asc_stats asc_stats; /* Board statistics */
3897 #endif /* ADVANSYS_STATS */
3899 * The following fields are used only for Narrow Boards.
3901 /* The following three structures must be in DMA-able memory. */
3902 ASC_SCSI_REQ_Q scsireqq;
3903 ASC_CAP_INFO cap_info;
3904 ASC_SCSI_INQUIRY inquiry;
3905 uchar sdtr_data[ASC_MAX_TID+1]; /* SDTR information */
3907 * The following fields are used only for Wide Boards.
3909 void *ioremap_addr; /* I/O Memory remap address. */
3910 ushort ioport; /* I/O Port address. */
3911 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3912 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3913 adv_req_t *adv_reqp; /* Request structures. */
3914 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3915 ushort bios_signature; /* BIOS Signature. */
3916 ushort bios_version; /* BIOS Version. */
3917 ushort bios_codeseg; /* BIOS Code Segment. */
3918 ushort bios_codelen; /* BIOS Code Segment Length. */
3922 * PCI configuration structures
3924 typedef struct _PCI_DATA_
3933 typedef struct _PCI_DEVICE_
3948 typedef struct _PCI_CONFIG_SPACE_
3960 ADV_PADDR baseAddress[6];
3962 ADV_PADDR optionRomAddr;
3963 ushort reserved2[4];
3975 /* Note: All driver global data should be initialized. */
3977 /* Number of boards detected in system. */
3978 STATIC int asc_board_count = 0;
3979 STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
3981 /* Overrun buffer used by all narrow boards. */
3982 STATIC uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3985 * Global structures required to issue a command.
3987 STATIC ASC_SCSI_Q asc_scsi_q = { { 0 } };
3988 STATIC ASC_SG_HEAD asc_sg_head = { 0 };
3990 /* List of supported bus types. */
3991 STATIC ushort asc_bus[ASC_NUM_BUS] __initdata = {
3999 * Used with the LILO 'advansys' option to eliminate or
4000 * limit I/O port probing at boot time, cf. advansys_setup().
4002 STATIC int asc_iopflag = ASC_FALSE;
4003 STATIC int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
4005 #ifdef ADVANSYS_DEBUG
4007 asc_bus_name[ASC_NUM_BUS] = {
4014 STATIC int asc_dbglvl = 3;
4015 #endif /* ADVANSYS_DEBUG */
4017 /* Declaration for Asc Library internal data referenced by driver. */
4018 STATIC PortAddr _asc_def_iop_base[];
4022 * --- Driver Function Prototypes
4024 * advansys.h contains function prototypes for functions global to Linux.
4027 STATIC irqreturn_t advansys_interrupt(int, void *, struct pt_regs *);
4028 STATIC int advansys_slave_configure(struct scsi_device *);
4029 STATIC void asc_scsi_done_list(struct scsi_cmnd *);
4030 STATIC int asc_execute_scsi_cmnd(struct scsi_cmnd *);
4031 STATIC int asc_build_req(asc_board_t *, struct scsi_cmnd *);
4032 STATIC int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
4033 STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
4034 STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
4035 STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
4036 STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
4037 STATIC void asc_enqueue(asc_queue_t *, REQP, int);
4038 STATIC REQP asc_dequeue(asc_queue_t *, int);
4039 STATIC REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
4040 STATIC int asc_rmqueue(asc_queue_t *, REQP);
4041 STATIC void asc_execute_queue(asc_queue_t *);
4042 #ifdef CONFIG_PROC_FS
4043 STATIC int asc_proc_copy(off_t, off_t, char *, int , char *, int);
4044 STATIC int asc_prt_board_devices(struct Scsi_Host *, char *, int);
4045 STATIC int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
4046 STATIC int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
4047 STATIC int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
4048 STATIC int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
4049 STATIC int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
4050 STATIC int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
4051 STATIC int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
4052 STATIC int asc_prt_line(char *, int, char *fmt, ...);
4053 #endif /* CONFIG_PROC_FS */
4055 /* Declaration for Asc Library internal functions referenced by driver. */
4056 STATIC int AscFindSignature(PortAddr);
4057 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
4059 /* Statistics function prototypes. */
4060 #ifdef ADVANSYS_STATS
4061 #ifdef CONFIG_PROC_FS
4062 STATIC int asc_prt_board_stats(struct Scsi_Host *, char *, int);
4063 STATIC int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
4064 #endif /* CONFIG_PROC_FS */
4065 #endif /* ADVANSYS_STATS */
4067 /* Debug function prototypes. */
4068 #ifdef ADVANSYS_DEBUG
4069 STATIC void asc_prt_scsi_host(struct Scsi_Host *);
4070 STATIC void asc_prt_scsi_cmnd(struct scsi_cmnd *);
4071 STATIC void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
4072 STATIC void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4073 STATIC void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4074 STATIC void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4075 STATIC void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4076 STATIC void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4077 STATIC void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4078 STATIC void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4079 STATIC void asc_prt_hex(char *f, uchar *, int);
4080 #endif /* ADVANSYS_DEBUG */
4084 * --- Linux 'Scsi_Host_Template' and advansys_setup() Functions
4087 #ifdef CONFIG_PROC_FS
4089 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4091 * *buffer: I/O buffer
4092 * **start: if inout == FALSE pointer into buffer where user read should start
4093 * offset: current offset into a /proc/scsi/advansys/[0...] file
4094 * length: length of buffer
4095 * hostno: Scsi_Host host_no
4096 * inout: TRUE - user is writing; FALSE - user is reading
4098 * Return the number of bytes read from or written to a
4099 * /proc/scsi/advansys/[0...] file.
4101 * Note: This function uses the per board buffer 'prtbuf' which is
4102 * allocated when the board is initialized in advansys_detect(). The
4103 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4104 * used to write to the buffer. The way asc_proc_copy() is written
4105 * if 'prtbuf' is too small it will not be overwritten. Instead the
4106 * user just won't get all the available statistics.
4109 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4110 off_t offset, int length, int inout)
4112 struct Scsi_Host *shp;
4113 asc_board_t *boardp;
4122 #ifdef ADVANSYS_STATS
4124 #endif /* ADVANSYS_STATS */
4126 ASC_DBG(1, "advansys_proc_info: begin\n");
4129 * User write not supported.
4131 if (inout == TRUE) {
4136 * User read of /proc/scsi/advansys/[0...] file.
4139 /* Find the specified board. */
4140 for (i = 0; i < asc_board_count; i++) {
4141 if (asc_host[i]->host_no == shost->host_no) {
4145 if (i == asc_board_count) {
4150 boardp = ASC_BOARDP(shp);
4152 /* Copy read data starting at the beginning of the buffer. */
4160 * Get board configuration information.
4162 * advansys_info() returns the board string from its own static buffer.
4164 cp = (char *) advansys_info(shp);
4167 /* Copy board information. */
4168 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4172 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4179 * Display Wide Board BIOS Information.
4181 if (ASC_WIDE_BOARD(boardp)) {
4182 cp = boardp->prtbuf;
4183 cplen = asc_prt_adv_bios(shp, cp, ASC_PRTBUF_SIZE);
4184 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4185 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4189 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4197 * Display driver information for each device attached to the board.
4199 cp = boardp->prtbuf;
4200 cplen = asc_prt_board_devices(shp, cp, ASC_PRTBUF_SIZE);
4201 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4202 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4206 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4213 * Display EEPROM configuration for the board.
4215 cp = boardp->prtbuf;
4216 if (ASC_NARROW_BOARD(boardp)) {
4217 cplen = asc_prt_asc_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4219 cplen = asc_prt_adv_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4221 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4222 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4226 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4233 * Display driver configuration and information for the board.
4235 cp = boardp->prtbuf;
4236 cplen = asc_prt_driver_conf(shp, cp, ASC_PRTBUF_SIZE);
4237 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4238 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4242 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4248 #ifdef ADVANSYS_STATS
4250 * Display driver statistics for the board.
4252 cp = boardp->prtbuf;
4253 cplen = asc_prt_board_stats(shp, cp, ASC_PRTBUF_SIZE);
4254 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4255 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4259 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4266 * Display driver statistics for each target.
4268 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4269 cp = boardp->prtbuf;
4270 cplen = asc_prt_target_stats(shp, tgt_id, cp, ASC_PRTBUF_SIZE);
4271 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4272 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4276 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4282 #endif /* ADVANSYS_STATS */
4285 * Display Asc Library dynamic configuration information
4288 cp = boardp->prtbuf;
4289 if (ASC_NARROW_BOARD(boardp)) {
4290 cplen = asc_prt_asc_board_info(shp, cp, ASC_PRTBUF_SIZE);
4292 cplen = asc_prt_adv_board_info(shp, cp, ASC_PRTBUF_SIZE);
4294 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4295 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4299 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4305 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4309 #endif /* CONFIG_PROC_FS */
4314 * Detect function for AdvanSys adapters.
4316 * Argument is a pointer to the host driver's scsi_hosts entry.
4318 * Return number of adapters found.
4320 * Note: Because this function is called during system initialization
4321 * it must not call SCSI mid-level functions including scsi_malloc()
4325 advansys_detect(struct scsi_host_template *tpnt)
4327 static int detect_called = ASC_FALSE;
4330 struct Scsi_Host *shp = NULL;
4331 asc_board_t *boardp = NULL;
4332 ASC_DVC_VAR *asc_dvc_varp = NULL;
4333 ADV_DVC_VAR *adv_dvc_varp = NULL;
4334 adv_sgblk_t *sgp = NULL;
4336 int share_irq = FALSE;
4339 int pci_init_search = 0;
4340 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
4341 int pci_card_cnt_max = 0;
4342 int pci_card_cnt = 0;
4343 struct device *dev = NULL;
4344 struct pci_dev *pci_devp = NULL;
4345 int pci_device_id_cnt = 0;
4346 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
4347 ASC_PCI_DEVICE_ID_1100,
4348 ASC_PCI_DEVICE_ID_1200,
4349 ASC_PCI_DEVICE_ID_1300,
4350 ASC_PCI_DEVICE_ID_2300,
4351 ASC_PCI_DEVICE_ID_2500,
4352 ASC_PCI_DEVICE_ID_2700
4354 ADV_PADDR pci_memory_address;
4355 #endif /* CONFIG_PCI */
4356 int warn_code, err_code;
4359 if (detect_called == ASC_FALSE) {
4360 detect_called = ASC_TRUE;
4362 printk("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
4366 ASC_DBG(1, "advansys_detect: begin\n");
4368 asc_board_count = 0;
4371 * If I/O port probing has been modified, then verify and
4372 * clean-up the 'asc_ioport' list.
4374 if (asc_iopflag == ASC_TRUE) {
4375 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4376 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
4377 ioport, asc_ioport[ioport]);
4378 if (asc_ioport[ioport] != 0) {
4379 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX; iop++) {
4380 if (_asc_def_iop_base[iop] == asc_ioport[ioport]) {
4384 if (iop == ASC_IOADR_TABLE_MAX_IX) {
4386 "AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
4387 asc_ioport[ioport]);
4388 asc_ioport[ioport] = 0;
4395 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
4397 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
4398 bus, asc_bus_name[bus]);
4401 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
4403 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
4406 switch (asc_bus[bus]) {
4410 if (asc_iopflag == ASC_FALSE) {
4411 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4414 * ISA and VL I/O port scanning has either been
4415 * eliminated or limited to selected ports on
4416 * the LILO command line, /etc/lilo.conf, or
4417 * by setting variables when the module was loaded.
4419 ASC_DBG(1, "advansys_detect: I/O port scanning modified\n");
4422 for (; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4423 if ((iop = asc_ioport[ioport]) != 0) {
4429 "advansys_detect: probing I/O port 0x%x...\n",
4431 if (check_region(iop, ASC_IOADR_GAP) != 0) {
4433 "AdvanSys SCSI: specified I/O Port 0x%X is busy\n", iop);
4434 /* Don't try this I/O port twice. */
4435 asc_ioport[ioport] = 0;
4436 goto ioport_try_again;
4437 } else if (AscFindSignature(iop) == ASC_FALSE) {
4439 "AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n", iop);
4440 /* Don't try this I/O port twice. */
4441 asc_ioport[ioport] = 0;
4442 goto ioport_try_again;
4445 * If this isn't an ISA board, then it must be
4446 * a VL board. If currently looking an ISA
4447 * board is being looked for then try for
4448 * another ISA board in 'asc_ioport'.
4450 if (asc_bus[bus] == ASC_IS_ISA &&
4451 (AscGetChipVersion(iop, ASC_IS_ISA) &
4452 ASC_CHIP_VER_ISA_BIT) == 0) {
4454 * Don't clear 'asc_ioport[ioport]'. Try
4455 * this board again for VL. Increment
4456 * 'ioport' past this board.
4459 goto ioport_try_again;
4463 * This board appears good, don't try the I/O port
4464 * again by clearing its value. Increment 'ioport'
4465 * for the next iteration.
4467 asc_ioport[ioport++] = 0;
4470 #endif /* CONFIG_ISA */
4475 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4476 #endif /* CONFIG_ISA */
4481 if (pci_init_search == 0) {
4484 pci_init_search = 1;
4486 /* Find all PCI cards. */
4487 while (pci_device_id_cnt < ASC_PCI_DEVICE_ID_CNT) {
4488 if ((pci_devp = pci_find_device(ASC_PCI_VENDORID,
4489 pci_device_id[pci_device_id_cnt], pci_devp)) ==
4491 pci_device_id_cnt++;
4493 if (pci_enable_device(pci_devp) == 0) {
4494 pci_devicep[pci_card_cnt_max++] = pci_devp;
4500 * Sort PCI cards in ascending order by PCI Bus, Slot,
4501 * and Device Number.
4503 for (i = 0; i < pci_card_cnt_max - 1; i++)
4505 for (j = i + 1; j < pci_card_cnt_max; j++) {
4506 if ((pci_devicep[j]->bus->number <
4507 pci_devicep[i]->bus->number) ||
4508 ((pci_devicep[j]->bus->number ==
4509 pci_devicep[i]->bus->number) &&
4510 (pci_devicep[j]->devfn <
4511 pci_devicep[i]->devfn))) {
4512 pci_devp = pci_devicep[i];
4513 pci_devicep[i] = pci_devicep[j];
4514 pci_devicep[j] = pci_devp;
4524 if (pci_card_cnt == pci_card_cnt_max) {
4527 pci_devp = pci_devicep[pci_card_cnt];
4530 "advansys_detect: devfn %d, bus number %d\n",
4531 pci_devp->devfn, pci_devp->bus->number);
4532 iop = pci_resource_start(pci_devp, 0);
4534 "advansys_detect: vendorID %X, deviceID %X\n",
4535 pci_devp->vendor, pci_devp->device);
4536 ASC_DBG2(2, "advansys_detect: iop %X, irqLine %d\n",
4537 iop, pci_devp->irq);
4540 dev = &pci_devp->dev;
4542 #endif /* CONFIG_PCI */
4546 ASC_PRINT1("advansys_detect: unknown bus type: %d\n",
4550 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
4553 * Adapter not found, try next bus type.
4562 * Register the adapter, get its configuration, and
4565 ASC_DBG(2, "advansys_detect: scsi_register()\n");
4566 shp = scsi_register(tpnt, sizeof(asc_board_t));
4572 scsi_set_device(shp, dev);
4574 /* Save a pointer to the Scsi_Host of each board found. */
4575 asc_host[asc_board_count++] = shp;
4577 /* Initialize private per board data */
4578 boardp = ASC_BOARDP(shp);
4579 memset(boardp, 0, sizeof(asc_board_t));
4580 boardp->id = asc_board_count - 1;
4582 /* Initialize spinlock. */
4583 boardp->lock = SPIN_LOCK_UNLOCKED;
4586 * Handle both narrow and wide boards.
4588 * If a Wide board was detected, set the board structure
4589 * wide board flag. Set-up the board structure based on
4593 if (asc_bus[bus] == ASC_IS_PCI &&
4594 (pci_devp->device == ASC_PCI_DEVICE_ID_2300 ||
4595 pci_devp->device == ASC_PCI_DEVICE_ID_2500 ||
4596 pci_devp->device == ASC_PCI_DEVICE_ID_2700))
4598 boardp->flags |= ASC_IS_WIDE_BOARD;
4600 #endif /* CONFIG_PCI */
4602 if (ASC_NARROW_BOARD(boardp)) {
4603 ASC_DBG(1, "advansys_detect: narrow board\n");
4604 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4605 asc_dvc_varp->bus_type = asc_bus[bus];
4606 asc_dvc_varp->drv_ptr = boardp;
4607 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
4608 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
4609 asc_dvc_varp->iop_base = iop;
4610 asc_dvc_varp->isr_callback = asc_isr_callback;
4612 ASC_DBG(1, "advansys_detect: wide board\n");
4613 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4614 adv_dvc_varp->drv_ptr = boardp;
4615 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
4616 adv_dvc_varp->isr_callback = adv_isr_callback;
4617 adv_dvc_varp->async_callback = adv_async_callback;
4619 if (pci_devp->device == ASC_PCI_DEVICE_ID_2300)
4621 ASC_DBG(1, "advansys_detect: ASC-3550\n");
4622 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
4623 } else if (pci_devp->device == ASC_PCI_DEVICE_ID_2500)
4625 ASC_DBG(1, "advansys_detect: ASC-38C0800\n");
4626 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
4629 ASC_DBG(1, "advansys_detect: ASC-38C1600\n");
4630 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
4632 #endif /* CONFIG_PCI */
4635 * Map the board's registers into virtual memory for
4636 * PCI slave access. Only memory accesses are used to
4637 * access the board's registers.
4639 * Note: The PCI register base address is not always
4640 * page aligned, but the address passed to ioremap()
4641 * must be page aligned. It is guaranteed that the
4642 * PCI register base address will not cross a page
4645 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4647 iolen = ADV_3550_IOLEN;
4648 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4650 iolen = ADV_38C0800_IOLEN;
4653 iolen = ADV_38C1600_IOLEN;
4656 pci_memory_address = pci_resource_start(pci_devp, 1);
4657 ASC_DBG1(1, "advansys_detect: pci_memory_address: 0x%lx\n",
4658 (ulong) pci_memory_address);
4659 if ((boardp->ioremap_addr =
4660 ioremap(pci_memory_address & PAGE_MASK,
4663 "advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
4664 boardp->id, pci_memory_address, iolen);
4665 scsi_unregister(shp);
4669 ASC_DBG1(1, "advansys_detect: ioremap_addr: 0x%lx\n",
4670 (ulong) boardp->ioremap_addr);
4671 adv_dvc_varp->iop_base = (AdvPortAddr)
4672 (boardp->ioremap_addr +
4673 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
4674 ASC_DBG1(1, "advansys_detect: iop_base: 0x%lx\n",
4675 adv_dvc_varp->iop_base);
4676 #endif /* CONFIG_PCI */
4679 * Even though it isn't used to access wide boards, other
4680 * than for the debug line below, save I/O Port address so
4681 * that it can be reported.
4683 boardp->ioport = iop;
4686 "advansys_detect: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
4687 (ushort) inp(iop + 1), (ushort) inpw(iop));
4690 #ifdef CONFIG_PROC_FS
4692 * Allocate buffer for printing information from
4693 * /proc/scsi/advansys/[0...].
4695 if ((boardp->prtbuf =
4696 kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
4698 "advansys_detect: board %d: kmalloc(%d, %d) returned NULL\n",
4699 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
4700 scsi_unregister(shp);
4704 #endif /* CONFIG_PROC_FS */
4706 if (ASC_NARROW_BOARD(boardp)) {
4707 asc_dvc_varp->cfg->dev = dev;
4709 * Set the board bus type and PCI IRQ before
4710 * calling AscInitGetConfig().
4712 switch (asc_dvc_varp->bus_type) {
4715 shp->unchecked_isa_dma = TRUE;
4719 shp->unchecked_isa_dma = FALSE;
4723 shp->unchecked_isa_dma = FALSE;
4726 #endif /* CONFIG_ISA */
4729 shp->irq = asc_dvc_varp->irq_no = pci_devp->irq;
4730 asc_dvc_varp->cfg->pci_slot_info =
4731 ASC_PCI_MKID(pci_devp->bus->number,
4732 PCI_SLOT(pci_devp->devfn),
4733 PCI_FUNC(pci_devp->devfn));
4734 shp->unchecked_isa_dma = FALSE;
4737 #endif /* CONFIG_PCI */
4740 "advansys_detect: board %d: unknown adapter type: %d\n",
4741 boardp->id, asc_dvc_varp->bus_type);
4742 shp->unchecked_isa_dma = TRUE;
4747 adv_dvc_varp->cfg->dev = dev;
4749 * For Wide boards set PCI information before calling
4750 * AdvInitGetConfig().
4753 shp->irq = adv_dvc_varp->irq_no = pci_devp->irq;
4754 adv_dvc_varp->cfg->pci_slot_info =
4755 ASC_PCI_MKID(pci_devp->bus->number,
4756 PCI_SLOT(pci_devp->devfn),
4757 PCI_FUNC(pci_devp->devfn));
4758 shp->unchecked_isa_dma = FALSE;
4760 #endif /* CONFIG_PCI */
4764 * Read the board configuration.
4766 if (ASC_NARROW_BOARD(boardp)) {
4768 * NOTE: AscInitGetConfig() may change the board's
4769 * bus_type value. The asc_bus[bus] value should no
4770 * longer be used. If the bus_type field must be
4771 * referenced only use the bit-wise AND operator "&".
4773 ASC_DBG(2, "advansys_detect: AscInitGetConfig()\n");
4774 switch(ret = AscInitGetConfig(asc_dvc_varp)) {
4775 case 0: /* No error */
4777 case ASC_WARN_IO_PORT_ROTATE:
4779 "AscInitGetConfig: board %d: I/O port address modified\n",
4782 case ASC_WARN_AUTO_CONFIG:
4784 "AscInitGetConfig: board %d: I/O port increment switch enabled\n",
4787 case ASC_WARN_EEPROM_CHKSUM:
4789 "AscInitGetConfig: board %d: EEPROM checksum error\n",
4792 case ASC_WARN_IRQ_MODIFIED:
4794 "AscInitGetConfig: board %d: IRQ modified\n",
4797 case ASC_WARN_CMD_QNG_CONFLICT:
4799 "AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
4804 "AscInitGetConfig: board %d: unknown warning: 0x%x\n",
4808 if ((err_code = asc_dvc_varp->err_code) != 0) {
4810 "AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4811 boardp->id, asc_dvc_varp->init_state,
4812 asc_dvc_varp->err_code);
4815 ASC_DBG(2, "advansys_detect: AdvInitGetConfig()\n");
4816 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
4817 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
4820 if ((err_code = adv_dvc_varp->err_code) != 0) {
4822 "AdvInitGetConfig: board %d error: err_code 0x%x\n",
4823 boardp->id, adv_dvc_varp->err_code);
4827 if (err_code != 0) {
4828 #ifdef CONFIG_PROC_FS
4829 kfree(boardp->prtbuf);
4830 #endif /* CONFIG_PROC_FS */
4831 scsi_unregister(shp);
4837 * Save the EEPROM configuration so that it can be displayed
4838 * from /proc/scsi/advansys/[0...].
4840 if (ASC_NARROW_BOARD(boardp)) {
4845 * Set the adapter's target id bit in the 'init_tidmask' field.
4847 boardp->init_tidmask |=
4848 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
4851 * Save EEPROM settings for the board.
4853 ep = &boardp->eep_config.asc_eep;
4855 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
4856 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
4857 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
4858 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
4859 ep->start_motor = asc_dvc_varp->start_motor;
4860 ep->cntl = asc_dvc_varp->dvc_cntl;
4861 ep->no_scam = asc_dvc_varp->no_scam;
4862 ep->max_total_qng = asc_dvc_varp->max_total_qng;
4863 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
4864 /* 'max_tag_qng' is set to the same value for every device. */
4865 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
4866 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
4867 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
4868 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
4869 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
4870 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
4871 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
4874 * Modify board configuration.
4876 ASC_DBG(2, "advansys_detect: AscInitSetConfig()\n");
4877 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
4878 case 0: /* No error. */
4880 case ASC_WARN_IO_PORT_ROTATE:
4882 "AscInitSetConfig: board %d: I/O port address modified\n",
4885 case ASC_WARN_AUTO_CONFIG:
4887 "AscInitSetConfig: board %d: I/O port increment switch enabled\n",
4890 case ASC_WARN_EEPROM_CHKSUM:
4892 "AscInitSetConfig: board %d: EEPROM checksum error\n",
4895 case ASC_WARN_IRQ_MODIFIED:
4897 "AscInitSetConfig: board %d: IRQ modified\n",
4900 case ASC_WARN_CMD_QNG_CONFLICT:
4902 "AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
4907 "AscInitSetConfig: board %d: unknown warning: 0x%x\n",
4911 if (asc_dvc_varp->err_code != 0) {
4913 "AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4914 boardp->id, asc_dvc_varp->init_state,
4915 asc_dvc_varp->err_code);
4916 #ifdef CONFIG_PROC_FS
4917 kfree(boardp->prtbuf);
4918 #endif /* CONFIG_PROC_FS */
4919 scsi_unregister(shp);
4925 * Finish initializing the 'Scsi_Host' structure.
4927 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
4928 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
4929 shp->irq = asc_dvc_varp->irq_no;
4932 ADVEEP_3550_CONFIG *ep_3550;
4933 ADVEEP_38C0800_CONFIG *ep_38C0800;
4934 ADVEEP_38C1600_CONFIG *ep_38C1600;
4937 * Save Wide EEP Configuration Information.
4939 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4941 ep_3550 = &boardp->eep_config.adv_3550_eep;
4943 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4944 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
4945 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4946 ep_3550->termination = adv_dvc_varp->cfg->termination;
4947 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
4948 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
4949 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
4950 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
4951 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
4952 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
4953 ep_3550->start_motor = adv_dvc_varp->start_motor;
4954 ep_3550->scsi_reset_delay = adv_dvc_varp->scsi_reset_wait;
4955 ep_3550->serial_number_word1 =
4956 adv_dvc_varp->cfg->serial1;
4957 ep_3550->serial_number_word2 =
4958 adv_dvc_varp->cfg->serial2;
4959 ep_3550->serial_number_word3 =
4960 adv_dvc_varp->cfg->serial3;
4961 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4963 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4965 ep_38C0800->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4966 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
4967 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4968 ep_38C0800->termination_lvd =
4969 adv_dvc_varp->cfg->termination;
4970 ep_38C0800->disc_enable = adv_dvc_varp->cfg->disc_enable;
4971 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
4972 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
4973 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4974 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4975 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4976 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4977 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4978 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4979 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
4980 ep_38C0800->scsi_reset_delay =
4981 adv_dvc_varp->scsi_reset_wait;
4982 ep_38C0800->serial_number_word1 =
4983 adv_dvc_varp->cfg->serial1;
4984 ep_38C0800->serial_number_word2 =
4985 adv_dvc_varp->cfg->serial2;
4986 ep_38C0800->serial_number_word3 =
4987 adv_dvc_varp->cfg->serial3;
4990 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4992 ep_38C1600->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4993 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
4994 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4995 ep_38C1600->termination_lvd =
4996 adv_dvc_varp->cfg->termination;
4997 ep_38C1600->disc_enable = adv_dvc_varp->cfg->disc_enable;
4998 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
4999 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
5000 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
5001 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
5002 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
5003 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
5004 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
5005 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
5006 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
5007 ep_38C1600->scsi_reset_delay =
5008 adv_dvc_varp->scsi_reset_wait;
5009 ep_38C1600->serial_number_word1 =
5010 adv_dvc_varp->cfg->serial1;
5011 ep_38C1600->serial_number_word2 =
5012 adv_dvc_varp->cfg->serial2;
5013 ep_38C1600->serial_number_word3 =
5014 adv_dvc_varp->cfg->serial3;
5018 * Set the adapter's target id bit in the 'init_tidmask' field.
5020 boardp->init_tidmask |=
5021 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
5024 * Finish initializing the 'Scsi_Host' structure.
5026 shp->irq = adv_dvc_varp->irq_no;
5030 * Channels are numbered beginning with 0. For AdvanSys one host
5031 * structure supports one channel. Multi-channel boards have a
5032 * separate host structure for each channel.
5034 shp->max_channel = 0;
5035 if (ASC_NARROW_BOARD(boardp)) {
5036 shp->max_id = ASC_MAX_TID + 1;
5037 shp->max_lun = ASC_MAX_LUN + 1;
5039 shp->io_port = asc_dvc_varp->iop_base;
5040 boardp->asc_n_io_port = ASC_IOADR_GAP;
5041 shp->this_id = asc_dvc_varp->cfg->chip_scsi_id;
5043 /* Set maximum number of queues the adapter can handle. */
5044 shp->can_queue = asc_dvc_varp->max_total_qng;
5046 shp->max_id = ADV_MAX_TID + 1;
5047 shp->max_lun = ADV_MAX_LUN + 1;
5050 * Save the I/O Port address and length even though
5051 * I/O ports are not used to access Wide boards.
5052 * Instead the Wide boards are accessed with
5053 * PCI Memory Mapped I/O.
5056 boardp->asc_n_io_port = iolen;
5058 shp->this_id = adv_dvc_varp->chip_scsi_id;
5060 /* Set maximum number of queues the adapter can handle. */
5061 shp->can_queue = adv_dvc_varp->max_host_qng;
5065 * 'n_io_port' currently is one byte.
5067 * Set a value to 'n_io_port', but never referenced it because
5068 * it may be truncated.
5070 shp->n_io_port = boardp->asc_n_io_port <= 255 ?
5071 boardp->asc_n_io_port : 255;
5074 * Following v1.3.89, 'cmd_per_lun' is no longer needed
5075 * and should be set to zero.
5077 * But because of a bug introduced in v1.3.89 if the driver is
5078 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
5079 * SCSI function 'allocate_device' will panic. To allow the driver
5080 * to work as a module in these kernels set 'cmd_per_lun' to 1.
5082 * Note: This is wrong. cmd_per_lun should be set to the depth
5083 * you want on untagged devices always.
5086 shp->cmd_per_lun = 1;
5088 shp->cmd_per_lun = 0;
5092 * Set the maximum number of scatter-gather elements the
5093 * adapter can handle.
5095 if (ASC_NARROW_BOARD(boardp)) {
5097 * Allow two commands with 'sg_tablesize' scatter-gather
5098 * elements to be executed simultaneously. This value is
5099 * the theoretical hardware limit. It may be decreased
5103 (((asc_dvc_varp->max_total_qng - 2) / 2) *
5104 ASC_SG_LIST_PER_Q) + 1;
5106 shp->sg_tablesize = ADV_MAX_SG_LIST;
5110 * The value of 'sg_tablesize' can not exceed the SCSI
5111 * mid-level driver definition of SG_ALL. SG_ALL also
5112 * must not be exceeded, because it is used to define the
5113 * size of the scatter-gather table in 'struct asc_sg_head'.
5115 if (shp->sg_tablesize > SG_ALL) {
5116 shp->sg_tablesize = SG_ALL;
5119 ASC_DBG1(1, "advansys_detect: sg_tablesize: %d\n",
5122 /* BIOS start address. */
5123 if (ASC_NARROW_BOARD(boardp)) {
5125 ((ulong) AscGetChipBiosAddress(
5126 asc_dvc_varp->iop_base,
5127 asc_dvc_varp->bus_type));
5130 * Fill-in BIOS board variables. The Wide BIOS saves
5131 * information in LRAM that is used by the driver.
5133 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_SIGNATURE,
5134 boardp->bios_signature);
5135 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_VERSION,
5136 boardp->bios_version);
5137 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODESEG,
5138 boardp->bios_codeseg);
5139 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODELEN,
5140 boardp->bios_codelen);
5143 "advansys_detect: bios_signature 0x%x, bios_version 0x%x\n",
5144 boardp->bios_signature, boardp->bios_version);
5147 "advansys_detect: bios_codeseg 0x%x, bios_codelen 0x%x\n",
5148 boardp->bios_codeseg, boardp->bios_codelen);
5151 * If the BIOS saved a valid signature, then fill in
5152 * the BIOS code segment base address.
5154 if (boardp->bios_signature == 0x55AA) {
5156 * Convert x86 realmode code segment to a linear
5157 * address by shifting left 4.
5159 shp->base = ((ulong) boardp->bios_codeseg << 4);
5166 * Register Board Resources - I/O Port, DMA, IRQ
5170 * Register I/O port range.
5172 * For Wide boards the I/O ports are not used to access
5173 * the board, but request the region anyway.
5175 * 'shp->n_io_port' is not referenced, because it may be truncated.
5178 "advansys_detect: request_region port 0x%lx, len 0x%x\n",
5179 (ulong) shp->io_port, boardp->asc_n_io_port);
5180 if (request_region(shp->io_port, boardp->asc_n_io_port,
5181 "advansys") == NULL) {
5183 "advansys_detect: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
5184 boardp->id, (ulong) shp->io_port, boardp->asc_n_io_port);
5185 #ifdef CONFIG_PROC_FS
5186 kfree(boardp->prtbuf);
5187 #endif /* CONFIG_PROC_FS */
5188 scsi_unregister(shp);
5193 /* Register DMA Channel for Narrow boards. */
5194 shp->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
5196 if (ASC_NARROW_BOARD(boardp)) {
5197 /* Register DMA channel for ISA bus. */
5198 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5199 shp->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
5201 request_dma(shp->dma_channel, "advansys")) != 0) {
5203 "advansys_detect: board %d: request_dma() %d failed %d\n",
5204 boardp->id, shp->dma_channel, ret);
5205 release_region(shp->io_port, boardp->asc_n_io_port);
5206 #ifdef CONFIG_PROC_FS
5207 kfree(boardp->prtbuf);
5208 #endif /* CONFIG_PROC_FS */
5209 scsi_unregister(shp);
5213 AscEnableIsaDma(shp->dma_channel);
5216 #endif /* CONFIG_ISA */
5218 /* Register IRQ Number. */
5219 ASC_DBG1(2, "advansys_detect: request_irq() %d\n", shp->irq);
5221 * If request_irq() fails with the SA_INTERRUPT flag set,
5222 * then try again without the SA_INTERRUPT flag set. This
5223 * allows IRQ sharing to work even with other drivers that
5224 * do not set the SA_INTERRUPT flag.
5226 * If SA_INTERRUPT is not set, then interrupts are enabled
5227 * before the driver interrupt function is called.
5229 if (((ret = request_irq(shp->irq, advansys_interrupt,
5230 SA_INTERRUPT | (share_irq == TRUE ? SA_SHIRQ : 0),
5231 "advansys", boardp)) != 0) &&
5232 ((ret = request_irq(shp->irq, advansys_interrupt,
5233 (share_irq == TRUE ? SA_SHIRQ : 0),
5234 "advansys", boardp)) != 0))
5236 if (ret == -EBUSY) {
5238 "advansys_detect: board %d: request_irq(): IRQ 0x%x already in use.\n",
5239 boardp->id, shp->irq);
5240 } else if (ret == -EINVAL) {
5242 "advansys_detect: board %d: request_irq(): IRQ 0x%x not valid.\n",
5243 boardp->id, shp->irq);
5246 "advansys_detect: board %d: request_irq(): IRQ 0x%x failed with %d\n",
5247 boardp->id, shp->irq, ret);
5249 release_region(shp->io_port, boardp->asc_n_io_port);
5250 iounmap(boardp->ioremap_addr);
5251 if (shp->dma_channel != NO_ISA_DMA) {
5252 free_dma(shp->dma_channel);
5254 #ifdef CONFIG_PROC_FS
5255 kfree(boardp->prtbuf);
5256 #endif /* CONFIG_PROC_FS */
5257 scsi_unregister(shp);
5263 * Initialize board RISC chip and enable interrupts.
5265 if (ASC_NARROW_BOARD(boardp)) {
5266 ASC_DBG(2, "advansys_detect: AscInitAsc1000Driver()\n");
5267 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
5268 err_code = asc_dvc_varp->err_code;
5270 if (warn_code || err_code) {
5272 "advansys_detect: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
5273 boardp->id, asc_dvc_varp->init_state,
5274 warn_code, err_code);
5279 adv_req_t *reqp = NULL;
5283 * Allocate buffer carrier structures. The total size
5284 * is about 4 KB, so allocate all at once.
5287 (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
5288 ASC_DBG1(1, "advansys_detect: carrp 0x%lx\n", (ulong) carrp);
5290 if (carrp == NULL) {
5295 * Allocate up to 'max_host_qng' request structures for
5296 * the Wide board. The total size is about 16 KB, so
5297 * allocate all at once. If the allocation fails decrement
5300 for (req_cnt = adv_dvc_varp->max_host_qng;
5301 req_cnt > 0; req_cnt--) {
5303 reqp = (adv_req_t *)
5304 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
5307 "advansys_detect: reqp 0x%lx, req_cnt %d, bytes %lu\n",
5308 (ulong) reqp, req_cnt,
5309 (ulong) sizeof(adv_req_t) * req_cnt);
5321 * Allocate up to ADV_TOT_SG_BLOCK request structures for
5322 * the Wide board. Each structure is about 136 bytes.
5324 boardp->adv_sgblkp = NULL;
5325 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
5327 sgp = (adv_sgblk_t *)
5328 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
5334 sgp->next_sgblkp = boardp->adv_sgblkp;
5335 boardp->adv_sgblkp = sgp;
5339 "advansys_detect: sg_cnt %d * %u = %u bytes\n",
5340 sg_cnt, sizeof(adv_sgblk_t),
5341 (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
5344 * If no request structures or scatter-gather structures could
5345 * be allocated, then return an error. Otherwise continue with
5352 "advansys_detect: board %d error: failed to kmalloc() carrier buffer.\n",
5354 err_code = ADV_ERROR;
5355 } else if (reqp == NULL) {
5358 "advansys_detect: board %d error: failed to kmalloc() adv_req_t buffer.\n",
5360 err_code = ADV_ERROR;
5361 } else if (boardp->adv_sgblkp == NULL) {
5365 "advansys_detect: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
5367 err_code = ADV_ERROR;
5370 /* Save carrier buffer pointer. */
5371 boardp->orig_carrp = carrp;
5374 * Save original pointer for kfree() in case the
5375 * driver is built as a module and can be unloaded.
5377 boardp->orig_reqp = reqp;
5379 adv_dvc_varp->carrier_buf = carrp;
5382 * Point 'adv_reqp' to the request structures and
5383 * link them together.
5386 reqp[req_cnt].next_reqp = NULL;
5387 for (; req_cnt > 0; req_cnt--) {
5388 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
5390 boardp->adv_reqp = &reqp[0];
5392 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5395 "advansys_detect: AdvInitAsc3550Driver()\n");
5396 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
5397 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5399 "advansys_detect: AdvInitAsc38C0800Driver()\n");
5400 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
5403 "advansys_detect: AdvInitAsc38C1600Driver()\n");
5404 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
5406 err_code = adv_dvc_varp->err_code;
5408 if (warn_code || err_code) {
5410 "advansys_detect: board %d error: warn 0x%x, error 0x%x\n",
5411 boardp->id, warn_code, err_code);
5416 if (err_code != 0) {
5417 release_region(shp->io_port, boardp->asc_n_io_port);
5418 if (ASC_WIDE_BOARD(boardp)) {
5419 iounmap(boardp->ioremap_addr);
5420 if (boardp->orig_carrp) {
5421 kfree(boardp->orig_carrp);
5422 boardp->orig_carrp = NULL;
5424 if (boardp->orig_reqp) {
5425 kfree(boardp->orig_reqp);
5426 boardp->orig_reqp = boardp->adv_reqp = NULL;
5428 while ((sgp = boardp->adv_sgblkp) != NULL)
5430 boardp->adv_sgblkp = sgp->next_sgblkp;
5434 if (shp->dma_channel != NO_ISA_DMA) {
5435 free_dma(shp->dma_channel);
5437 #ifdef CONFIG_PROC_FS
5438 kfree(boardp->prtbuf);
5439 #endif /* CONFIG_PROC_FS */
5440 free_irq(shp->irq, boardp);
5441 scsi_unregister(shp);
5445 ASC_DBG_PRT_SCSI_HOST(2, shp);
5449 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n", asc_board_count);
5450 return asc_board_count;
5454 * advansys_release()
5456 * Release resources allocated for a single AdvanSys adapter.
5459 advansys_release(struct Scsi_Host *shp)
5461 asc_board_t *boardp;
5463 ASC_DBG(1, "advansys_release: begin\n");
5464 boardp = ASC_BOARDP(shp);
5465 free_irq(shp->irq, boardp);
5466 if (shp->dma_channel != NO_ISA_DMA) {
5467 ASC_DBG(1, "advansys_release: free_dma()\n");
5468 free_dma(shp->dma_channel);
5470 release_region(shp->io_port, boardp->asc_n_io_port);
5471 if (ASC_WIDE_BOARD(boardp)) {
5472 adv_sgblk_t *sgp = NULL;
5474 iounmap(boardp->ioremap_addr);
5475 if (boardp->orig_carrp) {
5476 kfree(boardp->orig_carrp);
5477 boardp->orig_carrp = NULL;
5479 if (boardp->orig_reqp) {
5480 kfree(boardp->orig_reqp);
5481 boardp->orig_reqp = boardp->adv_reqp = NULL;
5483 while ((sgp = boardp->adv_sgblkp) != NULL)
5485 boardp->adv_sgblkp = sgp->next_sgblkp;
5489 #ifdef CONFIG_PROC_FS
5490 ASC_ASSERT(boardp->prtbuf != NULL);
5491 kfree(boardp->prtbuf);
5492 #endif /* CONFIG_PROC_FS */
5493 scsi_unregister(shp);
5494 ASC_DBG(1, "advansys_release: end\n");
5501 * Return suitable for printing on the console with the argument
5502 * adapter's configuration information.
5504 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
5505 * otherwise the static 'info' array will be overrun.
5508 advansys_info(struct Scsi_Host *shp)
5510 static char info[ASC_INFO_SIZE];
5511 asc_board_t *boardp;
5512 ASC_DVC_VAR *asc_dvc_varp;
5513 ADV_DVC_VAR *adv_dvc_varp;
5516 char *widename = NULL;
5518 boardp = ASC_BOARDP(shp);
5519 if (ASC_NARROW_BOARD(boardp)) {
5520 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5521 ASC_DBG(1, "advansys_info: begin\n");
5522 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5523 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == ASC_IS_ISAPNP) {
5524 busname = "ISA PnP";
5528 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5530 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
5531 ASC_VERSION, busname,
5532 (ulong) shp->io_port,
5533 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5534 shp->irq, shp->dma_channel);
5536 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
5538 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
5540 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
5541 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
5542 == ASC_IS_PCI_ULTRA) {
5543 busname = "PCI Ultra";
5549 ASC_PRINT2( "advansys_info: board %d: unknown bus type %d\n",
5550 boardp->id, asc_dvc_varp->bus_type);
5552 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5554 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
5555 ASC_VERSION, busname,
5556 (ulong) shp->io_port,
5557 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5562 * Wide Adapter Information
5564 * Memory-mapped I/O is used instead of I/O space to access
5565 * the adapter, but display the I/O Port range. The Memory
5566 * I/O address is displayed through the driver /proc file.
5568 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5569 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5571 iolen = ADV_3550_IOLEN;
5572 widename = "Ultra-Wide";
5573 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
5575 iolen = ADV_38C0800_IOLEN;
5576 widename = "Ultra2-Wide";
5579 iolen = ADV_38C1600_IOLEN;
5580 widename = "Ultra3-Wide";
5582 sprintf(info, "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
5585 (ulong) adv_dvc_varp->iop_base,
5586 (ulong) adv_dvc_varp->iop_base + iolen - 1,
5589 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
5590 ASC_DBG(1, "advansys_info: end\n");
5595 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
5597 * This function always returns 0. Command return status is saved
5598 * in the 'scp' result field.
5601 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
5603 struct Scsi_Host *shp;
5604 asc_board_t *boardp;
5606 struct scsi_cmnd *done_scp;
5608 shp = scp->device->host;
5609 boardp = ASC_BOARDP(shp);
5610 ASC_STATS(shp, queuecommand);
5612 /* host_lock taken by mid-level prior to call but need to protect */
5613 /* against own ISR */
5614 spin_lock_irqsave(&boardp->lock, flags);
5617 * Block new commands while handling a reset or abort request.
5619 if (boardp->flags & ASC_HOST_IN_RESET) {
5621 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
5623 scp->result = HOST_BYTE(DID_RESET);
5626 * Add blocked requests to the board's 'done' queue. The queued
5627 * requests will be completed at the end of the abort or reset
5630 asc_enqueue(&boardp->done, scp, ASC_BACK);
5631 spin_unlock_irqrestore(&boardp->lock, flags);
5636 * Attempt to execute any waiting commands for the board.
5638 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
5640 "advansys_queuecommand: before asc_execute_queue() waiting\n");
5641 asc_execute_queue(&boardp->waiting);
5645 * Save the function pointer to Linux mid-level 'done' function
5646 * and attempt to execute the command.
5648 * If ASC_NOERROR is returned the request has been added to the
5649 * board's 'active' queue and will be completed by the interrupt
5652 * If ASC_BUSY is returned add the request to the board's per
5653 * target waiting list. This is the first time the request has
5654 * been tried. Add it to the back of the waiting list. It will be
5657 * If an error occurred, the request will have been placed on the
5658 * board's 'done' queue and must be completed before returning.
5660 scp->scsi_done = done;
5661 switch (asc_execute_scsi_cmnd(scp)) {
5665 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
5669 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
5670 /* Interrupts could be enabled here. */
5671 asc_scsi_done_list(done_scp);
5674 spin_unlock_irqrestore(&boardp->lock, flags);
5682 * Reset the bus associated with the command 'scp'.
5684 * This function runs its own thread. Interrupts must be blocked but
5685 * sleeping is allowed and no locking other than for host structures is
5686 * required. Returns SUCCESS or FAILED.
5689 advansys_reset(struct scsi_cmnd *scp)
5691 struct Scsi_Host *shp;
5692 asc_board_t *boardp;
5693 ASC_DVC_VAR *asc_dvc_varp;
5694 ADV_DVC_VAR *adv_dvc_varp;
5696 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5697 struct scsi_cmnd *tscp, *new_last_scp;
5701 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong) scp);
5703 #ifdef ADVANSYS_STATS
5704 if (scp->device->host != NULL) {
5705 ASC_STATS(scp->device->host, reset);
5707 #endif /* ADVANSYS_STATS */
5709 if ((shp = scp->device->host) == NULL) {
5710 scp->result = HOST_BYTE(DID_ERROR);
5714 boardp = ASC_BOARDP(shp);
5716 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
5719 * Check for re-entrancy.
5721 spin_lock_irqsave(&boardp->lock, flags);
5722 if (boardp->flags & ASC_HOST_IN_RESET) {
5723 spin_unlock_irqrestore(&boardp->lock, flags);
5726 boardp->flags |= ASC_HOST_IN_RESET;
5727 spin_unlock_irqrestore(&boardp->lock, flags);
5729 if (ASC_NARROW_BOARD(boardp)) {
5733 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5736 * Reset the chip and SCSI bus.
5738 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
5739 status = AscInitAsc1000Driver(asc_dvc_varp);
5741 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
5742 if (asc_dvc_varp->err_code) {
5744 "advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
5745 boardp->id, asc_dvc_varp->err_code);
5747 } else if (status) {
5749 "advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
5750 boardp->id, status);
5753 "advansys_reset: board %d: SCSI bus reset successful.\n",
5757 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
5758 spin_lock_irqsave(&boardp->lock, flags);
5764 * If the suggest reset bus flags are set, then reset the bus.
5765 * Otherwise only reset the device.
5767 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5770 * Reset the target's SCSI bus.
5772 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
5773 switch (AdvResetChipAndSB(adv_dvc_varp)) {
5775 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset successful.\n",
5780 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset error.\n",
5785 spin_lock_irqsave(&boardp->lock, flags);
5786 (void) AdvISR(adv_dvc_varp);
5788 /* Board lock is held. */
5791 * Dequeue all board 'done' requests. A pointer to the last request
5792 * is returned in 'last_scp'.
5794 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
5797 * Dequeue all board 'active' requests for all devices and set
5798 * the request status to DID_RESET. A pointer to the last request
5799 * is returned in 'last_scp'.
5801 if (done_scp == NULL) {
5802 done_scp = asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
5803 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5804 tscp->result = HOST_BYTE(DID_RESET);
5807 /* Append to 'done_scp' at the end with 'last_scp'. */
5808 ASC_ASSERT(last_scp != NULL);
5809 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5810 &boardp->active, &new_last_scp, ASC_TID_ALL);
5811 if (new_last_scp != NULL) {
5812 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5813 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5814 tscp->result = HOST_BYTE(DID_RESET);
5816 last_scp = new_last_scp;
5821 * Dequeue all 'waiting' requests and set the request status
5824 if (done_scp == NULL) {
5825 done_scp = asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
5826 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5827 tscp->result = HOST_BYTE(DID_RESET);
5830 /* Append to 'done_scp' at the end with 'last_scp'. */
5831 ASC_ASSERT(last_scp != NULL);
5832 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5833 &boardp->waiting, &new_last_scp, ASC_TID_ALL);
5834 if (new_last_scp != NULL) {
5835 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5836 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5837 tscp->result = HOST_BYTE(DID_RESET);
5839 last_scp = new_last_scp;
5843 /* Save the time of the most recently completed reset. */
5844 boardp->last_reset = jiffies;
5846 /* Clear reset flag. */
5847 boardp->flags &= ~ASC_HOST_IN_RESET;
5848 spin_unlock_irqrestore(&boardp->lock, flags);
5851 * Complete all the 'done_scp' requests.
5853 if (done_scp != NULL) {
5854 asc_scsi_done_list(done_scp);
5857 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
5863 * advansys_biosparam()
5865 * Translate disk drive geometry if the "BIOS greater than 1 GB"
5866 * support is enabled for a drive.
5868 * ip (information pointer) is an int array with the following definition:
5874 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
5875 sector_t capacity, int ip[])
5877 asc_board_t *boardp;
5879 ASC_DBG(1, "advansys_biosparam: begin\n");
5880 ASC_STATS(sdev->host, biosparam);
5881 boardp = ASC_BOARDP(sdev->host);
5882 if (ASC_NARROW_BOARD(boardp)) {
5883 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
5884 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
5892 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
5893 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
5901 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
5902 ASC_DBG(1, "advansys_biosparam: end\n");
5909 * This function is called from init/main.c at boot time.
5910 * It it passed LILO parameters that can be set from the
5911 * LILO command line or in /etc/lilo.conf.
5913 * It is used by the AdvanSys driver to either disable I/O
5914 * port scanning or to limit scanning to 1 - 4 I/O ports.
5915 * Regardless of the option setting EISA and PCI boards
5916 * will still be searched for and detected. This option
5917 * only affects searching for ISA and VL boards.
5919 * If ADVANSYS_DEBUG is defined the driver debug level may
5920 * be set using the 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port.
5923 * 1. Eliminate I/O port scanning:
5924 * boot: linux advansys=
5926 * boot: linux advansys=0x0
5927 * 2. Limit I/O port scanning to one I/O port:
5928 * boot: linux advansys=0x110
5929 * 3. Limit I/O port scanning to four I/O ports:
5930 * boot: linux advansys=0x110,0x210,0x230,0x330
5931 * 4. If ADVANSYS_DEBUG, limit I/O port scanning to four I/O ports and
5932 * set the driver debug level to 2.
5933 * boot: linux advansys=0x110,0x210,0x230,0x330,0xdeb2
5935 * ints[0] - number of arguments
5936 * ints[1] - first argument
5937 * ints[2] - second argument
5941 advansys_setup(char *str, int *ints)
5945 if (asc_iopflag == ASC_TRUE) {
5946 printk("AdvanSys SCSI: 'advansys' LILO option may appear only once\n");
5950 asc_iopflag = ASC_TRUE;
5952 if (ints[0] > ASC_NUM_IOPORT_PROBE) {
5953 #ifdef ADVANSYS_DEBUG
5954 if ((ints[0] == ASC_NUM_IOPORT_PROBE + 1) &&
5955 (ints[ASC_NUM_IOPORT_PROBE + 1] >> 4 == 0xdeb)) {
5956 asc_dbglvl = ints[ASC_NUM_IOPORT_PROBE + 1] & 0xf;
5958 #endif /* ADVANSYS_DEBUG */
5959 printk("AdvanSys SCSI: only %d I/O ports accepted\n",
5960 ASC_NUM_IOPORT_PROBE);
5961 #ifdef ADVANSYS_DEBUG
5963 #endif /* ADVANSYS_DEBUG */
5966 #ifdef ADVANSYS_DEBUG
5967 ASC_DBG1(1, "advansys_setup: ints[0] %d\n", ints[0]);
5968 for (i = 1; i < ints[0]; i++) {
5969 ASC_DBG2(1, " ints[%d] 0x%x", i, ints[i]);
5972 #endif /* ADVANSYS_DEBUG */
5974 for (i = 1; i <= ints[0] && i <= ASC_NUM_IOPORT_PROBE; i++) {
5975 asc_ioport[i-1] = ints[i];
5976 ASC_DBG2(1, "advansys_setup: asc_ioport[%d] 0x%x\n",
5977 i - 1, asc_ioport[i-1]);
5983 * --- Loadable Driver Support
5986 static struct scsi_host_template driver_template = {
5987 .proc_name = "advansys",
5988 #ifdef CONFIG_PROC_FS
5989 .proc_info = advansys_proc_info,
5992 .detect = advansys_detect,
5993 .release = advansys_release,
5994 .info = advansys_info,
5995 .queuecommand = advansys_queuecommand,
5996 .eh_bus_reset_handler = advansys_reset,
5997 .bios_param = advansys_biosparam,
5998 .slave_configure = advansys_slave_configure,
6000 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
6001 * must be set. The flag will be cleared in advansys_detect for non-ISA
6002 * adapters. Refer to the comment in scsi_module.c for more information.
6004 .unchecked_isa_dma = 1,
6006 * All adapters controlled by this driver are capable of large
6007 * scatter-gather lists. According to the mid-level SCSI documentation
6008 * this obviates any performance gain provided by setting
6009 * 'use_clustering'. But empirically while CPU utilization is increased
6010 * by enabling clustering, I/O throughput increases as well.
6012 .use_clustering = ENABLE_CLUSTERING,
6014 #include "scsi_module.c"
6018 * --- Miscellaneous Driver Functions
6022 * First-level interrupt handler.
6024 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
6025 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
6026 * is not referenced. 'dev_id' could be used to identify an interrupt passed
6027 * to the AdvanSys driver which is for a device sharing an interrupt with
6028 * an AdvanSys adapter.
6031 advansys_interrupt(int irq, void *dev_id, struct pt_regs *regs)
6035 asc_board_t *boardp;
6036 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
6037 struct scsi_cmnd *new_last_scp;
6038 struct Scsi_Host *shp;
6040 ASC_DBG(1, "advansys_interrupt: begin\n");
6043 * Check for interrupts on all boards.
6044 * AscISR() will call asc_isr_callback().
6046 for (i = 0; i < asc_board_count; i++) {
6048 boardp = ASC_BOARDP(shp);
6049 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
6051 spin_lock_irqsave(&boardp->lock, flags);
6052 if (ASC_NARROW_BOARD(boardp)) {
6056 if (AscIsIntPending(shp->io_port)) {
6057 ASC_STATS(shp, interrupt);
6058 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
6059 AscISR(&boardp->dvc_var.asc_dvc_var);
6065 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
6066 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
6067 ASC_STATS(shp, interrupt);
6072 * Start waiting requests and create a list of completed requests.
6074 * If a reset request is being performed for the board, the reset
6075 * handler will complete pending requests after it has completed.
6077 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
6078 ASC_DBG2(1, "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
6079 (ulong) done_scp, (ulong) last_scp);
6081 /* Start any waiting commands for the board. */
6082 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
6083 ASC_DBG(1, "advansys_interrupt: before asc_execute_queue()\n");
6084 asc_execute_queue(&boardp->waiting);
6088 * Add to the list of requests that must be completed.
6090 * 'done_scp' will always be NULL on the first iteration
6091 * of this loop. 'last_scp' is set at the same time as
6094 if (done_scp == NULL) {
6095 done_scp = asc_dequeue_list(&boardp->done, &last_scp,
6098 ASC_ASSERT(last_scp != NULL);
6099 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
6100 &boardp->done, &new_last_scp, ASC_TID_ALL);
6101 if (new_last_scp != NULL) {
6102 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
6103 last_scp = new_last_scp;
6107 spin_unlock_irqrestore(&boardp->lock, flags);
6111 * If interrupts were enabled on entry, then they
6112 * are now enabled here.
6114 * Complete all requests on the done list.
6117 asc_scsi_done_list(done_scp);
6119 ASC_DBG(1, "advansys_interrupt: end\n");
6124 * Set the number of commands to queue per device for the
6125 * specified host adapter.
6128 advansys_slave_configure(struct scsi_device *device)
6130 asc_board_t *boardp;
6132 boardp = ASC_BOARDP(device->host);
6133 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
6135 * Save a pointer to the device and set its initial/maximum
6136 * queue depth. Only save the pointer for a lun0 dev though.
6138 if(device->lun == 0)
6139 boardp->device[device->id] = device;
6140 if(device->tagged_supported) {
6141 if (ASC_NARROW_BOARD(boardp)) {
6142 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6143 boardp->dvc_var.asc_dvc_var.max_dvc_qng[device->id]);
6145 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6146 boardp->dvc_var.adv_dvc_var.max_dvc_qng);
6149 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
6151 ASC_DBG4(1, "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
6152 (ulong) device, (ulong) boardp, device->id, device->queue_depth);
6157 * Complete all requests on the singly linked list pointed
6160 * Interrupts can be enabled on entry.
6163 asc_scsi_done_list(struct scsi_cmnd *scp)
6165 struct scsi_cmnd *tscp;
6167 ASC_DBG(2, "asc_scsi_done_list: begin\n");
6168 while (scp != NULL) {
6169 asc_board_t *boardp;
6172 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong) scp);
6173 tscp = REQPNEXT(scp);
6174 scp->host_scribble = NULL;
6176 boardp = ASC_BOARDP(scp->device->host);
6178 if (ASC_NARROW_BOARD(boardp))
6179 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6181 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6184 dma_unmap_sg(dev, (struct scatterlist *)scp->request_buffer,
6185 scp->use_sg, scp->sc_data_direction);
6186 else if (scp->request_bufflen)
6187 dma_unmap_single(dev, scp->SCp.dma_handle,
6188 scp->request_bufflen, scp->sc_data_direction);
6190 ASC_STATS(scp->device->host, done);
6191 ASC_ASSERT(scp->scsi_done != NULL);
6193 scp->scsi_done(scp);
6197 ASC_DBG(2, "asc_scsi_done_list: done\n");
6202 * Execute a single 'Scsi_Cmnd'.
6204 * The function 'done' is called when the request has been completed.
6208 * host - board controlling device
6209 * device - device to send command
6210 * target - target of device
6211 * lun - lun of device
6212 * cmd_len - length of SCSI CDB
6213 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
6214 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
6216 * if (use_sg == 0) {
6217 * request_buffer - buffer address for request
6218 * request_bufflen - length of request buffer
6220 * request_buffer - pointer to scatterlist structure
6223 * sense_buffer - sense command buffer
6225 * result (4 bytes of an int):
6227 * 0 SCSI Status Byte Code
6228 * 1 SCSI One Byte Message Code
6230 * 3 Mid-Level Error Code
6232 * host driver fields:
6233 * SCp - Scsi_Pointer used for command processing status
6234 * scsi_done - used to save caller's done function
6235 * host_scribble - used for pointer to another struct scsi_cmnd
6237 * If this function returns ASC_NOERROR the request has been enqueued
6238 * on the board's 'active' queue and will be completed from the
6239 * interrupt handler.
6241 * If this function returns ASC_NOERROR the request has been enqueued
6242 * on the board's 'done' queue and must be completed by the caller.
6244 * If ASC_BUSY is returned the request will be enqueued by the
6245 * caller on the target's waiting queue and re-tried later.
6248 asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
6250 asc_board_t *boardp;
6251 ASC_DVC_VAR *asc_dvc_varp;
6252 ADV_DVC_VAR *adv_dvc_varp;
6253 ADV_SCSI_REQ_Q *adv_scsiqp;
6254 struct scsi_device *device;
6257 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
6258 (ulong) scp, (ulong) scp->scsi_done);
6260 boardp = ASC_BOARDP(scp->device->host);
6261 device = boardp->device[scp->device->id];
6263 if (ASC_NARROW_BOARD(boardp)) {
6265 * Build and execute Narrow Board request.
6268 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6271 * Build Asc Library request structure using the
6272 * global structures 'asc_scsi_req' and 'asc_sg_head'.
6274 * If an error is returned, then the request has been
6275 * queued on the board done queue. It will be completed
6278 * asc_build_req() can not return ASC_BUSY.
6280 if (asc_build_req(boardp, scp) == ASC_ERROR) {
6281 ASC_STATS(scp->device->host, build_error);
6286 * Execute the command. If there is no error, add the command
6287 * to the active queue.
6289 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
6291 ASC_STATS(scp->device->host, exe_noerror);
6293 * Increment monotonically increasing per device successful
6294 * request counter. Wrapping doesn't matter.
6296 boardp->reqcnt[scp->device->id]++;
6297 asc_enqueue(&boardp->active, scp, ASC_BACK);
6299 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
6303 * Caller will enqueue request on the target's waiting queue
6306 ASC_STATS(scp->device->host, exe_busy);
6310 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6311 boardp->id, asc_dvc_varp->err_code);
6312 ASC_STATS(scp->device->host, exe_error);
6313 scp->result = HOST_BYTE(DID_ERROR);
6314 asc_enqueue(&boardp->done, scp, ASC_BACK);
6318 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
6319 boardp->id, asc_dvc_varp->err_code);
6320 ASC_STATS(scp->device->host, exe_unknown);
6321 scp->result = HOST_BYTE(DID_ERROR);
6322 asc_enqueue(&boardp->done, scp, ASC_BACK);
6327 * Build and execute Wide Board request.
6329 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6332 * Build and get a pointer to an Adv Library request structure.
6334 * If the request is successfully built then send it below,
6335 * otherwise return with an error.
6337 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
6339 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
6342 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
6344 * If busy is returned the request has not been enqueued.
6345 * It will be enqueued by the caller on the target's waiting
6346 * queue and retried later.
6348 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
6349 * count wide board busy conditions. They are updated in
6350 * adv_build_req and adv_get_sglist, respectively.
6355 * If an error is returned, then the request has been
6356 * queued on the board done queue. It will be completed
6360 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
6361 ASC_STATS(scp->device->host, build_error);
6366 * Execute the command. If there is no error, add the command
6367 * to the active queue.
6369 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
6371 ASC_STATS(scp->device->host, exe_noerror);
6373 * Increment monotonically increasing per device successful
6374 * request counter. Wrapping doesn't matter.
6376 boardp->reqcnt[scp->device->id]++;
6377 asc_enqueue(&boardp->active, scp, ASC_BACK);
6379 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
6383 * Caller will enqueue request on the target's waiting queue
6386 ASC_STATS(scp->device->host, exe_busy);
6390 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6391 boardp->id, adv_dvc_varp->err_code);
6392 ASC_STATS(scp->device->host, exe_error);
6393 scp->result = HOST_BYTE(DID_ERROR);
6394 asc_enqueue(&boardp->done, scp, ASC_BACK);
6398 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
6399 boardp->id, adv_dvc_varp->err_code);
6400 ASC_STATS(scp->device->host, exe_unknown);
6401 scp->result = HOST_BYTE(DID_ERROR);
6402 asc_enqueue(&boardp->done, scp, ASC_BACK);
6407 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
6412 * Build a request structure for the Asc Library (Narrow Board).
6414 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
6415 * used to build the request.
6417 * If an error occurs, then queue the request on the board done
6418 * queue and return ASC_ERROR.
6421 asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
6423 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6426 * Mutually exclusive access is required to 'asc_scsi_q' and
6427 * 'asc_sg_head' until after the request is started.
6429 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
6432 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
6434 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
6437 * Build the ASC_SCSI_Q request.
6439 * For narrow boards a CDB length maximum of 12 bytes
6442 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
6444 "asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
6445 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
6446 scp->result = HOST_BYTE(DID_ERROR);
6447 asc_enqueue(&boardp->done, scp, ASC_BACK);
6450 asc_scsi_q.cdbptr = &scp->cmnd[0];
6451 asc_scsi_q.q2.cdb_len = scp->cmd_len;
6452 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
6453 asc_scsi_q.q1.target_lun = scp->device->lun;
6454 asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
6455 asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6456 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
6459 * If there are any outstanding requests for the current target,
6460 * then every 255th request send an ORDERED request. This heuristic
6461 * tries to retain the benefit of request sorting while preventing
6462 * request starvation. 255 is the max number of tags or pending commands
6463 * a device may have outstanding.
6465 * The request count is incremented below for every successfully
6469 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
6470 (boardp->reqcnt[scp->device->id] % 255) == 0) {
6471 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
6473 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
6477 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
6480 if (scp->use_sg == 0) {
6482 * CDB request of single contiguous buffer.
6484 ASC_STATS(scp->device->host, cont_cnt);
6485 scp->SCp.dma_handle = scp->request_bufflen ?
6486 dma_map_single(dev, scp->request_buffer,
6487 scp->request_bufflen, scp->sc_data_direction) : 0;
6488 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
6489 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
6490 ASC_STATS_ADD(scp->device->host, cont_xfer,
6491 ASC_CEILING(scp->request_bufflen, 512));
6492 asc_scsi_q.q1.sg_queue_cnt = 0;
6493 asc_scsi_q.sg_head = NULL;
6496 * CDB scatter-gather request list.
6500 struct scatterlist *slp;
6502 slp = (struct scatterlist *)scp->request_buffer;
6503 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6505 if (use_sg > scp->device->host->sg_tablesize) {
6507 "asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
6508 boardp->id, use_sg, scp->device->host->sg_tablesize);
6509 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6510 scp->result = HOST_BYTE(DID_ERROR);
6511 asc_enqueue(&boardp->done, scp, ASC_BACK);
6515 ASC_STATS(scp->device->host, sg_cnt);
6518 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
6519 * structure to point to it.
6521 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
6523 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
6524 asc_scsi_q.sg_head = &asc_sg_head;
6525 asc_scsi_q.q1.data_cnt = 0;
6526 asc_scsi_q.q1.data_addr = 0;
6527 /* This is a byte value, otherwise it would need to be swapped. */
6528 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
6529 ASC_STATS_ADD(scp->device->host, sg_elem, asc_sg_head.entry_cnt);
6532 * Convert scatter-gather list into ASC_SG_HEAD list.
6534 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
6535 asc_sg_head.sg_list[sgcnt].addr = cpu_to_le32(sg_dma_address(slp));
6536 asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(sg_dma_len(slp));
6537 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6541 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
6542 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6548 * Build a request structure for the Adv Library (Wide Board).
6550 * If an adv_req_t can not be allocated to issue the request,
6551 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
6553 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
6554 * microcode for DMA addresses or math operations are byte swapped
6555 * to little-endian order.
6558 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
6559 ADV_SCSI_REQ_Q **adv_scsiqpp)
6562 ADV_SCSI_REQ_Q *scsiqp;
6565 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6568 * Allocate an adv_req_t structure from the board to execute
6571 if (boardp->adv_reqp == NULL) {
6572 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
6573 ASC_STATS(scp->device->host, adv_build_noreq);
6576 reqp = boardp->adv_reqp;
6577 boardp->adv_reqp = reqp->next_reqp;
6578 reqp->next_reqp = NULL;
6582 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
6584 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6587 * Initialize the structure.
6589 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
6592 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
6594 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
6597 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
6602 * Build the ADV_SCSI_REQ_Q request.
6606 * Set CDB length and copy it to the request structure.
6607 * For wide boards a CDB length maximum of 16 bytes
6610 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
6612 "adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
6613 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
6614 scp->result = HOST_BYTE(DID_ERROR);
6615 asc_enqueue(&boardp->done, scp, ASC_BACK);
6618 scsiqp->cdb_len = scp->cmd_len;
6619 /* Copy first 12 CDB bytes to cdb[]. */
6620 for (i = 0; i < scp->cmd_len && i < 12; i++) {
6621 scsiqp->cdb[i] = scp->cmnd[i];
6623 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
6624 for (; i < scp->cmd_len; i++) {
6625 scsiqp->cdb16[i - 12] = scp->cmnd[i];
6628 scsiqp->target_id = scp->device->id;
6629 scsiqp->target_lun = scp->device->lun;
6631 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6632 scsiqp->sense_len = sizeof(scp->sense_buffer);
6635 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
6639 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6640 scsiqp->vdata_addr = scp->request_buffer;
6641 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
6643 if (scp->use_sg == 0) {
6645 * CDB request of single contiguous buffer.
6647 reqp->sgblkp = NULL;
6648 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6649 if (scp->request_bufflen) {
6650 scsiqp->vdata_addr = scp->request_buffer;
6651 scp->SCp.dma_handle =
6652 dma_map_single(dev, scp->request_buffer,
6653 scp->request_bufflen, scp->sc_data_direction);
6655 scsiqp->vdata_addr = 0;
6656 scp->SCp.dma_handle = 0;
6658 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
6659 scsiqp->sg_list_ptr = NULL;
6660 scsiqp->sg_real_addr = 0;
6661 ASC_STATS(scp->device->host, cont_cnt);
6662 ASC_STATS_ADD(scp->device->host, cont_xfer,
6663 ASC_CEILING(scp->request_bufflen, 512));
6666 * CDB scatter-gather request list.
6668 struct scatterlist *slp;
6671 slp = (struct scatterlist *)scp->request_buffer;
6672 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6674 if (use_sg > ADV_MAX_SG_LIST) {
6676 "adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
6677 boardp->id, use_sg, scp->device->host->sg_tablesize);
6678 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6679 scp->result = HOST_BYTE(DID_ERROR);
6680 asc_enqueue(&boardp->done, scp, ASC_BACK);
6683 * Free the 'adv_req_t' structure by adding it back to the
6686 reqp->next_reqp = boardp->adv_reqp;
6687 boardp->adv_reqp = reqp;
6692 if ((ret = adv_get_sglist(boardp, reqp, scp, use_sg)) != ADV_SUCCESS) {
6694 * Free the adv_req_t structure by adding it back to the
6697 reqp->next_reqp = boardp->adv_reqp;
6698 boardp->adv_reqp = reqp;
6703 ASC_STATS(scp->device->host, sg_cnt);
6704 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
6707 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6708 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6710 *adv_scsiqpp = scsiqp;
6716 * Build scatter-gather list for Adv Library (Wide Board).
6718 * Additional ADV_SG_BLOCK structures will need to be allocated
6719 * if the total number of scatter-gather elements exceeds
6720 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
6721 * assumed to be physically contiguous.
6724 * ADV_SUCCESS(1) - SG List successfully created
6725 * ADV_ERROR(-1) - SG List creation failed
6728 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, int use_sg)
6730 adv_sgblk_t *sgblkp;
6731 ADV_SCSI_REQ_Q *scsiqp;
6732 struct scatterlist *slp;
6734 ADV_SG_BLOCK *sg_block, *prev_sg_block;
6735 ADV_PADDR sg_block_paddr;
6738 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6739 slp = (struct scatterlist *) scp->request_buffer;
6740 sg_elem_cnt = use_sg;
6741 prev_sg_block = NULL;
6742 reqp->sgblkp = NULL;
6747 * Allocate a 'adv_sgblk_t' structure from the board free
6748 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
6749 * (15) scatter-gather elements.
6751 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
6752 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
6753 ASC_STATS(scp->device->host, adv_build_nosg);
6756 * Allocation failed. Free 'adv_sgblk_t' structures already
6757 * allocated for the request.
6759 while ((sgblkp = reqp->sgblkp) != NULL)
6761 /* Remove 'sgblkp' from the request list. */
6762 reqp->sgblkp = sgblkp->next_sgblkp;
6764 /* Add 'sgblkp' to the board free list. */
6765 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6766 boardp->adv_sgblkp = sgblkp;
6770 /* Complete 'adv_sgblk_t' board allocation. */
6771 boardp->adv_sgblkp = sgblkp->next_sgblkp;
6772 sgblkp->next_sgblkp = NULL;
6775 * Get 8 byte aligned virtual and physical addresses for
6776 * the allocated ADV_SG_BLOCK structure.
6778 sg_block = (ADV_SG_BLOCK *) ADV_8BALIGN(&sgblkp->sg_block);
6779 sg_block_paddr = virt_to_bus(sg_block);
6782 * Check if this is the first 'adv_sgblk_t' for the request.
6784 if (reqp->sgblkp == NULL)
6786 /* Request's first scatter-gather block. */
6787 reqp->sgblkp = sgblkp;
6790 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
6793 scsiqp->sg_list_ptr = sg_block;
6794 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
6797 /* Request's second or later scatter-gather block. */
6798 sgblkp->next_sgblkp = reqp->sgblkp;
6799 reqp->sgblkp = sgblkp;
6802 * Point the previous ADV_SG_BLOCK structure to
6803 * the newly allocated ADV_SG_BLOCK structure.
6805 ASC_ASSERT(prev_sg_block != NULL);
6806 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
6810 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
6812 sg_block->sg_list[i].sg_addr = cpu_to_le32(sg_dma_address(slp));
6813 sg_block->sg_list[i].sg_count = cpu_to_le32(sg_dma_len(slp));
6814 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6816 if (--sg_elem_cnt == 0)
6817 { /* Last ADV_SG_BLOCK and scatter-gather entry. */
6818 sg_block->sg_cnt = i + 1;
6819 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
6824 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
6825 prev_sg_block = sg_block;
6832 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6834 * Interrupt callback function for the Narrow SCSI Asc Library.
6837 asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6839 asc_board_t *boardp;
6840 struct scsi_cmnd *scp;
6841 struct Scsi_Host *shp;
6844 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
6845 (ulong) asc_dvc_varp, (ulong) qdonep);
6846 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6849 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6850 * command that has been completed.
6852 scp = (struct scsi_cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
6853 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong) scp);
6856 ASC_PRINT("asc_isr_callback: scp is NULL\n");
6859 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6862 * If the request's host pointer is not valid, display a
6863 * message and return.
6865 shp = scp->device->host;
6866 for (i = 0; i < asc_board_count; i++) {
6867 if (asc_host[i] == shp) {
6871 if (i == asc_board_count) {
6873 "asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
6874 (ulong) scp, (ulong) shp);
6878 ASC_STATS(shp, callback);
6879 ASC_DBG1(1, "asc_isr_callback: shp 0x%lx\n", (ulong) shp);
6882 * If the request isn't found on the active queue, it may
6883 * have been removed to handle a reset request.
6884 * Display a message and return.
6886 boardp = ASC_BOARDP(shp);
6887 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
6888 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
6890 "asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
6891 boardp->id, (ulong) scp);
6896 * 'qdonep' contains the command's ending status.
6898 switch (qdonep->d3.done_stat) {
6900 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
6904 * If an INQUIRY command completed successfully, then call
6905 * the AscInquiryHandling() function to set-up the device.
6907 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
6908 (scp->request_bufflen - qdonep->remain_bytes) >= 8)
6910 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
6911 (ASC_SCSI_INQUIRY *) scp->request_buffer);
6915 * Check for an underrun condition.
6917 * If there was no error and an underrun condition, then
6918 * then return the number of underrun bytes.
6920 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
6921 qdonep->remain_bytes <= scp->request_bufflen) {
6922 ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
6923 (unsigned) qdonep->remain_bytes);
6924 scp->resid = qdonep->remain_bytes;
6929 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
6930 switch (qdonep->d3.host_stat) {
6931 case QHSTA_NO_ERROR:
6932 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6933 ASC_DBG(2, "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
6934 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6935 sizeof(scp->sense_buffer));
6937 * Note: The 'status_byte()' macro used by target drivers
6938 * defined in scsi.h shifts the status byte returned by
6939 * host drivers right by 1 bit. This is why target drivers
6940 * also use right shifted status byte definitions. For
6941 * instance target drivers use CHECK_CONDITION, defined to
6942 * 0x1, instead of the SCSI defined check condition value
6943 * of 0x2. Host drivers are supposed to return the status
6944 * byte as it is defined by SCSI.
6946 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6947 STATUS_BYTE(qdonep->d3.scsi_stat);
6949 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6954 /* QHSTA error occurred */
6955 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
6956 qdonep->d3.host_stat);
6957 scp->result = HOST_BYTE(DID_BAD_TARGET);
6962 case QD_ABORTED_BY_HOST:
6963 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
6964 scp->result = HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.scsi_msg) |
6965 STATUS_BYTE(qdonep->d3.scsi_stat);
6969 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", qdonep->d3.done_stat);
6970 scp->result = HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.scsi_msg) |
6971 STATUS_BYTE(qdonep->d3.scsi_stat);
6976 * If the 'init_tidmask' bit isn't already set for the target and the
6977 * current request finished normally, then set the bit for the target
6978 * to indicate that a device is present.
6980 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6981 qdonep->d3.done_stat == QD_NO_ERROR &&
6982 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6983 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6987 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
6988 * function, add the command to the end of the board's done queue.
6989 * The done function for the command will be called from
6990 * advansys_interrupt().
6992 asc_enqueue(&boardp->done, scp, ASC_BACK);
6998 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
7000 * Callback function for the Wide SCSI Adv Library.
7003 adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
7005 asc_board_t *boardp;
7007 adv_sgblk_t *sgblkp;
7008 struct scsi_cmnd *scp;
7009 struct Scsi_Host *shp;
7014 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
7015 (ulong) adv_dvc_varp, (ulong) scsiqp);
7016 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7019 * Get the adv_req_t structure for the command that has been
7020 * completed. The adv_req_t structure actually contains the
7021 * completed ADV_SCSI_REQ_Q structure.
7023 reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
7024 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong) reqp);
7026 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
7031 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
7032 * command that has been completed.
7034 * Note: The adv_req_t request structure and adv_sgblk_t structure,
7035 * if any, are dropped, because a board structure pointer can not be
7039 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong) scp);
7041 ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
7044 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7047 * If the request's host pointer is not valid, display a message
7050 shp = scp->device->host;
7051 for (i = 0; i < asc_board_count; i++) {
7052 if (asc_host[i] == shp) {
7057 * Note: If the host structure is not found, the adv_req_t request
7058 * structure and adv_sgblk_t structure, if any, is dropped.
7060 if (i == asc_board_count) {
7062 "adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
7063 (ulong) scp, (ulong) shp);
7067 ASC_STATS(shp, callback);
7068 ASC_DBG1(1, "adv_isr_callback: shp 0x%lx\n", (ulong) shp);
7071 * If the request isn't found on the active queue, it may have been
7072 * removed to handle a reset request. Display a message and return.
7074 * Note: Because the structure may still be in use don't attempt
7075 * to free the adv_req_t and adv_sgblk_t, if any, structures.
7077 boardp = ASC_BOARDP(shp);
7078 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
7079 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
7081 "adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
7082 boardp->id, (ulong) scp);
7087 * 'done_status' contains the command's ending status.
7089 switch (scsiqp->done_status) {
7091 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
7095 * Check for an underrun condition.
7097 * If there was no error and an underrun condition, then
7098 * then return the number of underrun bytes.
7100 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
7101 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
7102 resid_cnt <= scp->request_bufflen) {
7103 ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
7105 scp->resid = resid_cnt;
7110 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
7111 switch (scsiqp->host_status) {
7112 case QHSTA_NO_ERROR:
7113 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
7114 ASC_DBG(2, "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
7115 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7116 sizeof(scp->sense_buffer));
7118 * Note: The 'status_byte()' macro used by target drivers
7119 * defined in scsi.h shifts the status byte returned by
7120 * host drivers right by 1 bit. This is why target drivers
7121 * also use right shifted status byte definitions. For
7122 * instance target drivers use CHECK_CONDITION, defined to
7123 * 0x1, instead of the SCSI defined check condition value
7124 * of 0x2. Host drivers are supposed to return the status
7125 * byte as it is defined by SCSI.
7127 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7128 STATUS_BYTE(scsiqp->scsi_status);
7130 scp->result = STATUS_BYTE(scsiqp->scsi_status);
7135 /* Some other QHSTA error occurred. */
7136 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
7137 scsiqp->host_status);
7138 scp->result = HOST_BYTE(DID_BAD_TARGET);
7143 case QD_ABORTED_BY_HOST:
7144 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
7145 scp->result = HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
7149 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", scsiqp->done_status);
7150 scp->result = HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
7155 * If the 'init_tidmask' bit isn't already set for the target and the
7156 * current request finished normally, then set the bit for the target
7157 * to indicate that a device is present.
7159 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7160 scsiqp->done_status == QD_NO_ERROR &&
7161 scsiqp->host_status == QHSTA_NO_ERROR) {
7162 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7166 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
7167 * function, add the command to the end of the board's done queue.
7168 * The done function for the command will be called from
7169 * advansys_interrupt().
7171 asc_enqueue(&boardp->done, scp, ASC_BACK);
7174 * Free all 'adv_sgblk_t' structures allocated for the request.
7176 while ((sgblkp = reqp->sgblkp) != NULL)
7178 /* Remove 'sgblkp' from the request list. */
7179 reqp->sgblkp = sgblkp->next_sgblkp;
7181 /* Add 'sgblkp' to the board free list. */
7182 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7183 boardp->adv_sgblkp = sgblkp;
7187 * Free the adv_req_t structure used with the command by adding
7188 * it back to the board free list.
7190 reqp->next_reqp = boardp->adv_reqp;
7191 boardp->adv_reqp = reqp;
7193 ASC_DBG(1, "adv_isr_callback: done\n");
7199 * adv_async_callback() - Adv Library asynchronous event callback function.
7202 adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
7206 case ADV_ASYNC_SCSI_BUS_RESET_DET:
7208 * The firmware detected a SCSI Bus reset.
7210 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
7213 case ADV_ASYNC_RDMA_FAILURE:
7215 * Handle RDMA failure by resetting the SCSI Bus and
7216 * possibly the chip if it is unresponsive. Log the error
7217 * with a unique code.
7219 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
7220 AdvResetChipAndSB(adv_dvc_varp);
7223 case ADV_HOST_SCSI_BUS_RESET:
7225 * Host generated SCSI bus reset occurred.
7227 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
7231 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
7237 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
7238 * to indicate a command is queued for the device.
7240 * 'flag' may be either ASC_FRONT or ASC_BACK.
7242 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7245 asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
7249 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
7250 (ulong) ascq, (ulong) reqp, flag);
7251 ASC_ASSERT(reqp != NULL);
7252 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
7253 tid = REQPTID(reqp);
7254 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7255 if (flag == ASC_FRONT) {
7256 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
7257 ascq->q_first[tid] = reqp;
7258 /* If the queue was empty, set the last pointer. */
7259 if (ascq->q_last[tid] == NULL) {
7260 ascq->q_last[tid] = reqp;
7262 } else { /* ASC_BACK */
7263 if (ascq->q_last[tid] != NULL) {
7264 ascq->q_last[tid]->host_scribble = (unsigned char *)reqp;
7266 ascq->q_last[tid] = reqp;
7267 reqp->host_scribble = NULL;
7268 /* If the queue was empty, set the first pointer. */
7269 if (ascq->q_first[tid] == NULL) {
7270 ascq->q_first[tid] = reqp;
7273 /* The queue has at least one entry, set its bit. */
7274 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
7275 #ifdef ADVANSYS_STATS
7276 /* Maintain request queue statistics. */
7277 ascq->q_tot_cnt[tid]++;
7278 ascq->q_cur_cnt[tid]++;
7279 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
7280 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
7281 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
7282 tid, ascq->q_max_cnt[tid]);
7284 REQPTIME(reqp) = REQTIMESTAMP();
7285 #endif /* ADVANSYS_STATS */
7286 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong) reqp);
7291 * Return first queued 'REQP' on the specified queue for
7292 * the specified target device. Clear the 'tidmask' bit for
7293 * the device if no more commands are left queued for it.
7295 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7298 asc_dequeue(asc_queue_t *ascq, int tid)
7302 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7303 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7304 if ((reqp = ascq->q_first[tid]) != NULL) {
7305 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
7306 ascq->q_first[tid] = REQPNEXT(reqp);
7307 /* If the queue is empty, clear its bit and the last pointer. */
7308 if (ascq->q_first[tid] == NULL) {
7309 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7310 ASC_ASSERT(ascq->q_last[tid] == reqp);
7311 ascq->q_last[tid] = NULL;
7313 #ifdef ADVANSYS_STATS
7314 /* Maintain request queue statistics. */
7315 ascq->q_cur_cnt[tid]--;
7316 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7317 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
7318 #endif /* ADVANSYS_STATS */
7320 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong) reqp);
7325 * Return a pointer to a singly linked list of all the requests queued
7326 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
7328 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
7329 * the last request returned in the singly linked list.
7331 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
7332 * then all queued requests are concatenated into one list and
7335 * Note: If 'lastpp' is used to append a new list to the end of
7336 * an old list, only change the old list last pointer if '*lastpp'
7337 * (or the function return value) is not NULL, i.e. use a temporary
7338 * variable for 'lastpp' and check its value after the function return
7339 * before assigning it to the list last pointer.
7341 * Unfortunately collecting queuing time statistics adds overhead to
7342 * the function that isn't inherent to the function's algorithm.
7345 asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
7350 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7351 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
7354 * If 'tid' is not ASC_TID_ALL, return requests only for
7355 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
7356 * requests for all tids.
7358 if (tid != ASC_TID_ALL) {
7359 /* Return all requests for the specified 'tid'. */
7360 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
7361 /* List is empty; Set first and last return pointers to NULL. */
7362 firstp = lastp = NULL;
7364 firstp = ascq->q_first[tid];
7365 lastp = ascq->q_last[tid];
7366 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
7367 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7368 #ifdef ADVANSYS_STATS
7371 ascq->q_cur_cnt[tid] = 0;
7372 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7373 REQTIMESTAT("asc_dequeue_list", ascq, reqp, tid);
7376 #endif /* ADVANSYS_STATS */
7379 /* Return all requests for all tids. */
7380 firstp = lastp = NULL;
7381 for (i = 0; i <= ADV_MAX_TID; i++) {
7382 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
7383 if (firstp == NULL) {
7384 firstp = ascq->q_first[i];
7385 lastp = ascq->q_last[i];
7387 ASC_ASSERT(lastp != NULL);
7388 lastp->host_scribble = (unsigned char *)ascq->q_first[i];
7389 lastp = ascq->q_last[i];
7391 ascq->q_first[i] = ascq->q_last[i] = NULL;
7392 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7393 #ifdef ADVANSYS_STATS
7394 ascq->q_cur_cnt[i] = 0;
7395 #endif /* ADVANSYS_STATS */
7398 #ifdef ADVANSYS_STATS
7401 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7402 REQTIMESTAT("asc_dequeue_list", ascq, reqp, reqp->device->id);
7405 #endif /* ADVANSYS_STATS */
7410 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong) firstp);
7415 * Remove the specified 'REQP' from the specified queue for
7416 * the specified target device. Clear the 'tidmask' bit for the
7417 * device if no more commands are left queued for it.
7419 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
7421 * Return ASC_TRUE if the command was found and removed,
7422 * otherwise return ASC_FALSE.
7425 asc_rmqueue(asc_queue_t *ascq, REQP reqp)
7429 int ret = ASC_FALSE;
7431 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
7432 (ulong) ascq, (ulong) reqp);
7433 ASC_ASSERT(reqp != NULL);
7435 tid = REQPTID(reqp);
7436 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7439 * Handle the common case of 'reqp' being the first
7440 * entry on the queue.
7442 if (reqp == ascq->q_first[tid]) {
7444 ascq->q_first[tid] = REQPNEXT(reqp);
7445 /* If the queue is now empty, clear its bit and the last pointer. */
7446 if (ascq->q_first[tid] == NULL) {
7447 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7448 ASC_ASSERT(ascq->q_last[tid] == reqp);
7449 ascq->q_last[tid] = NULL;
7451 } else if (ascq->q_first[tid] != NULL) {
7452 ASC_ASSERT(ascq->q_last[tid] != NULL);
7454 * Because the case of 'reqp' being the first entry has been
7455 * handled above and it is known the queue is not empty, if
7456 * 'reqp' is found on the queue it is guaranteed the queue will
7457 * not become empty and that 'q_first[tid]' will not be changed.
7459 * Set 'prevp' to the first entry, 'currp' to the second entry,
7460 * and search for 'reqp'.
7462 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
7463 currp; prevp = currp, currp = REQPNEXT(currp)) {
7464 if (currp == reqp) {
7466 prevp->host_scribble = (unsigned char *)REQPNEXT(currp);
7467 reqp->host_scribble = NULL;
7468 if (ascq->q_last[tid] == reqp) {
7469 ascq->q_last[tid] = prevp;
7475 #ifdef ADVANSYS_STATS
7476 /* Maintain request queue statistics. */
7477 if (ret == ASC_TRUE) {
7478 ascq->q_cur_cnt[tid]--;
7479 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
7481 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7482 #endif /* ADVANSYS_STATS */
7483 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong) reqp, ret);
7488 * Execute as many queued requests as possible for the specified queue.
7490 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
7493 asc_execute_queue(asc_queue_t *ascq)
7495 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
7499 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong) ascq);
7501 * Execute queued commands for devices attached to
7502 * the current board in round-robin fashion.
7504 scan_tidmask = ascq->q_tidmask;
7506 for (i = 0; i <= ADV_MAX_TID; i++) {
7507 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
7508 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
7509 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7510 } else if (asc_execute_scsi_cmnd((struct scsi_cmnd *) reqp)
7512 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7514 * The request returned ASC_BUSY. Enqueue at the front of
7515 * target's waiting list to maintain correct ordering.
7517 asc_enqueue(ascq, reqp, ASC_FRONT);
7521 } while (scan_tidmask);
7525 #ifdef CONFIG_PROC_FS
7527 * asc_prt_board_devices()
7529 * Print driver information for devices attached to the board.
7531 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7532 * cf. asc_prt_line().
7534 * Return the number of characters copied into 'cp'. No more than
7535 * 'cplen' characters will be copied to 'cp'.
7538 asc_prt_board_devices(struct Scsi_Host *shp, char *cp, int cplen)
7540 asc_board_t *boardp;
7547 boardp = ASC_BOARDP(shp);
7551 len = asc_prt_line(cp, leftlen,
7552 "\nDevice Information for AdvanSys SCSI Host %d:\n", shp->host_no);
7555 if (ASC_NARROW_BOARD(boardp)) {
7556 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7558 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7561 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
7563 for (i = 0; i <= ADV_MAX_TID; i++) {
7564 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
7565 len = asc_prt_line(cp, leftlen, " %X,", i);
7569 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
7576 * Display Wide Board BIOS Information.
7579 asc_prt_adv_bios(struct Scsi_Host *shp, char *cp, int cplen)
7581 asc_board_t *boardp;
7585 ushort major, minor, letter;
7587 boardp = ASC_BOARDP(shp);
7591 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
7595 * If the BIOS saved a valid signature, then fill in
7596 * the BIOS code segment base address.
7598 if (boardp->bios_signature != 0x55AA) {
7599 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
7601 len = asc_prt_line(cp, leftlen,
7602 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
7604 len = asc_prt_line(cp, leftlen,
7605 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
7608 major = (boardp->bios_version >> 12) & 0xF;
7609 minor = (boardp->bios_version >> 8) & 0xF;
7610 letter = (boardp->bios_version & 0xFF);
7612 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
7613 major, minor, letter >= 26 ? '?' : letter + 'A');
7617 * Current available ROM BIOS release is 3.1I for UW
7618 * and 3.2I for U2W. This code doesn't differentiate
7619 * UW and U2W boards.
7621 if (major < 3 || (major <= 3 && minor < 1) ||
7622 (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
7623 len = asc_prt_line(cp, leftlen,
7624 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
7626 len = asc_prt_line(cp, leftlen,
7627 "ftp://ftp.connectcom.net/pub\n");
7636 * Add serial number to information bar if signature AAh
7637 * is found in at bit 15-9 (7 bits) of word 1.
7639 * Serial Number consists fo 12 alpha-numeric digits.
7641 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
7642 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
7643 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
7644 * 5 - Product revision (A-J) Word0: " "
7646 * Signature Word1: 15-9 (7 bits)
7647 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
7648 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
7650 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
7652 * Note 1: Only production cards will have a serial number.
7654 * Note 2: Signature is most significant 7 bits (0xFE).
7656 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
7659 asc_get_eeprom_string(ushort *serialnum, uchar *cp)
7663 if ((serialnum[1] & 0xFE00) != ((ushort) 0xAA << 8)) {
7667 * First word - 6 digits.
7671 /* Product type - 1st digit. */
7672 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
7673 /* Product type is P=Prototype */
7678 /* Manufacturing location - 2nd digit. */
7679 *cp++ = 'A' + ((w & 0x1C00) >> 10);
7681 /* Product ID - 3rd, 4th digits. */
7683 *cp++ = '0' + (num / 100);
7685 *cp++ = '0' + (num / 10);
7687 /* Product revision - 5th digit. */
7688 *cp++ = 'A' + (num % 10);
7698 * If bit 15 of third word is set, then the
7699 * last digit of the year is greater than 7.
7701 if (serialnum[2] & 0x8000) {
7702 *cp++ = '8' + ((w & 0x1C0) >> 6);
7704 *cp++ = '0' + ((w & 0x1C0) >> 6);
7707 /* Week of year - 7th, 8th digits. */
7709 *cp++ = '0' + num / 10;
7716 w = serialnum[2] & 0x7FFF;
7718 /* Serial number - 9th digit. */
7719 *cp++ = 'A' + (w / 1000);
7721 /* 10th, 11th, 12th digits. */
7723 *cp++ = '0' + num / 100;
7725 *cp++ = '0' + num / 10;
7729 *cp = '\0'; /* Null Terminate the string. */
7735 * asc_prt_asc_board_eeprom()
7737 * Print board EEPROM configuration.
7739 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7740 * cf. asc_prt_line().
7742 * Return the number of characters copied into 'cp'. No more than
7743 * 'cplen' characters will be copied to 'cp'.
7746 asc_prt_asc_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7748 asc_board_t *boardp;
7749 ASC_DVC_VAR *asc_dvc_varp;
7756 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
7757 #endif /* CONFIG_ISA */
7758 uchar serialstr[13];
7760 boardp = ASC_BOARDP(shp);
7761 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
7762 ep = &boardp->eep_config.asc_eep;
7767 len = asc_prt_line(cp, leftlen,
7768 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7771 if (asc_get_eeprom_string((ushort *) &ep->adapter_info[0], serialstr) ==
7773 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7776 if (ep->adapter_info[5] == 0xBB) {
7777 len = asc_prt_line(cp, leftlen,
7778 " Default Settings Used for EEPROM-less Adapter.\n");
7781 len = asc_prt_line(cp, leftlen,
7782 " Serial Number Signature Not Present.\n");
7787 len = asc_prt_line(cp, leftlen,
7788 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7789 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, ep->max_tag_qng);
7792 len = asc_prt_line(cp, leftlen,
7793 " cntl 0x%x, no_scam 0x%x\n",
7794 ep->cntl, ep->no_scam);
7797 len = asc_prt_line(cp, leftlen,
7800 for (i = 0; i <= ASC_MAX_TID; i++) {
7801 len = asc_prt_line(cp, leftlen, " %d", i);
7804 len = asc_prt_line(cp, leftlen, "\n");
7807 len = asc_prt_line(cp, leftlen,
7810 for (i = 0; i <= ASC_MAX_TID; i++) {
7811 len = asc_prt_line(cp, leftlen, " %c",
7812 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7815 len = asc_prt_line(cp, leftlen, "\n");
7818 len = asc_prt_line(cp, leftlen,
7819 " Command Queuing: ");
7821 for (i = 0; i <= ASC_MAX_TID; i++) {
7822 len = asc_prt_line(cp, leftlen, " %c",
7823 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7826 len = asc_prt_line(cp, leftlen, "\n");
7829 len = asc_prt_line(cp, leftlen,
7832 for (i = 0; i <= ASC_MAX_TID; i++) {
7833 len = asc_prt_line(cp, leftlen, " %c",
7834 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7837 len = asc_prt_line(cp, leftlen, "\n");
7840 len = asc_prt_line(cp, leftlen,
7841 " Synchronous Transfer:");
7843 for (i = 0; i <= ASC_MAX_TID; i++) {
7844 len = asc_prt_line(cp, leftlen, " %c",
7845 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7848 len = asc_prt_line(cp, leftlen, "\n");
7852 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
7853 len = asc_prt_line(cp, leftlen,
7854 " Host ISA DMA speed: %d MB/S\n",
7855 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
7858 #endif /* CONFIG_ISA */
7864 * asc_prt_adv_board_eeprom()
7866 * Print board EEPROM configuration.
7868 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7869 * cf. asc_prt_line().
7871 * Return the number of characters copied into 'cp'. No more than
7872 * 'cplen' characters will be copied to 'cp'.
7875 asc_prt_adv_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7877 asc_board_t *boardp;
7878 ADV_DVC_VAR *adv_dvc_varp;
7884 uchar serialstr[13];
7885 ADVEEP_3550_CONFIG *ep_3550 = NULL;
7886 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
7887 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
7890 ushort sdtr_speed = 0;
7892 boardp = ASC_BOARDP(shp);
7893 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
7894 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7896 ep_3550 = &boardp->eep_config.adv_3550_eep;
7897 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7899 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
7902 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
7908 len = asc_prt_line(cp, leftlen,
7909 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7912 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7914 wordp = &ep_3550->serial_number_word1;
7915 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7917 wordp = &ep_38C0800->serial_number_word1;
7920 wordp = &ep_38C1600->serial_number_word1;
7923 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
7924 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7927 len = asc_prt_line(cp, leftlen,
7928 " Serial Number Signature Not Present.\n");
7932 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7934 len = asc_prt_line(cp, leftlen,
7935 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7936 ep_3550->adapter_scsi_id, ep_3550->max_host_qng,
7937 ep_3550->max_dvc_qng);
7939 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7941 len = asc_prt_line(cp, leftlen,
7942 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7943 ep_38C0800->adapter_scsi_id, ep_38C0800->max_host_qng,
7944 ep_38C0800->max_dvc_qng);
7948 len = asc_prt_line(cp, leftlen,
7949 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7950 ep_38C1600->adapter_scsi_id, ep_38C1600->max_host_qng,
7951 ep_38C1600->max_dvc_qng);
7954 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7956 word = ep_3550->termination;
7957 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7959 word = ep_38C0800->termination_lvd;
7962 word = ep_38C1600->termination_lvd;
7966 termstr = "Low Off/High Off";
7969 termstr = "Low Off/High On";
7972 termstr = "Low On/High On";
7976 termstr = "Automatic";
7980 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7982 len = asc_prt_line(cp, leftlen,
7983 " termination: %u (%s), bios_ctrl: 0x%x\n",
7984 ep_3550->termination, termstr, ep_3550->bios_ctrl);
7986 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7988 len = asc_prt_line(cp, leftlen,
7989 " termination: %u (%s), bios_ctrl: 0x%x\n",
7990 ep_38C0800->termination_lvd, termstr, ep_38C0800->bios_ctrl);
7994 len = asc_prt_line(cp, leftlen,
7995 " termination: %u (%s), bios_ctrl: 0x%x\n",
7996 ep_38C1600->termination_lvd, termstr, ep_38C1600->bios_ctrl);
8000 len = asc_prt_line(cp, leftlen,
8003 for (i = 0; i <= ADV_MAX_TID; i++) {
8004 len = asc_prt_line(cp, leftlen, " %X", i);
8007 len = asc_prt_line(cp, leftlen, "\n");
8010 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8012 word = ep_3550->disc_enable;
8013 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8015 word = ep_38C0800->disc_enable;
8018 word = ep_38C1600->disc_enable;
8020 len = asc_prt_line(cp, leftlen,
8023 for (i = 0; i <= ADV_MAX_TID; i++) {
8024 len = asc_prt_line(cp, leftlen, " %c",
8025 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8028 len = asc_prt_line(cp, leftlen, "\n");
8031 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8033 word = ep_3550->tagqng_able;
8034 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8036 word = ep_38C0800->tagqng_able;
8039 word = ep_38C1600->tagqng_able;
8041 len = asc_prt_line(cp, leftlen,
8042 " Command Queuing: ");
8044 for (i = 0; i <= ADV_MAX_TID; i++) {
8045 len = asc_prt_line(cp, leftlen, " %c",
8046 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8049 len = asc_prt_line(cp, leftlen, "\n");
8052 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8054 word = ep_3550->start_motor;
8055 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8057 word = ep_38C0800->start_motor;
8060 word = ep_38C1600->start_motor;
8062 len = asc_prt_line(cp, leftlen,
8065 for (i = 0; i <= ADV_MAX_TID; i++) {
8066 len = asc_prt_line(cp, leftlen, " %c",
8067 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8070 len = asc_prt_line(cp, leftlen, "\n");
8073 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8075 len = asc_prt_line(cp, leftlen,
8076 " Synchronous Transfer:");
8078 for (i = 0; i <= ADV_MAX_TID; i++) {
8079 len = asc_prt_line(cp, leftlen, " %c",
8080 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8083 len = asc_prt_line(cp, leftlen, "\n");
8087 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8089 len = asc_prt_line(cp, leftlen,
8090 " Ultra Transfer: ");
8092 for (i = 0; i <= ADV_MAX_TID; i++) {
8093 len = asc_prt_line(cp, leftlen, " %c",
8094 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8097 len = asc_prt_line(cp, leftlen, "\n");
8101 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8103 word = ep_3550->wdtr_able;
8104 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8106 word = ep_38C0800->wdtr_able;
8109 word = ep_38C1600->wdtr_able;
8111 len = asc_prt_line(cp, leftlen,
8112 " Wide Transfer: ");
8114 for (i = 0; i <= ADV_MAX_TID; i++) {
8115 len = asc_prt_line(cp, leftlen, " %c",
8116 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8119 len = asc_prt_line(cp, leftlen, "\n");
8122 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
8123 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600)
8125 len = asc_prt_line(cp, leftlen,
8126 " Synchronous Transfer Speed (Mhz):\n ");
8128 for (i = 0; i <= ADV_MAX_TID; i++) {
8133 sdtr_speed = adv_dvc_varp->sdtr_speed1;
8136 sdtr_speed = adv_dvc_varp->sdtr_speed2;
8139 sdtr_speed = adv_dvc_varp->sdtr_speed3;
8142 sdtr_speed = adv_dvc_varp->sdtr_speed4;
8144 switch (sdtr_speed & ADV_MAX_TID)
8146 case 0: speed_str = "Off"; break;
8147 case 1: speed_str = " 5"; break;
8148 case 2: speed_str = " 10"; break;
8149 case 3: speed_str = " 20"; break;
8150 case 4: speed_str = " 40"; break;
8151 case 5: speed_str = " 80"; break;
8152 default: speed_str = "Unk"; break;
8154 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
8158 len = asc_prt_line(cp, leftlen, "\n ");
8163 len = asc_prt_line(cp, leftlen, "\n");
8171 * asc_prt_driver_conf()
8173 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8174 * cf. asc_prt_line().
8176 * Return the number of characters copied into 'cp'. No more than
8177 * 'cplen' characters will be copied to 'cp'.
8180 asc_prt_driver_conf(struct Scsi_Host *shp, char *cp, int cplen)
8182 asc_board_t *boardp;
8188 boardp = ASC_BOARDP(shp);
8193 len = asc_prt_line(cp, leftlen,
8194 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
8198 len = asc_prt_line(cp, leftlen,
8199 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
8200 shp->host_busy, shp->last_reset, shp->max_id, shp->max_lun,
8204 len = asc_prt_line(cp, leftlen,
8205 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
8206 shp->unique_id, shp->can_queue, shp->this_id, shp->sg_tablesize,
8210 len = asc_prt_line(cp, leftlen,
8211 " unchecked_isa_dma %d, use_clustering %d\n",
8212 shp->unchecked_isa_dma, shp->use_clustering);
8215 len = asc_prt_line(cp, leftlen,
8216 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
8217 boardp->flags, boardp->last_reset, jiffies, boardp->asc_n_io_port);
8220 /* 'shp->n_io_port' may be truncated because it is only one byte. */
8221 len = asc_prt_line(cp, leftlen,
8222 " io_port 0x%x, n_io_port 0x%x\n",
8223 shp->io_port, shp->n_io_port);
8226 if (ASC_NARROW_BOARD(boardp)) {
8227 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
8229 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
8236 * asc_prt_asc_board_info()
8238 * Print dynamic board configuration information.
8240 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8241 * cf. asc_prt_line().
8243 * Return the number of characters copied into 'cp'. No more than
8244 * 'cplen' characters will be copied to 'cp'.
8247 asc_prt_asc_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8249 asc_board_t *boardp;
8257 int renegotiate = 0;
8259 boardp = ASC_BOARDP(shp);
8260 v = &boardp->dvc_var.asc_dvc_var;
8261 c = &boardp->dvc_cfg.asc_dvc_cfg;
8262 chip_scsi_id = c->chip_scsi_id;
8267 len = asc_prt_line(cp, leftlen,
8268 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8272 len = asc_prt_line(cp, leftlen,
8273 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
8274 c->chip_version, c->lib_version, c->lib_serial_no, c->mcode_date);
8277 len = asc_prt_line(cp, leftlen,
8278 " mcode_version 0x%x, err_code %u\n",
8279 c->mcode_version, v->err_code);
8282 /* Current number of commands waiting for the host. */
8283 len = asc_prt_line(cp, leftlen,
8284 " Total Command Pending: %d\n", v->cur_total_qng);
8287 len = asc_prt_line(cp, leftlen,
8288 " Command Queuing:");
8290 for (i = 0; i <= ASC_MAX_TID; i++) {
8291 if ((chip_scsi_id == i) ||
8292 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8295 len = asc_prt_line(cp, leftlen, " %X:%c",
8296 i, (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8299 len = asc_prt_line(cp, leftlen, "\n");
8302 /* Current number of commands waiting for a device. */
8303 len = asc_prt_line(cp, leftlen,
8304 " Command Queue Pending:");
8306 for (i = 0; i <= ASC_MAX_TID; i++) {
8307 if ((chip_scsi_id == i) ||
8308 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8311 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
8314 len = asc_prt_line(cp, leftlen, "\n");
8317 /* Current limit on number of commands that can be sent to a device. */
8318 len = asc_prt_line(cp, leftlen,
8319 " Command Queue Limit:");
8321 for (i = 0; i <= ASC_MAX_TID; i++) {
8322 if ((chip_scsi_id == i) ||
8323 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8326 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
8329 len = asc_prt_line(cp, leftlen, "\n");
8332 /* Indicate whether the device has returned queue full status. */
8333 len = asc_prt_line(cp, leftlen,
8334 " Command Queue Full:");
8336 for (i = 0; i <= ASC_MAX_TID; i++) {
8337 if ((chip_scsi_id == i) ||
8338 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8341 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
8342 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
8343 i, boardp->queue_full_cnt[i]);
8345 len = asc_prt_line(cp, leftlen, " %X:N", i);
8349 len = asc_prt_line(cp, leftlen, "\n");
8352 len = asc_prt_line(cp, leftlen,
8353 " Synchronous Transfer:");
8355 for (i = 0; i <= ASC_MAX_TID; i++) {
8356 if ((chip_scsi_id == i) ||
8357 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8360 len = asc_prt_line(cp, leftlen, " %X:%c",
8361 i, (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8364 len = asc_prt_line(cp, leftlen, "\n");
8367 for (i = 0; i <= ASC_MAX_TID; i++) {
8368 uchar syn_period_ix;
8370 if ((chip_scsi_id == i) ||
8371 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8372 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
8376 len = asc_prt_line(cp, leftlen, " %X:", i);
8379 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0)
8381 len = asc_prt_line(cp, leftlen, " Asynchronous");
8386 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 1);
8388 len = asc_prt_line(cp, leftlen,
8389 " Transfer Period Factor: %d (%d.%d Mhz),",
8390 v->sdtr_period_tbl[syn_period_ix],
8391 250 / v->sdtr_period_tbl[syn_period_ix],
8392 ASC_TENTHS(250, v->sdtr_period_tbl[syn_period_ix]));
8395 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8396 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
8400 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8401 len = asc_prt_line(cp, leftlen, "*\n");
8405 len = asc_prt_line(cp, leftlen, "\n");
8412 len = asc_prt_line(cp, leftlen,
8413 " * = Re-negotiation pending before next command.\n");
8421 * asc_prt_adv_board_info()
8423 * Print dynamic board configuration information.
8425 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8426 * cf. asc_prt_line().
8428 * Return the number of characters copied into 'cp'. No more than
8429 * 'cplen' characters will be copied to 'cp'.
8432 asc_prt_adv_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8434 asc_board_t *boardp;
8441 AdvPortAddr iop_base;
8442 ushort chip_scsi_id;
8446 ushort sdtr_able, wdtr_able;
8447 ushort wdtr_done, sdtr_done;
8449 int renegotiate = 0;
8451 boardp = ASC_BOARDP(shp);
8452 v = &boardp->dvc_var.adv_dvc_var;
8453 c = &boardp->dvc_cfg.adv_dvc_cfg;
8454 iop_base = v->iop_base;
8455 chip_scsi_id = v->chip_scsi_id;
8460 len = asc_prt_line(cp, leftlen,
8461 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8465 len = asc_prt_line(cp, leftlen,
8466 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
8468 AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1) & CABLE_DETECT,
8472 len = asc_prt_line(cp, leftlen,
8473 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
8474 c->chip_version, c->lib_version, c->mcode_date, c->mcode_version);
8477 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8478 len = asc_prt_line(cp, leftlen,
8479 " Queuing Enabled:");
8481 for (i = 0; i <= ADV_MAX_TID; i++) {
8482 if ((chip_scsi_id == i) ||
8483 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8487 len = asc_prt_line(cp, leftlen, " %X:%c",
8488 i, (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8491 len = asc_prt_line(cp, leftlen, "\n");
8494 len = asc_prt_line(cp, leftlen,
8497 for (i = 0; i <= ADV_MAX_TID; i++) {
8498 if ((chip_scsi_id == i) ||
8499 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8503 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, lrambyte);
8505 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8508 len = asc_prt_line(cp, leftlen, "\n");
8511 len = asc_prt_line(cp, leftlen,
8512 " Command Pending:");
8514 for (i = 0; i <= ADV_MAX_TID; i++) {
8515 if ((chip_scsi_id == i) ||
8516 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8520 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, lrambyte);
8522 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8525 len = asc_prt_line(cp, leftlen, "\n");
8528 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8529 len = asc_prt_line(cp, leftlen,
8532 for (i = 0; i <= ADV_MAX_TID; i++) {
8533 if ((chip_scsi_id == i) ||
8534 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8538 len = asc_prt_line(cp, leftlen, " %X:%c",
8539 i, (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8542 len = asc_prt_line(cp, leftlen, "\n");
8545 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
8546 len = asc_prt_line(cp, leftlen,
8547 " Transfer Bit Width:");
8549 for (i = 0; i <= ADV_MAX_TID; i++) {
8550 if ((chip_scsi_id == i) ||
8551 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8555 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8558 len = asc_prt_line(cp, leftlen, " %X:%d",
8559 i, (lramword & 0x8000) ? 16 : 8);
8562 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
8563 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8564 len = asc_prt_line(cp, leftlen, "*");
8569 len = asc_prt_line(cp, leftlen, "\n");
8572 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8573 len = asc_prt_line(cp, leftlen,
8574 " Synchronous Enabled:");
8576 for (i = 0; i <= ADV_MAX_TID; i++) {
8577 if ((chip_scsi_id == i) ||
8578 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8582 len = asc_prt_line(cp, leftlen, " %X:%c",
8583 i, (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8586 len = asc_prt_line(cp, leftlen, "\n");
8589 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
8590 for (i = 0; i <= ADV_MAX_TID; i++) {
8592 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8594 lramword &= ~0x8000;
8596 if ((chip_scsi_id == i) ||
8597 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8598 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
8602 len = asc_prt_line(cp, leftlen, " %X:", i);
8605 if ((lramword & 0x1F) == 0) /* Check for REQ/ACK Offset 0. */
8607 len = asc_prt_line(cp, leftlen, " Asynchronous");
8611 len = asc_prt_line(cp, leftlen, " Transfer Period Factor: ");
8614 if ((lramword & 0x1F00) == 0x1100) /* 80 Mhz */
8616 len = asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
8618 } else if ((lramword & 0x1F00) == 0x1000) /* 40 Mhz */
8620 len = asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
8622 } else /* 20 Mhz or below. */
8624 period = (((lramword >> 8) * 25) + 50)/4;
8626 if (period == 0) /* Should never happen. */
8628 len = asc_prt_line(cp, leftlen, "%d (? Mhz), ");
8632 len = asc_prt_line(cp, leftlen,
8634 period, 250/period, ASC_TENTHS(250, period));
8639 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8644 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8645 len = asc_prt_line(cp, leftlen, "*\n");
8649 len = asc_prt_line(cp, leftlen, "\n");
8656 len = asc_prt_line(cp, leftlen,
8657 " * = Re-negotiation pending before next command.\n");
8667 * Copy proc information to a read buffer taking into account the current
8668 * read offset in the file and the remaining space in the read buffer.
8671 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
8672 char *cp, int cplen)
8676 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
8677 (unsigned) offset, (unsigned) advoffset, cplen);
8678 if (offset <= advoffset) {
8679 /* Read offset below current offset, copy everything. */
8680 cnt = min(cplen, leftlen);
8681 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8682 (ulong) curbuf, (ulong) cp, cnt);
8683 memcpy(curbuf, cp, cnt);
8684 } else if (offset < advoffset + cplen) {
8685 /* Read offset within current range, partial copy. */
8686 cnt = (advoffset + cplen) - offset;
8687 cp = (cp + cplen) - cnt;
8688 cnt = min(cnt, leftlen);
8689 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8690 (ulong) curbuf, (ulong) cp, cnt);
8691 memcpy(curbuf, cp, cnt);
8699 * If 'cp' is NULL print to the console, otherwise print to a buffer.
8701 * Return 0 if printing to the console, otherwise return the number of
8702 * bytes written to the buffer.
8704 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
8705 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
8708 asc_prt_line(char *buf, int buflen, char *fmt, ...)
8712 char s[ASC_PRTLINE_SIZE];
8714 va_start(args, fmt);
8715 ret = vsprintf(s, fmt, args);
8716 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
8721 ret = min(buflen, ret);
8722 memcpy(buf, s, ret);
8727 #endif /* CONFIG_PROC_FS */
8731 * --- Functions Required by the Asc Library
8735 * Delay for 'n' milliseconds. Don't use the 'jiffies'
8736 * global variable which is incremented once every 5 ms
8737 * from a timer interrupt, because this function may be
8738 * called when interrupts are disabled.
8741 DvcSleepMilliSecond(ADV_DCNT n)
8743 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
8748 * Currently and inline noop but leave as a placeholder.
8749 * Leave DvcEnterCritical() as a noop placeholder.
8752 DvcEnterCritical(void)
8758 * Critical sections are all protected by the board spinlock.
8759 * Leave DvcLeaveCritical() as a noop placeholder.
8762 DvcLeaveCritical(ulong flags)
8769 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8771 * Calling/Exit State:
8775 * Output an ASC_SCSI_Q structure to the chip
8778 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8782 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8783 AscSetChipLramAddr(iop_base, s_addr);
8784 for (i = 0; i < 2 * words; i += 2) {
8785 if (i == 4 || i == 20) {
8788 outpw(iop_base + IOP_RAM_DATA,
8789 ((ushort) outbuf[i + 1] << 8) | outbuf[i]);
8795 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8797 * Calling/Exit State:
8801 * Input an ASC_QDONE_INFO structure from the chip
8804 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8809 AscSetChipLramAddr(iop_base, s_addr);
8810 for (i = 0; i < 2 * words; i += 2) {
8814 word = inpw(iop_base + IOP_RAM_DATA);
8815 inbuf[i] = word & 0xff;
8816 inbuf[i + 1] = (word >> 8) & 0xff;
8818 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
8822 * Read a PCI configuration byte.
8825 DvcReadPCIConfigByte(
8826 ASC_DVC_VAR *asc_dvc,
8831 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8833 #else /* !defined(CONFIG_PCI) */
8835 #endif /* !defined(CONFIG_PCI) */
8839 * Write a PCI configuration byte.
8842 DvcWritePCIConfigByte(
8843 ASC_DVC_VAR *asc_dvc,
8848 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8849 #endif /* CONFIG_PCI */
8853 * Return the BIOS address of the adapter at the specified
8854 * I/O port and with the specified bus type.
8856 STATIC ushort __init
8857 AscGetChipBiosAddress(
8865 * The PCI BIOS is re-located by the motherboard BIOS. Because
8866 * of this the driver can not determine where a PCI BIOS is
8867 * loaded and executes.
8869 if (bus_type & ASC_IS_PCI)
8875 if((bus_type & ASC_IS_EISA) != 0)
8877 cfg_lsw = AscGetEisaChipCfg(iop_base);
8879 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
8880 (cfg_lsw * ASC_BIOS_BANK_SIZE));
8883 #endif /* CONFIG_ISA */
8885 cfg_lsw = AscGetChipCfgLsw(iop_base);
8888 * ISA PnP uses the top bit as the 32K BIOS flag
8890 if (bus_type == ASC_IS_ISAPNP)
8895 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
8902 * --- Functions Required by the Adv Library
8908 * Return the physical address of 'vaddr' and set '*lenp' to the
8909 * number of physically contiguous bytes that follow 'vaddr'.
8910 * 'flag' indicates the type of structure whose physical address
8911 * is being translated.
8913 * Note: Because Linux currently doesn't page the kernel and all
8914 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
8917 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
8918 uchar *vaddr, ADV_SDCNT *lenp, int flag)
8922 paddr = virt_to_bus(vaddr);
8925 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
8926 (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
8932 * Read a PCI configuration byte.
8935 DvcAdvReadPCIConfigByte(
8936 ADV_DVC_VAR *asc_dvc,
8941 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8943 #else /* CONFIG_PCI */
8945 #endif /* CONFIG_PCI */
8949 * Write a PCI configuration byte.
8952 DvcAdvWritePCIConfigByte(
8953 ADV_DVC_VAR *asc_dvc,
8958 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8959 #else /* CONFIG_PCI */
8961 #endif /* CONFIG_PCI */
8965 * --- Tracing and Debugging Functions
8968 #ifdef ADVANSYS_STATS
8969 #ifdef CONFIG_PROC_FS
8971 * asc_prt_board_stats()
8973 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8974 * cf. asc_prt_line().
8976 * Return the number of characters copied into 'cp'. No more than
8977 * 'cplen' characters will be copied to 'cp'.
8980 asc_prt_board_stats(struct Scsi_Host *shp, char *cp, int cplen)
8985 struct asc_stats *s;
8986 asc_board_t *boardp;
8991 boardp = ASC_BOARDP(shp);
8992 s = &boardp->asc_stats;
8994 len = asc_prt_line(cp, leftlen,
8995 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", shp->host_no);
8998 len = asc_prt_line(cp, leftlen,
8999 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
9000 s->queuecommand, s->reset, s->biosparam, s->interrupt);
9003 len = asc_prt_line(cp, leftlen,
9004 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
9005 s->callback, s->done, s->build_error, s->adv_build_noreq,
9009 len = asc_prt_line(cp, leftlen,
9010 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
9011 s->exe_noerror, s->exe_busy, s->exe_error, s->exe_unknown);
9015 * Display data transfer statistics.
9017 if (s->cont_cnt > 0) {
9018 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
9021 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
9023 ASC_TENTHS(s->cont_xfer, 2));
9026 /* Contiguous transfer average size */
9027 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
9028 (s->cont_xfer/2)/s->cont_cnt,
9029 ASC_TENTHS((s->cont_xfer/2), s->cont_cnt));
9033 if (s->sg_cnt > 0) {
9035 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
9036 s->sg_cnt, s->sg_elem);
9039 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
9041 ASC_TENTHS(s->sg_xfer, 2));
9044 /* Scatter gather transfer statistics */
9045 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
9046 s->sg_elem/s->sg_cnt,
9047 ASC_TENTHS(s->sg_elem, s->sg_cnt));
9050 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
9051 (s->sg_xfer/2)/s->sg_elem,
9052 ASC_TENTHS((s->sg_xfer/2), s->sg_elem));
9055 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
9056 (s->sg_xfer/2)/s->sg_cnt,
9057 ASC_TENTHS((s->sg_xfer/2), s->sg_cnt));
9062 * Display request queuing statistics.
9064 len = asc_prt_line(cp, leftlen,
9065 " Active and Waiting Request Queues (Time Unit: %d HZ):\n", HZ);
9073 * asc_prt_target_stats()
9075 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
9076 * cf. asc_prt_line().
9078 * This is separated from asc_prt_board_stats because a full set
9079 * of targets will overflow ASC_PRTBUF_SIZE.
9081 * Return the number of characters copied into 'cp'. No more than
9082 * 'cplen' characters will be copied to 'cp'.
9085 asc_prt_target_stats(struct Scsi_Host *shp, int tgt_id, char *cp, int cplen)
9090 struct asc_stats *s;
9091 ushort chip_scsi_id;
9092 asc_board_t *boardp;
9093 asc_queue_t *active;
9094 asc_queue_t *waiting;
9099 boardp = ASC_BOARDP(shp);
9100 s = &boardp->asc_stats;
9102 active = &ASC_BOARDP(shp)->active;
9103 waiting = &ASC_BOARDP(shp)->waiting;
9105 if (ASC_NARROW_BOARD(boardp)) {
9106 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
9108 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
9111 if ((chip_scsi_id == tgt_id) ||
9112 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
9117 if (active->q_tot_cnt[tgt_id] > 0 || waiting->q_tot_cnt[tgt_id] > 0) {
9118 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
9121 len = asc_prt_line(cp, leftlen,
9122 " active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
9123 active->q_cur_cnt[tgt_id], active->q_max_cnt[tgt_id],
9124 active->q_tot_cnt[tgt_id],
9125 active->q_min_tim[tgt_id], active->q_max_tim[tgt_id],
9126 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9127 (active->q_tot_tim[tgt_id]/active->q_tot_cnt[tgt_id]),
9128 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9129 ASC_TENTHS(active->q_tot_tim[tgt_id],
9130 active->q_tot_cnt[tgt_id]));
9133 len = asc_prt_line(cp, leftlen,
9134 " waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
9135 waiting->q_cur_cnt[tgt_id], waiting->q_max_cnt[tgt_id],
9136 waiting->q_tot_cnt[tgt_id],
9137 waiting->q_min_tim[tgt_id], waiting->q_max_tim[tgt_id],
9138 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9139 (waiting->q_tot_tim[tgt_id]/waiting->q_tot_cnt[tgt_id]),
9140 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9141 ASC_TENTHS(waiting->q_tot_tim[tgt_id],
9142 waiting->q_tot_cnt[tgt_id]));
9149 #endif /* CONFIG_PROC_FS */
9150 #endif /* ADVANSYS_STATS */
9152 #ifdef ADVANSYS_DEBUG
9154 * asc_prt_scsi_host()
9157 asc_prt_scsi_host(struct Scsi_Host *s)
9159 asc_board_t *boardp;
9161 boardp = ASC_BOARDP(s);
9163 printk("Scsi_Host at addr 0x%lx\n", (ulong) s);
9165 " host_busy %u, host_no %d, last_reset %d,\n",
9166 s->host_busy, s->host_no,
9167 (unsigned) s->last_reset);
9170 " base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
9171 (ulong) s->base, (ulong) s->io_port, s->n_io_port, s->irq);
9174 " dma_channel %d, this_id %d, can_queue %d,\n",
9175 s->dma_channel, s->this_id, s->can_queue);
9178 " cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
9179 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
9181 if (ASC_NARROW_BOARD(boardp)) {
9182 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
9183 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
9185 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
9186 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
9191 * asc_prt_scsi_cmnd()
9194 asc_prt_scsi_cmnd(struct scsi_cmnd *s)
9196 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong) s);
9199 " host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
9200 (ulong) s->device->host, (ulong) s->device, s->device->id, s->device->lun,
9201 s->device->channel);
9203 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
9206 "sc_data_direction %u, resid %d\n",
9207 s->sc_data_direction, s->resid);
9210 " use_sg %u, sglist_len %u, abort_reason 0x%x\n",
9211 s->use_sg, s->sglist_len, s->abort_reason);
9214 " serial_number 0x%x, serial_number_at_timeout 0x%x, retries %d, allowed %d\n",
9215 (unsigned) s->serial_number, (unsigned) s->serial_number_at_timeout,
9216 s->retries, s->allowed);
9219 " timeout_per_command %d, timeout_total %d, timeout %d\n",
9220 s->timeout_per_command, s->timeout_total, s->timeout);
9222 printk(" internal_timeout %u\n", s->internal_timeout);
9225 " scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
9226 (ulong) s->scsi_done, (ulong) s->done,
9227 (ulong) s->host_scribble, s->result);
9230 " tag %u, pid %u\n",
9231 (unsigned) s->tag, (unsigned) s->pid);
9235 * asc_prt_asc_dvc_var()
9238 asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
9240 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong) h);
9243 " iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
9244 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
9247 " bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
9248 h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
9249 (unsigned) h->init_sdtr);
9252 " sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
9253 (unsigned) h->sdtr_done, (unsigned) h->use_tagged_qng,
9254 (unsigned) h->unit_not_ready, (unsigned) h->chip_no);
9257 " queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
9258 (unsigned) h->queue_full_or_busy, (unsigned) h->start_motor,
9259 (unsigned) h->scsi_reset_wait);
9262 " is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
9263 (unsigned) h->is_in_int, (unsigned) h->max_total_qng,
9264 (unsigned) h->cur_total_qng, (unsigned) h->in_critical_cnt);
9267 " last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
9268 (unsigned) h->last_q_shortage, (unsigned) h->init_state,
9269 (unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
9272 " cfg 0x%lx, irq_no 0x%x\n",
9273 (ulong) h->cfg, (unsigned) h->irq_no);
9277 * asc_prt_asc_dvc_cfg()
9280 asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
9282 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong) h);
9285 " can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
9286 h->can_tagged_qng, h->cmd_qng_enabled);
9288 " disc_enable 0x%x, sdtr_enable 0x%x,\n",
9289 h->disc_enable, h->sdtr_enable);
9292 " chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
9293 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
9297 " pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
9298 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
9302 " mcode_version %d, overrun_buf 0x%lx\n",
9303 h->mcode_version, (ulong) h->overrun_buf);
9307 * asc_prt_asc_scsi_q()
9310 asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
9315 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong) q);
9318 " target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
9319 q->q2.target_ix, q->q1.target_lun,
9320 (ulong) q->q2.srb_ptr, q->q2.tag_code);
9323 " data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9324 (ulong) le32_to_cpu(q->q1.data_addr),
9325 (ulong) le32_to_cpu(q->q1.data_cnt),
9326 (ulong) le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
9329 " cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
9330 (ulong) q->cdbptr, q->q2.cdb_len,
9331 (ulong) q->sg_head, q->q1.sg_queue_cnt);
9335 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong) sgp);
9336 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
9337 for (i = 0; i < sgp->entry_cnt; i++) {
9338 printk(" [%u]: addr 0x%lx, bytes %lu\n",
9339 i, (ulong) le32_to_cpu(sgp->sg_list[i].addr),
9340 (ulong) le32_to_cpu(sgp->sg_list[i].bytes));
9347 * asc_prt_asc_qdone_info()
9350 asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
9352 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong) q);
9354 " srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
9355 (ulong) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
9358 " done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
9359 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
9363 * asc_prt_adv_dvc_var()
9365 * Display an ADV_DVC_VAR structure.
9368 asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
9370 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong) h);
9373 " iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
9374 (ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
9377 " isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
9378 (ulong) h->isr_callback, (unsigned) h->sdtr_able,
9379 (unsigned) h->wdtr_able);
9382 " start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
9383 (unsigned) h->start_motor,
9384 (unsigned) h->scsi_reset_wait, (unsigned) h->irq_no);
9387 " max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
9388 (unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
9389 (ulong) h->carr_freelist);
9392 " icq_sp 0x%lx, irq_sp 0x%lx\n",
9393 (ulong) h->icq_sp, (ulong) h->irq_sp);
9396 " no_scam 0x%x, tagqng_able 0x%x\n",
9397 (unsigned) h->no_scam, (unsigned) h->tagqng_able);
9400 " chip_scsi_id 0x%x, cfg 0x%lx\n",
9401 (unsigned) h->chip_scsi_id, (ulong) h->cfg);
9405 * asc_prt_adv_dvc_cfg()
9407 * Display an ADV_DVC_CFG structure.
9410 asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
9412 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong) h);
9415 " disc_enable 0x%x, termination 0x%x\n",
9416 h->disc_enable, h->termination);
9419 " chip_version 0x%x, mcode_date 0x%x\n",
9420 h->chip_version, h->mcode_date);
9423 " mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
9424 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
9427 " control_flag 0x%x, pci_slot_info 0x%x\n",
9428 h->control_flag, h->pci_slot_info);
9432 * asc_prt_adv_scsi_req_q()
9434 * Display an ADV_SCSI_REQ_Q structure.
9437 asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
9440 struct asc_sg_block *sg_ptr;
9442 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong) q);
9445 " target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
9446 q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
9448 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
9449 q->cntl, (ulong) le32_to_cpu(q->data_addr), (ulong) q->vdata_addr);
9452 " data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9453 (ulong) le32_to_cpu(q->data_cnt),
9454 (ulong) le32_to_cpu(q->sense_addr), q->sense_len);
9457 " cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
9458 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
9461 " sg_working_ix 0x%x, target_cmd %u\n",
9462 q->sg_working_ix, q->target_cmd);
9465 " scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
9466 (ulong) le32_to_cpu(q->scsiq_rptr),
9467 (ulong) le32_to_cpu(q->sg_real_addr), (ulong) q->sg_list_ptr);
9469 /* Display the request's ADV_SG_BLOCK structures. */
9470 if (q->sg_list_ptr != NULL)
9475 * 'sg_ptr' is a physical address. Convert it to a virtual
9476 * address by indexing 'sg_blk_cnt' into the virtual address
9477 * array 'sg_list_ptr'.
9479 * XXX - Assumes all SG physical blocks are virtually contiguous.
9481 sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
9482 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
9483 if (sg_ptr->sg_ptr == 0)
9493 * asc_prt_adv_sgblock()
9495 * Display an ADV_SG_BLOCK structure.
9498 asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
9502 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
9503 (ulong) b, sgblockno);
9504 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
9505 b->sg_cnt, (ulong) le32_to_cpu(b->sg_ptr));
9506 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
9509 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
9511 for (i = 0; i < b->sg_cnt; i++) {
9512 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
9513 i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
9520 * Print hexadecimal output in 4 byte groupings 32 bytes
9521 * or 8 double-words per line.
9524 asc_prt_hex(char *f, uchar *s, int l)
9531 printk("%s: (%d bytes)\n", f, l);
9533 for (i = 0; i < l; i += 32) {
9535 /* Display a maximum of 8 double-words per line. */
9536 if ((k = (l - i) / 4) >= 8) {
9543 for (j = 0; j < k; j++) {
9544 printk(" %2.2X%2.2X%2.2X%2.2X",
9545 (unsigned) s[i+(j*4)], (unsigned) s[i+(j*4)+1],
9546 (unsigned) s[i+(j*4)+2], (unsigned) s[i+(j*4)+3]);
9555 (unsigned) s[i+(j*4)]);
9558 printk(" %2.2X%2.2X",
9559 (unsigned) s[i+(j*4)],
9560 (unsigned) s[i+(j*4)+1]);
9563 printk(" %2.2X%2.2X%2.2X",
9564 (unsigned) s[i+(j*4)+1],
9565 (unsigned) s[i+(j*4)+2],
9566 (unsigned) s[i+(j*4)+3]);
9573 #endif /* ADVANSYS_DEBUG */
9576 * --- Asc Library Functions
9579 STATIC ushort __init
9583 PortAddr eisa_cfg_iop;
9585 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9586 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9587 return (inpw(eisa_cfg_iop));
9598 if (AscGetChipScsiID(iop_base) == new_host_id) {
9599 return (new_host_id);
9601 cfg_lsw = AscGetChipCfgLsw(iop_base);
9603 cfg_lsw |= (ushort) ((new_host_id & ASC_MAX_TID) << 8);
9604 AscSetChipCfgLsw(iop_base, cfg_lsw);
9605 return (AscGetChipScsiID(iop_base));
9614 AscSetBank(iop_base, 1);
9615 sc = inp(iop_base + IOP_REG_SC);
9616 AscSetBank(iop_base, 0);
9626 if ((bus_type & ASC_IS_EISA) != 0) {
9629 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9630 (PortAddr) ASC_EISA_REV_IOP_MASK;
9631 revision = inp(eisa_iop);
9632 return ((uchar) ((ASC_CHIP_MIN_VER_EISA - 1) + revision));
9634 return (AscGetChipVerNo(iop_base));
9637 STATIC ushort __init
9643 chip_ver = AscGetChipVerNo(iop_base);
9645 (chip_ver >= ASC_CHIP_MIN_VER_VL)
9646 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
9649 ((iop_base & 0x0C30) == 0x0C30)
9650 || ((iop_base & 0x0C50) == 0x0C50)
9652 return (ASC_IS_EISA);
9656 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
9657 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
9658 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
9659 return (ASC_IS_ISAPNP);
9661 return (ASC_IS_ISA);
9662 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
9663 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
9664 return (ASC_IS_PCI);
9678 ushort mcode_word_size;
9679 ushort mcode_chksum;
9681 /* Write the microcode buffer starting at LRAM address 0. */
9682 mcode_word_size = (ushort) (mcode_size >> 1);
9683 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
9684 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
9686 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
9687 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong) chksum);
9688 mcode_chksum = (ushort) AscMemSumLramWord(iop_base,
9689 (ushort) ASC_CODE_SEC_BEG,
9690 (ushort) ((mcode_size - s_addr - (ushort) ASC_CODE_SEC_BEG) / 2));
9691 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
9692 (ulong) mcode_chksum);
9693 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
9694 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
9705 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
9706 iop_base, AscGetChipSignatureByte(iop_base));
9707 if (AscGetChipSignatureByte(iop_base) == (uchar) ASC_1000_ID1B) {
9708 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
9709 iop_base, AscGetChipSignatureWord(iop_base));
9710 sig_word = AscGetChipSignatureWord(iop_base);
9711 if ((sig_word == (ushort) ASC_1000_ID0W) ||
9712 (sig_word == (ushort) ASC_1000_ID0W_FIX)) {
9719 STATIC PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata =
9721 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
9722 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
9726 STATIC uchar _isa_pnp_inited __initdata = 0;
9728 STATIC PortAddr __init
9729 AscSearchIOPortAddr(
9733 if (bus_type & ASC_IS_VL) {
9734 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9735 if (AscGetChipVersion(iop_beg, bus_type) <= ASC_CHIP_MAX_VER_VL) {
9741 if (bus_type & ASC_IS_ISA) {
9742 if (_isa_pnp_inited == 0) {
9743 AscSetISAPNPWaitForKey();
9746 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9747 if ((AscGetChipVersion(iop_beg, bus_type) & ASC_CHIP_VER_ISA_BIT) != 0) {
9753 if (bus_type & ASC_IS_EISA) {
9754 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
9762 STATIC PortAddr __init
9763 AscSearchIOPortAddr11(
9770 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9771 if (_asc_def_iop_base[i] > s_addr) {
9775 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9776 iop_base = _asc_def_iop_base[i];
9777 if (check_region(iop_base, ASC_IOADR_GAP) != 0) {
9779 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
9783 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n", iop_base);
9784 if (AscFindSignature(iop_base)) {
9792 AscSetISAPNPWaitForKey(void)
9794 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
9795 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
9798 #endif /* CONFIG_ISA */
9805 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
9806 AscSetChipStatus(iop_base, 0);
9818 if ((bus_type & ASC_IS_EISA) != 0) {
9819 cfg_lsw = AscGetEisaChipCfg(iop_base);
9820 chip_irq = (uchar) (((cfg_lsw >> 8) & 0x07) + 10);
9821 if ((chip_irq == 13) || (chip_irq > 15)) {
9826 if ((bus_type & ASC_IS_VL) != 0) {
9827 cfg_lsw = AscGetChipCfgLsw(iop_base);
9828 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x07));
9829 if ((chip_irq == 0) ||
9834 return ((uchar) (chip_irq + (ASC_MIN_IRQ_NO - 1)));
9836 cfg_lsw = AscGetChipCfgLsw(iop_base);
9837 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x03));
9839 chip_irq += (uchar) 2;
9840 return ((uchar) (chip_irq + ASC_MIN_IRQ_NO));
9851 if ((bus_type & ASC_IS_VL) != 0) {
9853 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) {
9856 irq_no -= (uchar) ((ASC_MIN_IRQ_NO - 1));
9859 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE3);
9860 cfg_lsw |= (ushort) 0x0010;
9861 AscSetChipCfgLsw(iop_base, cfg_lsw);
9862 AscToggleIRQAct(iop_base);
9863 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE0);
9864 cfg_lsw |= (ushort) ((irq_no & 0x07) << 2);
9865 AscSetChipCfgLsw(iop_base, cfg_lsw);
9866 AscToggleIRQAct(iop_base);
9867 return (AscGetChipIRQ(iop_base, bus_type));
9869 if ((bus_type & (ASC_IS_ISA)) != 0) {
9871 irq_no -= (uchar) 2;
9872 irq_no -= (uchar) ASC_MIN_IRQ_NO;
9873 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFF3);
9874 cfg_lsw |= (ushort) ((irq_no & 0x03) << 2);
9875 AscSetChipCfgLsw(iop_base, cfg_lsw);
9876 return (AscGetChipIRQ(iop_base, bus_type));
9886 if (dma_channel < 4) {
9887 outp(0x000B, (ushort) (0xC0 | dma_channel));
9888 outp(0x000A, dma_channel);
9889 } else if (dma_channel < 8) {
9890 outp(0x00D6, (ushort) (0xC0 | (dma_channel - 4)));
9891 outp(0x00D4, (ushort) (dma_channel - 4));
9895 #endif /* CONFIG_ISA */
9899 ASC_DVC_VAR *asc_dvc
9906 ushort int_halt_code;
9907 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9908 ASC_SCSI_BIT_ID_TYPE target_id;
9915 uchar q_cntl, tid_no;
9919 asc_board_t *boardp;
9921 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
9922 boardp = asc_dvc->drv_ptr;
9924 iop_base = asc_dvc->iop_base;
9925 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
9927 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
9928 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
9929 target_ix = AscReadLramByte(iop_base,
9930 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TARGET_IX));
9931 q_cntl = AscReadLramByte(iop_base,
9932 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL));
9933 tid_no = ASC_TIX_TO_TID(target_ix);
9934 target_id = (uchar) ASC_TID_TO_TARGET_ID(tid_no);
9935 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9936 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
9940 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
9941 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9942 AscSetChipSDTR(iop_base, 0, tid_no);
9943 boardp->sdtr_data[tid_no] = 0;
9945 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9947 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
9948 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9949 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9950 boardp->sdtr_data[tid_no] = asyn_sdtr;
9952 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9954 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
9956 AscMemWordCopyPtrFromLram(iop_base,
9959 sizeof(EXT_MSG) >> 1);
9961 if (ext_msg.msg_type == MS_EXTEND &&
9962 ext_msg.msg_req == MS_SDTR_CODE &&
9963 ext_msg.msg_len == MS_SDTR_LEN) {
9965 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
9967 sdtr_accept = FALSE;
9968 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
9970 if ((ext_msg.xfer_period <
9971 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index]) ||
9972 (ext_msg.xfer_period >
9973 asc_dvc->sdtr_period_tbl[asc_dvc->max_sdtr_index])) {
9974 sdtr_accept = FALSE;
9975 ext_msg.xfer_period =
9976 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index];
9979 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9980 ext_msg.req_ack_offset);
9981 if ((sdtr_data == 0xFF)) {
9983 q_cntl |= QC_MSG_OUT;
9984 asc_dvc->init_sdtr &= ~target_id;
9985 asc_dvc->sdtr_done &= ~target_id;
9986 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9987 boardp->sdtr_data[tid_no] = asyn_sdtr;
9990 if (ext_msg.req_ack_offset == 0) {
9992 q_cntl &= ~QC_MSG_OUT;
9993 asc_dvc->init_sdtr &= ~target_id;
9994 asc_dvc->sdtr_done &= ~target_id;
9995 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9997 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
9999 q_cntl &= ~QC_MSG_OUT;
10000 asc_dvc->sdtr_done |= target_id;
10001 asc_dvc->init_sdtr |= target_id;
10002 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
10003 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
10004 ext_msg.req_ack_offset);
10005 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
10006 boardp->sdtr_data[tid_no] = sdtr_data;
10009 q_cntl |= QC_MSG_OUT;
10010 AscMsgOutSDTR(asc_dvc,
10011 ext_msg.xfer_period,
10012 ext_msg.req_ack_offset);
10013 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
10014 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
10015 ext_msg.req_ack_offset);
10016 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
10017 boardp->sdtr_data[tid_no] = sdtr_data;
10018 asc_dvc->sdtr_done |= target_id;
10019 asc_dvc->init_sdtr |= target_id;
10023 AscWriteLramByte(iop_base,
10024 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10026 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10028 } else if (ext_msg.msg_type == MS_EXTEND &&
10029 ext_msg.msg_req == MS_WDTR_CODE &&
10030 ext_msg.msg_len == MS_WDTR_LEN) {
10032 ext_msg.wdtr_width = 0;
10033 AscMemWordCopyPtrToLram(iop_base,
10035 (uchar *) &ext_msg,
10036 sizeof(EXT_MSG) >> 1);
10037 q_cntl |= QC_MSG_OUT;
10038 AscWriteLramByte(iop_base,
10039 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10041 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10045 ext_msg.msg_type = MESSAGE_REJECT;
10046 AscMemWordCopyPtrToLram(iop_base,
10048 (uchar *) &ext_msg,
10049 sizeof(EXT_MSG) >> 1);
10050 q_cntl |= QC_MSG_OUT;
10051 AscWriteLramByte(iop_base,
10052 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10054 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10057 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
10059 q_cntl |= QC_REQ_SENSE;
10061 if ((asc_dvc->init_sdtr & target_id) != 0) {
10063 asc_dvc->sdtr_done &= ~target_id;
10065 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10066 q_cntl |= QC_MSG_OUT;
10067 AscMsgOutSDTR(asc_dvc,
10068 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10069 (uchar) (asc_dvc->max_sdtr_index - 1)],
10070 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10073 AscWriteLramByte(iop_base,
10074 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10077 tag_code = AscReadLramByte(iop_base,
10078 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE));
10081 (asc_dvc->pci_fix_asyn_xfer & target_id)
10082 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
10085 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
10086 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
10089 AscWriteLramByte(iop_base,
10090 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE),
10093 q_status = AscReadLramByte(iop_base,
10094 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10095 q_status |= (QS_READY | QS_BUSY);
10096 AscWriteLramByte(iop_base,
10097 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10100 scsi_busy = AscReadLramByte(iop_base,
10101 (ushort) ASCV_SCSIBUSY_B);
10102 scsi_busy &= ~target_id;
10103 AscWriteLramByte(iop_base, (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10105 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10107 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
10109 AscMemWordCopyPtrFromLram(iop_base,
10111 (uchar *) &out_msg,
10112 sizeof(EXT_MSG) >> 1);
10114 if ((out_msg.msg_type == MS_EXTEND) &&
10115 (out_msg.msg_len == MS_SDTR_LEN) &&
10116 (out_msg.msg_req == MS_SDTR_CODE)) {
10118 asc_dvc->init_sdtr &= ~target_id;
10119 asc_dvc->sdtr_done &= ~target_id;
10120 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
10121 boardp->sdtr_data[tid_no] = asyn_sdtr;
10123 q_cntl &= ~QC_MSG_OUT;
10124 AscWriteLramByte(iop_base,
10125 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10127 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10129 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
10131 scsi_status = AscReadLramByte(iop_base,
10132 (ushort) ((ushort) halt_q_addr + (ushort) ASC_SCSIQ_SCSI_STATUS));
10133 cur_dvc_qng = AscReadLramByte(iop_base,
10134 (ushort) ((ushort) ASC_QADR_BEG + (ushort) target_ix));
10135 if ((cur_dvc_qng > 0) &&
10136 (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
10138 scsi_busy = AscReadLramByte(iop_base,
10139 (ushort) ASCV_SCSIBUSY_B);
10140 scsi_busy |= target_id;
10141 AscWriteLramByte(iop_base,
10142 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10143 asc_dvc->queue_full_or_busy |= target_id;
10145 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
10146 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
10148 asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng;
10150 AscWriteLramByte(iop_base,
10151 (ushort) ((ushort) ASCV_MAX_DVC_QNG_BEG +
10156 * Set the device queue depth to the number of
10157 * active requests when the QUEUE FULL condition
10160 boardp->queue_full |= target_id;
10161 boardp->queue_full_cnt[tid_no] = cur_dvc_qng;
10165 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10168 #if CC_VERY_LONG_SG_LIST
10169 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
10174 uchar first_sg_wk_q_no;
10175 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
10176 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
10177 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
10178 ushort sg_list_dwords;
10179 ushort sg_entry_cnt;
10183 q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
10184 if (q_no == ASC_QLINK_END)
10189 q_addr = ASC_QNO_TO_QADDR(q_no);
10192 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
10193 * structure pointer using a macro provided by the driver.
10194 * The ASC_SCSI_REQ pointer provides a pointer to the
10195 * host ASC_SG_HEAD structure.
10197 /* Read request's SRB pointer. */
10198 scsiq = (ASC_SCSI_Q *)
10200 ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
10201 (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
10204 * Get request's first and working SG queue.
10206 sg_wk_q_no = AscReadLramByte(iop_base,
10207 (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
10209 first_sg_wk_q_no = AscReadLramByte(iop_base,
10210 (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
10213 * Reset request's working SG queue back to the
10216 AscWriteLramByte(iop_base,
10217 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
10220 sg_head = scsiq->sg_head;
10223 * Set sg_entry_cnt to the number of SG elements
10224 * that will be completed on this interrupt.
10226 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
10227 * SG elements. The data_cnt and data_addr fields which
10228 * add 1 to the SG element capacity are not used when
10229 * restarting SG handling after a halt.
10231 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
10233 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10236 * Keep track of remaining number of SG elements that will
10237 * need to be handled on the next interrupt.
10239 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
10242 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
10243 scsiq->remain_sg_entry_cnt = 0;
10247 * Copy SG elements into the list of allocated SG queues.
10249 * Last index completed is saved in scsiq->next_sg_index.
10251 next_qp = first_sg_wk_q_no;
10252 q_addr = ASC_QNO_TO_QADDR(next_qp);
10253 scsi_sg_q.sg_head_qp = q_no;
10254 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10255 for( i = 0; i < sg_head->queue_cnt; i++)
10257 scsi_sg_q.seq_no = i + 1;
10258 if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
10260 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
10261 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10263 * After very first SG queue RISC FW uses next
10264 * SG queue first element then checks sg_list_cnt
10265 * against zero and then decrements, so set
10266 * sg_list_cnt 1 less than number of SG elements
10267 * in each SG queue.
10269 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
10270 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
10273 * This is the last SG queue in the list of
10274 * allocated SG queues. If there are more
10275 * SG elements than will fit in the allocated
10276 * queues, then set the QCSG_SG_XFER_MORE flag.
10278 if (scsiq->remain_sg_entry_cnt != 0)
10280 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10283 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10285 /* equals sg_entry_cnt * 2 */
10286 sg_list_dwords = sg_entry_cnt << 1;
10287 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
10288 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
10292 scsi_sg_q.q_no = next_qp;
10293 AscMemWordCopyPtrToLram(iop_base,
10294 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10295 (uchar *) &scsi_sg_q,
10296 sizeof(ASC_SG_LIST_Q) >> 1);
10298 AscMemDWordCopyPtrToLram(iop_base,
10299 q_addr + ASC_SGQ_LIST_BEG,
10300 (uchar *) &sg_head->sg_list[scsiq->next_sg_index],
10303 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
10306 * If the just completed SG queue contained the
10307 * last SG element, then no more SG queues need
10310 if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
10315 next_qp = AscReadLramByte( iop_base,
10316 ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
10317 q_addr = ASC_QNO_TO_QADDR( next_qp );
10321 * Clear the halt condition so the RISC will be restarted
10322 * after the return.
10324 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10327 #endif /* CC_VERY_LONG_SG_LIST */
10332 _AscCopyLramScsiDoneQ(
10335 ASC_QDONE_INFO * scsiq,
10336 ASC_DCNT max_dma_count
10340 uchar sg_queue_cnt;
10342 DvcGetQinfo(iop_base,
10343 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
10345 (sizeof (ASC_SCSIQ_2) + sizeof (ASC_SCSIQ_3)) / 2);
10347 _val = AscReadLramWord(iop_base,
10348 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10349 scsiq->q_status = (uchar) _val;
10350 scsiq->q_no = (uchar) (_val >> 8);
10351 _val = AscReadLramWord(iop_base,
10352 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_CNTL));
10353 scsiq->cntl = (uchar) _val;
10354 sg_queue_cnt = (uchar) (_val >> 8);
10355 _val = AscReadLramWord(iop_base,
10356 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SENSE_LEN));
10357 scsiq->sense_len = (uchar) _val;
10358 scsiq->extra_bytes = (uchar) (_val >> 8);
10361 * Read high word of remain bytes from alternate location.
10363 scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
10364 (ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
10366 * Read low word of remain bytes from original location.
10368 scsiq->remain_bytes += AscReadLramWord(iop_base,
10369 (ushort) (q_addr+ (ushort) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
10371 scsiq->remain_bytes &= max_dma_count;
10372 return (sg_queue_cnt);
10377 ASC_DVC_VAR *asc_dvc
10383 uchar sg_queue_cnt;
10387 ASC_SCSI_BIT_ID_TYPE scsi_busy;
10388 ASC_SCSI_BIT_ID_TYPE target_id;
10392 uchar cur_target_qng;
10393 ASC_QDONE_INFO scsiq_buf;
10394 ASC_QDONE_INFO *scsiq;
10396 ASC_ISR_CALLBACK asc_isr_callback;
10398 iop_base = asc_dvc->iop_base;
10399 asc_isr_callback = asc_dvc->isr_callback;
10401 scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
10402 done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
10403 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
10404 next_qp = AscReadLramByte(iop_base,
10405 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_FWD));
10406 if (next_qp != ASC_QLINK_END) {
10407 AscPutVarDoneQTail(iop_base, next_qp);
10408 q_addr = ASC_QNO_TO_QADDR(next_qp);
10409 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
10410 asc_dvc->max_dma_count);
10411 AscWriteLramByte(iop_base,
10412 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10413 (uchar) (scsiq->q_status & (uchar) ~ (QS_READY | QS_ABORTED)));
10414 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
10415 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
10416 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
10417 sg_q_addr = q_addr;
10418 sg_list_qp = next_qp;
10419 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
10420 sg_list_qp = AscReadLramByte(iop_base,
10421 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_FWD));
10422 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
10423 if (sg_list_qp == ASC_QLINK_END) {
10424 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SG_Q_LINKS);
10425 scsiq->d3.done_stat = QD_WITH_ERROR;
10426 scsiq->d3.host_stat = QHSTA_D_QDONE_SG_LIST_CORRUPTED;
10427 goto FATAL_ERR_QDONE;
10429 AscWriteLramByte(iop_base,
10430 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10433 n_q_used = sg_queue_cnt + 1;
10434 AscPutVarDoneQTail(iop_base, sg_list_qp);
10436 if (asc_dvc->queue_full_or_busy & target_id) {
10437 cur_target_qng = AscReadLramByte(iop_base,
10438 (ushort) ((ushort) ASC_QADR_BEG + (ushort) scsiq->d2.target_ix));
10439 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
10440 scsi_busy = AscReadLramByte(iop_base,
10441 (ushort) ASCV_SCSIBUSY_B);
10442 scsi_busy &= ~target_id;
10443 AscWriteLramByte(iop_base,
10444 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10445 asc_dvc->queue_full_or_busy &= ~target_id;
10448 if (asc_dvc->cur_total_qng >= n_q_used) {
10449 asc_dvc->cur_total_qng -= n_q_used;
10450 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
10451 asc_dvc->cur_dvc_qng[tid_no]--;
10454 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
10455 scsiq->d3.done_stat = QD_WITH_ERROR;
10456 goto FATAL_ERR_QDONE;
10458 if ((scsiq->d2.srb_ptr == 0UL) ||
10459 ((scsiq->q_status & QS_ABORTED) != 0)) {
10461 } else if (scsiq->q_status == QS_DONE) {
10462 false_overrun = FALSE;
10463 if (scsiq->extra_bytes != 0) {
10464 scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
10466 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
10467 if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
10468 if ((scsiq->cntl & (QC_DATA_IN | QC_DATA_OUT)) == 0) {
10469 scsiq->d3.done_stat = QD_NO_ERROR;
10470 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10471 } else if (false_overrun) {
10472 scsiq->d3.done_stat = QD_NO_ERROR;
10473 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10475 } else if (scsiq->d3.host_stat ==
10476 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
10477 AscStopChip(iop_base);
10478 AscSetChipControl(iop_base,
10479 (uchar) (CC_SCSI_RESET | CC_HALT));
10480 DvcDelayNanoSecond(asc_dvc, 60000);
10481 AscSetChipControl(iop_base, CC_HALT);
10482 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10483 AscSetChipStatus(iop_base, 0);
10484 AscSetChipControl(iop_base, 0);
10487 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10488 (*asc_isr_callback) (asc_dvc, scsiq);
10490 if ((AscReadLramByte(iop_base,
10491 (ushort) (q_addr + (ushort) ASC_SCSIQ_CDB_BEG)) ==
10493 asc_dvc->unit_not_ready &= ~target_id;
10494 if (scsiq->d3.done_stat != QD_NO_ERROR) {
10495 asc_dvc->start_motor &= ~target_id;
10501 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
10503 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10504 (*asc_isr_callback) (asc_dvc, scsiq);
10514 ASC_DVC_VAR *asc_dvc
10517 ASC_CS_TYPE chipstat;
10519 ushort saved_ram_addr;
10521 uchar saved_ctrl_reg;
10526 iop_base = asc_dvc->iop_base;
10527 int_pending = FALSE;
10529 if (AscIsIntPending(iop_base) == 0)
10531 return int_pending;
10534 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
10535 || (asc_dvc->isr_callback == 0)
10539 if (asc_dvc->in_critical_cnt != 0) {
10540 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
10543 if (asc_dvc->is_in_int) {
10544 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
10547 asc_dvc->is_in_int = TRUE;
10548 ctrl_reg = AscGetChipControl(iop_base);
10549 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
10550 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
10551 chipstat = AscGetChipStatus(iop_base);
10552 if (chipstat & CSW_SCSI_RESET_LATCH) {
10553 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
10555 int_pending = TRUE;
10556 asc_dvc->sdtr_done = 0;
10557 saved_ctrl_reg &= (uchar) (~CC_HALT);
10558 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) &&
10561 DvcSleepMilliSecond(100);
10563 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
10564 AscSetChipControl(iop_base, CC_HALT);
10565 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10566 AscSetChipStatus(iop_base, 0);
10567 chipstat = AscGetChipStatus(iop_base);
10570 saved_ram_addr = AscGetChipLramAddr(iop_base);
10571 host_flag = AscReadLramByte(iop_base,
10572 ASCV_HOST_FLAG_B) & (uchar) (~ASC_HOST_FLAG_IN_ISR);
10573 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10574 (uchar) (host_flag | (uchar) ASC_HOST_FLAG_IN_ISR));
10575 if ((chipstat & CSW_INT_PENDING)
10578 AscAckInterrupt(iop_base);
10579 int_pending = TRUE;
10580 if ((chipstat & CSW_HALTED) &&
10581 (ctrl_reg & CC_SINGLE_STEP)) {
10582 if (AscIsrChipHalted(asc_dvc) == ERR) {
10583 goto ISR_REPORT_QDONE_FATAL_ERROR;
10585 saved_ctrl_reg &= (uchar) (~CC_HALT);
10588 ISR_REPORT_QDONE_FATAL_ERROR:
10589 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
10590 while (((status = AscIsrQDone(asc_dvc)) & 0x01) != 0) {
10594 if ((status = AscIsrQDone(asc_dvc)) == 1) {
10597 } while (status == 0x11);
10599 if ((status & 0x80) != 0)
10603 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10604 AscSetChipLramAddr(iop_base, saved_ram_addr);
10605 AscSetChipControl(iop_base, saved_ctrl_reg);
10606 asc_dvc->is_in_int = FALSE;
10607 return (int_pending);
10610 /* Microcode buffer is kept after initialization for error recovery. */
10611 STATIC uchar _asc_mcode_buf[] =
10613 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10614 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10617 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
10618 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10619 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
10620 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00,
10621 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
10622 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80,
10623 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80,
10624 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
10625 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D, 0x00,
10626 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1,
10627 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
10628 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, 0x84, 0x97, 0x07, 0xA6,
10629 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00,
10630 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
10631 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33,
10632 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04,
10633 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
10634 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A, 0x00,
10635 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04,
10636 0x36, 0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
10637 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, 0x3C, 0x01, 0x00, 0x05,
10638 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01,
10639 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
10640 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23,
10641 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0,
10642 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
10643 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84, 0x97,
10644 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80,
10645 0xF0, 0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
10646 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, 0x04, 0x98, 0xF0, 0x80,
10647 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6,
10648 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
10649 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02,
10650 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96,
10651 0x48, 0x82, 0x04, 0x23, 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
10652 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5, 0x01,
10653 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02,
10654 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
10655 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, 0x80, 0x63, 0x00, 0x43,
10656 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01,
10657 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
10658 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00,
10659 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6,
10660 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
10661 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE, 0x82,
10662 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8,
10663 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
10664 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, 0x3C, 0x04, 0x06, 0xA6,
10665 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83,
10666 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
10667 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03,
10668 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03,
10669 0xEC, 0x00, 0x6E, 0x00, 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
10670 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00, 0xA6,
10671 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03,
10672 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
10673 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, 0xC0, 0x83, 0x00, 0x33,
10674 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23,
10675 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
10676 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04,
10677 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84,
10678 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
10679 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00, 0x33,
10680 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC,
10681 0x00, 0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
10682 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0xA3, 0x01,
10683 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00,
10684 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
10685 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3,
10686 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23,
10687 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
10688 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8, 0x81,
10689 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81,
10690 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
10691 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, 0xF4, 0x04, 0x00, 0x33,
10692 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01,
10693 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
10694 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04,
10695 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85,
10696 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
10697 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81, 0x01,
10698 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01,
10699 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
10700 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, 0x07, 0xA4, 0xF8, 0x05,
10701 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0,
10702 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
10703 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85,
10704 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0,
10705 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
10706 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80, 0x63,
10707 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23,
10708 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
10709 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, 0x07, 0x41, 0x83, 0x03,
10710 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6,
10711 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
10712 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61,
10713 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01,
10714 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
10715 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06, 0xA6,
10716 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20,
10717 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
10718 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, 0x40, 0x0E, 0x80, 0x63,
10719 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43,
10720 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
10721 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06,
10722 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6,
10723 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
10724 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04, 0x01,
10725 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33,
10726 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
10727 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, 0x00, 0x00, 0x80, 0x67,
10728 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61,
10729 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
10730 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05,
10731 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01,
10732 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
10733 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70, 0x00,
10734 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00,
10735 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
10736 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, 0xC4, 0x07, 0x00, 0x33,
10737 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01,
10738 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
10739 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63,
10740 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02,
10741 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
10742 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3, 0x04,
10743 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08,
10744 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
10745 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, 0x5A, 0x88, 0x02, 0x01,
10746 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08,
10747 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
10748 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B,
10749 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09,
10750 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
10751 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40, 0x3A,
10752 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3,
10753 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
10754 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, 0xA1, 0x23, 0xA1, 0x01,
10755 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2,
10756 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
10759 STATIC ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
10760 STATIC ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
10762 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10763 STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
10785 ASC_DVC_VAR *asc_dvc,
10790 ulong last_int_level;
10793 int disable_syn_offset_one_fix;
10796 ASC_EXE_CALLBACK asc_exe_callback;
10797 ushort sg_entry_cnt = 0;
10798 ushort sg_entry_cnt_minus_one = 0;
10805 ASC_SG_HEAD *sg_head;
10808 iop_base = asc_dvc->iop_base;
10809 sg_head = scsiq->sg_head;
10810 asc_exe_callback = asc_dvc->exe_callback;
10811 if (asc_dvc->err_code != 0)
10813 if (scsiq == (ASC_SCSI_Q *) 0L) {
10814 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
10817 scsiq->q1.q_no = 0;
10818 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10819 scsiq->q1.extra_bytes = 0;
10822 target_ix = scsiq->q2.target_ix;
10823 tid_no = ASC_TIX_TO_TID(target_ix);
10825 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10826 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10827 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10828 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10829 AscMsgOutSDTR(asc_dvc,
10830 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10831 (uchar) (asc_dvc->max_sdtr_index - 1)],
10832 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10833 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10836 last_int_level = DvcEnterCritical();
10837 if (asc_dvc->in_critical_cnt != 0) {
10838 DvcLeaveCritical(last_int_level);
10839 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10842 asc_dvc->in_critical_cnt++;
10843 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10844 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10845 asc_dvc->in_critical_cnt--;
10846 DvcLeaveCritical(last_int_level);
10849 #if !CC_VERY_LONG_SG_LIST
10850 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10852 asc_dvc->in_critical_cnt--;
10853 DvcLeaveCritical(last_int_level);
10856 #endif /* !CC_VERY_LONG_SG_LIST */
10857 if (sg_entry_cnt == 1) {
10858 scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
10859 scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
10860 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10862 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10864 scsi_cmd = scsiq->cdbptr[0];
10865 disable_syn_offset_one_fix = FALSE;
10866 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10867 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10868 if (scsiq->q1.cntl & QC_SG_HEAD) {
10870 for (i = 0; i < sg_entry_cnt; i++) {
10871 data_cnt += (ADV_DCNT) le32_to_cpu(sg_head->sg_list[i].bytes);
10874 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10876 if (data_cnt != 0UL) {
10877 if (data_cnt < 512UL) {
10878 disable_syn_offset_one_fix = TRUE;
10880 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; i++) {
10881 disable_cmd = _syn_offset_one_disable_cmd[i];
10882 if (disable_cmd == 0xFF) {
10885 if (scsi_cmd == disable_cmd) {
10886 disable_syn_offset_one_fix = TRUE;
10893 if (disable_syn_offset_one_fix) {
10894 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10895 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10896 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10898 scsiq->q2.tag_code &= 0x27;
10900 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10901 if (asc_dvc->bug_fix_cntl) {
10902 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10903 if ((scsi_cmd == READ_6) ||
10904 (scsi_cmd == READ_10)) {
10906 (ADV_PADDR) le32_to_cpu(
10907 sg_head->sg_list[sg_entry_cnt_minus_one].addr) +
10908 (ADV_DCNT) le32_to_cpu(
10909 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10910 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10911 if ((extra_bytes != 0) &&
10912 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10914 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10915 scsiq->q1.extra_bytes = extra_bytes;
10916 data_cnt = le32_to_cpu(
10917 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10918 data_cnt -= (ASC_DCNT) extra_bytes;
10919 sg_head->sg_list[sg_entry_cnt_minus_one].bytes =
10920 cpu_to_le32(data_cnt);
10925 sg_head->entry_to_copy = sg_head->entry_cnt;
10926 #if CC_VERY_LONG_SG_LIST
10928 * Set the sg_entry_cnt to the maximum possible. The rest of
10929 * the SG elements will be copied when the RISC completes the
10930 * SG elements that fit and halts.
10932 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10934 sg_entry_cnt = ASC_MAX_SG_LIST;
10936 #endif /* CC_VERY_LONG_SG_LIST */
10937 n_q_required = AscSgListToQueue(sg_entry_cnt);
10938 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10939 (uint) n_q_required) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10940 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10941 n_q_required)) == 1) {
10942 asc_dvc->in_critical_cnt--;
10943 if (asc_exe_callback != 0) {
10944 (*asc_exe_callback) (asc_dvc, scsiq);
10946 DvcLeaveCritical(last_int_level);
10951 if (asc_dvc->bug_fix_cntl) {
10952 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10953 if ((scsi_cmd == READ_6) ||
10954 (scsi_cmd == READ_10)) {
10955 addr = le32_to_cpu(scsiq->q1.data_addr) +
10956 le32_to_cpu(scsiq->q1.data_cnt);
10957 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10958 if ((extra_bytes != 0) &&
10959 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10961 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10962 if (((ushort) data_cnt & 0x01FF) == 0) {
10963 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10964 data_cnt -= (ASC_DCNT) extra_bytes;
10965 scsiq->q1.data_cnt = cpu_to_le32(data_cnt);
10966 scsiq->q1.extra_bytes = extra_bytes;
10973 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10974 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10975 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10976 n_q_required)) == 1) {
10977 asc_dvc->in_critical_cnt--;
10978 if (asc_exe_callback != 0) {
10979 (*asc_exe_callback) (asc_dvc, scsiq);
10981 DvcLeaveCritical(last_int_level);
10986 asc_dvc->in_critical_cnt--;
10987 DvcLeaveCritical(last_int_level);
10993 ASC_DVC_VAR *asc_dvc,
11005 iop_base = asc_dvc->iop_base;
11006 target_ix = scsiq->q2.target_ix;
11007 tid_no = ASC_TIX_TO_TID(target_ix);
11009 free_q_head = (uchar) AscGetVarFreeQHead(iop_base);
11010 if (n_q_required > 1) {
11011 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
11012 free_q_head, (uchar) (n_q_required)))
11013 != (uchar) ASC_QLINK_END) {
11014 asc_dvc->last_q_shortage = 0;
11015 scsiq->sg_head->queue_cnt = n_q_required - 1;
11016 scsiq->q1.q_no = free_q_head;
11017 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
11018 free_q_head)) == 1) {
11019 AscPutVarFreeQHead(iop_base, next_qp);
11020 asc_dvc->cur_total_qng += (uchar) (n_q_required);
11021 asc_dvc->cur_dvc_qng[tid_no]++;
11025 } else if (n_q_required == 1) {
11026 if ((next_qp = AscAllocFreeQueue(iop_base,
11027 free_q_head)) != ASC_QLINK_END) {
11028 scsiq->q1.q_no = free_q_head;
11029 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
11030 free_q_head)) == 1) {
11031 AscPutVarFreeQHead(iop_base, next_qp);
11032 asc_dvc->cur_total_qng++;
11033 asc_dvc->cur_dvc_qng[tid_no]++;
11048 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
11049 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
11051 return (n_sg_list_qs + 1);
11056 AscGetNumOfFreeQueue(
11057 ASC_DVC_VAR *asc_dvc,
11064 ASC_SCSI_BIT_ID_TYPE target_id;
11067 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
11068 tid_no = ASC_TIX_TO_TID(target_ix);
11069 if ((asc_dvc->unit_not_ready & target_id) ||
11070 (asc_dvc->queue_full_or_busy & target_id)) {
11074 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11075 (uint) asc_dvc->last_q_shortage +
11076 (uint) ASC_MIN_FREE_Q;
11078 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11079 (uint) ASC_MIN_FREE_Q;
11081 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
11082 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
11083 if (asc_dvc->cur_dvc_qng[tid_no] >=
11084 asc_dvc->max_dvc_qng[tid_no]) {
11087 return (cur_free_qs);
11090 if ((n_qs > asc_dvc->last_q_shortage) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
11091 asc_dvc->last_q_shortage = n_qs;
11099 ASC_DVC_VAR *asc_dvc,
11107 uchar syn_period_ix;
11111 iop_base = asc_dvc->iop_base;
11112 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
11113 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
11114 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
11115 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
11116 syn_period_ix = (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
11117 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
11118 AscMsgOutSDTR(asc_dvc,
11119 asc_dvc->sdtr_period_tbl[syn_period_ix],
11121 scsiq->q1.cntl |= QC_MSG_OUT;
11123 q_addr = ASC_QNO_TO_QADDR(q_no);
11124 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
11125 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG ;
11127 scsiq->q1.status = QS_FREE;
11128 AscMemWordCopyPtrToLram(iop_base,
11129 q_addr + ASC_SCSIQ_CDB_BEG,
11130 (uchar *) scsiq->cdbptr,
11131 scsiq->q2.cdb_len >> 1);
11133 DvcPutScsiQ(iop_base,
11134 q_addr + ASC_SCSIQ_CPY_BEG,
11135 (uchar *) &scsiq->q1.cntl,
11136 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
11137 AscWriteLramWord(iop_base,
11138 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
11139 (ushort) (((ushort) scsiq->q1.q_no << 8) | (ushort) QS_READY));
11144 AscPutReadySgListQueue(
11145 ASC_DVC_VAR *asc_dvc,
11152 ASC_SG_HEAD *sg_head;
11153 ASC_SG_LIST_Q scsi_sg_q;
11154 ASC_DCNT saved_data_addr;
11155 ASC_DCNT saved_data_cnt;
11157 ushort sg_list_dwords;
11159 ushort sg_entry_cnt;
11163 iop_base = asc_dvc->iop_base;
11164 sg_head = scsiq->sg_head;
11165 saved_data_addr = scsiq->q1.data_addr;
11166 saved_data_cnt = scsiq->q1.data_cnt;
11167 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
11168 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
11169 #if CC_VERY_LONG_SG_LIST
11171 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
11172 * then not all SG elements will fit in the allocated queues.
11173 * The rest of the SG elements will be copied when the RISC
11174 * completes the SG elements that fit and halts.
11176 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11179 * Set sg_entry_cnt to be the number of SG elements that
11180 * will fit in the allocated SG queues. It is minus 1, because
11181 * the first SG element is handled above. ASC_MAX_SG_LIST is
11182 * already inflated by 1 to account for this. For example it
11183 * may be 50 which is 1 + 7 queues * 7 SG elements.
11185 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
11188 * Keep track of remaining number of SG elements that will
11189 * need to be handled from a_isr.c.
11191 scsiq->remain_sg_entry_cnt = sg_head->entry_cnt - ASC_MAX_SG_LIST;
11194 #endif /* CC_VERY_LONG_SG_LIST */
11196 * Set sg_entry_cnt to be the number of SG elements that
11197 * will fit in the allocated SG queues. It is minus 1, because
11198 * the first SG element is handled above.
11200 sg_entry_cnt = sg_head->entry_cnt - 1;
11201 #if CC_VERY_LONG_SG_LIST
11203 #endif /* CC_VERY_LONG_SG_LIST */
11204 if (sg_entry_cnt != 0) {
11205 scsiq->q1.cntl |= QC_SG_HEAD;
11206 q_addr = ASC_QNO_TO_QADDR(q_no);
11208 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
11209 scsi_sg_q.sg_head_qp = q_no;
11210 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
11211 for (i = 0; i < sg_head->queue_cnt; i++) {
11212 scsi_sg_q.seq_no = i + 1;
11213 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
11214 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
11215 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
11217 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
11218 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
11220 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
11221 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
11224 #if CC_VERY_LONG_SG_LIST
11226 * This is the last SG queue in the list of
11227 * allocated SG queues. If there are more
11228 * SG elements than will fit in the allocated
11229 * queues, then set the QCSG_SG_XFER_MORE flag.
11231 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11233 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
11236 #endif /* CC_VERY_LONG_SG_LIST */
11237 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
11238 #if CC_VERY_LONG_SG_LIST
11240 #endif /* CC_VERY_LONG_SG_LIST */
11241 sg_list_dwords = sg_entry_cnt << 1;
11243 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
11244 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
11246 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
11247 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
11251 next_qp = AscReadLramByte(iop_base,
11252 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11253 scsi_sg_q.q_no = next_qp;
11254 q_addr = ASC_QNO_TO_QADDR(next_qp);
11255 AscMemWordCopyPtrToLram(iop_base,
11256 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
11257 (uchar *) &scsi_sg_q,
11258 sizeof(ASC_SG_LIST_Q) >> 1);
11259 AscMemDWordCopyPtrToLram(iop_base,
11260 q_addr + ASC_SGQ_LIST_BEG,
11261 (uchar *) &sg_head->sg_list[sg_index],
11263 sg_index += ASC_SG_LIST_PER_Q;
11264 scsiq->next_sg_index = sg_index;
11267 scsiq->q1.cntl &= ~QC_SG_HEAD;
11269 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
11270 scsiq->q1.data_addr = saved_data_addr;
11271 scsiq->q1.data_cnt = saved_data_cnt;
11276 AscSetRunChipSynRegAtID(
11284 if (AscHostReqRiscHalt(iop_base)) {
11285 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11286 AscStartChip(iop_base);
11293 AscSetChipSynRegAtID(
11299 ASC_SCSI_BIT_ID_TYPE org_id;
11303 AscSetBank(iop_base, 1);
11304 org_id = AscReadChipDvcID(iop_base);
11305 for (i = 0; i <= ASC_MAX_TID; i++) {
11306 if (org_id == (0x01 << i))
11309 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
11310 AscWriteChipDvcID(iop_base, id);
11311 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
11312 AscSetBank(iop_base, 0);
11313 AscSetChipSyn(iop_base, sdtr_data);
11314 if (AscGetChipSyn(iop_base) != sdtr_data) {
11320 AscSetBank(iop_base, 1);
11321 AscWriteChipDvcID(iop_base, org_id);
11322 AscSetBank(iop_base, 0);
11328 ASC_DVC_VAR *asc_dvc
11336 iop_base = asc_dvc->iop_base;
11338 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
11339 (ushort) (((int) (asc_dvc->max_total_qng + 2 + 1) * 64) >> 1)
11341 i = ASC_MIN_ACTIVE_QNO;
11342 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
11343 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11345 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11346 (uchar) (asc_dvc->max_total_qng));
11347 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11350 s_addr += ASC_QBLK_SIZE;
11351 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
11352 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11354 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11356 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11359 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11360 (uchar) ASC_QLINK_END);
11361 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11362 (uchar) (asc_dvc->max_total_qng - 1));
11363 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11364 (uchar) asc_dvc->max_total_qng);
11366 s_addr += ASC_QBLK_SIZE;
11367 for (; i <= (uchar) (asc_dvc->max_total_qng + 3);
11368 i++, s_addr += ASC_QBLK_SIZE) {
11369 AscWriteLramByte(iop_base,
11370 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_FWD), i);
11371 AscWriteLramByte(iop_base,
11372 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_BWD), i);
11373 AscWriteLramByte(iop_base,
11374 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_QNO), i);
11376 return (warn_code);
11381 ASC_DVC_VAR *asc_dvc
11388 iop_base = asc_dvc->iop_base;
11389 AscPutRiscVarFreeQHead(iop_base, 1);
11390 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11391 AscPutVarFreeQHead(iop_base, 1);
11392 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11393 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
11394 (uchar) ((int) asc_dvc->max_total_qng + 1));
11395 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
11396 (uchar) ((int) asc_dvc->max_total_qng + 2));
11397 AscWriteLramByte(iop_base, (ushort) ASCV_TOTAL_READY_Q_B,
11398 asc_dvc->max_total_qng);
11399 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
11400 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
11401 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
11402 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
11403 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
11404 AscPutQDoneInProgress(iop_base, 0);
11405 lram_addr = ASC_QADR_BEG;
11406 for (i = 0; i < 32; i++, lram_addr += 2) {
11407 AscWriteLramWord(iop_base, lram_addr, 0);
11413 AscSetLibErrorCode(
11414 ASC_DVC_VAR *asc_dvc,
11418 if (asc_dvc->err_code == 0) {
11419 asc_dvc->err_code = err_code;
11420 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
11429 ASC_DVC_VAR *asc_dvc,
11435 uchar sdtr_period_index;
11438 iop_base = asc_dvc->iop_base;
11439 sdtr_buf.msg_type = MS_EXTEND;
11440 sdtr_buf.msg_len = MS_SDTR_LEN;
11441 sdtr_buf.msg_req = MS_SDTR_CODE;
11442 sdtr_buf.xfer_period = sdtr_period;
11443 sdtr_offset &= ASC_SYN_MAX_OFFSET;
11444 sdtr_buf.req_ack_offset = sdtr_offset;
11445 if ((sdtr_period_index =
11446 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
11447 asc_dvc->max_sdtr_index) {
11448 AscMemWordCopyPtrToLram(iop_base,
11450 (uchar *) &sdtr_buf,
11451 sizeof (EXT_MSG) >> 1);
11452 return ((sdtr_period_index << 4) | sdtr_offset);
11455 sdtr_buf.req_ack_offset = 0;
11456 AscMemWordCopyPtrToLram(iop_base,
11458 (uchar *) &sdtr_buf,
11459 sizeof (EXT_MSG) >> 1);
11466 ASC_DVC_VAR *asc_dvc,
11472 uchar sdtr_period_ix;
11474 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
11476 (sdtr_period_ix > asc_dvc->max_sdtr_index)
11480 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
11491 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11492 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
11497 AscGetSynPeriodIndex(
11498 ASC_DVC_VAR *asc_dvc,
11502 uchar *period_table;
11507 period_table = asc_dvc->sdtr_period_tbl;
11508 max_index = (int) asc_dvc->max_sdtr_index;
11509 min_index = (int)asc_dvc->host_init_sdtr_index;
11510 if ((syn_time <= period_table[max_index])) {
11511 for (i = min_index; i < (max_index - 1); i++) {
11512 if (syn_time <= period_table[i]) {
11513 return ((uchar) i);
11516 return ((uchar) max_index);
11518 return ((uchar) (max_index + 1));
11532 q_addr = ASC_QNO_TO_QADDR(free_q_head);
11533 q_status = (uchar) AscReadLramByte(iop_base,
11534 (ushort) (q_addr + ASC_SCSIQ_B_STATUS));
11535 next_qp = AscReadLramByte(iop_base,
11536 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11537 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
11540 return (ASC_QLINK_END);
11544 AscAllocMultipleFreeQueue(
11552 for (i = 0; i < n_free_q; i++) {
11553 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
11554 == ASC_QLINK_END) {
11555 return (ASC_QLINK_END);
11558 return (free_q_head);
11562 AscHostReqRiscHalt(
11568 uchar saved_stop_code;
11570 if (AscIsChipHalted(iop_base))
11572 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
11573 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11574 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP
11577 if (AscIsChipHalted(iop_base)) {
11581 DvcSleepMilliSecond(100);
11582 } while (count++ < 20);
11583 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
11594 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11595 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11596 ASC_STOP_REQ_RISC_STOP);
11599 AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11600 ASC_STOP_ACK_RISC_STOP) {
11603 DvcSleepMilliSecond(100);
11604 } while (count++ < 20);
11610 DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
11616 DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
11618 udelay((nano_sec + 999)/1000);
11622 STATIC ASC_DCNT __init
11623 AscGetEisaProductID(
11627 ushort product_id_high, product_id_low;
11628 ASC_DCNT product_id;
11630 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
11631 product_id_low = inpw(eisa_iop);
11632 product_id_high = inpw(eisa_iop + 2);
11633 product_id = ((ASC_DCNT) product_id_high << 16) |
11634 (ASC_DCNT) product_id_low;
11635 return (product_id);
11638 STATIC PortAddr __init
11639 AscSearchIOPortAddrEISA(
11642 ASC_DCNT eisa_product_id;
11644 if (iop_base == 0) {
11645 iop_base = ASC_EISA_MIN_IOP_ADDR;
11647 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11649 if ((iop_base & 0x0050) == 0x0050) {
11650 iop_base += ASC_EISA_BIG_IOP_GAP;
11652 iop_base += ASC_EISA_SMALL_IOP_GAP;
11655 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
11656 eisa_product_id = AscGetEisaProductID(iop_base);
11657 if ((eisa_product_id == ASC_EISA_ID_740) ||
11658 (eisa_product_id == ASC_EISA_ID_750)) {
11659 if (AscFindSignature(iop_base)) {
11660 inpw(iop_base + 4);
11664 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11666 if ((iop_base & 0x0050) == 0x0050) {
11667 iop_base += ASC_EISA_BIG_IOP_GAP;
11669 iop_base += ASC_EISA_SMALL_IOP_GAP;
11674 #endif /* CONFIG_ISA */
11681 AscSetChipControl(iop_base, 0);
11682 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11695 cc_val = AscGetChipControl(iop_base) & (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
11696 AscSetChipControl(iop_base, (uchar) (cc_val | CC_HALT));
11697 AscSetChipIH(iop_base, INS_HALT);
11698 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11699 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
11710 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11711 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
11724 AscSetBank(iop_base, 1);
11725 AscWriteChipIH(iop_base, ins_code);
11726 AscSetBank(iop_base, 0);
11741 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
11742 if (loop++ > 0x7FFF) {
11745 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
11746 host_flag = AscReadLramByte(iop_base, ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
11747 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
11748 (uchar) (host_flag | ASC_HOST_FLAG_ACK_INT));
11749 AscSetChipStatus(iop_base, CIW_INT_ACK);
11751 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
11752 AscSetChipStatus(iop_base, CIW_INT_ACK);
11757 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
11762 AscDisableInterrupt(
11768 cfg = AscGetChipCfgLsw(iop_base);
11769 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
11774 AscEnableInterrupt(
11780 cfg = AscGetChipCfgLsw(iop_base);
11781 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
11795 val = AscGetChipControl(iop_base) &
11796 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | CC_CHIP_RESET));
11798 val |= CC_BANK_ONE;
11799 } else if (bank == 2) {
11800 val |= CC_DIAG | CC_BANK_ONE;
11802 val &= ~CC_BANK_ONE;
11804 AscSetChipControl(iop_base, val);
11809 AscResetChipAndScsiBus(
11810 ASC_DVC_VAR *asc_dvc
11816 iop_base = asc_dvc->iop_base;
11817 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) && (i-- > 0))
11819 DvcSleepMilliSecond(100);
11821 AscStopChip(iop_base);
11822 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
11823 DvcDelayNanoSecond(asc_dvc, 60000);
11824 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11825 AscSetChipIH(iop_base, INS_HALT);
11826 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
11827 AscSetChipControl(iop_base, CC_HALT);
11828 DvcSleepMilliSecond(200);
11829 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
11830 AscSetChipStatus(iop_base, 0);
11831 return (AscIsChipHalted(iop_base));
11834 STATIC ASC_DCNT __init
11838 if (bus_type & ASC_IS_ISA)
11839 return (ASC_MAX_ISA_DMA_COUNT);
11840 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11841 return (ASC_MAX_VL_DMA_COUNT);
11842 return (ASC_MAX_PCI_DMA_COUNT);
11846 STATIC ushort __init
11847 AscGetIsaDmaChannel(
11852 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11853 if (channel == 0x03)
11855 else if (channel == 0x00)
11857 return (channel + 4);
11860 STATIC ushort __init
11861 AscSetIsaDmaChannel(
11863 ushort dma_channel)
11868 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11869 if (dma_channel == 7)
11872 value = dma_channel - 4;
11873 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11875 AscSetChipCfgLsw(iop_base, cfg_lsw);
11876 return (AscGetIsaDmaChannel(iop_base));
11881 STATIC uchar __init
11886 speed_value &= 0x07;
11887 AscSetBank(iop_base, 1);
11888 AscWriteChipDmaSpeed(iop_base, speed_value);
11889 AscSetBank(iop_base, 0);
11890 return (AscGetIsaDmaSpeed(iop_base));
11893 STATIC uchar __init
11900 AscSetBank(iop_base, 1);
11901 speed_value = AscReadChipDmaSpeed(iop_base);
11902 speed_value &= 0x07;
11903 AscSetBank(iop_base, 0);
11904 return (speed_value);
11906 #endif /* CONFIG_ISA */
11908 STATIC ushort __init
11909 AscReadPCIConfigWord(
11910 ASC_DVC_VAR *asc_dvc,
11911 ushort pci_config_offset)
11915 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
11916 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
11917 return ((ushort) ((msb << 8) | lsb));
11920 STATIC ushort __init
11922 ASC_DVC_VAR *asc_dvc
11927 ushort PCIDeviceID;
11928 ushort PCIVendorID;
11929 uchar PCIRevisionID;
11930 uchar prevCmdRegBits;
11933 iop_base = asc_dvc->iop_base;
11934 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11935 if (asc_dvc->err_code != 0) {
11938 if (asc_dvc->bus_type == ASC_IS_PCI) {
11939 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
11940 AscPCIConfigVendorIDRegister);
11942 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
11943 AscPCIConfigDeviceIDRegister);
11945 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
11946 AscPCIConfigRevisionIDRegister);
11948 if (PCIVendorID != ASC_PCI_VENDORID) {
11949 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11951 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
11952 AscPCIConfigCommandRegister);
11954 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
11955 AscPCICmdRegBits_IOMemBusMaster) {
11956 DvcWritePCIConfigByte(asc_dvc,
11957 AscPCIConfigCommandRegister,
11959 AscPCICmdRegBits_IOMemBusMaster));
11961 if ((DvcReadPCIConfigByte(asc_dvc,
11962 AscPCIConfigCommandRegister)
11963 & AscPCICmdRegBits_IOMemBusMaster)
11964 != AscPCICmdRegBits_IOMemBusMaster) {
11965 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11968 if ((PCIDeviceID == ASC_PCI_DEVICEID_1200A) ||
11969 (PCIDeviceID == ASC_PCI_DEVICEID_1200B)) {
11970 DvcWritePCIConfigByte(asc_dvc,
11971 AscPCIConfigLatencyTimer, 0x00);
11972 if (DvcReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer)
11974 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11976 } else if (PCIDeviceID == ASC_PCI_DEVICEID_ULTRA) {
11977 if (DvcReadPCIConfigByte(asc_dvc,
11978 AscPCIConfigLatencyTimer) < 0x20) {
11979 DvcWritePCIConfigByte(asc_dvc,
11980 AscPCIConfigLatencyTimer, 0x20);
11982 if (DvcReadPCIConfigByte(asc_dvc,
11983 AscPCIConfigLatencyTimer) < 0x20) {
11984 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11990 if (AscFindSignature(iop_base)) {
11991 warn_code |= AscInitAscDvcVar(asc_dvc);
11992 warn_code |= AscInitFromEEP(asc_dvc);
11993 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11994 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
11995 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11998 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12003 STATIC ushort __init
12005 ASC_DVC_VAR *asc_dvc
12008 ushort warn_code = 0;
12010 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
12011 if (asc_dvc->err_code != 0)
12013 if (AscFindSignature(asc_dvc->iop_base)) {
12014 warn_code |= AscInitFromAscDvcVar(asc_dvc);
12015 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12017 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12019 return (warn_code);
12022 STATIC ushort __init
12023 AscInitFromAscDvcVar(
12024 ASC_DVC_VAR *asc_dvc
12030 ushort pci_device_id;
12032 iop_base = asc_dvc->iop_base;
12033 if (asc_dvc->cfg->dev)
12034 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
12038 cfg_msw = AscGetChipCfgMsw(iop_base);
12039 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12040 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12041 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12042 AscSetChipCfgMsw(iop_base, cfg_msw);
12044 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12045 asc_dvc->cfg->cmd_qng_enabled) {
12046 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12047 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12049 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12050 warn_code |= ASC_WARN_AUTO_CONFIG;
12052 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12053 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12054 != asc_dvc->irq_no) {
12055 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12058 if (asc_dvc->bus_type & ASC_IS_PCI) {
12060 AscSetChipCfgMsw(iop_base, cfg_msw);
12061 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12063 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
12064 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
12065 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12066 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12069 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12070 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12071 == ASC_CHIP_VER_ASYN_BUG) {
12072 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12075 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12076 asc_dvc->cfg->chip_scsi_id) {
12077 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12080 if (asc_dvc->bus_type & ASC_IS_ISA) {
12081 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12082 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12084 #endif /* CONFIG_ISA */
12085 return (warn_code);
12089 AscInitAsc1000Driver(
12090 ASC_DVC_VAR *asc_dvc
12096 iop_base = asc_dvc->iop_base;
12098 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
12099 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
12100 AscResetChipAndScsiBus(asc_dvc);
12101 DvcSleepMilliSecond((ASC_DCNT)
12102 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12104 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
12105 if (asc_dvc->err_code != 0)
12107 if (!AscFindSignature(asc_dvc->iop_base)) {
12108 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12109 return (warn_code);
12111 AscDisableInterrupt(iop_base);
12112 warn_code |= AscInitLram(asc_dvc);
12113 if (asc_dvc->err_code != 0)
12115 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
12116 (ulong) _asc_mcode_chksum);
12117 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
12118 _asc_mcode_size) != _asc_mcode_chksum) {
12119 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
12120 return (warn_code);
12122 warn_code |= AscInitMicroCodeVar(asc_dvc);
12123 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
12124 AscEnableInterrupt(iop_base);
12125 return (warn_code);
12128 STATIC ushort __init
12130 ASC_DVC_VAR *asc_dvc)
12135 uchar chip_version;
12137 iop_base = asc_dvc->iop_base;
12139 asc_dvc->err_code = 0;
12140 if ((asc_dvc->bus_type &
12141 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
12142 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
12144 AscSetChipControl(iop_base, CC_HALT);
12145 AscSetChipStatus(iop_base, 0);
12146 asc_dvc->bug_fix_cntl = 0;
12147 asc_dvc->pci_fix_asyn_xfer = 0;
12148 asc_dvc->pci_fix_asyn_xfer_always = 0;
12149 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
12150 asc_dvc->sdtr_done = 0;
12151 asc_dvc->cur_total_qng = 0;
12152 asc_dvc->is_in_int = 0;
12153 asc_dvc->in_critical_cnt = 0;
12154 asc_dvc->last_q_shortage = 0;
12155 asc_dvc->use_tagged_qng = 0;
12156 asc_dvc->no_scam = 0;
12157 asc_dvc->unit_not_ready = 0;
12158 asc_dvc->queue_full_or_busy = 0;
12159 asc_dvc->redo_scam = 0;
12161 asc_dvc->host_init_sdtr_index = 0;
12162 asc_dvc->cfg->can_tagged_qng = 0;
12163 asc_dvc->cfg->cmd_qng_enabled = 0;
12164 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
12165 asc_dvc->init_sdtr = 0;
12166 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
12167 asc_dvc->scsi_reset_wait = 3;
12168 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
12169 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
12170 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
12171 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
12172 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
12173 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
12174 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
12175 ASC_LIB_VERSION_MINOR;
12176 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
12177 asc_dvc->cfg->chip_version = chip_version;
12178 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
12179 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
12180 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
12181 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
12182 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
12183 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
12184 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
12185 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
12186 asc_dvc->max_sdtr_index = 7;
12187 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
12188 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
12189 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
12190 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
12191 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
12192 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
12193 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
12194 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
12195 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
12196 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
12197 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
12198 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
12199 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
12200 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
12201 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
12202 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
12203 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
12204 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
12205 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
12206 asc_dvc->max_sdtr_index = 15;
12207 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
12209 AscSetExtraControl(iop_base,
12210 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12211 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
12212 AscSetExtraControl(iop_base,
12213 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
12216 if (asc_dvc->bus_type == ASC_IS_PCI) {
12217 AscSetExtraControl(iop_base, (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12220 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
12221 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
12222 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
12223 asc_dvc->bus_type = ASC_IS_ISAPNP;
12226 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
12227 asc_dvc->cfg->isa_dma_channel = (uchar) AscGetIsaDmaChannel(iop_base);
12229 #endif /* CONFIG_ISA */
12230 for (i = 0; i <= ASC_MAX_TID; i++) {
12231 asc_dvc->cur_dvc_qng[i] = 0;
12232 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
12233 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *) 0L;
12234 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *) 0L;
12235 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
12237 return (warn_code);
12240 STATIC ushort __init
12241 AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12243 ASCEEP_CONFIG eep_config_buf;
12244 ASCEEP_CONFIG *eep_config;
12248 ushort cfg_msw, cfg_lsw;
12252 iop_base = asc_dvc->iop_base;
12254 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12255 AscStopQueueExe(iop_base);
12256 if ((AscStopChip(iop_base) == FALSE) ||
12257 (AscGetChipScsiCtrl(iop_base) != 0)) {
12258 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12259 AscResetChipAndScsiBus(asc_dvc);
12260 DvcSleepMilliSecond((ASC_DCNT)
12261 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12263 if (AscIsChipHalted(iop_base) == FALSE) {
12264 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12265 return (warn_code);
12267 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12268 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12269 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12270 return (warn_code);
12272 eep_config = (ASCEEP_CONFIG *) &eep_config_buf;
12273 cfg_msw = AscGetChipCfgMsw(iop_base);
12274 cfg_lsw = AscGetChipCfgLsw(iop_base);
12275 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12276 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12277 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12278 AscSetChipCfgMsw(iop_base, cfg_msw);
12280 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12281 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12285 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12286 warn_code |= ASC_WARN_AUTO_CONFIG;
12287 if (asc_dvc->cfg->chip_version == 3) {
12288 if (eep_config->cfg_lsw != cfg_lsw) {
12289 warn_code |= ASC_WARN_EEPROM_RECOVER;
12290 eep_config->cfg_lsw = AscGetChipCfgLsw(iop_base);
12292 if (eep_config->cfg_msw != cfg_msw) {
12293 warn_code |= ASC_WARN_EEPROM_RECOVER;
12294 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12298 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12299 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12300 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12301 eep_config->chksum);
12302 if (chksum != eep_config->chksum) {
12303 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12304 ASC_CHIP_VER_PCI_ULTRA_3050 )
12307 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12308 eep_config->init_sdtr = 0xFF;
12309 eep_config->disc_enable = 0xFF;
12310 eep_config->start_motor = 0xFF;
12311 eep_config->use_cmd_qng = 0;
12312 eep_config->max_total_qng = 0xF0;
12313 eep_config->max_tag_qng = 0x20;
12314 eep_config->cntl = 0xBFFF;
12315 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12316 eep_config->no_scam = 0;
12317 eep_config->adapter_info[0] = 0;
12318 eep_config->adapter_info[1] = 0;
12319 eep_config->adapter_info[2] = 0;
12320 eep_config->adapter_info[3] = 0;
12321 eep_config->adapter_info[4] = 0;
12322 /* Indicate EEPROM-less board. */
12323 eep_config->adapter_info[5] = 0xBB;
12326 "AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12328 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12331 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12332 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12333 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12334 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12335 asc_dvc->start_motor = eep_config->start_motor;
12336 asc_dvc->dvc_cntl = eep_config->cntl;
12337 asc_dvc->no_scam = eep_config->no_scam;
12338 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12339 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12340 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12341 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12342 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12343 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12344 if (!AscTestExternalLram(asc_dvc)) {
12345 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
12346 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12347 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12349 eep_config->cfg_msw |= 0x0800;
12351 AscSetChipCfgMsw(iop_base, cfg_msw);
12352 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12353 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12357 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12358 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12360 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12361 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12363 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12364 eep_config->max_tag_qng = eep_config->max_total_qng;
12366 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12367 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12369 asc_dvc->max_total_qng = eep_config->max_total_qng;
12370 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12371 eep_config->use_cmd_qng) {
12372 eep_config->disc_enable = eep_config->use_cmd_qng;
12373 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12375 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12376 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12378 ASC_EEP_SET_CHIP_ID(eep_config, ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12379 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12380 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12381 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12382 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12385 for (i = 0; i <= ASC_MAX_TID; i++) {
12386 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12387 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12388 asc_dvc->cfg->sdtr_period_offset[i] =
12389 (uchar) (ASC_DEF_SDTR_OFFSET |
12390 (asc_dvc->host_init_sdtr_index << 4));
12392 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12394 if ((i = AscSetEEPConfig(iop_base, eep_config, asc_dvc->bus_type)) !=
12397 "AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", i);
12399 ASC_PRINT("AscInitFromEEP: Succesfully re-wrote EEPROM.");
12402 return (warn_code);
12406 AscInitMicroCodeVar(
12407 ASC_DVC_VAR *asc_dvc
12413 ASC_PADDR phy_addr;
12416 iop_base = asc_dvc->iop_base;
12418 for (i = 0; i <= ASC_MAX_TID; i++) {
12419 AscPutMCodeInitSDTRAtID(iop_base, i,
12420 asc_dvc->cfg->sdtr_period_offset[i]
12424 AscInitQLinkVar(asc_dvc);
12425 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
12426 asc_dvc->cfg->disc_enable);
12427 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
12428 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
12430 /* Align overrun buffer on an 8 byte boundary. */
12431 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
12432 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
12433 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
12434 (uchar *) &phy_addr, 1);
12435 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
12436 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
12437 (uchar *) &phy_size, 1);
12439 asc_dvc->cfg->mcode_date =
12440 AscReadLramWord(iop_base, (ushort) ASCV_MC_DATE_W);
12441 asc_dvc->cfg->mcode_version =
12442 AscReadLramWord(iop_base, (ushort) ASCV_MC_VER_W);
12444 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12445 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12446 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12447 return (warn_code);
12449 if (AscStartChip(iop_base) != 1) {
12450 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12451 return (warn_code);
12454 return (warn_code);
12458 AscTestExternalLram(
12459 ASC_DVC_VAR *asc_dvc)
12466 iop_base = asc_dvc->iop_base;
12468 q_addr = ASC_QNO_TO_QADDR(241);
12469 saved_word = AscReadLramWord(iop_base, q_addr);
12470 AscSetChipLramAddr(iop_base, q_addr);
12471 AscSetChipLramData(iop_base, 0x55AA);
12472 DvcSleepMilliSecond(10);
12473 AscSetChipLramAddr(iop_base, q_addr);
12474 if (AscGetChipLramData(iop_base) == 0x55AA) {
12476 AscWriteLramWord(iop_base, q_addr, saved_word);
12492 AscSetChipEEPCmd(iop_base, cmd_reg);
12493 DvcSleepMilliSecond(1);
12494 read_back = AscGetChipEEPCmd(iop_base);
12495 if (read_back == cmd_reg) {
12498 if (retry++ > ASC_EEP_MAX_RETRY) {
12505 AscWriteEEPDataReg(
12515 AscSetChipEEPData(iop_base, data_reg);
12516 DvcSleepMilliSecond(1);
12517 read_back = AscGetChipEEPData(iop_base);
12518 if (read_back == data_reg) {
12521 if (retry++ > ASC_EEP_MAX_RETRY) {
12528 AscWaitEEPRead(void)
12530 DvcSleepMilliSecond(1);
12535 AscWaitEEPWrite(void)
12537 DvcSleepMilliSecond(20);
12541 STATIC ushort __init
12549 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12551 cmd_reg = addr | ASC_EEP_CMD_READ;
12552 AscWriteEEPCmdReg(iop_base, cmd_reg);
12554 read_wval = AscGetChipEEPData(iop_base);
12556 return (read_wval);
12559 STATIC ushort __init
12567 read_wval = AscReadEEPWord(iop_base, addr);
12568 if (read_wval != word_val) {
12569 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12571 AscWriteEEPDataReg(iop_base, word_val);
12573 AscWriteEEPCmdReg(iop_base,
12574 (uchar) ((uchar) ASC_EEP_CMD_WRITE | addr));
12576 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12578 return (AscReadEEPWord(iop_base, addr));
12580 return (read_wval);
12583 STATIC ushort __init
12586 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12593 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12596 wbuf = (ushort *) cfg_buf;
12598 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
12599 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12600 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12603 if (bus_type & ASC_IS_VL) {
12604 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12605 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12607 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12608 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12610 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12611 wval = AscReadEEPWord( iop_base, ( uchar )s_addr ) ;
12612 if (s_addr <= uchar_end_in_config) {
12614 * Swap all char fields - must unswap bytes already swapped
12615 * by AscReadEEPWord().
12617 *wbuf = le16_to_cpu(wval);
12619 /* Don't swap word field at the end - cntl field. */
12622 sum += wval; /* Checksum treats all EEPROM data as words. */
12625 * Read the checksum word which will be compared against 'sum'
12626 * by the caller. Word field already swapped.
12628 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12633 AscSetEEPConfigOnce(
12635 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12644 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12647 wbuf = (ushort *) cfg_buf;
12650 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12651 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12653 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12657 if (bus_type & ASC_IS_VL) {
12658 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12659 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12661 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12662 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12664 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12665 if (s_addr <= uchar_end_in_config) {
12667 * This is a char field. Swap char fields before they are
12668 * swapped again by AscWriteEEPWord().
12670 word = cpu_to_le16(*wbuf);
12671 if (word != AscWriteEEPWord( iop_base, (uchar) s_addr, word)) {
12675 /* Don't swap word field at the end - cntl field. */
12676 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12680 sum += *wbuf; /* Checksum calculated from word values. */
12682 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12684 if (sum != AscWriteEEPWord(iop_base, (uchar) s_addr, sum)) {
12688 /* Read EEPROM back again. */
12689 wbuf = (ushort *) cfg_buf;
12691 * Read two config words; Byte-swapping done by AscReadEEPWord().
12693 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12694 if (*wbuf != AscReadEEPWord(iop_base, (uchar) s_addr)) {
12698 if (bus_type & ASC_IS_VL) {
12699 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12700 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12702 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12703 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12705 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12706 if (s_addr <= uchar_end_in_config) {
12708 * Swap all char fields. Must unswap bytes already swapped
12709 * by AscReadEEPWord().
12711 word = le16_to_cpu(AscReadEEPWord(iop_base, (uchar) s_addr));
12713 /* Don't swap word field at the end - cntl field. */
12714 word = AscReadEEPWord(iop_base, (uchar) s_addr);
12716 if (*wbuf != word) {
12720 /* Read checksum; Byte swapping not needed. */
12721 if (AscReadEEPWord(iop_base, (uchar) s_addr) != sum) {
12730 ASCEEP_CONFIG * cfg_buf, ushort bus_type
12738 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12742 if (++retry > ASC_EEP_MAX_RETRY) {
12751 ASC_DVC_VAR *asc_dvc,
12753 ASC_SCSI_INQUIRY *inq)
12756 ASC_SCSI_BIT_ID_TYPE tid_bits;
12758 dvc_type = ASC_INQ_DVC_TYPE(inq);
12759 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
12761 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)
12763 if (!(asc_dvc->init_sdtr & tid_bits))
12765 if ((dvc_type == TYPE_ROM) &&
12766 (AscCompareString((uchar *) inq->vendor_id,
12767 (uchar *) "HP ", 3) == 0))
12769 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
12771 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
12772 if ((dvc_type == TYPE_PROCESSOR) ||
12773 (dvc_type == TYPE_SCANNER) ||
12774 (dvc_type == TYPE_ROM) ||
12775 (dvc_type == TYPE_TAPE))
12777 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
12780 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
12782 AscSetRunChipSynRegAtID(asc_dvc->iop_base, tid_no,
12783 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
12791 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
12793 if ((inq->add_len >= 32) &&
12794 (AscCompareString((uchar *) inq->vendor_id,
12795 (uchar *) "QUANTUM XP34301", 15) == 0) &&
12796 (AscCompareString((uchar *) inq->product_rev_level,
12797 (uchar *) "1071", 4) == 0))
12805 AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
12806 uchar tid_no, ASC_SCSI_INQUIRY *inq)
12808 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
12809 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
12811 orig_init_sdtr = asc_dvc->init_sdtr;
12812 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
12814 asc_dvc->init_sdtr &= ~tid_bit;
12815 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
12816 asc_dvc->use_tagged_qng &= ~tid_bit;
12818 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
12819 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
12820 asc_dvc->init_sdtr |= tid_bit;
12822 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
12823 ASC_INQ_CMD_QUEUE(inq)) {
12824 if (AscTagQueuingSafe(inq)) {
12825 asc_dvc->use_tagged_qng |= tid_bit;
12826 asc_dvc->cfg->can_tagged_qng |= tid_bit;
12830 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
12831 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
12832 asc_dvc->cfg->disc_enable);
12833 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
12834 asc_dvc->use_tagged_qng);
12835 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
12836 asc_dvc->cfg->can_tagged_qng);
12838 asc_dvc->max_dvc_qng[tid_no] =
12839 asc_dvc->cfg->max_tag_qng[tid_no];
12840 AscWriteLramByte(asc_dvc->iop_base,
12841 (ushort) (ASCV_MAX_DVC_QNG_BEG + tid_no),
12842 asc_dvc->max_dvc_qng[tid_no]);
12844 if (orig_init_sdtr != asc_dvc->init_sdtr) {
12845 AscAsyncFix(asc_dvc, tid_no, inq);
12860 for (i = 0; i < len; i++) {
12861 diff = (int) (str1[i] - str2[i]);
12877 if (isodd_word(addr)) {
12878 AscSetChipLramAddr(iop_base, addr - 1);
12879 word_data = AscGetChipLramData(iop_base);
12880 byte_data = (uchar) ((word_data >> 8) & 0xFF);
12882 AscSetChipLramAddr(iop_base, addr);
12883 word_data = AscGetChipLramData(iop_base);
12884 byte_data = (uchar) (word_data & 0xFF);
12886 return (byte_data);
12896 AscSetChipLramAddr(iop_base, addr);
12897 word_data = AscGetChipLramData(iop_base);
12898 return (word_data);
12901 #if CC_VERY_LONG_SG_LIST
12908 ushort val_low, val_high;
12909 ASC_DCNT dword_data;
12911 AscSetChipLramAddr(iop_base, addr);
12912 val_low = AscGetChipLramData(iop_base);
12913 val_high = AscGetChipLramData(iop_base);
12914 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
12915 return (dword_data);
12917 #endif /* CC_VERY_LONG_SG_LIST */
12926 AscSetChipLramAddr(iop_base, addr);
12927 AscSetChipLramData(iop_base, word_val);
12940 if (isodd_word(addr)) {
12942 word_data = AscReadLramWord(iop_base, addr);
12943 word_data &= 0x00FF;
12944 word_data |= (((ushort) byte_val << 8) & 0xFF00);
12946 word_data = AscReadLramWord(iop_base, addr);
12947 word_data &= 0xFF00;
12948 word_data |= ((ushort) byte_val & 0x00FF);
12950 AscWriteLramWord(iop_base, addr, word_data);
12955 * Copy 2 bytes to LRAM.
12957 * The source data is assumed to be in little-endian order in memory
12958 * and is maintained in little-endian order when written to LRAM.
12961 AscMemWordCopyPtrToLram(
12970 AscSetChipLramAddr(iop_base, s_addr);
12971 for (i = 0; i < 2 * words; i += 2) {
12973 * On a little-endian system the second argument below
12974 * produces a little-endian ushort which is written to
12975 * LRAM in little-endian order. On a big-endian system
12976 * the second argument produces a big-endian ushort which
12977 * is "transparently" byte-swapped by outpw() and written
12978 * in little-endian order to LRAM.
12980 outpw(iop_base + IOP_RAM_DATA,
12981 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]);
12987 * Copy 4 bytes to LRAM.
12989 * The source data is assumed to be in little-endian order in memory
12990 * and is maintained in little-endian order when writen to LRAM.
12993 AscMemDWordCopyPtrToLram(
13002 AscSetChipLramAddr(iop_base, s_addr);
13003 for (i = 0; i < 4 * dwords; i += 4) {
13004 outpw(iop_base + IOP_RAM_DATA,
13005 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
13006 outpw(iop_base + IOP_RAM_DATA,
13007 ((ushort) s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
13013 * Copy 2 bytes from LRAM.
13015 * The source data is assumed to be in little-endian order in LRAM
13016 * and is maintained in little-endian order when written to memory.
13019 AscMemWordCopyPtrFromLram(
13029 AscSetChipLramAddr(iop_base, s_addr);
13030 for (i = 0; i < 2 * words; i += 2) {
13031 word = inpw(iop_base + IOP_RAM_DATA);
13032 d_buffer[i] = word & 0xff;
13033 d_buffer[i + 1] = (word >> 8) & 0xff;
13049 for (i = 0; i < words; i++, s_addr += 2) {
13050 sum += AscReadLramWord(iop_base, s_addr);
13065 AscSetChipLramAddr(iop_base, s_addr);
13066 for (i = 0; i < words; i++) {
13067 AscSetChipLramData(iop_base, set_wval);
13074 * --- Adv Library Functions
13079 /* Microcode buffer is kept after initialization for error recovery. */
13080 STATIC unsigned char _adv_asc3550_buf[] = {
13081 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, 0x01, 0x00, 0x48, 0xe4,
13082 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7,
13083 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
13084 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, 0x00, 0xec, 0x85, 0xf0,
13085 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00,
13086 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
13087 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea,
13088 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
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13315 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1, 0x05, 0xc6, 0x28, 0x84,
13316 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
13317 0x05, 0x50, 0xb4, 0x0c, 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
13318 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06, 0x21, 0x44, 0x01, 0xfe,
13319 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14, 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b,
13320 0x16, 0x44, 0xfe, 0x4a, 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
13321 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xd8, 0x14, 0x02, 0x5c,
13322 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe, 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72,
13323 0x03, 0x8f, 0xfe, 0xdc, 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
13324 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0xfe, 0xff, 0x7f,
13325 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c,
13326 0x3d, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
13327 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, 0x03, 0x0a, 0x50, 0x01,
13328 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4,
13329 0x19, 0x48, 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
13330 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe,
13331 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60,
13332 0x89, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
13333 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, 0xcc, 0x12, 0x49, 0x04,
13334 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13,
13335 0x06, 0x17, 0xc3, 0x78, 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
13336 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, 0x13, 0x06, 0xfe, 0x56,
13337 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93,
13338 0x13, 0x06, 0xfe, 0x28, 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
13339 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, 0x01, 0xba, 0xfe, 0x4e,
13340 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe,
13341 0x04, 0xf4, 0x6c, 0xfe, 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
13342 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13343 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13344 0x19, 0x83, 0x60, 0x23, 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
13345 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x0b, 0x01,
13346 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03,
13347 0x15, 0x06, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
13348 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, 0x4a, 0x01, 0x08, 0x03,
13349 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00,
13350 0x3b, 0x72, 0x9f, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
13351 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, 0x01, 0x43, 0x1e, 0xcd,
13352 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10,
13353 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
13354 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, 0x88, 0x03, 0x0a, 0x42,
13355 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2,
13356 0xfe, 0x49, 0xe4, 0x10, 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
13357 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe,
13358 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe,
13359 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
13360 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, 0x05, 0xfe, 0x66, 0x01,
13361 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66,
13362 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
13363 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x83,
13364 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe,
13365 0x94, 0x14, 0xfe, 0x10, 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13366 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x30, 0xbc, 0xfe,
13367 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a,
13368 0x16, 0xfe, 0x5c, 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13369 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, 0xfe, 0x1d, 0xf7, 0x4f,
13370 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58,
13371 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
13372 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, 0x06, 0x37, 0x95, 0xa9,
13373 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d,
13374 0x13, 0x0d, 0x03, 0x71, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
13375 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x3c, 0x8a, 0x0a,
13376 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc,
13377 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
13378 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xf6, 0xfe, 0xd6, 0xf0,
13379 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76,
13380 0x27, 0x01, 0xda, 0x17, 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
13381 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, 0xc8, 0xfe, 0x48, 0x55,
13382 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0,
13383 0x0a, 0x40, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
13384 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, 0x0e, 0x73, 0x75, 0x03,
13385 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b,
13386 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
13387 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, 0xfe, 0x94, 0x00, 0xfe,
13388 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e,
13389 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
13390 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1b, 0xfe, 0x5a,
13391 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07,
13392 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
13393 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, 0x03, 0x25, 0xfe, 0xca,
13394 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
13397 STATIC unsigned short _adv_asc3550_size =
13398 sizeof(_adv_asc3550_buf); /* 0x13AD */
13399 STATIC ADV_DCNT _adv_asc3550_chksum =
13400 0x04D52DDDUL; /* Expanded little-endian checksum. */
13402 /* Microcode buffer is kept after initialization for error recovery. */
13403 STATIC unsigned char _adv_asc38C0800_buf[] = {
13404 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, 0x01, 0x00, 0x48, 0xe4,
13405 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6,
13406 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
13407 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0, 0x18, 0xf4, 0x08, 0x00,
13408 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0,
13409 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
13410 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13, 0xba, 0x13, 0x18, 0x40,
13411 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01,
13412 0x76, 0x01, 0xb9, 0x54, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
13413 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12, 0x08, 0x12, 0x02, 0x4a,
13414 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa,
13415 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
13416 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d, 0x06, 0x13, 0x4c, 0x1c,
13417 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00,
13418 0xbe, 0x00, 0x00, 0x01, 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
13419 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, 0x05, 0x00, 0x34, 0x00,
13420 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f,
13421 0x0c, 0x10, 0x22, 0x11, 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
13422 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0,
13423 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00,
13424 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
13425 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13, 0x12, 0x13, 0x24, 0x14,
13426 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44,
13427 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
13428 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, 0x04, 0xf8,
13429 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13430 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
13431 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08, 0x68, 0x08, 0x69, 0x08,
13432 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10,
13433 0x2a, 0x11, 0x06, 0x12, 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
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13664 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01, 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02,
13665 0x00, 0x57, 0x52, 0x93, 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
13666 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04,
13667 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52,
13668 0x93, 0xfe, 0x0b, 0x58, 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
13669 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52, 0xfe, 0x00, 0x7d, 0xfe,
13670 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f,
13671 0x7d, 0x40, 0x04, 0xdd, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
13672 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33,
13673 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59,
13674 0x03, 0xcd, 0x28, 0xfe, 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
13675 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, 0x30, 0xfe, 0x78, 0x10,
13676 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00,
13677 0x96, 0xf2, 0x18, 0x6d, 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
13678 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, 0x10, 0x69, 0x06, 0xfe,
13679 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06,
13680 0x88, 0x98, 0xfe, 0x90, 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
13681 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, 0x9e, 0xfe, 0xf3, 0x10,
13682 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13683 0x6e, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13684 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, 0xf4, 0x00, 0xe9, 0x91,
13685 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01,
13686 0x0b, 0x26, 0xf3, 0x16, 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
13687 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x19, 0x01, 0x0b,
13688 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76,
13689 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
13690 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01,
13691 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00,
13692 0xfe, 0x20, 0x13, 0x1d, 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
13693 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, 0x07, 0x11, 0xae, 0x09,
13694 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80,
13695 0xe7, 0x11, 0x07, 0x11, 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
13696 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xfe, 0x80, 0x4c,
13697 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87,
13698 0x04, 0x18, 0x11, 0x75, 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
13699 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, 0x17, 0xad, 0x9a, 0x1b,
13700 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10,
13701 0x18, 0x11, 0x75, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
13702 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c,
13703 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17,
13704 0xfe, 0xb6, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
13705 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x2e, 0x97, 0xfe, 0x5a,
13706 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13707 0x04, 0xb9, 0x23, 0xfe, 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
13708 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xcb, 0x97, 0xfe, 0x92,
13709 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13710 0xf6, 0x11, 0x75, 0xfe, 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
13711 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x9a, 0x5b, 0x41, 0xfe,
13712 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd,
13713 0x00, 0x6a, 0x2a, 0x04, 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
13714 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, 0xfe, 0x7e, 0x18, 0x1e,
13715 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
13716 0x7c, 0x6f, 0x4f, 0x32, 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
13717 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc,
13718 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c,
13719 0x01, 0x73, 0xfe, 0x16, 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
13720 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, 0xe7, 0x0a, 0x10, 0xfe,
13721 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37,
13722 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
13723 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, 0x13, 0xa3, 0x04, 0x09,
13724 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8,
13725 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
13726 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, 0x1c, 0x19, 0x03, 0xfe,
13727 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19,
13728 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
13729 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, 0x08, 0x10, 0x03, 0xfe,
13730 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7,
13731 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
13732 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, 0x04, 0x07, 0x7e, 0xfe,
13733 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a,
13734 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
13735 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, 0xa9, 0xb8, 0x04, 0x15,
13736 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c,
13737 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
13738 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13741 STATIC unsigned short _adv_asc38C0800_size =
13742 sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13743 STATIC ADV_DCNT _adv_asc38C0800_chksum =
13744 0x050D3FD8UL; /* Expanded little-endian checksum. */
13746 /* Microcode buffer is kept after initialization for error recovery. */
13747 STATIC unsigned char _adv_asc38C1600_buf[] = {
13748 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, 0x18, 0xe4, 0x01, 0x00,
13749 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f,
13750 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
13751 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x01, 0xe6,
13752 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0,
13753 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
13754 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01, 0x06, 0x13, 0x0c, 0x1c,
13755 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80,
13756 0x62, 0x0a, 0x5a, 0x12, 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
13757 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x04, 0x13, 0xbb, 0x55,
13758 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00,
13759 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
13760 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01,
13761 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01,
13762 0xc6, 0x0e, 0x0c, 0x10, 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
13763 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x06, 0x00,
13764 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c,
13765 0x10, 0x44, 0x00, 0x4c, 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
13766 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00,
13767 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09,
13768 0x68, 0x0d, 0x02, 0x10, 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
13769 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
13770 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00,
13771 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
13772 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x42, 0x1d, 0x08, 0x44,
13773 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59,
13774 0x31, 0xe4, 0x02, 0xe6, 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
13775 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13776 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01,
13777 0xc8, 0x01, 0xca, 0x01, 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
13778 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10, 0xf3, 0x10, 0x06, 0x12,
13779 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe,
13780 0xec, 0x0e, 0xff, 0x10, 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
13781 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13782 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
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14121 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe, 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03,
14122 0xfe, 0x96, 0x00, 0xd1, 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
14123 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe,
14124 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa, 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a,
14125 0xf0, 0xfe, 0xba, 0x1d, 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
14126 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe, 0x1a, 0x10, 0x09, 0x0d,
14127 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42,
14128 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
14129 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, 0xfe, 0x82, 0xf0, 0xfe,
14130 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18,
14131 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
14132 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, 0x83, 0x33, 0x0b, 0x0e,
14133 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04,
14134 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
14135 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, 0xfe, 0x99, 0x83, 0xfe,
14136 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47,
14137 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14138 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x08, 0x90, 0x04,
14139 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79,
14140 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14141 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x3c, 0x90, 0x04,
14142 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83,
14143 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
14146 STATIC unsigned short _adv_asc38C1600_size =
14147 sizeof(_adv_asc38C1600_buf); /* 0x1673 */
14148 STATIC ADV_DCNT _adv_asc38C1600_chksum =
14149 0x0604EF77UL; /* Expanded little-endian checksum. */
14153 * EEPROM Configuration.
14155 * All drivers should use this structure to set the default EEPROM
14156 * configuration. The BIOS now uses this structure when it is built.
14157 * Additional structure information can be found in a_condor.h where
14158 * the structure is defined.
14160 * The *_Field_IsChar structs are needed to correct for endianness.
14161 * These values are read from the board 16 bits at a time directly
14162 * into the structs. Because some fields are char, the values will be
14163 * in the wrong order. The *_Field_IsChar tells when to flip the
14164 * bytes. Data read and written to PCI memory is automatically swapped
14165 * on big-endian platforms so char fields read as words are actually being
14166 * unswapped on big-endian platforms.
14168 STATIC ADVEEP_3550_CONFIG
14169 Default_3550_EEPROM_Config __initdata = {
14170 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
14171 0x0000, /* cfg_msw */
14172 0xFFFF, /* disc_enable */
14173 0xFFFF, /* wdtr_able */
14174 0xFFFF, /* sdtr_able */
14175 0xFFFF, /* start_motor */
14176 0xFFFF, /* tagqng_able */
14177 0xFFFF, /* bios_scan */
14178 0, /* scam_tolerant */
14179 7, /* adapter_scsi_id */
14180 0, /* bios_boot_delay */
14181 3, /* scsi_reset_delay */
14182 0, /* bios_id_lun */
14183 0, /* termination */
14185 0xFFE7, /* bios_ctrl */
14186 0xFFFF, /* ultra_able */
14188 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
14189 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14192 0, /* serial_number_word1 */
14193 0, /* serial_number_word2 */
14194 0, /* serial_number_word3 */
14196 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */
14197 0, /* dvc_err_code */
14198 0, /* adv_err_code */
14199 0, /* adv_err_addr */
14200 0, /* saved_dvc_err_code */
14201 0, /* saved_adv_err_code */
14202 0, /* saved_adv_err_addr */
14206 STATIC ADVEEP_3550_CONFIG
14207 ADVEEP_3550_Config_Field_IsChar __initdata = {
14210 0, /* -disc_enable */
14213 0, /* start_motor */
14214 0, /* tagqng_able */
14216 0, /* scam_tolerant */
14217 1, /* adapter_scsi_id */
14218 1, /* bios_boot_delay */
14219 1, /* scsi_reset_delay */
14220 1, /* bios_id_lun */
14221 1, /* termination */
14224 0, /* ultra_able */
14226 1, /* max_host_qng */
14227 1, /* max_dvc_qng */
14230 0, /* serial_number_word1 */
14231 0, /* serial_number_word2 */
14232 0, /* serial_number_word3 */
14234 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* oem_name[16] */
14235 0, /* dvc_err_code */
14236 0, /* adv_err_code */
14237 0, /* adv_err_addr */
14238 0, /* saved_dvc_err_code */
14239 0, /* saved_adv_err_code */
14240 0, /* saved_adv_err_addr */
14244 STATIC ADVEEP_38C0800_CONFIG
14245 Default_38C0800_EEPROM_Config __initdata = {
14246 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14247 0x0000, /* 01 cfg_msw */
14248 0xFFFF, /* 02 disc_enable */
14249 0xFFFF, /* 03 wdtr_able */
14250 0x4444, /* 04 sdtr_speed1 */
14251 0xFFFF, /* 05 start_motor */
14252 0xFFFF, /* 06 tagqng_able */
14253 0xFFFF, /* 07 bios_scan */
14254 0, /* 08 scam_tolerant */
14255 7, /* 09 adapter_scsi_id */
14256 0, /* bios_boot_delay */
14257 3, /* 10 scsi_reset_delay */
14258 0, /* bios_id_lun */
14259 0, /* 11 termination_se */
14260 0, /* termination_lvd */
14261 0xFFE7, /* 12 bios_ctrl */
14262 0x4444, /* 13 sdtr_speed2 */
14263 0x4444, /* 14 sdtr_speed3 */
14264 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14265 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14266 0, /* 16 dvc_cntl */
14267 0x4444, /* 17 sdtr_speed4 */
14268 0, /* 18 serial_number_word1 */
14269 0, /* 19 serial_number_word2 */
14270 0, /* 20 serial_number_word3 */
14271 0, /* 21 check_sum */
14272 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14273 0, /* 30 dvc_err_code */
14274 0, /* 31 adv_err_code */
14275 0, /* 32 adv_err_addr */
14276 0, /* 33 saved_dvc_err_code */
14277 0, /* 34 saved_adv_err_code */
14278 0, /* 35 saved_adv_err_addr */
14279 0, /* 36 reserved */
14280 0, /* 37 reserved */
14281 0, /* 38 reserved */
14282 0, /* 39 reserved */
14283 0, /* 40 reserved */
14284 0, /* 41 reserved */
14285 0, /* 42 reserved */
14286 0, /* 43 reserved */
14287 0, /* 44 reserved */
14288 0, /* 45 reserved */
14289 0, /* 46 reserved */
14290 0, /* 47 reserved */
14291 0, /* 48 reserved */
14292 0, /* 49 reserved */
14293 0, /* 50 reserved */
14294 0, /* 51 reserved */
14295 0, /* 52 reserved */
14296 0, /* 53 reserved */
14297 0, /* 54 reserved */
14298 0, /* 55 reserved */
14299 0, /* 56 cisptr_lsw */
14300 0, /* 57 cisprt_msw */
14301 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14302 ADV_PCI_DEVID_38C0800_REV1, /* 59 subsysid */
14303 0, /* 60 reserved */
14304 0, /* 61 reserved */
14305 0, /* 62 reserved */
14306 0 /* 63 reserved */
14309 STATIC ADVEEP_38C0800_CONFIG
14310 ADVEEP_38C0800_Config_Field_IsChar __initdata = {
14311 0, /* 00 cfg_lsw */
14312 0, /* 01 cfg_msw */
14313 0, /* 02 disc_enable */
14314 0, /* 03 wdtr_able */
14315 0, /* 04 sdtr_speed1 */
14316 0, /* 05 start_motor */
14317 0, /* 06 tagqng_able */
14318 0, /* 07 bios_scan */
14319 0, /* 08 scam_tolerant */
14320 1, /* 09 adapter_scsi_id */
14321 1, /* bios_boot_delay */
14322 1, /* 10 scsi_reset_delay */
14323 1, /* bios_id_lun */
14324 1, /* 11 termination_se */
14325 1, /* termination_lvd */
14326 0, /* 12 bios_ctrl */
14327 0, /* 13 sdtr_speed2 */
14328 0, /* 14 sdtr_speed3 */
14329 1, /* 15 max_host_qng */
14330 1, /* max_dvc_qng */
14331 0, /* 16 dvc_cntl */
14332 0, /* 17 sdtr_speed4 */
14333 0, /* 18 serial_number_word1 */
14334 0, /* 19 serial_number_word2 */
14335 0, /* 20 serial_number_word3 */
14336 0, /* 21 check_sum */
14337 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14338 0, /* 30 dvc_err_code */
14339 0, /* 31 adv_err_code */
14340 0, /* 32 adv_err_addr */
14341 0, /* 33 saved_dvc_err_code */
14342 0, /* 34 saved_adv_err_code */
14343 0, /* 35 saved_adv_err_addr */
14344 0, /* 36 reserved */
14345 0, /* 37 reserved */
14346 0, /* 38 reserved */
14347 0, /* 39 reserved */
14348 0, /* 40 reserved */
14349 0, /* 41 reserved */
14350 0, /* 42 reserved */
14351 0, /* 43 reserved */
14352 0, /* 44 reserved */
14353 0, /* 45 reserved */
14354 0, /* 46 reserved */
14355 0, /* 47 reserved */
14356 0, /* 48 reserved */
14357 0, /* 49 reserved */
14358 0, /* 50 reserved */
14359 0, /* 51 reserved */
14360 0, /* 52 reserved */
14361 0, /* 53 reserved */
14362 0, /* 54 reserved */
14363 0, /* 55 reserved */
14364 0, /* 56 cisptr_lsw */
14365 0, /* 57 cisprt_msw */
14366 0, /* 58 subsysvid */
14367 0, /* 59 subsysid */
14368 0, /* 60 reserved */
14369 0, /* 61 reserved */
14370 0, /* 62 reserved */
14371 0 /* 63 reserved */
14374 STATIC ADVEEP_38C1600_CONFIG
14375 Default_38C1600_EEPROM_Config __initdata = {
14376 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14377 0x0000, /* 01 cfg_msw */
14378 0xFFFF, /* 02 disc_enable */
14379 0xFFFF, /* 03 wdtr_able */
14380 0x5555, /* 04 sdtr_speed1 */
14381 0xFFFF, /* 05 start_motor */
14382 0xFFFF, /* 06 tagqng_able */
14383 0xFFFF, /* 07 bios_scan */
14384 0, /* 08 scam_tolerant */
14385 7, /* 09 adapter_scsi_id */
14386 0, /* bios_boot_delay */
14387 3, /* 10 scsi_reset_delay */
14388 0, /* bios_id_lun */
14389 0, /* 11 termination_se */
14390 0, /* termination_lvd */
14391 0xFFE7, /* 12 bios_ctrl */
14392 0x5555, /* 13 sdtr_speed2 */
14393 0x5555, /* 14 sdtr_speed3 */
14394 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14395 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14396 0, /* 16 dvc_cntl */
14397 0x5555, /* 17 sdtr_speed4 */
14398 0, /* 18 serial_number_word1 */
14399 0, /* 19 serial_number_word2 */
14400 0, /* 20 serial_number_word3 */
14401 0, /* 21 check_sum */
14402 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14403 0, /* 30 dvc_err_code */
14404 0, /* 31 adv_err_code */
14405 0, /* 32 adv_err_addr */
14406 0, /* 33 saved_dvc_err_code */
14407 0, /* 34 saved_adv_err_code */
14408 0, /* 35 saved_adv_err_addr */
14409 0, /* 36 reserved */
14410 0, /* 37 reserved */
14411 0, /* 38 reserved */
14412 0, /* 39 reserved */
14413 0, /* 40 reserved */
14414 0, /* 41 reserved */
14415 0, /* 42 reserved */
14416 0, /* 43 reserved */
14417 0, /* 44 reserved */
14418 0, /* 45 reserved */
14419 0, /* 46 reserved */
14420 0, /* 47 reserved */
14421 0, /* 48 reserved */
14422 0, /* 49 reserved */
14423 0, /* 50 reserved */
14424 0, /* 51 reserved */
14425 0, /* 52 reserved */
14426 0, /* 53 reserved */
14427 0, /* 54 reserved */
14428 0, /* 55 reserved */
14429 0, /* 56 cisptr_lsw */
14430 0, /* 57 cisprt_msw */
14431 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14432 ADV_PCI_DEVID_38C1600_REV1, /* 59 subsysid */
14433 0, /* 60 reserved */
14434 0, /* 61 reserved */
14435 0, /* 62 reserved */
14436 0 /* 63 reserved */
14439 STATIC ADVEEP_38C1600_CONFIG
14440 ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14441 0, /* 00 cfg_lsw */
14442 0, /* 01 cfg_msw */
14443 0, /* 02 disc_enable */
14444 0, /* 03 wdtr_able */
14445 0, /* 04 sdtr_speed1 */
14446 0, /* 05 start_motor */
14447 0, /* 06 tagqng_able */
14448 0, /* 07 bios_scan */
14449 0, /* 08 scam_tolerant */
14450 1, /* 09 adapter_scsi_id */
14451 1, /* bios_boot_delay */
14452 1, /* 10 scsi_reset_delay */
14453 1, /* bios_id_lun */
14454 1, /* 11 termination_se */
14455 1, /* termination_lvd */
14456 0, /* 12 bios_ctrl */
14457 0, /* 13 sdtr_speed2 */
14458 0, /* 14 sdtr_speed3 */
14459 1, /* 15 max_host_qng */
14460 1, /* max_dvc_qng */
14461 0, /* 16 dvc_cntl */
14462 0, /* 17 sdtr_speed4 */
14463 0, /* 18 serial_number_word1 */
14464 0, /* 19 serial_number_word2 */
14465 0, /* 20 serial_number_word3 */
14466 0, /* 21 check_sum */
14467 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14468 0, /* 30 dvc_err_code */
14469 0, /* 31 adv_err_code */
14470 0, /* 32 adv_err_addr */
14471 0, /* 33 saved_dvc_err_code */
14472 0, /* 34 saved_adv_err_code */
14473 0, /* 35 saved_adv_err_addr */
14474 0, /* 36 reserved */
14475 0, /* 37 reserved */
14476 0, /* 38 reserved */
14477 0, /* 39 reserved */
14478 0, /* 40 reserved */
14479 0, /* 41 reserved */
14480 0, /* 42 reserved */
14481 0, /* 43 reserved */
14482 0, /* 44 reserved */
14483 0, /* 45 reserved */
14484 0, /* 46 reserved */
14485 0, /* 47 reserved */
14486 0, /* 48 reserved */
14487 0, /* 49 reserved */
14488 0, /* 50 reserved */
14489 0, /* 51 reserved */
14490 0, /* 52 reserved */
14491 0, /* 53 reserved */
14492 0, /* 54 reserved */
14493 0, /* 55 reserved */
14494 0, /* 56 cisptr_lsw */
14495 0, /* 57 cisprt_msw */
14496 0, /* 58 subsysvid */
14497 0, /* 59 subsysid */
14498 0, /* 60 reserved */
14499 0, /* 61 reserved */
14500 0, /* 62 reserved */
14501 0 /* 63 reserved */
14505 * Initialize the ADV_DVC_VAR structure.
14507 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14509 * For a non-fatal error return a warning code. If there are no warnings
14510 * then 0 is returned.
14513 AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14516 AdvPortAddr iop_base;
14521 asc_dvc->err_code = 0;
14522 iop_base = asc_dvc->iop_base;
14525 * PCI Command Register
14527 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14528 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14531 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14532 AscPCIConfigCommandRegister))
14533 & AscPCICmdRegBits_BusMastering)
14534 != AscPCICmdRegBits_BusMastering)
14536 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14538 DvcAdvWritePCIConfigByte(asc_dvc,
14539 AscPCIConfigCommandRegister, pci_cmd_reg);
14541 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister))
14542 & AscPCICmdRegBits_BusMastering)
14543 != AscPCICmdRegBits_BusMastering)
14545 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14550 * PCI Latency Timer
14552 * If the "latency timer" register is 0x20 or above, then we don't need
14553 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14554 * comes up less than 0x20).
14556 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14557 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer, 0x20);
14558 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20)
14560 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14565 * Save the state of the PCI Configuration Command Register
14566 * "Parity Error Response Control" Bit. If the bit is clear (0),
14567 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14568 * DMA parity errors.
14570 asc_dvc->cfg->control_flag = 0;
14571 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14572 & AscPCICmdRegBits_ParErrRespCtrl)) == 0)
14574 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14577 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14578 ADV_LIB_VERSION_MINOR;
14579 asc_dvc->cfg->chip_version =
14580 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14582 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14583 (ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14584 (ushort) ADV_CHIP_ID_BYTE);
14586 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14587 (ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14588 (ushort) ADV_CHIP_ID_WORD);
14591 * Reset the chip to start and allow register writes.
14593 if (AdvFindSignature(iop_base) == 0)
14595 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14600 * The caller must set 'chip_type' to a valid setting.
14602 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14603 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14604 asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
14606 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14613 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14614 ADV_CTRL_REG_CMD_RESET);
14615 DvcSleepMilliSecond(100);
14616 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14617 ADV_CTRL_REG_CMD_WR_IO_REG);
14619 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
14621 if ((status = AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR)
14625 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
14627 if ((status = AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR)
14633 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR)
14638 warn_code |= status;
14645 * Initialize the ASC-3550.
14647 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14649 * For a non-fatal error return a warning code. If there are no warnings
14650 * then 0 is returned.
14652 * Needed after initialization for error recovery.
14655 AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14657 AdvPortAddr iop_base;
14665 int adv_asc3550_expanded_size;
14667 ADV_DCNT contig_len;
14668 ADV_SDCNT buf_size;
14669 ADV_PADDR carr_paddr;
14673 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
14674 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14675 uchar max_cmd[ADV_MAX_TID + 1];
14677 /* If there is already an error, don't continue. */
14678 if (asc_dvc->err_code != 0)
14684 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14686 if (asc_dvc->chip_type != ADV_CHIP_ASC3550)
14688 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14693 iop_base = asc_dvc->iop_base;
14696 * Save the RISC memory BIOS region before writing the microcode.
14697 * The BIOS may already be loaded and using its RISC LRAM region
14698 * so its region must be saved and restored.
14700 * Note: This code makes the assumption, which is currently true,
14701 * that a chip reset does not clear RISC LRAM.
14703 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14705 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14709 * Save current per TID negotiated values.
14711 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
14713 ushort bios_version, major, minor;
14715 bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
14716 major = (bios_version >> 12) & 0xF;
14717 minor = (bios_version >> 8) & 0xF;
14718 if (major < 3 || (major == 3 && minor == 1))
14720 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14721 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14724 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14727 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14728 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14729 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14731 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14736 * Load the Microcode
14738 * Write the microcode image to RISC memory starting at address 0.
14740 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14741 /* Assume the following compressed format of the microcode buffer:
14743 * 254 word (508 byte) table indexed by byte code followed
14744 * by the following byte codes:
14747 * 00: Emit word 0 in table.
14748 * 01: Emit word 1 in table.
14750 * FD: Emit word 253 in table.
14753 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14754 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14757 for (i = 253 * 2; i < _adv_asc3550_size; i++)
14759 if (_adv_asc3550_buf[i] == 0xff)
14761 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
14763 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14764 _adv_asc3550_buf[i + 3] << 8) |
14765 _adv_asc3550_buf[i + 2]));
14769 } else if (_adv_asc3550_buf[i] == 0xfe)
14771 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14772 _adv_asc3550_buf[i + 2] << 8) |
14773 _adv_asc3550_buf[i + 1]));
14778 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14779 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
14780 _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14786 * Set 'word' for later use to clear the rest of memory and save
14787 * the expanded mcode size.
14790 adv_asc3550_expanded_size = word;
14793 * Clear the rest of ASC-3550 Internal RAM (8KB).
14795 for (; word < ADV_3550_MEMSIZE; word += 2)
14797 AdvWriteWordAutoIncLram(iop_base, 0);
14801 * Verify the microcode checksum.
14804 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14806 for (word = 0; word < adv_asc3550_expanded_size; word += 2)
14808 sum += AdvReadWordAutoIncLram(iop_base);
14811 if (sum != _adv_asc3550_chksum)
14813 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14818 * Restore the RISC memory BIOS region.
14820 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14822 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14826 * Calculate and write the microcode code checksum to the microcode
14827 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14829 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14830 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14832 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14833 for (word = begin_addr; word < end_addr; word += 2)
14835 code_sum += AdvReadWordAutoIncLram(iop_base);
14837 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14840 * Read and save microcode version and date.
14842 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
14843 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
14846 * Set the chip type to indicate the ASC3550.
14848 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14851 * If the PCI Configuration Command Register "Parity Error Response
14852 * Control" Bit was clear (0), then set the microcode variable
14853 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14854 * to ignore DMA parity errors.
14856 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
14858 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14859 word |= CONTROL_FLAG_IGNORE_PERR;
14860 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14864 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14865 * threshold of 128 bytes. This register is only accessible to the host.
14867 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14868 START_CTL_EMFU | READ_CMD_MRM);
14871 * Microcode operating variables for WDTR, SDTR, and command tag
14872 * queuing will be set in AdvInquiryHandling() based on what a
14873 * device reports it is capable of in Inquiry byte 7.
14875 * If SCSI Bus Resets have been disabled, then directly set
14876 * SDTR and WDTR from the EEPROM configuration. This will allow
14877 * the BIOS and warm boot to work without a SCSI bus hang on
14878 * the Inquiry caused by host and target mismatched DTR values.
14879 * Without the SCSI Bus Reset, before an Inquiry a device can't
14880 * be assumed to be in Asynchronous, Narrow mode.
14882 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
14884 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
14885 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
14889 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14890 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14891 * bitmask. These values determine the maximum SDTR speed negotiated
14894 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14895 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14896 * without determining here whether the device supports SDTR.
14898 * 4-bit speed SDTR speed name
14899 * =========== ===============
14900 * 0000b (0x0) SDTR disabled
14901 * 0001b (0x1) 5 Mhz
14902 * 0010b (0x2) 10 Mhz
14903 * 0011b (0x3) 20 Mhz (Ultra)
14904 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14905 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14906 * 0110b (0x6) Undefined
14908 * 1111b (0xF) Undefined
14911 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14913 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able)
14915 /* Set Ultra speed for TID 'tid'. */
14916 word |= (0x3 << (4 * (tid % 4)));
14919 /* Set Fast speed for TID 'tid'. */
14920 word |= (0x2 << (4 * (tid % 4)));
14922 if (tid == 3) /* Check if done with sdtr_speed1. */
14924 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14926 } else if (tid == 7) /* Check if done with sdtr_speed2. */
14928 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14930 } else if (tid == 11) /* Check if done with sdtr_speed3. */
14932 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14934 } else if (tid == 15) /* Check if done with sdtr_speed4. */
14936 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14942 * Set microcode operating variable for the disconnect per TID bitmask.
14944 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
14947 * Set SCSI_CFG0 Microcode Default Value.
14949 * The microcode will set the SCSI_CFG0 register using this value
14950 * after it is started below.
14952 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14953 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14954 asc_dvc->chip_scsi_id);
14957 * Determine SCSI_CFG1 Microcode Default Value.
14959 * The microcode will set the SCSI_CFG1 register using this value
14960 * after it is started below.
14963 /* Read current SCSI_CFG1 Register value. */
14964 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14967 * If all three connectors are in use, return an error.
14969 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14970 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0)
14972 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14977 * If the internal narrow cable is reversed all of the SCSI_CTRL
14978 * register signals will be set. Check for and return an error if
14979 * this condition is found.
14981 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
14983 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14988 * If this is a differential board and a single-ended device
14989 * is attached to one of the connectors, return an error.
14991 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0)
14993 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14998 * If automatic termination control is enabled, then set the
14999 * termination value based on a table listed in a_condor.h.
15001 * If manual termination was specified with an EEPROM setting
15002 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
15003 * is ready to be 'ored' into SCSI_CFG1.
15005 if (asc_dvc->cfg->termination == 0)
15008 * The software always controls termination by setting TERM_CTL_SEL.
15009 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
15011 asc_dvc->cfg->termination |= TERM_CTL_SEL;
15013 switch(scsi_cfg1 & CABLE_DETECT)
15015 /* TERM_CTL_H: on, TERM_CTL_L: on */
15016 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF:
15017 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
15020 /* TERM_CTL_H: on, TERM_CTL_L: off */
15021 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC:
15022 asc_dvc->cfg->termination |= TERM_CTL_H;
15025 /* TERM_CTL_H: off, TERM_CTL_L: off */
15026 case 0x2: case 0x6:
15032 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
15034 scsi_cfg1 &= ~TERM_CTL;
15037 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
15038 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
15039 * referenced, because the hardware internally inverts
15040 * the Termination High and Low bits if TERM_POL is set.
15042 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
15045 * Set SCSI_CFG1 Microcode Default Value
15047 * Set filter value and possibly modified termination control
15048 * bits in the Microcode SCSI_CFG1 Register Value.
15050 * The microcode will set the SCSI_CFG1 register using this value
15051 * after it is started below.
15053 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
15054 FLTR_DISABLE | scsi_cfg1);
15057 * Set MEM_CFG Microcode Default Value
15059 * The microcode will set the MEM_CFG register using this value
15060 * after it is started below.
15062 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15065 * ASC-3550 has 8KB internal memory.
15067 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15068 BIOS_EN | RAM_SZ_8KB);
15071 * Set SEL_MASK Microcode Default Value
15073 * The microcode will set the SEL_MASK register using this value
15074 * after it is started below.
15076 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15077 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15080 * Build carrier freelist.
15082 * Driver must have already allocated memory and set 'carrier_buf'.
15084 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15086 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15087 asc_dvc->carr_freelist = NULL;
15088 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15090 buf_size = ADV_CARRIER_BUFSIZE;
15093 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15098 * Get physical address of the carrier 'carrp'.
15100 contig_len = sizeof(ADV_CARR_T);
15101 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15102 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15104 buf_size -= sizeof(ADV_CARR_T);
15107 * If the current carrier is not physically contiguous, then
15108 * maybe there was a page crossing. Try the next carrier aligned
15111 if (contig_len < sizeof(ADV_CARR_T))
15117 carrp->carr_pa = carr_paddr;
15118 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15121 * Insert the carrier at the beginning of the freelist.
15123 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15124 asc_dvc->carr_freelist = carrp;
15128 while (buf_size > 0);
15131 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15134 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15136 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15139 asc_dvc->carr_freelist = (ADV_CARR_T *)
15140 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15143 * The first command issued will be placed in the stopper carrier.
15145 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15148 * Set RISC ICQ physical address start value.
15150 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15153 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15155 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15157 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15160 asc_dvc->carr_freelist = (ADV_CARR_T *)
15161 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15164 * The first command completed by the RISC will be placed in
15167 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15168 * completed the RISC will set the ASC_RQ_STOPPER bit.
15170 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15173 * Set RISC IRQ physical address start value.
15175 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15176 asc_dvc->carr_pending_cnt = 0;
15178 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15179 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15181 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15182 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15184 /* finally, finally, gentlemen, start your engine */
15185 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15188 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15189 * Resets should be performed. The RISC has to be running
15190 * to issue a SCSI Bus Reset.
15192 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15195 * If the BIOS Signature is present in memory, restore the
15196 * BIOS Handshake Configuration Table and do not perform
15197 * a SCSI Bus Reset.
15199 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15202 * Restore per TID negotiated values.
15204 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15205 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15206 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15207 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15209 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15214 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15216 warn_code = ASC_WARN_BUSRESET_ERROR;
15225 * Initialize the ASC-38C0800.
15227 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
15229 * For a non-fatal error return a warning code. If there are no warnings
15230 * then 0 is returned.
15232 * Needed after initialization for error recovery.
15235 AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
15237 AdvPortAddr iop_base;
15245 int adv_asc38C0800_expanded_size;
15247 ADV_DCNT contig_len;
15248 ADV_SDCNT buf_size;
15249 ADV_PADDR carr_paddr;
15254 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15255 ushort wdtr_able, sdtr_able, tagqng_able;
15256 uchar max_cmd[ADV_MAX_TID + 1];
15258 /* If there is already an error, don't continue. */
15259 if (asc_dvc->err_code != 0)
15265 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
15267 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
15269 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15274 iop_base = asc_dvc->iop_base;
15277 * Save the RISC memory BIOS region before writing the microcode.
15278 * The BIOS may already be loaded and using its RISC LRAM region
15279 * so its region must be saved and restored.
15281 * Note: This code makes the assumption, which is currently true,
15282 * that a chip reset does not clear RISC LRAM.
15284 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15286 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15290 * Save current per TID negotiated values.
15292 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15293 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15294 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15295 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15297 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15302 * RAM BIST (RAM Built-In Self Test)
15304 * Address : I/O base + offset 0x38h register (byte).
15305 * Function: Bit 7-6(RW) : RAM mode
15306 * Normal Mode : 0x00
15307 * Pre-test Mode : 0x40
15308 * RAM Test Mode : 0x80
15310 * Bit 4(RO) : Done bit
15311 * Bit 3-0(RO) : Status
15312 * Host Error : 0x08
15313 * Int_RAM Error : 0x04
15314 * RISC Error : 0x02
15315 * SCSI Error : 0x01
15318 * Note: RAM BIST code should be put right here, before loading the
15319 * microcode and after saving the RISC memory BIOS region.
15325 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15326 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15327 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15328 * to NORMAL_MODE, return an error too.
15330 for (i = 0; i < 2; i++)
15332 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15333 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15334 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15335 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15337 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15341 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15342 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15343 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15346 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15352 * LRAM Test - It takes about 1.5 ms to run through the test.
15354 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15355 * If Done bit not set or Status not 0, save register byte, set the
15356 * err_code, and return an error.
15358 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15359 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15361 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15362 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15364 /* Get here if Done bit not set or Status not 0. */
15365 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15366 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15370 /* We need to reset back to normal mode after LRAM test passes. */
15371 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15374 * Load the Microcode
15376 * Write the microcode image to RISC memory starting at address 0.
15379 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15381 /* Assume the following compressed format of the microcode buffer:
15383 * 254 word (508 byte) table indexed by byte code followed
15384 * by the following byte codes:
15387 * 00: Emit word 0 in table.
15388 * 01: Emit word 1 in table.
15390 * FD: Emit word 253 in table.
15393 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15394 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15397 for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
15399 if (_adv_asc38C0800_buf[i] == 0xff)
15401 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
15403 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15404 _adv_asc38C0800_buf[i + 3] << 8) |
15405 _adv_asc38C0800_buf[i + 2]));
15409 } else if (_adv_asc38C0800_buf[i] == 0xfe)
15411 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15412 _adv_asc38C0800_buf[i + 2] << 8) |
15413 _adv_asc38C0800_buf[i + 1]));
15418 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15419 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
15420 _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15426 * Set 'word' for later use to clear the rest of memory and save
15427 * the expanded mcode size.
15430 adv_asc38C0800_expanded_size = word;
15433 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15435 for (; word < ADV_38C0800_MEMSIZE; word += 2)
15437 AdvWriteWordAutoIncLram(iop_base, 0);
15441 * Verify the microcode checksum.
15444 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15446 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
15448 sum += AdvReadWordAutoIncLram(iop_base);
15450 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15453 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15454 (ulong) sum, (ulong) _adv_asc38C0800_chksum);
15456 if (sum != _adv_asc38C0800_chksum)
15458 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15463 * Restore the RISC memory BIOS region.
15465 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15467 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15471 * Calculate and write the microcode code checksum to the microcode
15472 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15474 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15475 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15477 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15478 for (word = begin_addr; word < end_addr; word += 2)
15480 code_sum += AdvReadWordAutoIncLram(iop_base);
15482 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15485 * Read microcode version and date.
15487 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
15488 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
15491 * Set the chip type to indicate the ASC38C0800.
15493 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15496 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15497 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15498 * cable detection and then we are able to read C_DET[3:0].
15500 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15501 * Microcode Default Value' section below.
15503 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15504 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
15507 * If the PCI Configuration Command Register "Parity Error Response
15508 * Control" Bit was clear (0), then set the microcode variable
15509 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15510 * to ignore DMA parity errors.
15512 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
15514 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15515 word |= CONTROL_FLAG_IGNORE_PERR;
15516 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15520 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15521 * bits for the default FIFO threshold.
15523 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15525 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15527 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15528 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15531 * Microcode operating variables for WDTR, SDTR, and command tag
15532 * queuing will be set in AdvInquiryHandling() based on what a
15533 * device reports it is capable of in Inquiry byte 7.
15535 * If SCSI Bus Resets have been disabled, then directly set
15536 * SDTR and WDTR from the EEPROM configuration. This will allow
15537 * the BIOS and warm boot to work without a SCSI bus hang on
15538 * the Inquiry caused by host and target mismatched DTR values.
15539 * Without the SCSI Bus Reset, before an Inquiry a device can't
15540 * be assumed to be in Asynchronous, Narrow mode.
15542 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
15544 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
15545 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
15549 * Set microcode operating variables for DISC and SDTR_SPEED1,
15550 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15551 * configuration values.
15553 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15554 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15555 * without determining here whether the device supports SDTR.
15557 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
15558 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15559 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15560 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15561 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15564 * Set SCSI_CFG0 Microcode Default Value.
15566 * The microcode will set the SCSI_CFG0 register using this value
15567 * after it is started below.
15569 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15570 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15571 asc_dvc->chip_scsi_id);
15574 * Determine SCSI_CFG1 Microcode Default Value.
15576 * The microcode will set the SCSI_CFG1 register using this value
15577 * after it is started below.
15580 /* Read current SCSI_CFG1 Register value. */
15581 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15584 * If the internal narrow cable is reversed all of the SCSI_CTRL
15585 * register signals will be set. Check for and return an error if
15586 * this condition is found.
15588 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
15590 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15595 * All kind of combinations of devices attached to one of four connectors
15596 * are acceptable except HVD device attached. For example, LVD device can
15597 * be attached to SE connector while SE device attached to LVD connector.
15598 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15600 * If an HVD device is attached to one of LVD connectors, return an error.
15601 * However, there is no way to detect HVD device attached to SE connectors.
15603 if (scsi_cfg1 & HVD)
15605 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15610 * If either SE or LVD automatic termination control is enabled, then
15611 * set the termination value based on a table listed in a_condor.h.
15613 * If manual termination was specified with an EEPROM setting then
15614 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15615 * be 'ored' into SCSI_CFG1.
15617 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
15619 /* SE automatic termination control is enabled. */
15620 switch(scsi_cfg1 & C_DET_SE)
15622 /* TERM_SE_HI: on, TERM_SE_LO: on */
15623 case 0x1: case 0x2: case 0x3:
15624 asc_dvc->cfg->termination |= TERM_SE;
15627 /* TERM_SE_HI: on, TERM_SE_LO: off */
15629 asc_dvc->cfg->termination |= TERM_SE_HI;
15634 if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
15636 /* LVD automatic termination control is enabled. */
15637 switch(scsi_cfg1 & C_DET_LVD)
15639 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15640 case 0x4: case 0x8: case 0xC:
15641 asc_dvc->cfg->termination |= TERM_LVD;
15644 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15651 * Clear any set TERM_SE and TERM_LVD bits.
15653 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15656 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15658 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15661 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15662 * and set possibly modified termination control bits in the Microcode
15663 * SCSI_CFG1 Register Value.
15665 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15668 * Set SCSI_CFG1 Microcode Default Value
15670 * Set possibly modified termination control and reset DIS_TERM_DRV
15671 * bits in the Microcode SCSI_CFG1 Register Value.
15673 * The microcode will set the SCSI_CFG1 register using this value
15674 * after it is started below.
15676 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15679 * Set MEM_CFG Microcode Default Value
15681 * The microcode will set the MEM_CFG register using this value
15682 * after it is started below.
15684 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15687 * ASC-38C0800 has 16KB internal memory.
15689 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15690 BIOS_EN | RAM_SZ_16KB);
15693 * Set SEL_MASK Microcode Default Value
15695 * The microcode will set the SEL_MASK register using this value
15696 * after it is started below.
15698 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15699 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15702 * Build the carrier freelist.
15704 * Driver must have already allocated memory and set 'carrier_buf'.
15706 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15708 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15709 asc_dvc->carr_freelist = NULL;
15710 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15712 buf_size = ADV_CARRIER_BUFSIZE;
15715 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15720 * Get physical address for the carrier 'carrp'.
15722 contig_len = sizeof(ADV_CARR_T);
15723 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15724 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15726 buf_size -= sizeof(ADV_CARR_T);
15729 * If the current carrier is not physically contiguous, then
15730 * maybe there was a page crossing. Try the next carrier aligned
15733 if (contig_len < sizeof(ADV_CARR_T))
15739 carrp->carr_pa = carr_paddr;
15740 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15743 * Insert the carrier at the beginning of the freelist.
15745 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15746 asc_dvc->carr_freelist = carrp;
15750 while (buf_size > 0);
15753 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15756 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15758 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15761 asc_dvc->carr_freelist = (ADV_CARR_T *)
15762 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15765 * The first command issued will be placed in the stopper carrier.
15767 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15770 * Set RISC ICQ physical address start value.
15771 * carr_pa is LE, must be native before write
15773 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15776 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15778 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15780 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15783 asc_dvc->carr_freelist = (ADV_CARR_T *)
15784 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15787 * The first command completed by the RISC will be placed in
15790 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15791 * completed the RISC will set the ASC_RQ_STOPPER bit.
15793 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15796 * Set RISC IRQ physical address start value.
15798 * carr_pa is LE, must be native before write *
15800 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15801 asc_dvc->carr_pending_cnt = 0;
15803 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15804 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15806 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15807 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15809 /* finally, finally, gentlemen, start your engine */
15810 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15813 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15814 * Resets should be performed. The RISC has to be running
15815 * to issue a SCSI Bus Reset.
15817 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15820 * If the BIOS Signature is present in memory, restore the
15821 * BIOS Handshake Configuration Table and do not perform
15822 * a SCSI Bus Reset.
15824 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15827 * Restore per TID negotiated values.
15829 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15830 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15831 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15832 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15834 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15839 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15841 warn_code = ASC_WARN_BUSRESET_ERROR;
15850 * Initialize the ASC-38C1600.
15852 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15854 * For a non-fatal error return a warning code. If there are no warnings
15855 * then 0 is returned.
15857 * Needed after initialization for error recovery.
15860 AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15862 AdvPortAddr iop_base;
15870 int adv_asc38C1600_expanded_size;
15872 ADV_DCNT contig_len;
15873 ADV_SDCNT buf_size;
15874 ADV_PADDR carr_paddr;
15879 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15880 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15881 uchar max_cmd[ASC_MAX_TID + 1];
15883 /* If there is already an error, don't continue. */
15884 if (asc_dvc->err_code != 0)
15890 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15892 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
15894 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15899 iop_base = asc_dvc->iop_base;
15902 * Save the RISC memory BIOS region before writing the microcode.
15903 * The BIOS may already be loaded and using its RISC LRAM region
15904 * so its region must be saved and restored.
15906 * Note: This code makes the assumption, which is currently true,
15907 * that a chip reset does not clear RISC LRAM.
15909 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15911 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15915 * Save current per TID negotiated values.
15917 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15918 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15919 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15920 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15921 for (tid = 0; tid <= ASC_MAX_TID; tid++)
15923 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15928 * RAM BIST (Built-In Self Test)
15930 * Address : I/O base + offset 0x38h register (byte).
15931 * Function: Bit 7-6(RW) : RAM mode
15932 * Normal Mode : 0x00
15933 * Pre-test Mode : 0x40
15934 * RAM Test Mode : 0x80
15936 * Bit 4(RO) : Done bit
15937 * Bit 3-0(RO) : Status
15938 * Host Error : 0x08
15939 * Int_RAM Error : 0x04
15940 * RISC Error : 0x02
15941 * SCSI Error : 0x01
15944 * Note: RAM BIST code should be put right here, before loading the
15945 * microcode and after saving the RISC memory BIOS region.
15951 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15952 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15953 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15954 * to NORMAL_MODE, return an error too.
15956 for (i = 0; i < 2; i++)
15958 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15959 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15960 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15961 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15963 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15967 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15968 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15969 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15972 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15978 * LRAM Test - It takes about 1.5 ms to run through the test.
15980 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15981 * If Done bit not set or Status not 0, save register byte, set the
15982 * err_code, and return an error.
15984 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15985 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15987 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15988 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15990 /* Get here if Done bit not set or Status not 0. */
15991 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15992 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15996 /* We need to reset back to normal mode after LRAM test passes. */
15997 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
16000 * Load the Microcode
16002 * Write the microcode image to RISC memory starting at address 0.
16005 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16008 * Assume the following compressed format of the microcode buffer:
16010 * 254 word (508 byte) table indexed by byte code followed
16011 * by the following byte codes:
16014 * 00: Emit word 0 in table.
16015 * 01: Emit word 1 in table.
16017 * FD: Emit word 253 in table.
16020 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
16021 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
16024 for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
16026 if (_adv_asc38C1600_buf[i] == 0xff)
16028 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
16030 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16031 _adv_asc38C1600_buf[i + 3] << 8) |
16032 _adv_asc38C1600_buf[i + 2]));
16036 } else if (_adv_asc38C1600_buf[i] == 0xfe)
16038 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16039 _adv_asc38C1600_buf[i + 2] << 8) |
16040 _adv_asc38C1600_buf[i + 1]));
16045 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16046 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
16047 _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
16053 * Set 'word' for later use to clear the rest of memory and save
16054 * the expanded mcode size.
16057 adv_asc38C1600_expanded_size = word;
16060 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
16062 for (; word < ADV_38C1600_MEMSIZE; word += 2)
16064 AdvWriteWordAutoIncLram(iop_base, 0);
16068 * Verify the microcode checksum.
16071 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16073 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
16075 sum += AdvReadWordAutoIncLram(iop_base);
16078 if (sum != _adv_asc38C1600_chksum)
16080 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
16085 * Restore the RISC memory BIOS region.
16087 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
16089 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
16093 * Calculate and write the microcode code checksum to the microcode
16094 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
16096 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
16097 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
16099 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
16100 for (word = begin_addr; word < end_addr; word += 2)
16102 code_sum += AdvReadWordAutoIncLram(iop_base);
16104 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
16107 * Read microcode version and date.
16109 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
16110 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
16113 * Set the chip type to indicate the ASC38C1600.
16115 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
16118 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
16119 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
16120 * cable detection and then we are able to read C_DET[3:0].
16122 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
16123 * Microcode Default Value' section below.
16125 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16126 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
16129 * If the PCI Configuration Command Register "Parity Error Response
16130 * Control" Bit was clear (0), then set the microcode variable
16131 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
16132 * to ignore DMA parity errors.
16134 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
16136 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16137 word |= CONTROL_FLAG_IGNORE_PERR;
16138 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16142 * If the BIOS control flag AIPP (Asynchronous Information
16143 * Phase Protection) disable bit is not set, then set the firmware
16144 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
16145 * AIPP checking and encoding.
16147 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
16149 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16150 word |= CONTROL_FLAG_ENABLE_AIPP;
16151 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16155 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
16156 * and START_CTL_TH [3:2].
16158 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
16159 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
16162 * Microcode operating variables for WDTR, SDTR, and command tag
16163 * queuing will be set in AdvInquiryHandling() based on what a
16164 * device reports it is capable of in Inquiry byte 7.
16166 * If SCSI Bus Resets have been disabled, then directly set
16167 * SDTR and WDTR from the EEPROM configuration. This will allow
16168 * the BIOS and warm boot to work without a SCSI bus hang on
16169 * the Inquiry caused by host and target mismatched DTR values.
16170 * Without the SCSI Bus Reset, before an Inquiry a device can't
16171 * be assumed to be in Asynchronous, Narrow mode.
16173 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
16175 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
16176 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
16180 * Set microcode operating variables for DISC and SDTR_SPEED1,
16181 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
16182 * configuration values.
16184 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
16185 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
16186 * without determining here whether the device supports SDTR.
16188 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
16189 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
16190 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
16191 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
16192 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
16195 * Set SCSI_CFG0 Microcode Default Value.
16197 * The microcode will set the SCSI_CFG0 register using this value
16198 * after it is started below.
16200 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
16201 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
16202 asc_dvc->chip_scsi_id);
16205 * Calculate SCSI_CFG1 Microcode Default Value.
16207 * The microcode will set the SCSI_CFG1 register using this value
16208 * after it is started below.
16210 * Each ASC-38C1600 function has only two cable detect bits.
16211 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
16213 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16216 * If the cable is reversed all of the SCSI_CTRL register signals
16217 * will be set. Check for and return an error if this condition is
16220 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
16222 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
16227 * Each ASC-38C1600 function has two connectors. Only an HVD device
16228 * can not be connected to either connector. An LVD device or SE device
16229 * may be connected to either connecor. If an SE device is connected,
16230 * then at most Ultra speed (20 Mhz) can be used on both connectors.
16232 * If an HVD device is attached, return an error.
16234 if (scsi_cfg1 & HVD)
16236 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
16241 * Each function in the ASC-38C1600 uses only the SE cable detect and
16242 * termination because there are two connectors for each function. Each
16243 * function may use either LVD or SE mode. Corresponding the SE automatic
16244 * termination control EEPROM bits are used for each function. Each
16245 * function has its own EEPROM. If SE automatic control is enabled for
16246 * the function, then set the termination value based on a table listed
16249 * If manual termination is specified in the EEPROM for the function,
16250 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
16251 * ready to be 'ored' into SCSI_CFG1.
16253 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
16255 /* SE automatic termination control is enabled. */
16256 switch(scsi_cfg1 & C_DET_SE)
16258 /* TERM_SE_HI: on, TERM_SE_LO: on */
16259 case 0x1: case 0x2: case 0x3:
16260 asc_dvc->cfg->termination |= TERM_SE;
16264 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
16266 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
16270 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
16271 asc_dvc->cfg->termination |= TERM_SE_HI;
16278 * Clear any set TERM_SE bits.
16280 scsi_cfg1 &= ~TERM_SE;
16283 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
16285 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
16288 * Clear Big Endian and Terminator Polarity bits and set possibly
16289 * modified termination control bits in the Microcode SCSI_CFG1
16292 * Big Endian bit is not used even on big endian machines.
16294 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
16297 * Set SCSI_CFG1 Microcode Default Value
16299 * Set possibly modified termination control bits in the Microcode
16300 * SCSI_CFG1 Register Value.
16302 * The microcode will set the SCSI_CFG1 register using this value
16303 * after it is started below.
16305 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
16308 * Set MEM_CFG Microcode Default Value
16310 * The microcode will set the MEM_CFG register using this value
16311 * after it is started below.
16313 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
16316 * ASC-38C1600 has 32KB internal memory.
16318 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
16319 * out a special 16K Adv Library and Microcode version. After the issue
16320 * resolved, we should turn back to the 32K support. Both a_condor.h and
16321 * mcode.sas files also need to be updated.
16323 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
16324 * BIOS_EN | RAM_SZ_32KB);
16326 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
16329 * Set SEL_MASK Microcode Default Value
16331 * The microcode will set the SEL_MASK register using this value
16332 * after it is started below.
16334 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
16335 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
16338 * Build the carrier freelist.
16340 * Driver must have already allocated memory and set 'carrier_buf'.
16343 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
16345 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
16346 asc_dvc->carr_freelist = NULL;
16347 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
16349 buf_size = ADV_CARRIER_BUFSIZE;
16352 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
16357 * Get physical address for the carrier 'carrp'.
16359 contig_len = sizeof(ADV_CARR_T);
16360 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
16361 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
16363 buf_size -= sizeof(ADV_CARR_T);
16366 * If the current carrier is not physically contiguous, then
16367 * maybe there was a page crossing. Try the next carrier aligned
16370 if (contig_len < sizeof(ADV_CARR_T))
16376 carrp->carr_pa = carr_paddr;
16377 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16380 * Insert the carrier at the beginning of the freelist.
16382 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16383 asc_dvc->carr_freelist = carrp;
16387 while (buf_size > 0);
16390 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16392 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
16394 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16397 asc_dvc->carr_freelist = (ADV_CARR_T *)
16398 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16401 * The first command issued will be placed in the stopper carrier.
16403 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16406 * Set RISC ICQ physical address start value. Initialize the
16407 * COMMA register to the same value otherwise the RISC will
16408 * prematurely detect a command is available.
16410 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16411 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16412 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16415 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16417 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
16419 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16422 asc_dvc->carr_freelist = (ADV_CARR_T *)
16423 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16426 * The first command completed by the RISC will be placed in
16429 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16430 * completed the RISC will set the ASC_RQ_STOPPER bit.
16432 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16435 * Set RISC IRQ physical address start value.
16437 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16438 asc_dvc->carr_pending_cnt = 0;
16440 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16441 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
16442 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16443 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16445 /* finally, finally, gentlemen, start your engine */
16446 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16449 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16450 * Resets should be performed. The RISC has to be running
16451 * to issue a SCSI Bus Reset.
16453 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
16456 * If the BIOS Signature is present in memory, restore the
16457 * per TID microcode operating variables.
16459 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
16462 * Restore per TID negotiated values.
16464 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16465 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16466 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16467 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
16468 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16470 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
16475 if (AdvResetSB(asc_dvc) != ADV_TRUE)
16477 warn_code = ASC_WARN_BUSRESET_ERROR;
16486 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16487 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16488 * all of this is done.
16490 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16492 * For a non-fatal error return a warning code. If there are no warnings
16493 * then 0 is returned.
16495 * Note: Chip is stopped on entry.
16498 AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16500 AdvPortAddr iop_base;
16502 ADVEEP_3550_CONFIG eep_config;
16505 iop_base = asc_dvc->iop_base;
16510 * Read the board's EEPROM configuration.
16512 * Set default values if a bad checksum is found.
16514 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16516 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16519 * Set EEPROM default values.
16521 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
16523 *((uchar *) &eep_config + i) =
16524 *((uchar *) &Default_3550_EEPROM_Config + i);
16528 * Assume the 6 byte board serial number that was read
16529 * from EEPROM is correct even if the EEPROM checksum
16532 eep_config.serial_number_word3 =
16533 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16535 eep_config.serial_number_word2 =
16536 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16538 eep_config.serial_number_word1 =
16539 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16541 AdvSet3550EEPConfig(iop_base, &eep_config);
16544 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16545 * EEPROM configuration that was read.
16547 * This is the mapping of EEPROM fields to Adv Library fields.
16549 asc_dvc->wdtr_able = eep_config.wdtr_able;
16550 asc_dvc->sdtr_able = eep_config.sdtr_able;
16551 asc_dvc->ultra_able = eep_config.ultra_able;
16552 asc_dvc->tagqng_able = eep_config.tagqng_able;
16553 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16554 asc_dvc->max_host_qng = eep_config.max_host_qng;
16555 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16556 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16557 asc_dvc->start_motor = eep_config.start_motor;
16558 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16559 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16560 asc_dvc->no_scam = eep_config.scam_tolerant;
16561 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16562 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16563 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16566 * Set the host maximum queuing (max. 253, min. 16) and the per device
16567 * maximum queuing (max. 63, min. 4).
16569 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16571 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16572 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16574 /* If the value is zero, assume it is uninitialized. */
16575 if (eep_config.max_host_qng == 0)
16577 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16580 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16584 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16586 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16587 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16589 /* If the value is zero, assume it is uninitialized. */
16590 if (eep_config.max_dvc_qng == 0)
16592 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16595 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16600 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16601 * set 'max_dvc_qng' to 'max_host_qng'.
16603 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16605 eep_config.max_dvc_qng = eep_config.max_host_qng;
16609 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16610 * values based on possibly adjusted EEPROM values.
16612 asc_dvc->max_host_qng = eep_config.max_host_qng;
16613 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16617 * If the EEPROM 'termination' field is set to automatic (0), then set
16618 * the ADV_DVC_CFG 'termination' field to automatic also.
16620 * If the termination is specified with a non-zero 'termination'
16621 * value check that a legal value is set and set the ADV_DVC_CFG
16622 * 'termination' field appropriately.
16624 if (eep_config.termination == 0)
16626 asc_dvc->cfg->termination = 0; /* auto termination */
16629 /* Enable manual control with low off / high off. */
16630 if (eep_config.termination == 1)
16632 asc_dvc->cfg->termination = TERM_CTL_SEL;
16634 /* Enable manual control with low off / high on. */
16635 } else if (eep_config.termination == 2)
16637 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16639 /* Enable manual control with low on / high on. */
16640 } else if (eep_config.termination == 3)
16642 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16646 * The EEPROM 'termination' field contains a bad value. Use
16647 * automatic termination instead.
16649 asc_dvc->cfg->termination = 0;
16650 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16658 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16659 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16660 * all of this is done.
16662 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16664 * For a non-fatal error return a warning code. If there are no warnings
16665 * then 0 is returned.
16667 * Note: Chip is stopped on entry.
16670 AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16672 AdvPortAddr iop_base;
16674 ADVEEP_38C0800_CONFIG eep_config;
16676 uchar tid, termination;
16677 ushort sdtr_speed = 0;
16679 iop_base = asc_dvc->iop_base;
16684 * Read the board's EEPROM configuration.
16686 * Set default values if a bad checksum is found.
16688 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16690 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16693 * Set EEPROM default values.
16695 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
16697 *((uchar *) &eep_config + i) =
16698 *((uchar *) &Default_38C0800_EEPROM_Config + i);
16702 * Assume the 6 byte board serial number that was read
16703 * from EEPROM is correct even if the EEPROM checksum
16706 eep_config.serial_number_word3 =
16707 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16709 eep_config.serial_number_word2 =
16710 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16712 eep_config.serial_number_word1 =
16713 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16715 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16718 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16719 * EEPROM configuration that was read.
16721 * This is the mapping of EEPROM fields to Adv Library fields.
16723 asc_dvc->wdtr_able = eep_config.wdtr_able;
16724 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16725 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16726 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16727 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16728 asc_dvc->tagqng_able = eep_config.tagqng_able;
16729 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16730 asc_dvc->max_host_qng = eep_config.max_host_qng;
16731 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16732 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16733 asc_dvc->start_motor = eep_config.start_motor;
16734 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16735 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16736 asc_dvc->no_scam = eep_config.scam_tolerant;
16737 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16738 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16739 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16742 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16743 * are set, then set an 'sdtr_able' bit for it.
16745 asc_dvc->sdtr_able = 0;
16746 for (tid = 0; tid <= ADV_MAX_TID; tid++)
16750 sdtr_speed = asc_dvc->sdtr_speed1;
16751 } else if (tid == 4)
16753 sdtr_speed = asc_dvc->sdtr_speed2;
16754 } else if (tid == 8)
16756 sdtr_speed = asc_dvc->sdtr_speed3;
16757 } else if (tid == 12)
16759 sdtr_speed = asc_dvc->sdtr_speed4;
16761 if (sdtr_speed & ADV_MAX_TID)
16763 asc_dvc->sdtr_able |= (1 << tid);
16769 * Set the host maximum queuing (max. 253, min. 16) and the per device
16770 * maximum queuing (max. 63, min. 4).
16772 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16774 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16775 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16777 /* If the value is zero, assume it is uninitialized. */
16778 if (eep_config.max_host_qng == 0)
16780 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16783 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16787 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16789 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16790 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16792 /* If the value is zero, assume it is uninitialized. */
16793 if (eep_config.max_dvc_qng == 0)
16795 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16798 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16803 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16804 * set 'max_dvc_qng' to 'max_host_qng'.
16806 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16808 eep_config.max_dvc_qng = eep_config.max_host_qng;
16812 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16813 * values based on possibly adjusted EEPROM values.
16815 asc_dvc->max_host_qng = eep_config.max_host_qng;
16816 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16819 * If the EEPROM 'termination' field is set to automatic (0), then set
16820 * the ADV_DVC_CFG 'termination' field to automatic also.
16822 * If the termination is specified with a non-zero 'termination'
16823 * value check that a legal value is set and set the ADV_DVC_CFG
16824 * 'termination' field appropriately.
16826 if (eep_config.termination_se == 0)
16828 termination = 0; /* auto termination for SE */
16831 /* Enable manual control with low off / high off. */
16832 if (eep_config.termination_se == 1)
16836 /* Enable manual control with low off / high on. */
16837 } else if (eep_config.termination_se == 2)
16839 termination = TERM_SE_HI;
16841 /* Enable manual control with low on / high on. */
16842 } else if (eep_config.termination_se == 3)
16844 termination = TERM_SE;
16848 * The EEPROM 'termination_se' field contains a bad value.
16849 * Use automatic termination instead.
16852 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16856 if (eep_config.termination_lvd == 0)
16858 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16861 /* Enable manual control with low off / high off. */
16862 if (eep_config.termination_lvd == 1)
16864 asc_dvc->cfg->termination = termination;
16866 /* Enable manual control with low off / high on. */
16867 } else if (eep_config.termination_lvd == 2)
16869 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16871 /* Enable manual control with low on / high on. */
16872 } else if (eep_config.termination_lvd == 3)
16874 asc_dvc->cfg->termination =
16875 termination | TERM_LVD;
16879 * The EEPROM 'termination_lvd' field contains a bad value.
16880 * Use automatic termination instead.
16882 asc_dvc->cfg->termination = termination;
16883 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16891 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16892 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16893 * all of this is done.
16895 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16897 * For a non-fatal error return a warning code. If there are no warnings
16898 * then 0 is returned.
16900 * Note: Chip is stopped on entry.
16903 AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16905 AdvPortAddr iop_base;
16907 ADVEEP_38C1600_CONFIG eep_config;
16909 uchar tid, termination;
16910 ushort sdtr_speed = 0;
16912 iop_base = asc_dvc->iop_base;
16917 * Read the board's EEPROM configuration.
16919 * Set default values if a bad checksum is found.
16921 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16923 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16926 * Set EEPROM default values.
16928 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
16930 if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
16933 * Set Function 1 EEPROM Word 0 MSB
16935 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16938 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16939 * old Mac system booting problem. The Expansion ROM must
16940 * be disabled in Function 1 for these systems.
16943 *((uchar *) &eep_config + i) =
16944 ((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
16945 (~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
16949 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16950 * the Function 1 interrupt line is wired to INTA.
16952 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16953 * 1 - Function 1 interrupt line wired to INT A.
16954 * 0 - Function 1 interrupt line wired to INT B.
16956 * Note: Adapter boards always have Function 0 wired to INTA.
16957 * Put all 5 GPIO bits in input mode and then read
16958 * their input values.
16960 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
16961 if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
16963 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16964 *((uchar *) &eep_config + i) |=
16965 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16970 *((uchar *) &eep_config + i) =
16971 *((uchar *) &Default_38C1600_EEPROM_Config + i);
16976 * Assume the 6 byte board serial number that was read
16977 * from EEPROM is correct even if the EEPROM checksum
16980 eep_config.serial_number_word3 =
16981 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16983 eep_config.serial_number_word2 =
16984 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16986 eep_config.serial_number_word1 =
16987 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16989 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16993 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16994 * EEPROM configuration that was read.
16996 * This is the mapping of EEPROM fields to Adv Library fields.
16998 asc_dvc->wdtr_able = eep_config.wdtr_able;
16999 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
17000 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
17001 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
17002 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
17003 asc_dvc->ppr_able = 0;
17004 asc_dvc->tagqng_able = eep_config.tagqng_able;
17005 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
17006 asc_dvc->max_host_qng = eep_config.max_host_qng;
17007 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17008 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
17009 asc_dvc->start_motor = eep_config.start_motor;
17010 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
17011 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
17012 asc_dvc->no_scam = eep_config.scam_tolerant;
17015 * For every Target ID if any of its 'sdtr_speed[1234]' bits
17016 * are set, then set an 'sdtr_able' bit for it.
17018 asc_dvc->sdtr_able = 0;
17019 for (tid = 0; tid <= ASC_MAX_TID; tid++)
17023 sdtr_speed = asc_dvc->sdtr_speed1;
17024 } else if (tid == 4)
17026 sdtr_speed = asc_dvc->sdtr_speed2;
17027 } else if (tid == 8)
17029 sdtr_speed = asc_dvc->sdtr_speed3;
17030 } else if (tid == 12)
17032 sdtr_speed = asc_dvc->sdtr_speed4;
17034 if (sdtr_speed & ASC_MAX_TID)
17036 asc_dvc->sdtr_able |= (1 << tid);
17042 * Set the host maximum queuing (max. 253, min. 16) and the per device
17043 * maximum queuing (max. 63, min. 4).
17045 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
17047 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17048 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
17050 /* If the value is zero, assume it is uninitialized. */
17051 if (eep_config.max_host_qng == 0)
17053 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17056 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
17060 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
17062 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17063 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
17065 /* If the value is zero, assume it is uninitialized. */
17066 if (eep_config.max_dvc_qng == 0)
17068 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17071 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
17076 * If 'max_dvc_qng' is greater than 'max_host_qng', then
17077 * set 'max_dvc_qng' to 'max_host_qng'.
17079 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
17081 eep_config.max_dvc_qng = eep_config.max_host_qng;
17085 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
17086 * values based on possibly adjusted EEPROM values.
17088 asc_dvc->max_host_qng = eep_config.max_host_qng;
17089 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17092 * If the EEPROM 'termination' field is set to automatic (0), then set
17093 * the ASC_DVC_CFG 'termination' field to automatic also.
17095 * If the termination is specified with a non-zero 'termination'
17096 * value check that a legal value is set and set the ASC_DVC_CFG
17097 * 'termination' field appropriately.
17099 if (eep_config.termination_se == 0)
17101 termination = 0; /* auto termination for SE */
17104 /* Enable manual control with low off / high off. */
17105 if (eep_config.termination_se == 1)
17109 /* Enable manual control with low off / high on. */
17110 } else if (eep_config.termination_se == 2)
17112 termination = TERM_SE_HI;
17114 /* Enable manual control with low on / high on. */
17115 } else if (eep_config.termination_se == 3)
17117 termination = TERM_SE;
17121 * The EEPROM 'termination_se' field contains a bad value.
17122 * Use automatic termination instead.
17125 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17129 if (eep_config.termination_lvd == 0)
17131 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
17134 /* Enable manual control with low off / high off. */
17135 if (eep_config.termination_lvd == 1)
17137 asc_dvc->cfg->termination = termination;
17139 /* Enable manual control with low off / high on. */
17140 } else if (eep_config.termination_lvd == 2)
17142 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
17144 /* Enable manual control with low on / high on. */
17145 } else if (eep_config.termination_lvd == 3)
17147 asc_dvc->cfg->termination =
17148 termination | TERM_LVD;
17152 * The EEPROM 'termination_lvd' field contains a bad value.
17153 * Use automatic termination instead.
17155 asc_dvc->cfg->termination = termination;
17156 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17164 * Read EEPROM configuration into the specified buffer.
17166 * Return a checksum based on the EEPROM configuration read.
17168 STATIC ushort __init
17169 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17171 ushort wval, chksum;
17174 ushort *charfields;
17176 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17177 wbuf = (ushort *) cfg_buf;
17180 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17181 eep_addr < ADV_EEP_DVC_CFG_END;
17182 eep_addr++, wbuf++)
17184 wval = AdvReadEEPWord(iop_base, eep_addr);
17185 chksum += wval; /* Checksum is calculated from word values. */
17186 if (*charfields++) {
17187 *wbuf = le16_to_cpu(wval);
17192 /* Read checksum word. */
17193 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17194 wbuf++; charfields++;
17196 /* Read rest of EEPROM not covered by the checksum. */
17197 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17198 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17199 eep_addr++, wbuf++)
17201 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17202 if (*charfields++) {
17203 *wbuf = le16_to_cpu(*wbuf);
17210 * Read EEPROM configuration into the specified buffer.
17212 * Return a checksum based on the EEPROM configuration read.
17214 STATIC ushort __init
17215 AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
17216 ADVEEP_38C0800_CONFIG *cfg_buf)
17218 ushort wval, chksum;
17221 ushort *charfields;
17223 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17224 wbuf = (ushort *) cfg_buf;
17227 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17228 eep_addr < ADV_EEP_DVC_CFG_END;
17229 eep_addr++, wbuf++)
17231 wval = AdvReadEEPWord(iop_base, eep_addr);
17232 chksum += wval; /* Checksum is calculated from word values. */
17233 if (*charfields++) {
17234 *wbuf = le16_to_cpu(wval);
17239 /* Read checksum word. */
17240 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17241 wbuf++; charfields++;
17243 /* Read rest of EEPROM not covered by the checksum. */
17244 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17245 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17246 eep_addr++, wbuf++)
17248 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17249 if (*charfields++) {
17250 *wbuf = le16_to_cpu(*wbuf);
17257 * Read EEPROM configuration into the specified buffer.
17259 * Return a checksum based on the EEPROM configuration read.
17261 STATIC ushort __init
17262 AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
17263 ADVEEP_38C1600_CONFIG *cfg_buf)
17265 ushort wval, chksum;
17268 ushort *charfields;
17270 charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
17271 wbuf = (ushort *) cfg_buf;
17274 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17275 eep_addr < ADV_EEP_DVC_CFG_END;
17276 eep_addr++, wbuf++)
17278 wval = AdvReadEEPWord(iop_base, eep_addr);
17279 chksum += wval; /* Checksum is calculated from word values. */
17280 if (*charfields++) {
17281 *wbuf = le16_to_cpu(wval);
17286 /* Read checksum word. */
17287 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17288 wbuf++; charfields++;
17290 /* Read rest of EEPROM not covered by the checksum. */
17291 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17292 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17293 eep_addr++, wbuf++)
17295 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17296 if (*charfields++) {
17297 *wbuf = le16_to_cpu(*wbuf);
17304 * Read the EEPROM from specified location
17306 STATIC ushort __init
17307 AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
17309 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17310 ASC_EEP_CMD_READ | eep_word_addr);
17311 AdvWaitEEPCmd(iop_base);
17312 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
17316 * Wait for EEPROM command to complete
17319 AdvWaitEEPCmd(AdvPortAddr iop_base)
17323 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
17325 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
17329 DvcSleepMilliSecond(1);
17331 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
17339 * Write the EEPROM from 'cfg_buf'.
17342 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17345 ushort addr, chksum;
17346 ushort *charfields;
17348 wbuf = (ushort *) cfg_buf;
17349 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17352 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17353 AdvWaitEEPCmd(iop_base);
17356 * Write EEPROM from word 0 to word 20.
17358 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17359 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17363 if (*charfields++) {
17364 word = cpu_to_le16(*wbuf);
17368 chksum += *wbuf; /* Checksum is calculated from word values. */
17369 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17370 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17371 AdvWaitEEPCmd(iop_base);
17372 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17376 * Write EEPROM checksum at word 21.
17378 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17379 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17380 AdvWaitEEPCmd(iop_base);
17381 wbuf++; charfields++;
17384 * Write EEPROM OEM name at words 22 to 29.
17386 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17387 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17391 if (*charfields++) {
17392 word = cpu_to_le16(*wbuf);
17396 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17397 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17398 AdvWaitEEPCmd(iop_base);
17400 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17401 AdvWaitEEPCmd(iop_base);
17406 * Write the EEPROM from 'cfg_buf'.
17409 AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
17410 ADVEEP_38C0800_CONFIG *cfg_buf)
17413 ushort *charfields;
17414 ushort addr, chksum;
17416 wbuf = (ushort *) cfg_buf;
17417 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17420 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17421 AdvWaitEEPCmd(iop_base);
17424 * Write EEPROM from word 0 to word 20.
17426 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17427 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17431 if (*charfields++) {
17432 word = cpu_to_le16(*wbuf);
17436 chksum += *wbuf; /* Checksum is calculated from word values. */
17437 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17438 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17439 AdvWaitEEPCmd(iop_base);
17440 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17444 * Write EEPROM checksum at word 21.
17446 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17447 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17448 AdvWaitEEPCmd(iop_base);
17449 wbuf++; charfields++;
17452 * Write EEPROM OEM name at words 22 to 29.
17454 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17455 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17459 if (*charfields++) {
17460 word = cpu_to_le16(*wbuf);
17464 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17465 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17466 AdvWaitEEPCmd(iop_base);
17468 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17469 AdvWaitEEPCmd(iop_base);
17474 * Write the EEPROM from 'cfg_buf'.
17477 AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
17478 ADVEEP_38C1600_CONFIG *cfg_buf)
17481 ushort *charfields;
17482 ushort addr, chksum;
17484 wbuf = (ushort *) cfg_buf;
17485 charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
17488 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17489 AdvWaitEEPCmd(iop_base);
17492 * Write EEPROM from word 0 to word 20.
17494 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17495 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17499 if (*charfields++) {
17500 word = cpu_to_le16(*wbuf);
17504 chksum += *wbuf; /* Checksum is calculated from word values. */
17505 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17506 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17507 AdvWaitEEPCmd(iop_base);
17508 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17512 * Write EEPROM checksum at word 21.
17514 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17515 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17516 AdvWaitEEPCmd(iop_base);
17517 wbuf++; charfields++;
17520 * Write EEPROM OEM name at words 22 to 29.
17522 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17523 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17527 if (*charfields++) {
17528 word = cpu_to_le16(*wbuf);
17532 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17533 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17534 AdvWaitEEPCmd(iop_base);
17536 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17537 AdvWaitEEPCmd(iop_base);
17543 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17545 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17546 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17547 * RISC to notify it a new command is ready to be executed.
17549 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17550 * set to SCSI_MAX_RETRY.
17552 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17553 * for DMA addresses or math operations are byte swapped to little-endian
17557 * ADV_SUCCESS(1) - The request was successfully queued.
17558 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17559 * request completes.
17560 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17564 AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
17565 ADV_SCSI_REQ_Q *scsiq)
17567 ulong last_int_level;
17568 AdvPortAddr iop_base;
17570 ADV_PADDR req_paddr;
17571 ADV_CARR_T *new_carrp;
17573 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17576 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17578 if (scsiq->target_id > ADV_MAX_TID)
17580 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17581 scsiq->done_status = QD_WITH_ERROR;
17585 iop_base = asc_dvc->iop_base;
17587 last_int_level = DvcEnterCritical();
17590 * Allocate a carrier ensuring at least one carrier always
17591 * remains on the freelist and initialize fields.
17593 if ((new_carrp = asc_dvc->carr_freelist) == NULL)
17595 DvcLeaveCritical(last_int_level);
17598 asc_dvc->carr_freelist = (ADV_CARR_T *)
17599 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17600 asc_dvc->carr_pending_cnt++;
17603 * Set the carrier to be a stopper by setting 'next_vpa'
17604 * to the stopper value. The current stopper will be changed
17605 * below to point to the new stopper.
17607 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17610 * Clear the ADV_SCSI_REQ_Q done flag.
17612 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17614 req_size = sizeof(ADV_SCSI_REQ_Q);
17615 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
17616 (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
17618 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17619 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17621 /* Wait for assertion before making little-endian */
17622 req_paddr = cpu_to_le32(req_paddr);
17624 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17625 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17626 scsiq->scsiq_rptr = req_paddr;
17628 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17630 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17631 * order during initialization.
17633 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17636 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17637 * the microcode. The newly allocated stopper will become the new
17640 asc_dvc->icq_sp->areq_vpa = req_paddr;
17643 * Set the 'next_vpa' pointer for the old stopper to be the
17644 * physical address of the new stopper. The RISC can only
17645 * follow physical addresses.
17647 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17650 * Set the host adapter stopper pointer to point to the new carrier.
17652 asc_dvc->icq_sp = new_carrp;
17654 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17655 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17658 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17660 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17661 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17664 * Clear the tickle value. In the ASC-3550 the RISC flag
17665 * command 'clr_tickle_a' does not work unless the host
17666 * value is cleared.
17668 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17670 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17673 * Notify the RISC a carrier is ready by writing the physical
17674 * address of the new carrier stopper to the COMMA register.
17676 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17677 le32_to_cpu(new_carrp->carr_pa));
17680 DvcLeaveCritical(last_int_level);
17682 return ADV_SUCCESS;
17686 * Reset SCSI Bus and purge all outstanding requests.
17689 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17690 * ADV_FALSE(0) - Microcode command failed.
17691 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17692 * may be hung which requires driver recovery.
17695 AdvResetSB(ADV_DVC_VAR *asc_dvc)
17700 * Send the SCSI Bus Reset idle start idle command which asserts
17701 * the SCSI Bus Reset signal.
17703 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
17704 if (status != ADV_TRUE)
17710 * Delay for the specified SCSI Bus Reset hold time.
17712 * The hold time delay is done on the host because the RISC has no
17713 * microsecond accurate timer.
17715 DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
17718 * Send the SCSI Bus Reset end idle command which de-asserts
17719 * the SCSI Bus Reset signal and purges any pending requests.
17721 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
17722 if (status != ADV_TRUE)
17727 DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
17733 * Reset chip and SCSI Bus.
17736 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17737 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17740 AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17743 ushort wdtr_able, sdtr_able, tagqng_able;
17744 ushort ppr_able = 0;
17745 uchar tid, max_cmd[ADV_MAX_TID + 1];
17746 AdvPortAddr iop_base;
17749 iop_base = asc_dvc->iop_base;
17752 * Save current per TID negotiated values.
17754 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17755 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17756 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17758 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17760 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17761 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17763 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17768 * Force the AdvInitAsc3550/38C0800Driver() function to
17769 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17770 * The initialization functions assumes a SCSI Bus Reset is not
17771 * needed if the BIOS signature word is present.
17773 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17774 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17777 * Stop chip and reset it.
17779 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17780 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17781 DvcSleepMilliSecond(100);
17782 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
17785 * Reset Adv Library error code, if any, and try
17786 * re-initializing the chip.
17788 asc_dvc->err_code = 0;
17789 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17791 status = AdvInitAsc38C1600Driver(asc_dvc);
17793 else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17795 status = AdvInitAsc38C0800Driver(asc_dvc);
17798 status = AdvInitAsc3550Driver(asc_dvc);
17801 /* Translate initialization return value to status value. */
17807 status = ADV_FALSE;
17811 * Restore the BIOS signature word.
17813 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17816 * Restore per TID negotiated values.
17818 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17819 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17820 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17822 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17824 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17825 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17827 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17835 * Adv Library Interrupt Service Routine
17837 * This function is called by a driver's interrupt service routine.
17838 * The function disables and re-enables interrupts.
17840 * When a microcode idle command is completed, the ADV_DVC_VAR
17841 * 'idle_cmd_done' field is set to ADV_TRUE.
17843 * Note: AdvISR() can be called when interrupts are disabled or even
17844 * when there is no hardware interrupt condition present. It will
17845 * always check for completed idle commands and microcode requests.
17846 * This is an important feature that shouldn't be changed because it
17847 * allows commands to be completed from polling mode loops.
17850 * ADV_TRUE(1) - interrupt was pending
17851 * ADV_FALSE(0) - no interrupt was pending
17854 AdvISR(ADV_DVC_VAR *asc_dvc)
17856 AdvPortAddr iop_base;
17859 ADV_CARR_T *free_carrp;
17860 ADV_VADDR irq_next_vpa;
17862 ADV_SCSI_REQ_Q *scsiq;
17864 flags = DvcEnterCritical();
17866 iop_base = asc_dvc->iop_base;
17868 /* Reading the register clears the interrupt. */
17869 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17871 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17872 ADV_INTR_STATUS_INTRC)) == 0)
17874 DvcLeaveCritical(flags);
17879 * Notify the driver of an asynchronous microcode condition by
17880 * calling the ADV_DVC_VAR.async_callback function. The function
17881 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17883 if (int_stat & ADV_INTR_STATUS_INTRB)
17887 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17889 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17890 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17892 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17893 asc_dvc->carr_pending_cnt != 0)
17895 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17896 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17898 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17903 if (asc_dvc->async_callback != 0)
17905 (*asc_dvc->async_callback)(asc_dvc, intrb_code);
17910 * Check if the IRQ stopper carrier contains a completed request.
17912 while (((irq_next_vpa =
17913 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
17916 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17917 * The RISC will have set 'areq_vpa' to a virtual address.
17919 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17920 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17921 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17922 * in AdvExeScsiQueue().
17924 scsiq = (ADV_SCSI_REQ_Q *)
17925 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17928 * Request finished with good status and the queue was not
17929 * DMAed to host memory by the firmware. Set all status fields
17930 * to indicate good status.
17932 if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
17934 scsiq->done_status = QD_NO_ERROR;
17935 scsiq->host_status = scsiq->scsi_status = 0;
17936 scsiq->data_cnt = 0L;
17940 * Advance the stopper pointer to the next carrier
17941 * ignoring the lower four bits. Free the previous
17944 free_carrp = asc_dvc->irq_sp;
17945 asc_dvc->irq_sp = (ADV_CARR_T *)
17946 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17948 free_carrp->next_vpa =
17949 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17950 asc_dvc->carr_freelist = free_carrp;
17951 asc_dvc->carr_pending_cnt--;
17953 ASC_ASSERT(scsiq != NULL);
17954 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17957 * Clear request microcode control flag.
17962 * If the command that completed was a SCSI INQUIRY and
17963 * LUN 0 was sent the command, then process the INQUIRY
17964 * command information for the device.
17966 * Note: If data returned were either VPD or CmdDt data,
17967 * don't process the INQUIRY command information for
17968 * the device, otherwise may erroneously set *_able bits.
17970 if (scsiq->done_status == QD_NO_ERROR &&
17971 scsiq->cdb[0] == INQUIRY &&
17972 scsiq->target_lun == 0 &&
17973 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17974 == ADV_INQ_RTN_STD_INQUIRY_DATA)
17976 AdvInquiryHandling(asc_dvc, scsiq);
17980 * Notify the driver of the completed request by passing
17981 * the ADV_SCSI_REQ_Q pointer to its callback function.
17983 scsiq->a_flag |= ADV_SCSIQ_DONE;
17984 (*asc_dvc->isr_callback)(asc_dvc, scsiq);
17986 * Note: After the driver callback function is called, 'scsiq'
17987 * can no longer be referenced.
17989 * Fall through and continue processing other completed
17994 * Disable interrupts again in case the driver inadvertently
17995 * enabled interrupts in its callback function.
17997 * The DvcEnterCritical() return value is ignored, because
17998 * the 'flags' saved when AdvISR() was first entered will be
17999 * used to restore the interrupt flag on exit.
18001 (void) DvcEnterCritical();
18003 DvcLeaveCritical(flags);
18008 * Send an idle command to the chip and wait for completion.
18010 * Command completion is polled for once per microsecond.
18012 * The function can be called from anywhere including an interrupt handler.
18013 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
18014 * functions to prevent reentrancy.
18017 * ADV_TRUE - command completed successfully
18018 * ADV_FALSE - command failed
18019 * ADV_ERROR - command timed out
18022 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
18024 ADV_DCNT idle_cmd_parameter)
18026 ulong last_int_level;
18029 AdvPortAddr iop_base;
18031 last_int_level = DvcEnterCritical();
18033 iop_base = asc_dvc->iop_base;
18036 * Clear the idle command status which is set by the microcode
18037 * to a non-zero value to indicate when the command is completed.
18038 * The non-zero result is one of the IDLE_CMD_STATUS_* values
18039 * defined in a_advlib.h.
18041 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
18044 * Write the idle command value after the idle command parameter
18045 * has been written to avoid a race condition. If the order is not
18046 * followed, the microcode may process the idle command before the
18047 * parameters have been written to LRAM.
18049 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
18050 cpu_to_le32(idle_cmd_parameter));
18051 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
18054 * Tickle the RISC to tell it to process the idle command.
18056 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
18057 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
18060 * Clear the tickle value. In the ASC-3550 the RISC flag
18061 * command 'clr_tickle_b' does not work unless the host
18062 * value is cleared.
18064 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
18067 /* Wait for up to 100 millisecond for the idle command to timeout. */
18068 for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
18070 /* Poll once each microsecond for command completion. */
18071 for (j = 0; j < SCSI_US_PER_MSEC; j++)
18073 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
18076 DvcLeaveCritical(last_int_level);
18079 DvcDelayMicroSecond(asc_dvc, (ushort) 1);
18083 ASC_ASSERT(0); /* The idle command should never timeout. */
18084 DvcLeaveCritical(last_int_level);
18089 * Inquiry Information Byte 7 Handling
18091 * Handle SCSI Inquiry Command information for a device by setting
18092 * microcode operating variables that affect WDTR, SDTR, and Tag
18096 AdvInquiryHandling(
18097 ADV_DVC_VAR *asc_dvc,
18098 ADV_SCSI_REQ_Q *scsiq)
18100 AdvPortAddr iop_base;
18102 ADV_SCSI_INQUIRY *inq;
18107 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
18110 * If less than 8 bytes of INQUIRY information were requested or less
18111 * than 8 bytes were transferred, then return. cdb[4] is the request
18112 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
18113 * microcode to the transfer residual count.
18116 if (scsiq->cdb[4] < 8 ||
18117 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
18122 iop_base = asc_dvc->iop_base;
18123 tid = scsiq->target_id;
18125 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
18128 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
18130 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
18136 * INQUIRY Byte 7 Handling
18138 * Use a device's INQUIRY byte 7 to determine whether it
18139 * supports WDTR, SDTR, and Tag Queuing. If the feature
18140 * is enabled in the EEPROM and the device supports the
18141 * feature, then enable it in the microcode.
18144 tidmask = ADV_TID_TO_TIDMASK(tid);
18149 * If the EEPROM enabled WDTR for the device and the device
18150 * supports wide bus (16 bit) transfers, then turn on the
18151 * device's 'wdtr_able' bit and write the new value to the
18154 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
18156 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18157 if ((cfg_word & tidmask) == 0)
18159 cfg_word |= tidmask;
18160 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18163 * Clear the microcode "SDTR negotiation" and "WDTR
18164 * negotiation" done indicators for the target to cause
18165 * it to negotiate with the new setting set above.
18166 * WDTR when accepted causes the target to enter
18167 * asynchronous mode, so SDTR must be negotiated.
18169 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18170 cfg_word &= ~tidmask;
18171 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18172 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18173 cfg_word &= ~tidmask;
18174 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18179 * Synchronous Transfers
18181 * If the EEPROM enabled SDTR for the device and the device
18182 * supports synchronous transfers, then turn on the device's
18183 * 'sdtr_able' bit. Write the new value to the microcode.
18185 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
18187 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18188 if ((cfg_word & tidmask) == 0)
18190 cfg_word |= tidmask;
18191 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18194 * Clear the microcode "SDTR negotiation" done indicator
18195 * for the target to cause it to negotiate with the new
18196 * setting set above.
18198 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18199 cfg_word &= ~tidmask;
18200 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18204 * If the Inquiry data included enough space for the SPI-3
18205 * Clocking field, then check if DT mode is supported.
18207 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
18208 (scsiq->cdb[4] >= 57 ||
18209 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
18212 * PPR (Parallel Protocol Request) Capable
18214 * If the device supports DT mode, then it must be PPR capable.
18215 * The PPR message will be used in place of the SDTR and WDTR
18216 * messages to negotiate synchronous speed and offset, transfer
18217 * width, and protocol options.
18219 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
18221 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18222 asc_dvc->ppr_able |= tidmask;
18223 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18228 * If the EEPROM enabled Tag Queuing for the device and the
18229 * device supports Tag Queueing, then turn on the device's
18230 * 'tagqng_enable' bit in the microcode and set the microcode
18231 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
18234 * Tag Queuing is disabled for the BIOS which runs in polled
18235 * mode and would see no benefit from Tag Queuing. Also by
18236 * disabling Tag Queuing in the BIOS devices with Tag Queuing
18237 * bugs will at least work with the BIOS.
18239 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
18241 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18242 cfg_word |= tidmask;
18243 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18245 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
18246 asc_dvc->max_dvc_qng);
18250 MODULE_LICENSE("Dual BSD/GPL");