1 #define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that redistributions of source
12 * code retain the above copyright notice and this comment without
15 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
16 * changed its name to ConnectCom Solutions, Inc.
22 Documentation for the AdvanSys Driver
24 A. Linux Kernels Supported by this Driver
25 B. Adapters Supported by this Driver
26 C. Linux source files modified by AdvanSys Driver
28 E. Driver Compile Time Options and Debugging
30 G. Tests to run before releasing new driver
32 I. Known Problems/Fix List
33 J. Credits (Chronological Order)
35 A. Linux Kernels Supported by this Driver
37 This driver has been tested in the following Linux kernels: v2.2.18
38 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
39 alpha, and PowerPC platforms.
41 B. Adapters Supported by this Driver
43 AdvanSys (Advanced System Products, Inc.) manufactures the following
44 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
45 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
46 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
47 transfer) SCSI Host Adapters for the PCI bus.
49 The CDB counts below indicate the number of SCSI CDB (Command
50 Descriptor Block) requests that can be stored in the RISC chip
51 cache and board LRAM. A CDB is a single SCSI command. The driver
52 detect routine will display the number of CDBs available for each
53 adapter detected. The number of CDBs used by the driver can be
54 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
57 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
59 Connectivity Products:
60 ABP510/5150 - Bus-Master ISA (240 CDB)
61 ABP5140 - Bus-Master ISA PnP (16 CDB)
62 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
63 ABP902/3902 - Bus-Master PCI (16 CDB)
64 ABP3905 - Bus-Master PCI (16 CDB)
65 ABP915 - Bus-Master PCI (16 CDB)
66 ABP920 - Bus-Master PCI (16 CDB)
67 ABP3922 - Bus-Master PCI (16 CDB)
68 ABP3925 - Bus-Master PCI (16 CDB)
69 ABP930 - Bus-Master PCI (16 CDB)
70 ABP930U - Bus-Master PCI Ultra (16 CDB)
71 ABP930UA - Bus-Master PCI Ultra (16 CDB)
72 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
73 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
75 Single Channel Products:
76 ABP542 - Bus-Master ISA with floppy (240 CDB)
77 ABP742 - Bus-Master EISA (240 CDB)
78 ABP842 - Bus-Master VL (240 CDB)
79 ABP940 - Bus-Master PCI (240 CDB)
80 ABP940U - Bus-Master PCI Ultra (240 CDB)
81 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
82 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
83 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
84 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
85 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
86 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
87 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
89 Multi-Channel Products:
90 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
91 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
92 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
93 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
94 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
95 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
96 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
97 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
98 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
100 C. Linux source files modified by AdvanSys Driver
102 This section for historical purposes documents the changes
103 originally made to the Linux kernel source to add the advansys
104 driver. As Linux has changed some of these files have also
107 1. linux/arch/i386/config.in:
109 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
111 2. linux/drivers/scsi/hosts.c:
113 #ifdef CONFIG_SCSI_ADVANSYS
114 #include "advansys.h"
117 and after "static struct scsi_host_template builtin_scsi_hosts[] =":
119 #ifdef CONFIG_SCSI_ADVANSYS
123 3. linux/drivers/scsi/Makefile:
125 ifdef CONFIG_SCSI_ADVANSYS
126 SCSI_SRCS := $(SCSI_SRCS) advansys.c
127 SCSI_OBJS := $(SCSI_OBJS) advansys.o
129 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
132 4. linux/init/main.c:
134 extern void advansys_setup(char *str, int *ints);
136 and add the following lines to the bootsetups[] array.
138 #ifdef CONFIG_SCSI_ADVANSYS
139 { "advansys=", advansys_setup },
144 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
146 2. This driver should be maintained in multiple files. But to make
147 it easier to include with Linux and to follow Linux conventions,
148 the whole driver is maintained in the source files advansys.h and
149 advansys.c. In this file logical sections of the driver begin with
150 a comment that contains '---'. The following are the logical sections
154 --- Linux Include File
157 --- Asc Library Constants and Macros
158 --- Adv Library Constants and Macros
159 --- Driver Constants and Macros
160 --- Driver Structures
162 --- Driver Function Prototypes
163 --- Linux 'struct scsi_host_template' and advansys_setup() Functions
164 --- Loadable Driver Support
165 --- Miscellaneous Driver Functions
166 --- Functions Required by the Asc Library
167 --- Functions Required by the Adv Library
168 --- Tracing and Debugging Functions
169 --- Asc Library Functions
170 --- Adv Library Functions
172 3. The string 'XXX' is used to flag code that needs to be re-written
173 or that contains a problem that needs to be addressed.
175 4. I have stripped comments from and reformatted the source for the
176 Asc Library and Adv Library to reduce the size of this file. This
177 source can be found under the following headings. The Asc Library
178 is used to support Narrow Boards. The Adv Library is used to
181 --- Asc Library Constants and Macros
182 --- Adv Library Constants and Macros
183 --- Asc Library Functions
184 --- Adv Library Functions
186 E. Driver Compile Time Options and Debugging
188 In this source file the following constants can be defined. They are
189 defined in the source below. Both of these options are enabled by
192 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
194 Enabling this option adds assertion logic statements to the
195 driver. If an assertion fails a message will be displayed to
196 the console, but the system will continue to operate. Any
197 assertions encountered should be reported to the person
198 responsible for the driver. Assertion statements may proactively
199 detect problems with the driver and facilitate fixing these
200 problems. Enabling assertions will add a small overhead to the
201 execution of the driver.
203 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
205 Enabling this option adds tracing functions to the driver and
206 the ability to set a driver tracing level at boot time. This
207 option will also export symbols not required outside the driver to
208 the kernel name space. This option is very useful for debugging
209 the driver, but it will add to the size of the driver execution
210 image and add overhead to the execution of the driver.
212 The amount of debugging output can be controlled with the global
213 variable 'asc_dbglvl'. The higher the number the more output. By
214 default the debug level is 0.
216 If the driver is loaded at boot time and the LILO Driver Option
217 is included in the system, the debug level can be changed by
218 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
219 first three hex digits of the pseudo I/O Port must be set to
220 'deb' and the fourth hex digit specifies the debug level: 0 - F.
221 The following command line will look for an adapter at 0x330
222 and set the debug level to 2.
224 linux advansys=0x330,0,0,0,0xdeb2
226 If the driver is built as a loadable module this variable can be
227 defined when the driver is loaded. The following insmod command
228 will set the debug level to one.
230 insmod advansys.o asc_dbglvl=1
232 Debugging Message Levels:
234 1: High-Level Tracing
237 To enable debug output to console, please make sure that:
239 a. System and kernel logging is enabled (syslogd, klogd running).
240 b. Kernel messages are routed to console output. Check
241 /etc/syslog.conf for an entry similar to this:
245 c. klogd is started with the appropriate -c parameter
248 This will cause printk() messages to be be displayed on the
249 current console. Refer to the klogd(8) and syslogd(8) man pages
252 Alternatively you can enable printk() to console with this
253 program. However, this is not the 'official' way to do this.
254 Debug output is logged in /var/log/messages.
258 syscall(103, 7, 0, 0);
261 Increasing LOG_BUF_LEN in kernel/printk.c to something like
262 40960 allows more debug messages to be buffered in the kernel
263 and written to the console or log file.
265 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
267 Enabling this option adds statistics collection and display
268 through /proc to the driver. The information is useful for
269 monitoring driver and device performance. It will add to the
270 size of the driver execution image and add minor overhead to
271 the execution of the driver.
273 Statistics are maintained on a per adapter basis. Driver entry
274 point call counts and transfer size counts are maintained.
275 Statistics are only available for kernels greater than or equal
276 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
278 AdvanSys SCSI adapter files have the following path name format:
280 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
282 This information can be displayed with cat. For example:
284 cat /proc/scsi/advansys/0
286 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
287 contain adapter and device configuration information.
289 F. Driver LILO Option
291 If init/main.c is modified as described in the 'Directions for Adding
292 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
293 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
294 This option can be used to either disable I/O port scanning or to limit
295 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
296 PCI boards will still be searched for and detected. This option only
297 affects searching for ISA and VL boards.
300 1. Eliminate I/O port scanning:
301 boot: linux advansys=
303 boot: linux advansys=0x0
304 2. Limit I/O port scanning to one I/O port:
305 boot: linux advansys=0x110
306 3. Limit I/O port scanning to four I/O ports:
307 boot: linux advansys=0x110,0x210,0x230,0x330
309 For a loadable module the same effect can be achieved by setting
310 the 'asc_iopflag' variable and 'asc_ioport' array when loading
313 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
315 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
316 I/O Port may be added to specify the driver debug level. Refer to
317 the 'Driver Compile Time Options and Debugging' section above for
320 G. Tests to run before releasing new driver
322 1. In the supported kernels verify there are no warning or compile
323 errors when the kernel is built as both a driver and as a module
324 and with the following options:
326 ADVANSYS_DEBUG - enabled and disabled
327 CONFIG_SMP - enabled and disabled
328 CONFIG_PROC_FS - enabled and disabled
330 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
331 card and one wide card attached to a hard disk and CD-ROM drive:
332 fdisk, mkfs, fsck, bonnie, copy/compare test from the
333 CD-ROM to the hard drive.
341 1. Prevent advansys_detect() from being called twice.
342 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
345 1. Prevent re-entrancy in the interrupt handler which
346 resulted in the driver hanging Linux.
347 2. Fix problem that prevented ABP-940 cards from being
348 recognized on some PCI motherboards.
349 3. Add support for the ABP-5140 PnP ISA card.
350 4. Fix check condition return status.
351 5. Add conditionally compiled code for Linux v1.3.X.
354 1. Fix problem in advansys_biosparam() that resulted in the
355 wrong drive geometry being returned for drives > 1GB with
356 extended translation enabled.
357 2. Add additional tracing during device initialization.
358 3. Change code that only applies to ISA PnP adapter.
359 4. Eliminate 'make dep' warning.
360 5. Try to fix problem with handling resets by increasing their
364 1. Change definitions to eliminate conflicts with other subsystems.
365 2. Add versioning code for the shared interrupt changes.
366 3. Eliminate problem in asc_rmqueue() with iterating after removing
368 4. Remove reset request loop problem from the "Known Problems or
369 Issues" section. This problem was isolated and fixed in the
370 mid-level SCSI driver.
373 1. Add support for ABP-940U (PCI Ultra) adapter.
374 2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
375 request_irq and supplying a dev_id pointer to both request_irq()
377 3. In AscSearchIOPortAddr11() restore a call to check_region() which
378 should be used before I/O port probing.
379 4. Fix bug in asc_prt_hex() which resulted in the displaying
381 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
382 6. Change driver versioning to be specific to each Linux sub-level.
383 7. Change statistics gathering to be per adapter instead of global
385 8. Add more information and statistics to the adapter /proc file:
386 /proc/scsi/advansys[0...].
387 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
388 This problem has been addressed with the SCSI mid-level changes
389 made in v1.3.89. The advansys_select_queue_depths() function
390 was added for the v1.3.89 changes.
393 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
396 1. Enable clustering and optimize the setting of the maximum number
397 of scatter gather elements for any particular board. Clustering
398 increases CPU utilization, but results in a relatively larger
399 increase in I/O throughput.
400 2. Improve the performance of the request queuing functions by
401 adding a last pointer to the queue structure.
402 3. Correct problems with reset and abort request handling that
403 could have hung or crashed Linux.
404 4. Add more information to the adapter /proc file:
405 /proc/scsi/advansys[0...].
406 5. Remove the request timeout issue form the driver issues list.
407 6. Miscellaneous documentation additions and changes.
410 1. Make changes to handle the new v2.1.0 kernel memory mapping
411 in which a kernel virtual address may not be equivalent to its
412 bus or DMA memory address.
413 2. Change abort and reset request handling to make it yet even
415 3. Try to mitigate request starvation by sending ordered requests
416 to heavily loaded, tag queuing enabled devices.
417 4. Maintain statistics on request response time.
418 5. Add request response time statistics and other information to
419 the adapter /proc file: /proc/scsi/advansys[0...].
422 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
423 make use of mid-level SCSI driver device queue depth flow
424 control mechanism. This will eliminate aborts caused by a
425 device being unable to keep up with requests and eliminate
426 repeat busy or QUEUE FULL status returned by a device.
427 2. Incorporate miscellaneous Asc Library bug fixes.
428 3. To allow the driver to work in kernels with broken module
429 support set 'cmd_per_lun' if the driver is compiled as a
430 module. This change affects kernels v1.3.89 to present.
431 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
432 is relocated by the motherboard BIOS and its new address can
433 not be determined by the driver.
434 5. Add mid-level SCSI queue depth information to the adapter
435 /proc file: /proc/scsi/advansys[0...].
438 1. Change allocation of global structures used for device
439 initialization to guarantee they are in DMA-able memory.
440 Previously when the driver was loaded as a module these
441 structures might not have been in DMA-able memory, causing
442 device initialization to fail.
445 1. In advansys_reset(), if the request is a synchronous reset
446 request, even if the request serial number has changed, then
447 complete the request.
448 2. Add Asc Library bug fixes including new microcode.
449 3. Clear inquiry buffer before using it.
450 4. Correct ifdef typo.
453 1. Add Asc Library bug fixes including new microcode.
454 2. Add synchronous data transfer rate information to the
455 adapter /proc file: /proc/scsi/advansys[0...].
456 3. Change ADVANSYS_DEBUG to be disabled by default. This
457 will reduce the size of the driver image, eliminate execution
458 overhead, and remove unneeded symbols from the kernel symbol
459 space that were previously added by the driver.
460 4. Add new compile-time option ADVANSYS_ASSERT for assertion
461 code that used to be defined within ADVANSYS_DEBUG. This
462 option is enabled by default.
465 1. Change version number to 2.8 to synchronize the Linux driver
466 version numbering with other AdvanSys drivers.
467 2. Reformat source files without tabs to present the same view
468 of the file to everyone regardless of the editor tab setting
470 3. Add Asc Library bug fixes.
473 1. Change version number to 3.1 to indicate that support for
474 Ultra-Wide adapters (ABP-940UW) is included in this release.
475 2. Add Asc Library (Narrow Board) bug fixes.
476 3. Report an underrun condition with the host status byte set
477 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
478 causes the underrun condition to be ignored. When Linux defines
479 its own DID_UNDERRUN the constant defined in this file can be
481 4. Add patch to AscWaitTixISRDone().
482 5. Add support for up to 16 different AdvanSys host adapter SCSI
483 channels in one system. This allows four cards with four channels
484 to be used in one system.
487 1. Handle that PCI register base addresses are not always page
488 aligned even though ioremap() requires that the address argument
492 1. Update latest BIOS version checked for from the /proc file.
493 2. Don't set microcode SDTR variable at initialization. Instead
494 wait until device capabilities have been detected from an Inquiry
498 1. Improve performance when the driver is compiled as module by
499 allowing up to 64 scatter-gather elements instead of 8.
502 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
503 2. Include SMP locking changes.
504 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
506 4. Update board serial number printing.
507 5. Try allocating an IRQ both with and without the SA_INTERRUPT
508 flag set to allow IRQ sharing with drivers that do not set
509 the SA_INTERRUPT flag. Also display a more descriptive error
510 message if request_irq() fails.
511 6. Update to latest Asc and Adv Libraries.
514 1. Update Adv Library to 4.16 which includes support for
515 the ASC38C0800 (Ultra2/LVD) IC.
518 1. Correct PCI compile time option for v2.1.93 and greater
519 kernels, advansys_info() string, and debug compile time
521 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
522 kernels. This caused an LVD detection/BIST problem problem
524 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
525 to be consistent with the BIOS.
526 4. Update to Asc Library S121 and Adv Library 5.2.
529 1. Correct PCI card detection bug introduced in 3.2B that
530 prevented PCI cards from being detected in kernels older
534 1. Correct /proc device synchronous speed information display.
535 Also when re-negotiation is pending for a target device
536 note this condition with an * and footnote.
537 2. Correct initialization problem with Ultra-Wide cards that
538 have a pre-3.2 BIOS. A microcode variable changed locations
539 in 3.2 and greater BIOSes which caused WDTR to be attempted
540 erroneously with drives that don't support WDTR.
543 1. Fix compile error caused by v2.3.13 PCI structure change.
544 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
545 checksum error for ISA cards.
546 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
547 SCSI changes that it depended on were never included in Linux.
550 1. Handle new initial function code added in v2.3.16 for all
554 1. Fix PCI board detection in v2.3.13 and greater kernels.
555 2. Fix comiple errors in v2.3.X with debugging enabled.
558 1. Add 64-bit address, long support for Alpha and UltraSPARC.
559 The driver has been verified to work on an Alpha system.
560 2. Add partial byte order handling support for Power PC and
561 other big-endian platforms. This support has not yet been
562 completed or verified.
563 3. For wide boards replace block zeroing of request and
564 scatter-gather structures with individual field initialization
565 to improve performance.
566 4. Correct and clarify ROM BIOS version detection.
569 1. Update to Adv Library 5.4.
570 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
571 adv_isr_callback(). Remove DID_UNDERRUN constant and other
572 no longer needed code that previously documented the lack
573 of underrun handling.
576 1. Eliminate compile errors for v2.0 and earlier kernels.
579 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
580 2. Update Adv Library to 5.5.
581 3. Add ifdef handling for /proc changes added in v2.3.28.
582 4. Increase Wide board scatter-gather list maximum length to
583 255 when the driver is compiled into the kernel.
586 1. Fix bug in adv_get_sglist() that caused an assertion failure
587 at line 7475. The reqp->sgblkp pointer must be initialized
588 to NULL in adv_get_sglist().
591 1. Really fix bug in adv_get_sglist().
592 2. Incorporate v2.3.29 changes into driver.
595 1. Add CONFIG_ISA ifdef code.
596 2. Include advansys_interrupts_enabled name change patch.
597 3. For >= v2.3.28 use new SCSI error handling with new function
598 advansys_eh_bus_reset(). Don't include an abort function
599 because of base library limitations.
600 4. For >= v2.3.28 use per board lock instead of io_request_lock.
601 5. For >= v2.3.28 eliminate advansys_command() and
602 advansys_command_done().
603 6. Add some changes for PowerPC (Big Endian) support, but it isn't
605 7. Fix "nonexistent resource free" problem that occurred on a module
606 unload for boards with an I/O space >= 255. The 'n_io_port' field
607 is only one byte and can not be used to hold an ioport length more
611 1. Update to Adv Library 5.8.
612 2. For wide cards add support for CDBs up to 16 bytes.
613 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
616 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
618 2. Change bitfields to shift and mask access for endian
622 1. Update for latest 2.4 kernel.
623 2. Test ABP-480 CardBus support in 2.4 kernel - works!
624 3. Update to Asc Library S123.
625 4. Update to Adv Library 5.12.
628 1. Update for latest 2.4 kernel.
629 2. Create patches for 2.2 and 2.4 kernels.
632 1. Now that 2.4 is released remove ifdef code for kernel versions
633 less than 2.2. The driver is now only supported in kernels 2.2,
635 2. Add code to release and acquire the io_request_lock in
636 the driver entrypoint functions: advansys_detect and
637 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
638 still holds the io_request_lock on entry to SCSI low-level drivers.
639 This was supposed to be removed before 2.4 was released but never
640 happened. When the mid-level SCSI driver is changed all references
641 to the io_request_lock should be removed from the driver.
642 3. Simplify error handling by removing advansys_abort(),
643 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
644 now handled by resetting the SCSI bus and fully re-initializing
645 the chip. This simple method of error recovery has proven to work
646 most reliably after attempts at different methods. Also now only
647 support the "new" error handling method and remove the obsolete
648 error handling interface.
649 4. Fix debug build errors.
652 1. Merge with ConnectCom version from Andy Kellner which
653 updates Adv Library to 5.14.
654 2. Make PowerPC (Big Endian) work for narrow cards and
655 fix problems writing EEPROM for wide cards.
656 3. Remove interrupts_enabled assertion function.
659 1. Return an error from narrow boards if passed a 16 byte
660 CDB. The wide board can already handle 16 byte CDBs.
663 1. hacks for lk 2.5 series (D. Gilbert)
666 1. change select_queue_depths to slave_configure
667 2. make cmd_per_lun be sane again
670 1. continuing cleanup for lk 2.6 series
671 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
672 3. Fix problem that oopsed ISA cards
674 I. Known Problems/Fix List (XXX)
676 1. Need to add memory mapping workaround. Test the memory mapping.
677 If it doesn't work revert to I/O port access. Can a test be done
679 2. Handle an interrupt not working. Keep an interrupt counter in
680 the interrupt handler. In the timeout function if the interrupt
681 has not occurred then print a message and run in polled mode.
682 3. Allow bus type scanning order to be changed.
683 4. Need to add support for target mode commands, cf. CAM XPT.
685 J. Credits (Chronological Order)
687 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
688 and maintained it up to 3.3F. He continues to answer questions
689 and help maintain the driver.
691 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
692 basis for the Linux v1.3.X changes which were included in the
695 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
696 in advansys_biosparam() which was fixed in the 1.3 release.
698 Erik Ratcliffe <erik@caldera.com> has done testing of the
699 AdvanSys driver in the Caldera releases.
701 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
702 AscWaitTixISRDone() which he found necessary to make the
703 driver work with a SCSI-1 disk.
705 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
706 support in the 3.1A driver.
708 Doug Gilbert <dgilbert@interlog.com> has made changes and
709 suggestions to improve the driver and done a lot of testing.
711 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
714 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
715 patch and helped with PowerPC wide and narrow board support.
717 Philip Blundell <philb@gnu.org> provided an
718 advansys_interrupts_enabled patch.
720 Dave Jones <dave@denial.force9.co.uk> reported the compiler
721 warnings generated when CONFIG_PROC_FS was not defined in
724 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
725 problems) for wide cards.
727 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
730 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
731 board support and fixed a bug in AscGetEEPConfig().
733 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
734 save_flags/restore_flags changes.
736 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
737 driver development for ConnectCom (Version > 3.3F).
739 K. ConnectCom (AdvanSys) Contact Information
741 Mail: ConnectCom Solutions, Inc.
744 Operator/Sales: 1-408-383-9400
746 Tech Support: 1-408-467-2930
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754 * --- Linux Include Files
757 #include <linux/config.h>
758 #include <linux/module.h>
760 #if defined(CONFIG_X86) && !defined(CONFIG_ISA)
762 #endif /* CONFIG_X86 && !CONFIG_ISA */
764 #include <linux/string.h>
765 #include <linux/kernel.h>
766 #include <linux/types.h>
767 #include <linux/ioport.h>
768 #include <linux/interrupt.h>
769 #include <linux/delay.h>
770 #include <linux/slab.h>
771 #include <linux/mm.h>
772 #include <linux/proc_fs.h>
773 #include <linux/init.h>
774 #include <linux/blkdev.h>
775 #include <linux/stat.h>
776 #include <linux/spinlock.h>
777 #include <linux/dma-mapping.h>
780 #include <asm/system.h>
783 /* FIXME: (by jejb@steeleye.com) This warning is present for two
786 * 1) This driver badly needs converting to the correct driver model
789 * 2) Although all of the necessary command mapping places have the
790 * appropriate dma_map.. APIs, the driver still processes its internal
791 * queue using bus_to_virt() and virt_to_bus() which are illegal under
792 * the API. The entire queue processing structure will need to be
793 * altered to fix this.
795 #warning this driver is still not properly converted to the DMA API
797 #include <scsi/scsi_cmnd.h>
798 #include <scsi/scsi_device.h>
799 #include <scsi/scsi_tcq.h>
800 #include <scsi/scsi.h>
801 #include <scsi/scsi_host.h>
802 #include "advansys.h"
804 #include <linux/pci.h>
805 #endif /* CONFIG_PCI */
812 /* Enable driver assertions. */
813 #define ADVANSYS_ASSERT
815 /* Enable driver /proc statistics. */
816 #define ADVANSYS_STATS
818 /* Enable driver tracing. */
819 /* #define ADVANSYS_DEBUG */
823 * --- Debugging Header
826 #ifdef ADVANSYS_DEBUG
828 #else /* ADVANSYS_DEBUG */
829 #define STATIC static
830 #endif /* ADVANSYS_DEBUG */
834 * --- Asc Library Constants and Macros
837 #define ASC_LIB_VERSION_MAJOR 1
838 #define ASC_LIB_VERSION_MINOR 24
839 #define ASC_LIB_SERIAL_NUMBER 123
842 * Portable Data Types
844 * Any instance where a 32-bit long or pointer type is assumed
845 * for precision or HW defined structures, the following define
846 * types must be used. In Linux the char, short, and int types
847 * are all consistent at 8, 16, and 32 bits respectively. Pointers
848 * and long types are 64 bits on Alpha and UltraSPARC.
850 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
851 #define ASC_VADDR __u32 /* Virtual address data type. */
852 #define ASC_DCNT __u32 /* Unsigned Data count type. */
853 #define ASC_SDCNT __s32 /* Signed Data count type. */
856 * These macros are used to convert a virtual address to a
857 * 32-bit value. This currently can be used on Linux Alpha
858 * which uses 64-bit virtual address but a 32-bit bus address.
859 * This is likely to break in the future, but doing this now
860 * will give us time to change the HW and FW to handle 64-bit
863 #define ASC_VADDR_TO_U32 virt_to_bus
864 #define ASC_U32_TO_VADDR bus_to_virt
866 typedef unsigned char uchar;
877 #define UW_ERR (uint)(0xFFFF)
878 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
879 #define AscPCIConfigVendorIDRegister 0x0000
880 #define AscPCIConfigDeviceIDRegister 0x0002
881 #define AscPCIConfigCommandRegister 0x0004
882 #define AscPCIConfigStatusRegister 0x0006
883 #define AscPCIConfigRevisionIDRegister 0x0008
884 #define AscPCIConfigCacheSize 0x000C
885 #define AscPCIConfigLatencyTimer 0x000D
886 #define AscPCIIOBaseRegister 0x0010
887 #define AscPCICmdRegBits_IOMemBusMaster 0x0007
888 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
889 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
890 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
891 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
892 #define ASC_PCI_REVISION_3150 0x02
893 #define ASC_PCI_REVISION_3050 0x03
895 #define ASC_DVCLIB_CALL_DONE (1)
896 #define ASC_DVCLIB_CALL_FAILED (0)
897 #define ASC_DVCLIB_CALL_ERROR (-1)
900 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
901 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
902 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
905 #define CC_VERY_LONG_SG_LIST 0
906 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
908 #define PortAddr unsigned short /* port address size */
909 #define inp(port) inb(port)
910 #define outp(port, byte) outb((byte), (port))
912 #define inpw(port) inw(port)
913 #define outpw(port, word) outw((word), (port))
915 #define ASC_MAX_SG_QUEUE 7
916 #define ASC_MAX_SG_LIST 255
918 #define ASC_CS_TYPE unsigned short
920 #define ASC_IS_ISA (0x0001)
921 #define ASC_IS_ISAPNP (0x0081)
922 #define ASC_IS_EISA (0x0002)
923 #define ASC_IS_PCI (0x0004)
924 #define ASC_IS_PCI_ULTRA (0x0104)
925 #define ASC_IS_PCMCIA (0x0008)
926 #define ASC_IS_MCA (0x0020)
927 #define ASC_IS_VL (0x0040)
928 #define ASC_ISA_PNP_PORT_ADDR (0x279)
929 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
930 #define ASC_IS_WIDESCSI_16 (0x0100)
931 #define ASC_IS_WIDESCSI_32 (0x0200)
932 #define ASC_IS_BIG_ENDIAN (0x8000)
933 #define ASC_CHIP_MIN_VER_VL (0x01)
934 #define ASC_CHIP_MAX_VER_VL (0x07)
935 #define ASC_CHIP_MIN_VER_PCI (0x09)
936 #define ASC_CHIP_MAX_VER_PCI (0x0F)
937 #define ASC_CHIP_VER_PCI_BIT (0x08)
938 #define ASC_CHIP_MIN_VER_ISA (0x11)
939 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
940 #define ASC_CHIP_MAX_VER_ISA (0x27)
941 #define ASC_CHIP_VER_ISA_BIT (0x30)
942 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
943 #define ASC_CHIP_VER_ASYN_BUG (0x21)
944 #define ASC_CHIP_VER_PCI 0x08
945 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
946 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
947 #define ASC_CHIP_MIN_VER_EISA (0x41)
948 #define ASC_CHIP_MAX_VER_EISA (0x47)
949 #define ASC_CHIP_VER_EISA_BIT (0x40)
950 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
951 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
952 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
953 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
954 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
955 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
956 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
957 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
958 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
959 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
960 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
962 #define ASC_SCSI_ID_BITS 3
963 #define ASC_SCSI_TIX_TYPE uchar
964 #define ASC_ALL_DEVICE_BIT_SET 0xFF
965 #define ASC_SCSI_BIT_ID_TYPE uchar
966 #define ASC_MAX_TID 7
967 #define ASC_MAX_LUN 7
968 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
969 #define ASC_MAX_SENSE_LEN 32
970 #define ASC_MIN_SENSE_LEN 14
971 #define ASC_MAX_CDB_LEN 12
972 #define ASC_SCSI_RESET_HOLD_TIME_US 60
974 #define ADV_INQ_CLOCKING_ST_ONLY 0x0
975 #define ADV_INQ_CLOCKING_DT_ONLY 0x1
976 #define ADV_INQ_CLOCKING_ST_AND_DT 0x3
979 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
980 * and CmdDt (Command Support Data) field bit definitions.
982 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
983 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
984 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
985 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
987 #define ASC_SCSIDIR_NOCHK 0x00
988 #define ASC_SCSIDIR_T2H 0x08
989 #define ASC_SCSIDIR_H2T 0x10
990 #define ASC_SCSIDIR_NODATA 0x18
991 #define SCSI_ASC_NOMEDIA 0x3A
992 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
993 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
994 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
995 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
996 #define MS_CMD_DONE 0x00
997 #define MS_EXTEND 0x01
998 #define MS_SDTR_LEN 0x03
999 #define MS_SDTR_CODE 0x01
1000 #define MS_WDTR_LEN 0x02
1001 #define MS_WDTR_CODE 0x03
1002 #define MS_MDP_LEN 0x05
1003 #define MS_MDP_CODE 0x00
1006 * Inquiry data structure and bitfield macros
1008 * Only quantities of more than 1 bit are shifted, since the others are
1009 * just tested for true or false. C bitfields aren't portable between big
1010 * and little-endian platforms so they are not used.
1013 #define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1014 #define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1015 #define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1016 #define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1017 #define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1018 #define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1019 #define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1020 #define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1021 #define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1022 #define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1023 #define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1024 #define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1025 #define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1026 #define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1027 #define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1028 #define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1029 #define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1030 #define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1031 #define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1032 #define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1044 uchar product_id[16];
1045 uchar product_rev_level[4];
1048 #define ASC_SG_LIST_PER_Q 7
1049 #define QS_FREE 0x00
1050 #define QS_READY 0x01
1051 #define QS_DISC1 0x02
1052 #define QS_DISC2 0x04
1053 #define QS_BUSY 0x08
1054 #define QS_ABORTED 0x40
1055 #define QS_DONE 0x80
1056 #define QC_NO_CALLBACK 0x01
1057 #define QC_SG_SWAP_QUEUE 0x02
1058 #define QC_SG_HEAD 0x04
1059 #define QC_DATA_IN 0x08
1060 #define QC_DATA_OUT 0x10
1061 #define QC_URGENT 0x20
1062 #define QC_MSG_OUT 0x40
1063 #define QC_REQ_SENSE 0x80
1064 #define QCSG_SG_XFER_LIST 0x02
1065 #define QCSG_SG_XFER_MORE 0x04
1066 #define QCSG_SG_XFER_END 0x08
1067 #define QD_IN_PROGRESS 0x00
1068 #define QD_NO_ERROR 0x01
1069 #define QD_ABORTED_BY_HOST 0x02
1070 #define QD_WITH_ERROR 0x04
1071 #define QD_INVALID_REQUEST 0x80
1072 #define QD_INVALID_HOST_NUM 0x81
1073 #define QD_INVALID_DEVICE 0x82
1074 #define QD_ERR_INTERNAL 0xFF
1075 #define QHSTA_NO_ERROR 0x00
1076 #define QHSTA_M_SEL_TIMEOUT 0x11
1077 #define QHSTA_M_DATA_OVER_RUN 0x12
1078 #define QHSTA_M_DATA_UNDER_RUN 0x12
1079 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1080 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1081 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1082 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1083 #define QHSTA_D_HOST_ABORT_FAILED 0x23
1084 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1085 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1086 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1087 #define QHSTA_M_WTM_TIMEOUT 0x41
1088 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1089 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1090 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1091 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
1092 #define QHSTA_M_BAD_TAG_CODE 0x46
1093 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1094 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1095 #define QHSTA_D_LRAM_CMP_ERROR 0x81
1096 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1097 #define ASC_FLAG_SCSIQ_REQ 0x01
1098 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1099 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
1100 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1101 #define ASC_FLAG_WIN16 0x10
1102 #define ASC_FLAG_WIN32 0x20
1103 #define ASC_FLAG_ISA_OVER_16MB 0x40
1104 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
1105 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1106 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1107 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1108 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1109 #define ASC_SCSIQ_CPY_BEG 4
1110 #define ASC_SCSIQ_SGHD_CPY_BEG 2
1111 #define ASC_SCSIQ_B_FWD 0
1112 #define ASC_SCSIQ_B_BWD 1
1113 #define ASC_SCSIQ_B_STATUS 2
1114 #define ASC_SCSIQ_B_QNO 3
1115 #define ASC_SCSIQ_B_CNTL 4
1116 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1117 #define ASC_SCSIQ_D_DATA_ADDR 8
1118 #define ASC_SCSIQ_D_DATA_CNT 12
1119 #define ASC_SCSIQ_B_SENSE_LEN 20
1120 #define ASC_SCSIQ_DONE_INFO_BEG 22
1121 #define ASC_SCSIQ_D_SRBPTR 22
1122 #define ASC_SCSIQ_B_TARGET_IX 26
1123 #define ASC_SCSIQ_B_CDB_LEN 28
1124 #define ASC_SCSIQ_B_TAG_CODE 29
1125 #define ASC_SCSIQ_W_VM_ID 30
1126 #define ASC_SCSIQ_DONE_STATUS 32
1127 #define ASC_SCSIQ_HOST_STATUS 33
1128 #define ASC_SCSIQ_SCSI_STATUS 34
1129 #define ASC_SCSIQ_CDB_BEG 36
1130 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1131 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1132 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1133 #define ASC_SCSIQ_B_SG_WK_QP 49
1134 #define ASC_SCSIQ_B_SG_WK_IX 50
1135 #define ASC_SCSIQ_W_ALT_DC1 52
1136 #define ASC_SCSIQ_B_LIST_CNT 6
1137 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
1138 #define ASC_SGQ_B_SG_CNTL 4
1139 #define ASC_SGQ_B_SG_HEAD_QP 5
1140 #define ASC_SGQ_B_SG_LIST_CNT 6
1141 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1142 #define ASC_SGQ_LIST_BEG 8
1143 #define ASC_DEF_SCSI1_QNG 4
1144 #define ASC_MAX_SCSI1_QNG 4
1145 #define ASC_DEF_SCSI2_QNG 16
1146 #define ASC_MAX_SCSI2_QNG 32
1147 #define ASC_TAG_CODE_MASK 0x23
1148 #define ASC_STOP_REQ_RISC_STOP 0x01
1149 #define ASC_STOP_ACK_RISC_STOP 0x03
1150 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1151 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1152 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1153 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1154 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1155 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1156 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1157 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1158 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1159 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1161 typedef struct asc_scsiq_1 {
1168 ASC_PADDR data_addr;
1170 ASC_PADDR sense_addr;
1175 typedef struct asc_scsiq_2 {
1184 typedef struct asc_scsiq_3 {
1191 typedef struct asc_scsiq_4 {
1192 uchar cdb[ASC_MAX_CDB_LEN];
1193 uchar y_first_sg_list_qp;
1194 uchar y_working_sg_qp;
1195 uchar y_working_sg_ix;
1198 ushort x_reconnect_rtn;
1199 ASC_PADDR x_saved_data_addr;
1200 ASC_DCNT x_saved_data_cnt;
1203 typedef struct asc_q_done_info {
1212 ASC_DCNT remain_bytes;
1215 typedef struct asc_sg_list {
1220 typedef struct asc_sg_head {
1223 ushort entry_to_copy;
1225 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1228 #define ASC_MIN_SG_LIST 2
1230 typedef struct asc_min_sg_head {
1233 ushort entry_to_copy;
1235 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1238 #define QCX_SORT (0x0001)
1239 #define QCX_COALEASE (0x0002)
1241 typedef struct asc_scsi_q {
1245 ASC_SG_HEAD *sg_head;
1246 ushort remain_sg_entry_cnt;
1247 ushort next_sg_index;
1250 typedef struct asc_scsi_req_q {
1254 ASC_SG_HEAD *sg_head;
1257 uchar cdb[ASC_MAX_CDB_LEN];
1258 uchar sense[ASC_MIN_SENSE_LEN];
1261 typedef struct asc_scsi_bios_req_q {
1265 ASC_SG_HEAD *sg_head;
1268 uchar cdb[ASC_MAX_CDB_LEN];
1269 uchar sense[ASC_MIN_SENSE_LEN];
1270 } ASC_SCSI_BIOS_REQ_Q;
1272 typedef struct asc_risc_q {
1281 typedef struct asc_sg_list_q {
1287 uchar sg_cur_list_cnt;
1290 typedef struct asc_risc_sg_list_q {
1294 ASC_SG_LIST sg_list[7];
1295 } ASC_RISC_SG_LIST_Q;
1297 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1298 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1299 #define ASCQ_ERR_NO_ERROR 0
1300 #define ASCQ_ERR_IO_NOT_FOUND 1
1301 #define ASCQ_ERR_LOCAL_MEM 2
1302 #define ASCQ_ERR_CHKSUM 3
1303 #define ASCQ_ERR_START_CHIP 4
1304 #define ASCQ_ERR_INT_TARGET_ID 5
1305 #define ASCQ_ERR_INT_LOCAL_MEM 6
1306 #define ASCQ_ERR_HALT_RISC 7
1307 #define ASCQ_ERR_GET_ASPI_ENTRY 8
1308 #define ASCQ_ERR_CLOSE_ASPI 9
1309 #define ASCQ_ERR_HOST_INQUIRY 0x0A
1310 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1311 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1312 #define ASCQ_ERR_Q_STATUS 0x0D
1313 #define ASCQ_ERR_WR_SCSIQ 0x0E
1314 #define ASCQ_ERR_PC_ADDR 0x0F
1315 #define ASCQ_ERR_SYN_OFFSET 0x10
1316 #define ASCQ_ERR_SYN_XFER_TIME 0x11
1317 #define ASCQ_ERR_LOCK_DMA 0x12
1318 #define ASCQ_ERR_UNLOCK_DMA 0x13
1319 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1320 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
1321 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
1322 #define ASCQ_ERR_CUR_QNG 0x17
1323 #define ASCQ_ERR_SG_Q_LINKS 0x18
1324 #define ASCQ_ERR_SCSIQ_PTR 0x19
1325 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1326 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1327 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1328 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1329 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1330 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1331 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1332 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1333 #define ASCQ_ERR_SEND_SCSI_Q 0x22
1334 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1335 #define ASCQ_ERR_RESET_SDTR 0x24
1338 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1340 #define ASC_WARN_NO_ERROR 0x0000
1341 #define ASC_WARN_IO_PORT_ROTATE 0x0001
1342 #define ASC_WARN_EEPROM_CHKSUM 0x0002
1343 #define ASC_WARN_IRQ_MODIFIED 0x0004
1344 #define ASC_WARN_AUTO_CONFIG 0x0008
1345 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1346 #define ASC_WARN_EEPROM_RECOVER 0x0020
1347 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
1348 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1351 * Error code values are set in ASC_DVC_VAR 'err_code'.
1353 #define ASC_IERR_WRITE_EEPROM 0x0001
1354 #define ASC_IERR_MCODE_CHKSUM 0x0002
1355 #define ASC_IERR_SET_PC_ADDR 0x0004
1356 #define ASC_IERR_START_STOP_CHIP 0x0008
1357 #define ASC_IERR_IRQ_NO 0x0010
1358 #define ASC_IERR_SET_IRQ_NO 0x0020
1359 #define ASC_IERR_CHIP_VERSION 0x0040
1360 #define ASC_IERR_SET_SCSI_ID 0x0080
1361 #define ASC_IERR_GET_PHY_ADDR 0x0100
1362 #define ASC_IERR_BAD_SIGNATURE 0x0200
1363 #define ASC_IERR_NO_BUS_TYPE 0x0400
1364 #define ASC_IERR_SCAM 0x0800
1365 #define ASC_IERR_SET_SDTR 0x1000
1366 #define ASC_IERR_RW_LRAM 0x8000
1368 #define ASC_DEF_IRQ_NO 10
1369 #define ASC_MAX_IRQ_NO 15
1370 #define ASC_MIN_IRQ_NO 10
1371 #define ASC_MIN_REMAIN_Q (0x02)
1372 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1373 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
1374 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
1375 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1376 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1377 #define ASC_MAX_TOTAL_QNG 240
1378 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1379 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1380 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1381 #define ASC_MAX_INRAM_TAG_QNG 16
1382 #define ASC_IOADR_TABLE_MAX_IX 11
1383 #define ASC_IOADR_GAP 0x10
1384 #define ASC_SEARCH_IOP_GAP 0x10
1385 #define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1386 #define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1387 #define ASC_IOADR_1 (PortAddr)0x0110
1388 #define ASC_IOADR_2 (PortAddr)0x0130
1389 #define ASC_IOADR_3 (PortAddr)0x0150
1390 #define ASC_IOADR_4 (PortAddr)0x0190
1391 #define ASC_IOADR_5 (PortAddr)0x0210
1392 #define ASC_IOADR_6 (PortAddr)0x0230
1393 #define ASC_IOADR_7 (PortAddr)0x0250
1394 #define ASC_IOADR_8 (PortAddr)0x0330
1395 #define ASC_IOADR_DEF ASC_IOADR_8
1396 #define ASC_LIB_SCSIQ_WK_SP 256
1397 #define ASC_MAX_SYN_XFER_NO 16
1398 #define ASC_SYN_MAX_OFFSET 0x0F
1399 #define ASC_DEF_SDTR_OFFSET 0x0F
1400 #define ASC_DEF_SDTR_INDEX 0x00
1401 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1402 #define SYN_XFER_NS_0 25
1403 #define SYN_XFER_NS_1 30
1404 #define SYN_XFER_NS_2 35
1405 #define SYN_XFER_NS_3 40
1406 #define SYN_XFER_NS_4 50
1407 #define SYN_XFER_NS_5 60
1408 #define SYN_XFER_NS_6 70
1409 #define SYN_XFER_NS_7 85
1410 #define SYN_ULTRA_XFER_NS_0 12
1411 #define SYN_ULTRA_XFER_NS_1 19
1412 #define SYN_ULTRA_XFER_NS_2 25
1413 #define SYN_ULTRA_XFER_NS_3 32
1414 #define SYN_ULTRA_XFER_NS_4 38
1415 #define SYN_ULTRA_XFER_NS_5 44
1416 #define SYN_ULTRA_XFER_NS_6 50
1417 #define SYN_ULTRA_XFER_NS_7 57
1418 #define SYN_ULTRA_XFER_NS_8 63
1419 #define SYN_ULTRA_XFER_NS_9 69
1420 #define SYN_ULTRA_XFER_NS_10 75
1421 #define SYN_ULTRA_XFER_NS_11 82
1422 #define SYN_ULTRA_XFER_NS_12 88
1423 #define SYN_ULTRA_XFER_NS_13 94
1424 #define SYN_ULTRA_XFER_NS_14 100
1425 #define SYN_ULTRA_XFER_NS_15 107
1427 typedef struct ext_msg {
1433 uchar sdtr_xfer_period;
1434 uchar sdtr_req_ack_offset;
1449 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1450 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1451 #define wdtr_width u_ext_msg.wdtr.wdtr_width
1452 #define mdp_b3 u_ext_msg.mdp_b3
1453 #define mdp_b2 u_ext_msg.mdp_b2
1454 #define mdp_b1 u_ext_msg.mdp_b1
1455 #define mdp_b0 u_ext_msg.mdp_b0
1457 typedef struct asc_dvc_cfg {
1458 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1459 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1460 ASC_SCSI_BIT_ID_TYPE disc_enable;
1461 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1463 uchar isa_dma_speed;
1464 uchar isa_dma_channel;
1466 ushort lib_serial_no;
1469 ushort mcode_version;
1470 uchar max_tag_qng[ASC_MAX_TID + 1];
1472 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1473 ushort pci_slot_info;
1474 uchar adapter_info[6];
1478 #define ASC_DEF_DVC_CNTL 0xFFFF
1479 #define ASC_DEF_CHIP_SCSI_ID 7
1480 #define ASC_DEF_ISA_DMA_SPEED 4
1481 #define ASC_INIT_STATE_NULL 0x0000
1482 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1483 #define ASC_INIT_STATE_END_GET_CFG 0x0002
1484 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1485 #define ASC_INIT_STATE_END_SET_CFG 0x0008
1486 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1487 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
1488 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1489 #define ASC_INIT_STATE_END_INQUIRY 0x0080
1490 #define ASC_INIT_RESET_SCSI_DONE 0x0100
1491 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1492 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1493 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1494 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1495 #define ASC_MIN_TAGGED_CMD 7
1496 #define ASC_MAX_SCSI_RESET_WAIT 30
1498 struct asc_dvc_var; /* Forward Declaration. */
1500 typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
1501 typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
1503 typedef struct asc_dvc_var {
1507 ushort bug_fix_cntl;
1509 ASC_ISR_CALLBACK isr_callback;
1510 ASC_EXE_CALLBACK exe_callback;
1511 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1512 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1513 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1514 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1515 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1516 ASC_SCSI_BIT_ID_TYPE start_motor;
1517 uchar scsi_reset_wait;
1520 uchar max_total_qng;
1521 uchar cur_total_qng;
1522 uchar in_critical_cnt;
1524 uchar last_q_shortage;
1526 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1527 uchar max_dvc_qng[ASC_MAX_TID + 1];
1528 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1529 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1530 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1532 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1535 uchar dos_int13_table[ASC_MAX_TID + 1];
1536 ASC_DCNT max_dma_count;
1537 ASC_SCSI_BIT_ID_TYPE no_scam;
1538 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1539 uchar max_sdtr_index;
1540 uchar host_init_sdtr_index;
1541 struct asc_board *drv_ptr;
1545 typedef struct asc_dvc_inq_info {
1546 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1549 typedef struct asc_cap_info {
1554 typedef struct asc_cap_info_array {
1555 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1556 } ASC_CAP_INFO_ARRAY;
1558 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1559 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1560 #define ASC_CNTL_INITIATOR (ushort)0x0001
1561 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1562 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1563 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1564 #define ASC_CNTL_NO_SCAM (ushort)0x0010
1565 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1566 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1567 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1568 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
1569 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1570 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1571 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1572 #define ASC_CNTL_BURST_MODE (ushort)0x2000
1573 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1574 #define ASC_EEP_DVC_CFG_BEG_VL 2
1575 #define ASC_EEP_MAX_DVC_ADDR_VL 15
1576 #define ASC_EEP_DVC_CFG_BEG 32
1577 #define ASC_EEP_MAX_DVC_ADDR 45
1578 #define ASC_EEP_DEFINED_WORDS 10
1579 #define ASC_EEP_MAX_ADDR 63
1580 #define ASC_EEP_RES_WORDS 0
1581 #define ASC_EEP_MAX_RETRY 20
1582 #define ASC_MAX_INIT_BUSY_RETRY 8
1583 #define ASC_EEP_ISA_PNP_WSIZE 16
1586 * These macros keep the chip SCSI id and ISA DMA speed
1587 * bitfields in board order. C bitfields aren't portable
1588 * between big and little-endian platforms so they are
1592 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1593 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1594 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1595 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1596 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1597 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1599 typedef struct asceep_config {
1606 uchar max_total_qng;
1609 uchar power_up_wait;
1611 uchar id_speed; /* low order 4 bits is chip scsi id */
1612 /* high order 4 bits is isa dma speed */
1613 uchar dos_int13_table[ASC_MAX_TID + 1];
1614 uchar adapter_info[6];
1619 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1620 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1621 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1623 #define ASC_EEP_CMD_READ 0x80
1624 #define ASC_EEP_CMD_WRITE 0x40
1625 #define ASC_EEP_CMD_WRITE_ABLE 0x30
1626 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1627 #define ASC_OVERRUN_BSIZE 0x00000048UL
1628 #define ASC_CTRL_BREAK_ONCE 0x0001
1629 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1630 #define ASCV_MSGOUT_BEG 0x0000
1631 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1632 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1633 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1634 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1635 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1636 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1637 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1638 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1639 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1640 #define ASCV_BREAK_ADDR (ushort)0x0028
1641 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1642 #define ASCV_BREAK_CONTROL (ushort)0x002C
1643 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1645 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1646 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1647 #define ASCV_MCODE_SIZE_W (ushort)0x0034
1648 #define ASCV_STOP_CODE_B (ushort)0x0036
1649 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1650 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1651 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1652 #define ASCV_HALTCODE_W (ushort)0x0040
1653 #define ASCV_CHKSUM_W (ushort)0x0042
1654 #define ASCV_MC_DATE_W (ushort)0x0044
1655 #define ASCV_MC_VER_W (ushort)0x0046
1656 #define ASCV_NEXTRDY_B (ushort)0x0048
1657 #define ASCV_DONENEXT_B (ushort)0x0049
1658 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1659 #define ASCV_SCSIBUSY_B (ushort)0x004B
1660 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1661 #define ASCV_CURCDB_B (ushort)0x004D
1662 #define ASCV_RCLUN_B (ushort)0x004E
1663 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
1664 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
1665 #define ASCV_DISC_ENABLE_B (ushort)0x0052
1666 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1667 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1668 #define ASCV_MCODE_CNTL_B (ushort)0x0056
1669 #define ASCV_NULL_TARGET_B (ushort)0x0057
1670 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1671 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1672 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1673 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1674 #define ASCV_HOST_FLAG_B (ushort)0x005D
1675 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1676 #define ASCV_VER_SERIAL_B (ushort)0x0065
1677 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1678 #define ASCV_WTM_FLAG_B (ushort)0x0068
1679 #define ASCV_RISC_FLAG_B (ushort)0x006A
1680 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1681 #define ASC_HOST_FLAG_IN_ISR 0x01
1682 #define ASC_HOST_FLAG_ACK_INT 0x02
1683 #define ASC_RISC_FLAG_GEN_INT 0x01
1684 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1685 #define IOP_CTRL (0x0F)
1686 #define IOP_STATUS (0x0E)
1687 #define IOP_INT_ACK IOP_STATUS
1688 #define IOP_REG_IFC (0x0D)
1689 #define IOP_SYN_OFFSET (0x0B)
1690 #define IOP_EXTRA_CONTROL (0x0D)
1691 #define IOP_REG_PC (0x0C)
1692 #define IOP_RAM_ADDR (0x0A)
1693 #define IOP_RAM_DATA (0x08)
1694 #define IOP_EEP_DATA (0x06)
1695 #define IOP_EEP_CMD (0x07)
1696 #define IOP_VERSION (0x03)
1697 #define IOP_CONFIG_HIGH (0x04)
1698 #define IOP_CONFIG_LOW (0x02)
1699 #define IOP_SIG_BYTE (0x01)
1700 #define IOP_SIG_WORD (0x00)
1701 #define IOP_REG_DC1 (0x0E)
1702 #define IOP_REG_DC0 (0x0C)
1703 #define IOP_REG_SB (0x0B)
1704 #define IOP_REG_DA1 (0x0A)
1705 #define IOP_REG_DA0 (0x08)
1706 #define IOP_REG_SC (0x09)
1707 #define IOP_DMA_SPEED (0x07)
1708 #define IOP_REG_FLAG (0x07)
1709 #define IOP_FIFO_H (0x06)
1710 #define IOP_FIFO_L (0x04)
1711 #define IOP_REG_ID (0x05)
1712 #define IOP_REG_QP (0x03)
1713 #define IOP_REG_IH (0x02)
1714 #define IOP_REG_IX (0x01)
1715 #define IOP_REG_AX (0x00)
1716 #define IFC_REG_LOCK (0x00)
1717 #define IFC_REG_UNLOCK (0x09)
1718 #define IFC_WR_EN_FILTER (0x10)
1719 #define IFC_RD_NO_EEPROM (0x10)
1720 #define IFC_SLEW_RATE (0x20)
1721 #define IFC_ACT_NEG (0x40)
1722 #define IFC_INP_FILTER (0x80)
1723 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1724 #define SC_SEL (uchar)(0x80)
1725 #define SC_BSY (uchar)(0x40)
1726 #define SC_ACK (uchar)(0x20)
1727 #define SC_REQ (uchar)(0x10)
1728 #define SC_ATN (uchar)(0x08)
1729 #define SC_IO (uchar)(0x04)
1730 #define SC_CD (uchar)(0x02)
1731 #define SC_MSG (uchar)(0x01)
1732 #define SEC_SCSI_CTL (uchar)(0x80)
1733 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
1734 #define SEC_SLEW_RATE (uchar)(0x20)
1735 #define SEC_ENABLE_FILTER (uchar)(0x10)
1736 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
1737 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
1738 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1739 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1740 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1741 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1742 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1743 #define ASC_MAX_QNO 0xF8
1744 #define ASC_DATA_SEC_BEG (ushort)0x0080
1745 #define ASC_DATA_SEC_END (ushort)0x0080
1746 #define ASC_CODE_SEC_BEG (ushort)0x0080
1747 #define ASC_CODE_SEC_END (ushort)0x0080
1748 #define ASC_QADR_BEG (0x4000)
1749 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1750 #define ASC_QADR_END (ushort)0x7FFF
1751 #define ASC_QLAST_ADR (ushort)0x7FC0
1752 #define ASC_QBLK_SIZE 0x40
1753 #define ASC_BIOS_DATA_QBEG 0xF8
1754 #define ASC_MIN_ACTIVE_QNO 0x01
1755 #define ASC_QLINK_END 0xFF
1756 #define ASC_EEPROM_WORDS 0x10
1757 #define ASC_MAX_MGS_LEN 0x10
1758 #define ASC_BIOS_ADDR_DEF 0xDC00
1759 #define ASC_BIOS_SIZE 0x3800
1760 #define ASC_BIOS_RAM_OFF 0x3800
1761 #define ASC_BIOS_RAM_SIZE 0x800
1762 #define ASC_BIOS_MIN_ADDR 0xC000
1763 #define ASC_BIOS_MAX_ADDR 0xEC00
1764 #define ASC_BIOS_BANK_SIZE 0x0400
1765 #define ASC_MCODE_START_ADDR 0x0080
1766 #define ASC_CFG0_HOST_INT_ON 0x0020
1767 #define ASC_CFG0_BIOS_ON 0x0040
1768 #define ASC_CFG0_VERA_BURST_ON 0x0080
1769 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1770 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1771 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1772 #define ASC_CFG_MSW_CLR_MASK 0x3080
1773 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
1774 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1775 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1776 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1777 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1778 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
1779 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
1780 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1781 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1782 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1783 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1784 #define CSW_HALTED (ASC_CS_TYPE)0x0010
1785 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1786 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1787 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1788 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1789 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1790 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1791 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
1792 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
1793 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1794 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1795 #define CC_CHIP_RESET (uchar)0x80
1796 #define CC_SCSI_RESET (uchar)0x40
1797 #define CC_HALT (uchar)0x20
1798 #define CC_SINGLE_STEP (uchar)0x10
1799 #define CC_DMA_ABLE (uchar)0x08
1800 #define CC_TEST (uchar)0x04
1801 #define CC_BANK_ONE (uchar)0x02
1802 #define CC_DIAG (uchar)0x01
1803 #define ASC_1000_ID0W 0x04C1
1804 #define ASC_1000_ID0W_FIX 0x00C1
1805 #define ASC_1000_ID1B 0x25
1806 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1807 #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1808 #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1809 #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1810 #define ASC_EISA_REV_IOP_MASK (0x0C83)
1811 #define ASC_EISA_PID_IOP_MASK (0x0C80)
1812 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1813 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1814 #define ASC_EISA_ID_740 0x01745004UL
1815 #define ASC_EISA_ID_750 0x01755004UL
1816 #define INS_HALTINT (ushort)0x6281
1817 #define INS_HALT (ushort)0x6280
1818 #define INS_SINT (ushort)0x6200
1819 #define INS_RFLAG_WTM (ushort)0x7380
1820 #define ASC_MC_SAVE_CODE_WSIZE 0x500
1821 #define ASC_MC_SAVE_DATA_WSIZE 0x40
1823 typedef struct asc_mc_saved {
1824 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1825 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1828 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1829 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1830 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1831 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1832 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1833 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1834 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1835 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1836 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1837 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1838 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1839 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1840 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1841 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1842 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1843 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1844 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1845 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1846 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1847 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1848 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1849 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1850 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1851 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1852 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1853 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1854 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1855 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1856 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1857 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1858 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1859 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1860 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1861 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1862 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1863 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1864 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1865 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1866 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1867 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1868 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1869 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1870 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1871 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1872 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1873 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1874 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1875 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1876 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1877 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1878 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1879 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1880 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1881 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1882 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1883 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1884 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1885 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1886 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1887 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1888 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1889 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1890 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1891 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1892 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1893 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1894 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1895 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1897 STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1898 STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1899 STATIC void AscWaitEEPRead(void);
1900 STATIC void AscWaitEEPWrite(void);
1901 STATIC ushort AscReadEEPWord(PortAddr, uchar);
1902 STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1903 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1904 STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1905 STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1906 STATIC int AscStartChip(PortAddr);
1907 STATIC int AscStopChip(PortAddr);
1908 STATIC void AscSetChipIH(PortAddr, ushort);
1909 STATIC int AscIsChipHalted(PortAddr);
1910 STATIC void AscAckInterrupt(PortAddr);
1911 STATIC void AscDisableInterrupt(PortAddr);
1912 STATIC void AscEnableInterrupt(PortAddr);
1913 STATIC void AscSetBank(PortAddr, uchar);
1914 STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1916 STATIC ushort AscGetIsaDmaChannel(PortAddr);
1917 STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
1918 STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1919 STATIC uchar AscGetIsaDmaSpeed(PortAddr);
1920 #endif /* CONFIG_ISA */
1921 STATIC uchar AscReadLramByte(PortAddr, ushort);
1922 STATIC ushort AscReadLramWord(PortAddr, ushort);
1923 #if CC_VERY_LONG_SG_LIST
1924 STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1925 #endif /* CC_VERY_LONG_SG_LIST */
1926 STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
1927 STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
1928 STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1929 STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1930 STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1931 STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1932 STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1933 STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1934 STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
1935 STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1936 STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1937 STATIC int AscTestExternalLram(ASC_DVC_VAR *);
1938 STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1939 STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1940 STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
1941 STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1942 STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
1943 STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1944 STATIC int AscHostReqRiscHalt(PortAddr);
1945 STATIC int AscStopQueueExe(PortAddr);
1946 STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
1948 uchar n_q_required);
1949 STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
1950 ASC_SCSI_Q *, uchar);
1951 STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
1952 ASC_SCSI_Q *, uchar);
1953 STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1954 STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1955 STATIC ushort AscInitLram(ASC_DVC_VAR *);
1956 STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
1957 STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1958 STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
1959 STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1960 ASC_QDONE_INFO *, ASC_DCNT);
1961 STATIC int AscIsrQDone(ASC_DVC_VAR *);
1962 STATIC int AscCompareString(uchar *, uchar *, int);
1964 STATIC ushort AscGetEisaChipCfg(PortAddr);
1965 STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
1966 STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
1967 STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
1968 STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1969 STATIC void AscSetISAPNPWaitForKey(void);
1970 #endif /* CONFIG_ISA */
1971 STATIC uchar AscGetChipScsiCtrl(PortAddr);
1972 STATIC uchar AscSetChipScsiID(PortAddr, uchar);
1973 STATIC uchar AscGetChipVersion(PortAddr, ushort);
1974 STATIC ushort AscGetChipBusType(PortAddr);
1975 STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1976 STATIC int AscFindSignature(PortAddr);
1977 STATIC void AscToggleIRQAct(PortAddr);
1978 STATIC uchar AscGetChipIRQ(PortAddr, ushort);
1979 STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1980 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1981 STATIC inline ulong DvcEnterCritical(void);
1982 STATIC inline void DvcLeaveCritical(ulong);
1984 STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
1985 STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
1987 #endif /* CONFIG_PCI */
1988 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1989 STATIC void DvcSleepMilliSecond(ASC_DCNT);
1990 STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
1991 STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
1992 STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
1993 STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
1994 STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
1995 STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
1996 STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
1997 ASC_SCSI_INQUIRY *);
1998 STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
1999 STATIC void AscInquiryHandling(ASC_DVC_VAR *,
2000 uchar, ASC_SCSI_INQUIRY *);
2001 STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
2002 STATIC int AscISR(ASC_DVC_VAR *);
2003 STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
2005 STATIC int AscSgListToQueue(int);
2007 STATIC void AscEnableIsaDma(uchar);
2008 #endif /* CONFIG_ISA */
2009 STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
2013 * --- Adv Library Constants and Macros
2016 #define ADV_LIB_VERSION_MAJOR 5
2017 #define ADV_LIB_VERSION_MINOR 14
2020 * Define Adv Library required special types.
2024 * Portable Data Types
2026 * Any instance where a 32-bit long or pointer type is assumed
2027 * for precision or HW defined structures, the following define
2028 * types must be used. In Linux the char, short, and int types
2029 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2030 * and long types are 64 bits on Alpha and UltraSPARC.
2032 #define ADV_PADDR __u32 /* Physical address data type. */
2033 #define ADV_VADDR __u32 /* Virtual address data type. */
2034 #define ADV_DCNT __u32 /* Unsigned Data count type. */
2035 #define ADV_SDCNT __s32 /* Signed Data count type. */
2038 * These macros are used to convert a virtual address to a
2039 * 32-bit value. This currently can be used on Linux Alpha
2040 * which uses 64-bit virtual address but a 32-bit bus address.
2041 * This is likely to break in the future, but doing this now
2042 * will give us time to change the HW and FW to handle 64-bit
2045 #define ADV_VADDR_TO_U32 virt_to_bus
2046 #define ADV_U32_TO_VADDR bus_to_virt
2048 #define AdvPortAddr void __iomem * /* Virtual memory address size */
2051 * Define Adv Library required memory access macros.
2053 #define ADV_MEM_READB(addr) readb(addr)
2054 #define ADV_MEM_READW(addr) readw(addr)
2055 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2056 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2057 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2059 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2062 * For wide boards a CDB length maximum of 16 bytes
2065 #define ADV_MAX_CDB_LEN 16
2068 * Define total number of simultaneous maximum element scatter-gather
2069 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2070 * maximum number of outstanding commands per wide host adapter. Each
2071 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2072 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2073 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2074 * structures or 255 scatter-gather elements.
2077 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2080 * Define Adv Library required maximum number of scatter-gather
2081 * elements per request.
2083 #define ADV_MAX_SG_LIST 255
2085 /* Number of SG blocks needed. */
2086 #define ADV_NUM_SG_BLOCK \
2087 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2089 /* Total contiguous memory needed for SG blocks. */
2090 #define ADV_SG_TOTAL_MEM_SIZE \
2091 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2093 #define ADV_PAGE_SIZE PAGE_SIZE
2095 #define ADV_NUM_PAGE_CROSSING \
2096 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2098 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
2099 #define ADV_EEP_DVC_CFG_END (0x15)
2100 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2101 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
2103 #define ADV_EEP_DELAY_MS 100
2105 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2106 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2108 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2109 * For later ICs Bit 13 controls whether the CIS (Card Information
2110 * Service Section) is loaded from EEPROM.
2112 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2113 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2117 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2118 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2119 * Function 0 will specify INT B.
2121 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2122 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2123 * Function 1 will specify INT A.
2125 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2127 typedef struct adveep_3550_config
2129 /* Word Offset, Description */
2131 ushort cfg_lsw; /* 00 power up initialization */
2132 /* bit 13 set - Term Polarity Control */
2133 /* bit 14 set - BIOS Enable */
2134 /* bit 15 set - Big Endian Mode */
2135 ushort cfg_msw; /* 01 unused */
2136 ushort disc_enable; /* 02 disconnect enable */
2137 ushort wdtr_able; /* 03 Wide DTR able */
2138 ushort sdtr_able; /* 04 Synchronous DTR able */
2139 ushort start_motor; /* 05 send start up motor */
2140 ushort tagqng_able; /* 06 tag queuing able */
2141 ushort bios_scan; /* 07 BIOS device control */
2142 ushort scam_tolerant; /* 08 no scam */
2144 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2145 uchar bios_boot_delay; /* power up wait */
2147 uchar scsi_reset_delay; /* 10 reset delay */
2148 uchar bios_id_lun; /* first boot device scsi id & lun */
2149 /* high nibble is lun */
2150 /* low nibble is scsi id */
2152 uchar termination; /* 11 0 - automatic */
2153 /* 1 - low off / high off */
2154 /* 2 - low off / high on */
2155 /* 3 - low on / high on */
2156 /* There is no low on / high off */
2158 uchar reserved1; /* reserved byte (not used) */
2160 ushort bios_ctrl; /* 12 BIOS control bits */
2161 /* bit 0 BIOS don't act as initiator. */
2162 /* bit 1 BIOS > 1 GB support */
2163 /* bit 2 BIOS > 2 Disk Support */
2164 /* bit 3 BIOS don't support removables */
2165 /* bit 4 BIOS support bootable CD */
2166 /* bit 5 BIOS scan enabled */
2167 /* bit 6 BIOS support multiple LUNs */
2168 /* bit 7 BIOS display of message */
2169 /* bit 8 SCAM disabled */
2170 /* bit 9 Reset SCSI bus during init. */
2172 /* bit 11 No verbose initialization. */
2173 /* bit 12 SCSI parity enabled */
2177 ushort ultra_able; /* 13 ULTRA speed able */
2178 ushort reserved2; /* 14 reserved */
2179 uchar max_host_qng; /* 15 maximum host queuing */
2180 uchar max_dvc_qng; /* maximum per device queuing */
2181 ushort dvc_cntl; /* 16 control bit for driver */
2182 ushort bug_fix; /* 17 control bit for bug fix */
2183 ushort serial_number_word1; /* 18 Board serial number word 1 */
2184 ushort serial_number_word2; /* 19 Board serial number word 2 */
2185 ushort serial_number_word3; /* 20 Board serial number word 3 */
2186 ushort check_sum; /* 21 EEP check sum */
2187 uchar oem_name[16]; /* 22 OEM name */
2188 ushort dvc_err_code; /* 30 last device driver error code */
2189 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2190 ushort adv_err_addr; /* 32 last uc error address */
2191 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2192 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2193 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2194 ushort num_of_err; /* 36 number of error */
2195 } ADVEEP_3550_CONFIG;
2197 typedef struct adveep_38C0800_config
2199 /* Word Offset, Description */
2201 ushort cfg_lsw; /* 00 power up initialization */
2202 /* bit 13 set - Load CIS */
2203 /* bit 14 set - BIOS Enable */
2204 /* bit 15 set - Big Endian Mode */
2205 ushort cfg_msw; /* 01 unused */
2206 ushort disc_enable; /* 02 disconnect enable */
2207 ushort wdtr_able; /* 03 Wide DTR able */
2208 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2209 ushort start_motor; /* 05 send start up motor */
2210 ushort tagqng_able; /* 06 tag queuing able */
2211 ushort bios_scan; /* 07 BIOS device control */
2212 ushort scam_tolerant; /* 08 no scam */
2214 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2215 uchar bios_boot_delay; /* power up wait */
2217 uchar scsi_reset_delay; /* 10 reset delay */
2218 uchar bios_id_lun; /* first boot device scsi id & lun */
2219 /* high nibble is lun */
2220 /* low nibble is scsi id */
2222 uchar termination_se; /* 11 0 - automatic */
2223 /* 1 - low off / high off */
2224 /* 2 - low off / high on */
2225 /* 3 - low on / high on */
2226 /* There is no low on / high off */
2228 uchar termination_lvd; /* 11 0 - automatic */
2229 /* 1 - low off / high off */
2230 /* 2 - low off / high on */
2231 /* 3 - low on / high on */
2232 /* There is no low on / high off */
2234 ushort bios_ctrl; /* 12 BIOS control bits */
2235 /* bit 0 BIOS don't act as initiator. */
2236 /* bit 1 BIOS > 1 GB support */
2237 /* bit 2 BIOS > 2 Disk Support */
2238 /* bit 3 BIOS don't support removables */
2239 /* bit 4 BIOS support bootable CD */
2240 /* bit 5 BIOS scan enabled */
2241 /* bit 6 BIOS support multiple LUNs */
2242 /* bit 7 BIOS display of message */
2243 /* bit 8 SCAM disabled */
2244 /* bit 9 Reset SCSI bus during init. */
2246 /* bit 11 No verbose initialization. */
2247 /* bit 12 SCSI parity enabled */
2251 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2252 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2253 uchar max_host_qng; /* 15 maximum host queueing */
2254 uchar max_dvc_qng; /* maximum per device queuing */
2255 ushort dvc_cntl; /* 16 control bit for driver */
2256 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2257 ushort serial_number_word1; /* 18 Board serial number word 1 */
2258 ushort serial_number_word2; /* 19 Board serial number word 2 */
2259 ushort serial_number_word3; /* 20 Board serial number word 3 */
2260 ushort check_sum; /* 21 EEP check sum */
2261 uchar oem_name[16]; /* 22 OEM name */
2262 ushort dvc_err_code; /* 30 last device driver error code */
2263 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2264 ushort adv_err_addr; /* 32 last uc error address */
2265 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2266 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2267 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2268 ushort reserved36; /* 36 reserved */
2269 ushort reserved37; /* 37 reserved */
2270 ushort reserved38; /* 38 reserved */
2271 ushort reserved39; /* 39 reserved */
2272 ushort reserved40; /* 40 reserved */
2273 ushort reserved41; /* 41 reserved */
2274 ushort reserved42; /* 42 reserved */
2275 ushort reserved43; /* 43 reserved */
2276 ushort reserved44; /* 44 reserved */
2277 ushort reserved45; /* 45 reserved */
2278 ushort reserved46; /* 46 reserved */
2279 ushort reserved47; /* 47 reserved */
2280 ushort reserved48; /* 48 reserved */
2281 ushort reserved49; /* 49 reserved */
2282 ushort reserved50; /* 50 reserved */
2283 ushort reserved51; /* 51 reserved */
2284 ushort reserved52; /* 52 reserved */
2285 ushort reserved53; /* 53 reserved */
2286 ushort reserved54; /* 54 reserved */
2287 ushort reserved55; /* 55 reserved */
2288 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2289 ushort cisprt_msw; /* 57 CIS PTR MSW */
2290 ushort subsysvid; /* 58 SubSystem Vendor ID */
2291 ushort subsysid; /* 59 SubSystem ID */
2292 ushort reserved60; /* 60 reserved */
2293 ushort reserved61; /* 61 reserved */
2294 ushort reserved62; /* 62 reserved */
2295 ushort reserved63; /* 63 reserved */
2296 } ADVEEP_38C0800_CONFIG;
2298 typedef struct adveep_38C1600_config
2300 /* Word Offset, Description */
2302 ushort cfg_lsw; /* 00 power up initialization */
2303 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2304 /* clear - Func. 0 INTA, Func. 1 INTB */
2305 /* bit 13 set - Load CIS */
2306 /* bit 14 set - BIOS Enable */
2307 /* bit 15 set - Big Endian Mode */
2308 ushort cfg_msw; /* 01 unused */
2309 ushort disc_enable; /* 02 disconnect enable */
2310 ushort wdtr_able; /* 03 Wide DTR able */
2311 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2312 ushort start_motor; /* 05 send start up motor */
2313 ushort tagqng_able; /* 06 tag queuing able */
2314 ushort bios_scan; /* 07 BIOS device control */
2315 ushort scam_tolerant; /* 08 no scam */
2317 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2318 uchar bios_boot_delay; /* power up wait */
2320 uchar scsi_reset_delay; /* 10 reset delay */
2321 uchar bios_id_lun; /* first boot device scsi id & lun */
2322 /* high nibble is lun */
2323 /* low nibble is scsi id */
2325 uchar termination_se; /* 11 0 - automatic */
2326 /* 1 - low off / high off */
2327 /* 2 - low off / high on */
2328 /* 3 - low on / high on */
2329 /* There is no low on / high off */
2331 uchar termination_lvd; /* 11 0 - automatic */
2332 /* 1 - low off / high off */
2333 /* 2 - low off / high on */
2334 /* 3 - low on / high on */
2335 /* There is no low on / high off */
2337 ushort bios_ctrl; /* 12 BIOS control bits */
2338 /* bit 0 BIOS don't act as initiator. */
2339 /* bit 1 BIOS > 1 GB support */
2340 /* bit 2 BIOS > 2 Disk Support */
2341 /* bit 3 BIOS don't support removables */
2342 /* bit 4 BIOS support bootable CD */
2343 /* bit 5 BIOS scan enabled */
2344 /* bit 6 BIOS support multiple LUNs */
2345 /* bit 7 BIOS display of message */
2346 /* bit 8 SCAM disabled */
2347 /* bit 9 Reset SCSI bus during init. */
2348 /* bit 10 Basic Integrity Checking disabled */
2349 /* bit 11 No verbose initialization. */
2350 /* bit 12 SCSI parity enabled */
2351 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2354 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2355 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2356 uchar max_host_qng; /* 15 maximum host queueing */
2357 uchar max_dvc_qng; /* maximum per device queuing */
2358 ushort dvc_cntl; /* 16 control bit for driver */
2359 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2360 ushort serial_number_word1; /* 18 Board serial number word 1 */
2361 ushort serial_number_word2; /* 19 Board serial number word 2 */
2362 ushort serial_number_word3; /* 20 Board serial number word 3 */
2363 ushort check_sum; /* 21 EEP check sum */
2364 uchar oem_name[16]; /* 22 OEM name */
2365 ushort dvc_err_code; /* 30 last device driver error code */
2366 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2367 ushort adv_err_addr; /* 32 last uc error address */
2368 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2369 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2370 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2371 ushort reserved36; /* 36 reserved */
2372 ushort reserved37; /* 37 reserved */
2373 ushort reserved38; /* 38 reserved */
2374 ushort reserved39; /* 39 reserved */
2375 ushort reserved40; /* 40 reserved */
2376 ushort reserved41; /* 41 reserved */
2377 ushort reserved42; /* 42 reserved */
2378 ushort reserved43; /* 43 reserved */
2379 ushort reserved44; /* 44 reserved */
2380 ushort reserved45; /* 45 reserved */
2381 ushort reserved46; /* 46 reserved */
2382 ushort reserved47; /* 47 reserved */
2383 ushort reserved48; /* 48 reserved */
2384 ushort reserved49; /* 49 reserved */
2385 ushort reserved50; /* 50 reserved */
2386 ushort reserved51; /* 51 reserved */
2387 ushort reserved52; /* 52 reserved */
2388 ushort reserved53; /* 53 reserved */
2389 ushort reserved54; /* 54 reserved */
2390 ushort reserved55; /* 55 reserved */
2391 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2392 ushort cisprt_msw; /* 57 CIS PTR MSW */
2393 ushort subsysvid; /* 58 SubSystem Vendor ID */
2394 ushort subsysid; /* 59 SubSystem ID */
2395 ushort reserved60; /* 60 reserved */
2396 ushort reserved61; /* 61 reserved */
2397 ushort reserved62; /* 62 reserved */
2398 ushort reserved63; /* 63 reserved */
2399 } ADVEEP_38C1600_CONFIG;
2404 #define ASC_EEP_CMD_DONE 0x0200
2405 #define ASC_EEP_CMD_DONE_ERR 0x0001
2408 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2411 #define BIOS_CTRL_BIOS 0x0001
2412 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
2413 #define BIOS_CTRL_GT_2_DISK 0x0004
2414 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2415 #define BIOS_CTRL_BOOTABLE_CD 0x0010
2416 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
2417 #define BIOS_CTRL_DISPLAY_MSG 0x0080
2418 #define BIOS_CTRL_NO_SCAM 0x0100
2419 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2420 #define BIOS_CTRL_INIT_VERBOSE 0x0800
2421 #define BIOS_CTRL_SCSI_PARITY 0x1000
2422 #define BIOS_CTRL_AIPP_DIS 0x2000
2424 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2425 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2427 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2428 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2431 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2432 * a special 16K Adv Library and Microcode version. After the issue is
2433 * resolved, should restore 32K support.
2435 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2437 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2438 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2439 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2442 * Byte I/O register address from base of 'iop_base'.
2444 #define IOPB_INTR_STATUS_REG 0x00
2445 #define IOPB_CHIP_ID_1 0x01
2446 #define IOPB_INTR_ENABLES 0x02
2447 #define IOPB_CHIP_TYPE_REV 0x03
2448 #define IOPB_RES_ADDR_4 0x04
2449 #define IOPB_RES_ADDR_5 0x05
2450 #define IOPB_RAM_DATA 0x06
2451 #define IOPB_RES_ADDR_7 0x07
2452 #define IOPB_FLAG_REG 0x08
2453 #define IOPB_RES_ADDR_9 0x09
2454 #define IOPB_RISC_CSR 0x0A
2455 #define IOPB_RES_ADDR_B 0x0B
2456 #define IOPB_RES_ADDR_C 0x0C
2457 #define IOPB_RES_ADDR_D 0x0D
2458 #define IOPB_SOFT_OVER_WR 0x0E
2459 #define IOPB_RES_ADDR_F 0x0F
2460 #define IOPB_MEM_CFG 0x10
2461 #define IOPB_RES_ADDR_11 0x11
2462 #define IOPB_GPIO_DATA 0x12
2463 #define IOPB_RES_ADDR_13 0x13
2464 #define IOPB_FLASH_PAGE 0x14
2465 #define IOPB_RES_ADDR_15 0x15
2466 #define IOPB_GPIO_CNTL 0x16
2467 #define IOPB_RES_ADDR_17 0x17
2468 #define IOPB_FLASH_DATA 0x18
2469 #define IOPB_RES_ADDR_19 0x19
2470 #define IOPB_RES_ADDR_1A 0x1A
2471 #define IOPB_RES_ADDR_1B 0x1B
2472 #define IOPB_RES_ADDR_1C 0x1C
2473 #define IOPB_RES_ADDR_1D 0x1D
2474 #define IOPB_RES_ADDR_1E 0x1E
2475 #define IOPB_RES_ADDR_1F 0x1F
2476 #define IOPB_DMA_CFG0 0x20
2477 #define IOPB_DMA_CFG1 0x21
2478 #define IOPB_TICKLE 0x22
2479 #define IOPB_DMA_REG_WR 0x23
2480 #define IOPB_SDMA_STATUS 0x24
2481 #define IOPB_SCSI_BYTE_CNT 0x25
2482 #define IOPB_HOST_BYTE_CNT 0x26
2483 #define IOPB_BYTE_LEFT_TO_XFER 0x27
2484 #define IOPB_BYTE_TO_XFER_0 0x28
2485 #define IOPB_BYTE_TO_XFER_1 0x29
2486 #define IOPB_BYTE_TO_XFER_2 0x2A
2487 #define IOPB_BYTE_TO_XFER_3 0x2B
2488 #define IOPB_ACC_GRP 0x2C
2489 #define IOPB_RES_ADDR_2D 0x2D
2490 #define IOPB_DEV_ID 0x2E
2491 #define IOPB_RES_ADDR_2F 0x2F
2492 #define IOPB_SCSI_DATA 0x30
2493 #define IOPB_RES_ADDR_31 0x31
2494 #define IOPB_RES_ADDR_32 0x32
2495 #define IOPB_SCSI_DATA_HSHK 0x33
2496 #define IOPB_SCSI_CTRL 0x34
2497 #define IOPB_RES_ADDR_35 0x35
2498 #define IOPB_RES_ADDR_36 0x36
2499 #define IOPB_RES_ADDR_37 0x37
2500 #define IOPB_RAM_BIST 0x38
2501 #define IOPB_PLL_TEST 0x39
2502 #define IOPB_PCI_INT_CFG 0x3A
2503 #define IOPB_RES_ADDR_3B 0x3B
2504 #define IOPB_RFIFO_CNT 0x3C
2505 #define IOPB_RES_ADDR_3D 0x3D
2506 #define IOPB_RES_ADDR_3E 0x3E
2507 #define IOPB_RES_ADDR_3F 0x3F
2510 * Word I/O register address from base of 'iop_base'.
2512 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
2513 #define IOPW_CTRL_REG 0x02 /* CC */
2514 #define IOPW_RAM_ADDR 0x04 /* LA */
2515 #define IOPW_RAM_DATA 0x06 /* LD */
2516 #define IOPW_RES_ADDR_08 0x08
2517 #define IOPW_RISC_CSR 0x0A /* CSR */
2518 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2519 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2520 #define IOPW_RES_ADDR_10 0x10
2521 #define IOPW_SEL_MASK 0x12 /* SM */
2522 #define IOPW_RES_ADDR_14 0x14
2523 #define IOPW_FLASH_ADDR 0x16 /* FA */
2524 #define IOPW_RES_ADDR_18 0x18
2525 #define IOPW_EE_CMD 0x1A /* EC */
2526 #define IOPW_EE_DATA 0x1C /* ED */
2527 #define IOPW_SFIFO_CNT 0x1E /* SFC */
2528 #define IOPW_RES_ADDR_20 0x20
2529 #define IOPW_Q_BASE 0x22 /* QB */
2530 #define IOPW_QP 0x24 /* QP */
2531 #define IOPW_IX 0x26 /* IX */
2532 #define IOPW_SP 0x28 /* SP */
2533 #define IOPW_PC 0x2A /* PC */
2534 #define IOPW_RES_ADDR_2C 0x2C
2535 #define IOPW_RES_ADDR_2E 0x2E
2536 #define IOPW_SCSI_DATA 0x30 /* SD */
2537 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2538 #define IOPW_SCSI_CTRL 0x34 /* SC */
2539 #define IOPW_HSHK_CFG 0x36 /* HCFG */
2540 #define IOPW_SXFR_STATUS 0x36 /* SXS */
2541 #define IOPW_SXFR_CNTL 0x38 /* SXL */
2542 #define IOPW_SXFR_CNTH 0x3A /* SXH */
2543 #define IOPW_RES_ADDR_3C 0x3C
2544 #define IOPW_RFIFO_DATA 0x3E /* RFD */
2547 * Doubleword I/O register address from base of 'iop_base'.
2549 #define IOPDW_RES_ADDR_0 0x00
2550 #define IOPDW_RAM_DATA 0x04
2551 #define IOPDW_RES_ADDR_8 0x08
2552 #define IOPDW_RES_ADDR_C 0x0C
2553 #define IOPDW_RES_ADDR_10 0x10
2554 #define IOPDW_COMMA 0x14
2555 #define IOPDW_COMMB 0x18
2556 #define IOPDW_RES_ADDR_1C 0x1C
2557 #define IOPDW_SDMA_ADDR0 0x20
2558 #define IOPDW_SDMA_ADDR1 0x24
2559 #define IOPDW_SDMA_COUNT 0x28
2560 #define IOPDW_SDMA_ERROR 0x2C
2561 #define IOPDW_RDMA_ADDR0 0x30
2562 #define IOPDW_RDMA_ADDR1 0x34
2563 #define IOPDW_RDMA_COUNT 0x38
2564 #define IOPDW_RDMA_ERROR 0x3C
2566 #define ADV_CHIP_ID_BYTE 0x25
2567 #define ADV_CHIP_ID_WORD 0x04C1
2569 #define ADV_SC_SCSI_BUS_RESET 0x2000
2571 #define ADV_INTR_ENABLE_HOST_INTR 0x01
2572 #define ADV_INTR_ENABLE_SEL_INTR 0x02
2573 #define ADV_INTR_ENABLE_DPR_INTR 0x04
2574 #define ADV_INTR_ENABLE_RTA_INTR 0x08
2575 #define ADV_INTR_ENABLE_RMA_INTR 0x10
2576 #define ADV_INTR_ENABLE_RST_INTR 0x20
2577 #define ADV_INTR_ENABLE_DPE_INTR 0x40
2578 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2580 #define ADV_INTR_STATUS_INTRA 0x01
2581 #define ADV_INTR_STATUS_INTRB 0x02
2582 #define ADV_INTR_STATUS_INTRC 0x04
2584 #define ADV_RISC_CSR_STOP (0x0000)
2585 #define ADV_RISC_TEST_COND (0x2000)
2586 #define ADV_RISC_CSR_RUN (0x4000)
2587 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2589 #define ADV_CTRL_REG_HOST_INTR 0x0100
2590 #define ADV_CTRL_REG_SEL_INTR 0x0200
2591 #define ADV_CTRL_REG_DPR_INTR 0x0400
2592 #define ADV_CTRL_REG_RTA_INTR 0x0800
2593 #define ADV_CTRL_REG_RMA_INTR 0x1000
2594 #define ADV_CTRL_REG_RES_BIT14 0x2000
2595 #define ADV_CTRL_REG_DPE_INTR 0x4000
2596 #define ADV_CTRL_REG_POWER_DONE 0x8000
2597 #define ADV_CTRL_REG_ANY_INTR 0xFF00
2599 #define ADV_CTRL_REG_CMD_RESET 0x00C6
2600 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2601 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2602 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2603 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2605 #define ADV_TICKLE_NOP 0x00
2606 #define ADV_TICKLE_A 0x01
2607 #define ADV_TICKLE_B 0x02
2608 #define ADV_TICKLE_C 0x03
2610 #define ADV_SCSI_CTRL_RSTOUT 0x2000
2612 #define AdvIsIntPending(port) \
2613 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2616 * SCSI_CFG0 Register bit definitions
2618 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2619 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2620 #define EVEN_PARITY 0x1000 /* Select Even Parity */
2621 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2622 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2623 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2624 #define SCAM_EN 0x0080 /* Enable SCAM selection */
2625 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2626 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2627 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2628 #define OUR_ID 0x000F /* SCSI ID */
2631 * SCSI_CFG1 Register bit definitions
2633 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2634 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2635 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2636 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
2637 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2638 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2639 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2640 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2641 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2642 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2643 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2644 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2645 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2646 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2647 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2650 * Addendum for ASC-38C0800 Chip
2652 * The ASC-38C1600 Chip uses the same definitions except that the
2653 * bus mode override bits [12:10] have been moved to byte register
2654 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2655 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2656 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2657 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2658 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2660 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2661 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2662 #define HVD 0x1000 /* HVD Device Detect */
2663 #define LVD 0x0800 /* LVD Device Detect */
2664 #define SE 0x0400 /* SE Device Detect */
2665 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
2666 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2667 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2668 #define TERM_SE 0x0030 /* SE Termination Bits */
2669 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2670 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2671 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2672 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2673 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2674 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2675 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2676 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2679 #define CABLE_ILLEGAL_A 0x7
2680 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2682 #define CABLE_ILLEGAL_B 0xB
2683 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2686 * MEM_CFG Register bit definitions
2688 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2689 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2690 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2691 #define RAM_SZ_2KB 0x00 /* 2 KB */
2692 #define RAM_SZ_4KB 0x04 /* 4 KB */
2693 #define RAM_SZ_8KB 0x08 /* 8 KB */
2694 #define RAM_SZ_16KB 0x0C /* 16 KB */
2695 #define RAM_SZ_32KB 0x10 /* 32 KB */
2696 #define RAM_SZ_64KB 0x14 /* 64 KB */
2699 * DMA_CFG0 Register bit definitions
2701 * This register is only accessible to the host.
2703 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2704 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2705 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
2706 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
2707 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
2708 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
2709 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2710 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
2711 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
2712 #define START_CTL 0x0C /* DMA start conditions */
2713 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
2714 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2715 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2716 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2717 #define READ_CMD 0x03 /* Memory Read Method */
2718 #define READ_CMD_MR 0x00 /* Memory Read */
2719 #define READ_CMD_MRL 0x02 /* Memory Read Long */
2720 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2723 * ASC-38C0800 RAM BIST Register bit definitions
2725 #define RAM_TEST_MODE 0x80
2726 #define PRE_TEST_MODE 0x40
2727 #define NORMAL_MODE 0x00
2728 #define RAM_TEST_DONE 0x10
2729 #define RAM_TEST_STATUS 0x0F
2730 #define RAM_TEST_HOST_ERROR 0x08
2731 #define RAM_TEST_INTRAM_ERROR 0x04
2732 #define RAM_TEST_RISC_ERROR 0x02
2733 #define RAM_TEST_SCSI_ERROR 0x01
2734 #define RAM_TEST_SUCCESS 0x00
2735 #define PRE_TEST_VALUE 0x05
2736 #define NORMAL_VALUE 0x00
2739 * ASC38C1600 Definitions
2741 * IOPB_PCI_INT_CFG Bit Field Definitions
2744 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2747 * Bit 1 can be set to change the interrupt for the Function to operate in
2748 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2749 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2750 * mode, otherwise the operating mode is undefined.
2752 #define TOTEMPOLE 0x02
2755 * Bit 0 can be used to change the Int Pin for the Function. The value is
2756 * 0 by default for both Functions with Function 0 using INT A and Function
2757 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2760 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2761 * value specified in the PCI Configuration Space.
2768 * Adv Library Status Definitions
2772 #define ADV_NOERROR 1
2773 #define ADV_SUCCESS 1
2775 #define ADV_ERROR (-1)
2779 * ADV_DVC_VAR 'warn_code' values
2781 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2782 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2783 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2784 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2785 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2787 #define ADV_MAX_TID 15 /* max. target identifier */
2788 #define ADV_MAX_LUN 7 /* max. logical unit number */
2791 * Error code values are set in ADV_DVC_VAR 'err_code'.
2793 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2794 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2795 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2796 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2797 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2798 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2799 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2800 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2801 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2802 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2803 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2804 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2805 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2806 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2809 * Fixed locations of microcode operating variables.
2811 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2812 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2813 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2814 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2815 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2816 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2817 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2818 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2819 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2820 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2821 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2822 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2823 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2824 #define ASC_MC_CHIP_TYPE 0x009A
2825 #define ASC_MC_INTRB_CODE 0x009B
2826 #define ASC_MC_WDTR_ABLE 0x009C
2827 #define ASC_MC_SDTR_ABLE 0x009E
2828 #define ASC_MC_TAGQNG_ABLE 0x00A0
2829 #define ASC_MC_DISC_ENABLE 0x00A2
2830 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
2831 #define ASC_MC_IDLE_CMD 0x00A6
2832 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2833 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2834 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2835 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2836 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2837 #define ASC_MC_SDTR_DONE 0x00B6
2838 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2839 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2840 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2841 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2842 #define ASC_MC_WDTR_DONE 0x0124
2843 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2844 #define ASC_MC_ICQ 0x0160
2845 #define ASC_MC_IRQ 0x0164
2846 #define ASC_MC_PPR_ABLE 0x017A
2849 * BIOS LRAM variable absolute offsets.
2851 #define BIOS_CODESEG 0x54
2852 #define BIOS_CODELEN 0x56
2853 #define BIOS_SIGNATURE 0x58
2854 #define BIOS_VERSION 0x5A
2857 * Microcode Control Flags
2859 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2860 * and handled by the microcode.
2862 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2863 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2866 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2868 #define HSHK_CFG_WIDE_XFR 0x8000
2869 #define HSHK_CFG_RATE 0x0F00
2870 #define HSHK_CFG_OFFSET 0x001F
2872 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2873 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2874 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2875 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2877 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2878 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2879 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2880 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2881 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2883 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2884 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2885 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2886 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2887 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2889 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2890 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2892 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2893 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2896 * All fields here are accessed by the board microcode and need to be
2899 typedef struct adv_carr_t
2901 ADV_VADDR carr_va; /* Carrier Virtual Address */
2902 ADV_PADDR carr_pa; /* Carrier Physical Address */
2903 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2905 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2907 * next_vpa [3:1] Reserved Bits
2908 * next_vpa [0] Done Flag set in Response Queue.
2914 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2916 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2918 #define ASC_RQ_DONE 0x00000001
2919 #define ASC_RQ_GOOD 0x00000002
2920 #define ASC_CQ_STOPPER 0x00000000
2922 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2924 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2925 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2926 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2928 #define ADV_CARRIER_BUFSIZE \
2929 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2932 * ASC_SCSI_REQ_Q 'a_flag' definitions
2934 * The Adv Library should limit use to the lower nibble (4 bits) of
2935 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2937 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2938 #define ADV_SCSIQ_DONE 0x02 /* request done */
2939 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2941 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2942 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2943 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2946 * Adapter temporary configuration structure
2948 * This structure can be discarded after initialization. Don't add
2949 * fields here needed after initialization.
2951 * Field naming convention:
2953 * *_enable indicates the field enables or disables a feature. The
2954 * value of the field is never reset.
2956 typedef struct adv_dvc_cfg {
2957 ushort disc_enable; /* enable disconnection */
2958 uchar chip_version; /* chip version */
2959 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2960 ushort lib_version; /* Adv Library version number */
2961 ushort control_flag; /* Microcode Control Flag */
2962 ushort mcode_date; /* Microcode date */
2963 ushort mcode_version; /* Microcode version */
2964 ushort pci_slot_info; /* high byte device/function number */
2965 /* bits 7-3 device num., bits 2-0 function num. */
2966 /* low byte bus num. */
2967 ushort serial1; /* EEPROM serial number word 1 */
2968 ushort serial2; /* EEPROM serial number word 2 */
2969 ushort serial3; /* EEPROM serial number word 3 */
2970 struct device *dev; /* pointer to the pci dev structure for this board */
2974 struct adv_scsi_req_q;
2976 typedef void (* ADV_ISR_CALLBACK)
2977 (struct adv_dvc_var *, struct adv_scsi_req_q *);
2979 typedef void (* ADV_ASYNC_CALLBACK)
2980 (struct adv_dvc_var *, uchar);
2983 * Adapter operation variable structure.
2985 * One structure is required per host adapter.
2987 * Field naming convention:
2989 * *_able indicates both whether a feature should be enabled or disabled
2990 * and whether a device isi capable of the feature. At initialization
2991 * this field may be set, but later if a device is found to be incapable
2992 * of the feature, the field is cleared.
2994 typedef struct adv_dvc_var {
2995 AdvPortAddr iop_base; /* I/O port address */
2996 ushort err_code; /* fatal error code */
2997 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
2998 ADV_ISR_CALLBACK isr_callback;
2999 ADV_ASYNC_CALLBACK async_callback;
3000 ushort wdtr_able; /* try WDTR for a device */
3001 ushort sdtr_able; /* try SDTR for a device */
3002 ushort ultra_able; /* try SDTR Ultra speed for a device */
3003 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
3004 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
3005 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
3006 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
3007 ushort tagqng_able; /* try tagged queuing with a device */
3008 ushort ppr_able; /* PPR message capable per TID bitmask. */
3009 uchar max_dvc_qng; /* maximum number of tagged commands per device */
3010 ushort start_motor; /* start motor command allowed */
3011 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
3012 uchar chip_no; /* should be assigned by caller */
3013 uchar max_host_qng; /* maximum number of Q'ed command allowed */
3014 uchar irq_no; /* IRQ number */
3015 ushort no_scam; /* scam_tolerant of EEPROM */
3016 struct asc_board *drv_ptr; /* driver pointer to private structure */
3017 uchar chip_scsi_id; /* chip SCSI target ID */
3019 uchar bist_err_code;
3020 ADV_CARR_T *carrier_buf;
3021 ADV_CARR_T *carr_freelist; /* Carrier free list. */
3022 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
3023 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
3024 ushort carr_pending_cnt; /* Count of pending carriers. */
3026 * Note: The following fields will not be used after initialization. The
3027 * driver may discard the buffer after initialization is done.
3029 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3032 #define NO_OF_SG_PER_BLOCK 15
3034 typedef struct asc_sg_block {
3038 uchar sg_cnt; /* Valid entries in block. */
3039 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3041 ADV_PADDR sg_addr; /* SG element address. */
3042 ADV_DCNT sg_count; /* SG element count. */
3043 } sg_list[NO_OF_SG_PER_BLOCK];
3047 * ADV_SCSI_REQ_Q - microcode request structure
3049 * All fields in this structure up to byte 60 are used by the microcode.
3050 * The microcode makes assumptions about the size and ordering of fields
3051 * in this structure. Do not change the structure definition here without
3052 * coordinating the change with the microcode.
3054 * All fields accessed by microcode must be maintained in little_endian
3057 typedef struct adv_scsi_req_q {
3058 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3060 uchar target_id; /* Device target identifier. */
3061 uchar target_lun; /* Device target logical unit number. */
3062 ADV_PADDR data_addr; /* Data buffer physical address. */
3063 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3064 ADV_PADDR sense_addr;
3068 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3070 uchar done_status; /* Completion status. */
3071 uchar scsi_status; /* SCSI status byte. */
3072 uchar host_status; /* Ucode host status. */
3073 uchar sg_working_ix;
3074 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3075 ADV_PADDR sg_real_addr; /* SG list physical address. */
3076 ADV_PADDR scsiq_rptr;
3077 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3078 ADV_VADDR scsiq_ptr;
3081 * End of microcode structure - 60 bytes. The rest of the structure
3082 * is used by the Adv Library and ignored by the microcode.
3085 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3086 char *vdata_addr; /* Data buffer virtual address. */
3088 uchar pad[2]; /* Pad out to a word boundary. */
3092 * Microcode idle loop commands
3094 #define IDLE_CMD_COMPLETED 0
3095 #define IDLE_CMD_STOP_CHIP 0x0001
3096 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3097 #define IDLE_CMD_SEND_INT 0x0004
3098 #define IDLE_CMD_ABORT 0x0008
3099 #define IDLE_CMD_DEVICE_RESET 0x0010
3100 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3101 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3102 #define IDLE_CMD_SCSIREQ 0x0080
3104 #define IDLE_CMD_STATUS_SUCCESS 0x0001
3105 #define IDLE_CMD_STATUS_FAILURE 0x0002
3108 * AdvSendIdleCmd() flag definitions.
3110 #define ADV_NOWAIT 0x01
3113 * Wait loop time out values.
3115 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3116 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3117 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3118 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3119 #define SCSI_MAX_RETRY 10 /* retry count */
3121 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3122 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3123 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3124 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3127 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3130 * Device drivers must define the following functions.
3132 STATIC inline ulong DvcEnterCritical(void);
3133 STATIC inline void DvcLeaveCritical(ulong);
3134 STATIC void DvcSleepMilliSecond(ADV_DCNT);
3135 STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3136 STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3137 STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3138 uchar *, ASC_SDCNT *, int);
3139 STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3142 * Adv Library functions available to drivers.
3144 STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3145 STATIC int AdvISR(ADV_DVC_VAR *);
3146 STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
3147 STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3148 STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3149 STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3150 STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
3151 STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3154 * Internal Adv Library functions.
3156 STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3157 STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3158 STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3159 STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3160 STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3161 STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3162 STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3163 STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3164 STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3165 STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3166 STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3167 STATIC void AdvWaitEEPCmd(AdvPortAddr);
3168 STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
3171 * PCI Bus Definitions
3173 #define AscPCICmdRegBits_BusMastering 0x0007
3174 #define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3176 /* Read byte from a register. */
3177 #define AdvReadByteRegister(iop_base, reg_off) \
3178 (ADV_MEM_READB((iop_base) + (reg_off)))
3180 /* Write byte to a register. */
3181 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
3182 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3184 /* Read word (2 bytes) from a register. */
3185 #define AdvReadWordRegister(iop_base, reg_off) \
3186 (ADV_MEM_READW((iop_base) + (reg_off)))
3188 /* Write word (2 bytes) to a register. */
3189 #define AdvWriteWordRegister(iop_base, reg_off, word) \
3190 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3192 /* Write dword (4 bytes) to a register. */
3193 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3194 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3196 /* Read byte from LRAM. */
3197 #define AdvReadByteLram(iop_base, addr, byte) \
3199 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3200 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3203 /* Write byte to LRAM. */
3204 #define AdvWriteByteLram(iop_base, addr, byte) \
3205 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3206 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3208 /* Read word (2 bytes) from LRAM. */
3209 #define AdvReadWordLram(iop_base, addr, word) \
3211 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3212 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3215 /* Write word (2 bytes) to LRAM. */
3216 #define AdvWriteWordLram(iop_base, addr, word) \
3217 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3218 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3220 /* Write little-endian double word (4 bytes) to LRAM */
3221 /* Because of unspecified C language ordering don't use auto-increment. */
3222 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3223 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3224 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3225 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3226 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3227 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3228 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3230 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
3231 #define AdvReadWordAutoIncLram(iop_base) \
3232 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3234 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
3235 #define AdvWriteWordAutoIncLram(iop_base, word) \
3236 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3240 * Define macro to check for Condor signature.
3242 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3243 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3245 #define AdvFindSignature(iop_base) \
3246 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3247 ADV_CHIP_ID_BYTE) && \
3248 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3249 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3252 * Define macro to Return the version number of the chip at 'iop_base'.
3254 * The second parameter 'bus_type' is currently unused.
3256 #define AdvGetChipVersion(iop_base, bus_type) \
3257 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3260 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3261 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3263 * If the request has not yet been sent to the device it will simply be
3264 * aborted from RISC memory. If the request is disconnected it will be
3265 * aborted on reselection by sending an Abort Message to the target ID.
3268 * ADV_TRUE(1) - Queue was successfully aborted.
3269 * ADV_FALSE(0) - Queue was not found on the active queue list.
3271 #define AdvAbortQueue(asc_dvc, scsiq) \
3272 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3276 * Send a Bus Device Reset Message to the specified target ID.
3278 * All outstanding commands will be purged if sending the
3279 * Bus Device Reset Message is successful.
3282 * ADV_TRUE(1) - All requests on the target are purged.
3283 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3286 #define AdvResetDevice(asc_dvc, target_id) \
3287 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3288 (ADV_DCNT) (target_id))
3291 * SCSI Wide Type definition.
3293 #define ADV_SCSI_BIT_ID_TYPE ushort
3296 * AdvInitScsiTarget() 'cntl_flag' options.
3298 #define ADV_SCAN_LUN 0x01
3299 #define ADV_CAPINFO_NOLUN 0x02
3302 * Convert target id to target id bit mask.
3304 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3307 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3310 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
3311 #define QD_NO_ERROR 0x01
3312 #define QD_ABORTED_BY_HOST 0x02
3313 #define QD_WITH_ERROR 0x04
3315 #define QHSTA_NO_ERROR 0x00
3316 #define QHSTA_M_SEL_TIMEOUT 0x11
3317 #define QHSTA_M_DATA_OVER_RUN 0x12
3318 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3319 #define QHSTA_M_QUEUE_ABORTED 0x15
3320 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3321 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3322 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3323 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3324 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3325 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3326 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3327 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3328 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3329 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3330 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3331 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3332 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3333 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3334 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3335 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3336 #define QHSTA_M_WTM_TIMEOUT 0x41
3337 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3338 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3339 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3340 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3341 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3342 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3346 * Default EEPROM Configuration structure defined in a_init.c.
3348 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3349 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3350 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3353 * DvcGetPhyAddr() flag arguments
3355 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3356 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3357 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3358 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3359 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3360 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3362 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
3363 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3364 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3365 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3368 * Total contiguous memory needed for driver SG blocks.
3370 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3371 * number of scatter-gather elements the driver supports in a
3375 #define ADV_SG_LIST_MAX_BYTE_SIZE \
3376 (sizeof(ADV_SG_BLOCK) * \
3377 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3380 * Inquiry data structure and bitfield macros
3382 * Using bitfields to access the subchar data isn't portable across
3383 * endianness, so instead mask and shift. Only quantities of more
3384 * than 1 bit are shifted, since the others are just tested for true
3388 #define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3389 #define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3390 #define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3391 #define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3392 #define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3393 #define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3394 #define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3395 #define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3396 #define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3397 #define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3398 #define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3399 #define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3400 #define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3401 #define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3402 #define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3403 #define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3404 #define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3405 #define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3406 #define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3407 #define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3410 uchar periph; /* peripheral device type [0:4] */
3411 /* peripheral qualifier [5:7] */
3412 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3413 /* RMB - removable medium bit [7] */
3414 uchar ver; /* ANSI approved version [0:2] */
3415 /* ECMA version [3:5] */
3416 /* ISO version [6:7] */
3417 uchar byte3; /* response data format [0:3] */
3422 /* reserved [4:5] */
3423 /* terminate I/O process bit (see 5.6.22) [6] */
3424 /* asynch. event notification (processor) [7] */
3425 uchar add_len; /* additional length */
3426 uchar res1; /* reserved */
3427 uchar res2; /* reserved */
3428 uchar flags; /* soft reset implemented [0] */
3429 /* command queuing [1] */
3431 /* linked command for this logical unit [3] */
3432 /* synchronous data transfer [4] */
3433 /* wide bus 16 bit data transfer [5] */
3434 /* wide bus 32 bit data transfer [6] */
3435 /* relative addressing mode [7] */
3436 uchar vendor_id[8]; /* vendor identification */
3437 uchar product_id[16]; /* product identification */
3438 uchar product_rev_level[4]; /* product revision level */
3439 uchar vendor_specific[20]; /* vendor specific */
3440 uchar info; /* information unit supported [0] */
3441 /* quick arbitrate supported [1] */
3442 /* clocking field [2:3] */
3443 /* reserved [4:7] */
3444 uchar res3; /* reserved */
3445 } ADV_SCSI_INQUIRY; /* 58 bytes */
3449 * --- Driver Constants and Macros
3452 #define ASC_NUM_BOARD_SUPPORTED 16
3453 #define ASC_NUM_IOPORT_PROBE 4
3454 #define ASC_NUM_BUS 4
3456 /* Reference Scsi_Host hostdata */
3457 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3459 /* asc_board_t flags */
3460 #define ASC_HOST_IN_RESET 0x01
3461 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3462 #define ASC_SELECT_QUEUE_DEPTHS 0x08
3464 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3465 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3467 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3469 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
3471 #ifdef CONFIG_PROC_FS
3472 /* /proc/scsi/advansys/[0...] related definitions */
3473 #define ASC_PRTBUF_SIZE 2048
3474 #define ASC_PRTLINE_SIZE 160
3476 #define ASC_PRT_NEXT() \
3480 if (leftlen == 0) { \
3485 #endif /* CONFIG_PROC_FS */
3487 /* Asc Library return codes */
3490 #define ASC_NOERROR 1
3492 #define ASC_ERROR (-1)
3494 /* struct scsi_cmnd function return codes */
3495 #define STATUS_BYTE(byte) (byte)
3496 #define MSG_BYTE(byte) ((byte) << 8)
3497 #define HOST_BYTE(byte) ((byte) << 16)
3498 #define DRIVER_BYTE(byte) ((byte) << 24)
3501 * The following definitions and macros are OS independent interfaces to
3502 * the queue functions:
3503 * REQ - SCSI request structure
3504 * REQP - pointer to SCSI request structure
3505 * REQPTID(reqp) - reqp's target id
3506 * REQPNEXT(reqp) - reqp's next pointer
3507 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3508 * REQPTIME(reqp) - reqp's time stamp value
3509 * REQTIMESTAMP() - system time stamp value
3511 typedef struct scsi_cmnd REQ, *REQP;
3512 #define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3513 #define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3514 #define REQPTID(reqp) ((reqp)->device->id)
3515 #define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3516 #define REQTIMESTAMP() (jiffies)
3518 #define REQTIMESTAT(function, ascq, reqp, tid) \
3521 * If the request time stamp is less than the system time stamp, then \
3522 * maybe the system time stamp wrapped. Set the request time to zero.\
3524 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3525 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3527 /* Indicate an error occurred with the assertion. */ \
3528 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3529 REQPTIME(reqp) = 0; \
3531 /* Handle first minimum time case without external initialization. */ \
3532 if (((ascq)->q_tot_cnt[tid] == 1) || \
3533 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3534 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3535 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3536 (function), (tid), (ascq)->q_min_tim[tid]); \
3538 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3539 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3540 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3541 (function), tid, (ascq)->q_max_tim[tid]); \
3543 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3544 /* Reset the time stamp field. */ \
3545 REQPTIME(reqp) = 0; \
3548 /* asc_enqueue() flags */
3552 /* asc_dequeue_list() argument */
3553 #define ASC_TID_ALL (-1)
3555 /* Return non-zero, if the queue is empty. */
3556 #define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3558 #define PCI_MAX_SLOT 0x1F
3559 #define PCI_MAX_BUS 0xFF
3560 #define PCI_IOADDRESS_MASK 0xFFFE
3561 #define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3563 #ifndef ADVANSYS_STATS
3564 #define ASC_STATS(shp, counter)
3565 #define ASC_STATS_ADD(shp, counter, count)
3566 #else /* ADVANSYS_STATS */
3567 #define ASC_STATS(shp, counter) \
3568 (ASC_BOARDP(shp)->asc_stats.counter++)
3570 #define ASC_STATS_ADD(shp, counter, count) \
3571 (ASC_BOARDP(shp)->asc_stats.counter += (count))
3572 #endif /* ADVANSYS_STATS */
3574 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3576 /* If the result wraps when calculating tenths, return 0. */
3577 #define ASC_TENTHS(num, den) \
3578 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3579 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3582 * Display a message to the console.
3584 #define ASC_PRINT(s) \
3586 printk("advansys: "); \
3590 #define ASC_PRINT1(s, a1) \
3592 printk("advansys: "); \
3593 printk((s), (a1)); \
3596 #define ASC_PRINT2(s, a1, a2) \
3598 printk("advansys: "); \
3599 printk((s), (a1), (a2)); \
3602 #define ASC_PRINT3(s, a1, a2, a3) \
3604 printk("advansys: "); \
3605 printk((s), (a1), (a2), (a3)); \
3608 #define ASC_PRINT4(s, a1, a2, a3, a4) \
3610 printk("advansys: "); \
3611 printk((s), (a1), (a2), (a3), (a4)); \
3615 #ifndef ADVANSYS_DEBUG
3617 #define ASC_DBG(lvl, s)
3618 #define ASC_DBG1(lvl, s, a1)
3619 #define ASC_DBG2(lvl, s, a1, a2)
3620 #define ASC_DBG3(lvl, s, a1, a2, a3)
3621 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3622 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3623 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3624 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3625 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3626 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3627 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3628 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
3629 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
3630 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
3631 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3633 #else /* ADVANSYS_DEBUG */
3636 * Debugging Message Levels:
3638 * 1: High-Level Tracing
3639 * 2-N: Verbose Tracing
3642 #define ASC_DBG(lvl, s) \
3644 if (asc_dbglvl >= (lvl)) { \
3649 #define ASC_DBG1(lvl, s, a1) \
3651 if (asc_dbglvl >= (lvl)) { \
3652 printk((s), (a1)); \
3656 #define ASC_DBG2(lvl, s, a1, a2) \
3658 if (asc_dbglvl >= (lvl)) { \
3659 printk((s), (a1), (a2)); \
3663 #define ASC_DBG3(lvl, s, a1, a2, a3) \
3665 if (asc_dbglvl >= (lvl)) { \
3666 printk((s), (a1), (a2), (a3)); \
3670 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3672 if (asc_dbglvl >= (lvl)) { \
3673 printk((s), (a1), (a2), (a3), (a4)); \
3677 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3679 if (asc_dbglvl >= (lvl)) { \
3680 asc_prt_scsi_host(s); \
3684 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3686 if (asc_dbglvl >= (lvl)) { \
3687 asc_prt_scsi_cmnd(s); \
3691 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3693 if (asc_dbglvl >= (lvl)) { \
3694 asc_prt_asc_scsi_q(scsiqp); \
3698 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3700 if (asc_dbglvl >= (lvl)) { \
3701 asc_prt_asc_qdone_info(qdone); \
3705 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3707 if (asc_dbglvl >= (lvl)) { \
3708 asc_prt_adv_scsi_req_q(scsiqp); \
3712 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3714 if (asc_dbglvl >= (lvl)) { \
3715 asc_prt_hex((name), (start), (length)); \
3719 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3720 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3722 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3723 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3725 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3726 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3727 #endif /* ADVANSYS_DEBUG */
3729 #ifndef ADVANSYS_ASSERT
3730 #define ASC_ASSERT(a)
3731 #else /* ADVANSYS_ASSERT */
3733 #define ASC_ASSERT(a) \
3736 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3737 __FILE__, __LINE__); \
3741 #endif /* ADVANSYS_ASSERT */
3745 * --- Driver Structures
3748 #ifdef ADVANSYS_STATS
3750 /* Per board statistics structure */
3752 /* Driver Entrypoint Statistics */
3753 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3754 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3755 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3756 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3757 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3758 ADV_DCNT done; /* # calls to request's scsi_done function */
3759 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3760 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3761 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3762 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3763 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3764 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3765 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3766 ADV_DCNT exe_unknown; /* # unknown returns. */
3767 /* Data Transfer Statistics */
3768 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3769 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3770 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3771 ADV_DCNT sg_elem; /* # scatter-gather elements */
3772 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3774 #endif /* ADVANSYS_STATS */
3777 * Request queuing structure
3779 typedef struct asc_queue {
3780 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3781 REQP q_first[ADV_MAX_TID+1]; /* first queued request */
3782 REQP q_last[ADV_MAX_TID+1]; /* last queued request */
3783 #ifdef ADVANSYS_STATS
3784 short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
3785 short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
3786 ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
3787 ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
3788 ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
3789 ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
3790 #endif /* ADVANSYS_STATS */
3794 * Adv Library Request Structures
3796 * The following two structures are used to process Wide Board requests.
3798 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3799 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3800 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3801 * Mid-Level SCSI request structure.
3803 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3804 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3805 * up to 255 scatter-gather elements may be used per request or
3808 * Both structures must be 32 byte aligned.
3810 typedef struct adv_sgblk {
3811 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3812 uchar align[32]; /* Sgblock structure padding. */
3813 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3816 typedef struct adv_req {
3817 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3818 uchar align[32]; /* Request structure padding. */
3819 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3820 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3821 struct adv_req *next_reqp; /* Next Request Structure. */
3825 * Structure allocated for each board.
3827 * This structure is allocated by scsi_register() at the end
3828 * of the 'Scsi_Host' structure starting at the 'hostdata'
3829 * field. It is guaranteed to be allocated from DMA-able memory.
3831 typedef struct asc_board {
3832 int id; /* Board Id */
3833 uint flags; /* Board flags */
3835 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3836 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3839 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3840 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3842 ushort asc_n_io_port; /* Number I/O ports. */
3843 asc_queue_t active; /* Active command queue */
3844 asc_queue_t waiting; /* Waiting command queue */
3845 asc_queue_t done; /* Done command queue */
3846 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3847 struct scsi_device *device[ADV_MAX_TID+1]; /* Mid-Level Scsi Device */
3848 ushort reqcnt[ADV_MAX_TID+1]; /* Starvation request count */
3849 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3850 ushort queue_full_cnt[ADV_MAX_TID+1]; /* Queue full count */
3852 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3853 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3854 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3855 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3857 ulong last_reset; /* Saved last reset time */
3858 spinlock_t lock; /* Board spinlock */
3859 #ifdef CONFIG_PROC_FS
3860 /* /proc/scsi/advansys/[0...] */
3861 char *prtbuf; /* /proc print buffer */
3862 #endif /* CONFIG_PROC_FS */
3863 #ifdef ADVANSYS_STATS
3864 struct asc_stats asc_stats; /* Board statistics */
3865 #endif /* ADVANSYS_STATS */
3867 * The following fields are used only for Narrow Boards.
3869 /* The following three structures must be in DMA-able memory. */
3870 ASC_SCSI_REQ_Q scsireqq;
3871 ASC_CAP_INFO cap_info;
3872 ASC_SCSI_INQUIRY inquiry;
3873 uchar sdtr_data[ASC_MAX_TID+1]; /* SDTR information */
3875 * The following fields are used only for Wide Boards.
3877 void *ioremap_addr; /* I/O Memory remap address. */
3878 ushort ioport; /* I/O Port address. */
3879 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3880 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3881 adv_req_t *adv_reqp; /* Request structures. */
3882 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3883 ushort bios_signature; /* BIOS Signature. */
3884 ushort bios_version; /* BIOS Version. */
3885 ushort bios_codeseg; /* BIOS Code Segment. */
3886 ushort bios_codelen; /* BIOS Code Segment Length. */
3890 * PCI configuration structures
3892 typedef struct _PCI_DATA_
3901 typedef struct _PCI_DEVICE_
3916 typedef struct _PCI_CONFIG_SPACE_
3928 ADV_PADDR baseAddress[6];
3930 ADV_PADDR optionRomAddr;
3931 ushort reserved2[4];
3943 /* Note: All driver global data should be initialized. */
3945 /* Number of boards detected in system. */
3946 STATIC int asc_board_count = 0;
3947 STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
3949 /* Overrun buffer used by all narrow boards. */
3950 STATIC uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3953 * Global structures required to issue a command.
3955 STATIC ASC_SCSI_Q asc_scsi_q = { { 0 } };
3956 STATIC ASC_SG_HEAD asc_sg_head = { 0 };
3958 /* List of supported bus types. */
3959 STATIC ushort asc_bus[ASC_NUM_BUS] __initdata = {
3967 * Used with the LILO 'advansys' option to eliminate or
3968 * limit I/O port probing at boot time, cf. advansys_setup().
3970 STATIC int asc_iopflag = ASC_FALSE;
3971 STATIC int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
3973 #ifdef ADVANSYS_DEBUG
3975 asc_bus_name[ASC_NUM_BUS] = {
3982 STATIC int asc_dbglvl = 3;
3983 #endif /* ADVANSYS_DEBUG */
3985 /* Declaration for Asc Library internal data referenced by driver. */
3986 STATIC PortAddr _asc_def_iop_base[];
3990 * --- Driver Function Prototypes
3992 * advansys.h contains function prototypes for functions global to Linux.
3995 STATIC irqreturn_t advansys_interrupt(int, void *, struct pt_regs *);
3996 STATIC int advansys_slave_configure(struct scsi_device *);
3997 STATIC void asc_scsi_done_list(struct scsi_cmnd *);
3998 STATIC int asc_execute_scsi_cmnd(struct scsi_cmnd *);
3999 STATIC int asc_build_req(asc_board_t *, struct scsi_cmnd *);
4000 STATIC int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
4001 STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
4002 STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
4003 STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
4004 STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
4005 STATIC void asc_enqueue(asc_queue_t *, REQP, int);
4006 STATIC REQP asc_dequeue(asc_queue_t *, int);
4007 STATIC REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
4008 STATIC int asc_rmqueue(asc_queue_t *, REQP);
4009 STATIC void asc_execute_queue(asc_queue_t *);
4010 #ifdef CONFIG_PROC_FS
4011 STATIC int asc_proc_copy(off_t, off_t, char *, int , char *, int);
4012 STATIC int asc_prt_board_devices(struct Scsi_Host *, char *, int);
4013 STATIC int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
4014 STATIC int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
4015 STATIC int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
4016 STATIC int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
4017 STATIC int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
4018 STATIC int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
4019 STATIC int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
4020 STATIC int asc_prt_line(char *, int, char *fmt, ...);
4021 #endif /* CONFIG_PROC_FS */
4023 /* Declaration for Asc Library internal functions referenced by driver. */
4024 STATIC int AscFindSignature(PortAddr);
4025 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
4027 /* Statistics function prototypes. */
4028 #ifdef ADVANSYS_STATS
4029 #ifdef CONFIG_PROC_FS
4030 STATIC int asc_prt_board_stats(struct Scsi_Host *, char *, int);
4031 STATIC int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
4032 #endif /* CONFIG_PROC_FS */
4033 #endif /* ADVANSYS_STATS */
4035 /* Debug function prototypes. */
4036 #ifdef ADVANSYS_DEBUG
4037 STATIC void asc_prt_scsi_host(struct Scsi_Host *);
4038 STATIC void asc_prt_scsi_cmnd(struct scsi_cmnd *);
4039 STATIC void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
4040 STATIC void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4041 STATIC void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4042 STATIC void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4043 STATIC void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4044 STATIC void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4045 STATIC void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4046 STATIC void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4047 STATIC void asc_prt_hex(char *f, uchar *, int);
4048 #endif /* ADVANSYS_DEBUG */
4052 * --- Linux 'struct scsi_host_template' and advansys_setup() Functions
4055 #ifdef CONFIG_PROC_FS
4057 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4059 * *buffer: I/O buffer
4060 * **start: if inout == FALSE pointer into buffer where user read should start
4061 * offset: current offset into a /proc/scsi/advansys/[0...] file
4062 * length: length of buffer
4063 * hostno: Scsi_Host host_no
4064 * inout: TRUE - user is writing; FALSE - user is reading
4066 * Return the number of bytes read from or written to a
4067 * /proc/scsi/advansys/[0...] file.
4069 * Note: This function uses the per board buffer 'prtbuf' which is
4070 * allocated when the board is initialized in advansys_detect(). The
4071 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4072 * used to write to the buffer. The way asc_proc_copy() is written
4073 * if 'prtbuf' is too small it will not be overwritten. Instead the
4074 * user just won't get all the available statistics.
4077 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4078 off_t offset, int length, int inout)
4080 struct Scsi_Host *shp;
4081 asc_board_t *boardp;
4090 #ifdef ADVANSYS_STATS
4092 #endif /* ADVANSYS_STATS */
4094 ASC_DBG(1, "advansys_proc_info: begin\n");
4097 * User write not supported.
4099 if (inout == TRUE) {
4104 * User read of /proc/scsi/advansys/[0...] file.
4107 /* Find the specified board. */
4108 for (i = 0; i < asc_board_count; i++) {
4109 if (asc_host[i]->host_no == shost->host_no) {
4113 if (i == asc_board_count) {
4118 boardp = ASC_BOARDP(shp);
4120 /* Copy read data starting at the beginning of the buffer. */
4128 * Get board configuration information.
4130 * advansys_info() returns the board string from its own static buffer.
4132 cp = (char *) advansys_info(shp);
4135 /* Copy board information. */
4136 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4140 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4147 * Display Wide Board BIOS Information.
4149 if (ASC_WIDE_BOARD(boardp)) {
4150 cp = boardp->prtbuf;
4151 cplen = asc_prt_adv_bios(shp, cp, ASC_PRTBUF_SIZE);
4152 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4153 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4157 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4165 * Display driver information for each device attached to the board.
4167 cp = boardp->prtbuf;
4168 cplen = asc_prt_board_devices(shp, cp, ASC_PRTBUF_SIZE);
4169 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4170 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4174 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4181 * Display EEPROM configuration for the board.
4183 cp = boardp->prtbuf;
4184 if (ASC_NARROW_BOARD(boardp)) {
4185 cplen = asc_prt_asc_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4187 cplen = asc_prt_adv_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4189 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4190 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4194 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4201 * Display driver configuration and information for the board.
4203 cp = boardp->prtbuf;
4204 cplen = asc_prt_driver_conf(shp, cp, ASC_PRTBUF_SIZE);
4205 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4206 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4210 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4216 #ifdef ADVANSYS_STATS
4218 * Display driver statistics for the board.
4220 cp = boardp->prtbuf;
4221 cplen = asc_prt_board_stats(shp, cp, ASC_PRTBUF_SIZE);
4222 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4223 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4227 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4234 * Display driver statistics for each target.
4236 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4237 cp = boardp->prtbuf;
4238 cplen = asc_prt_target_stats(shp, tgt_id, cp, ASC_PRTBUF_SIZE);
4239 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4240 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4244 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4250 #endif /* ADVANSYS_STATS */
4253 * Display Asc Library dynamic configuration information
4256 cp = boardp->prtbuf;
4257 if (ASC_NARROW_BOARD(boardp)) {
4258 cplen = asc_prt_asc_board_info(shp, cp, ASC_PRTBUF_SIZE);
4260 cplen = asc_prt_adv_board_info(shp, cp, ASC_PRTBUF_SIZE);
4262 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4263 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4267 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4273 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4277 #endif /* CONFIG_PROC_FS */
4282 * Detect function for AdvanSys adapters.
4284 * Argument is a pointer to the host driver's scsi_hosts entry.
4286 * Return number of adapters found.
4288 * Note: Because this function is called during system initialization
4289 * it must not call SCSI mid-level functions including scsi_malloc()
4293 advansys_detect(struct scsi_host_template *tpnt)
4295 static int detect_called = ASC_FALSE;
4298 struct Scsi_Host *shp = NULL;
4299 asc_board_t *boardp = NULL;
4300 ASC_DVC_VAR *asc_dvc_varp = NULL;
4301 ADV_DVC_VAR *adv_dvc_varp = NULL;
4302 adv_sgblk_t *sgp = NULL;
4304 int share_irq = FALSE;
4306 struct device *dev = NULL;
4308 int pci_init_search = 0;
4309 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
4310 int pci_card_cnt_max = 0;
4311 int pci_card_cnt = 0;
4312 struct pci_dev *pci_devp = NULL;
4313 int pci_device_id_cnt = 0;
4314 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
4315 PCI_DEVICE_ID_ASP_1200A,
4316 PCI_DEVICE_ID_ASP_ABP940,
4317 PCI_DEVICE_ID_ASP_ABP940U,
4318 PCI_DEVICE_ID_ASP_ABP940UW,
4319 PCI_DEVICE_ID_38C0800_REV1,
4320 PCI_DEVICE_ID_38C1600_REV1
4322 ADV_PADDR pci_memory_address;
4323 #endif /* CONFIG_PCI */
4324 int warn_code, err_code;
4327 if (detect_called == ASC_FALSE) {
4328 detect_called = ASC_TRUE;
4330 printk("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
4334 ASC_DBG(1, "advansys_detect: begin\n");
4336 asc_board_count = 0;
4339 * If I/O port probing has been modified, then verify and
4340 * clean-up the 'asc_ioport' list.
4342 if (asc_iopflag == ASC_TRUE) {
4343 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4344 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
4345 ioport, asc_ioport[ioport]);
4346 if (asc_ioport[ioport] != 0) {
4347 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX; iop++) {
4348 if (_asc_def_iop_base[iop] == asc_ioport[ioport]) {
4352 if (iop == ASC_IOADR_TABLE_MAX_IX) {
4354 "AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
4355 asc_ioport[ioport]);
4356 asc_ioport[ioport] = 0;
4363 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
4365 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
4366 bus, asc_bus_name[bus]);
4369 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
4371 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
4374 switch (asc_bus[bus]) {
4378 if (asc_iopflag == ASC_FALSE) {
4379 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4382 * ISA and VL I/O port scanning has either been
4383 * eliminated or limited to selected ports on
4384 * the LILO command line, /etc/lilo.conf, or
4385 * by setting variables when the module was loaded.
4387 ASC_DBG(1, "advansys_detect: I/O port scanning modified\n");
4390 for (; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4391 if ((iop = asc_ioport[ioport]) != 0) {
4397 "advansys_detect: probing I/O port 0x%x...\n",
4399 if (check_region(iop, ASC_IOADR_GAP) != 0) {
4401 "AdvanSys SCSI: specified I/O Port 0x%X is busy\n", iop);
4402 /* Don't try this I/O port twice. */
4403 asc_ioport[ioport] = 0;
4404 goto ioport_try_again;
4405 } else if (AscFindSignature(iop) == ASC_FALSE) {
4407 "AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n", iop);
4408 /* Don't try this I/O port twice. */
4409 asc_ioport[ioport] = 0;
4410 goto ioport_try_again;
4413 * If this isn't an ISA board, then it must be
4414 * a VL board. If currently looking an ISA
4415 * board is being looked for then try for
4416 * another ISA board in 'asc_ioport'.
4418 if (asc_bus[bus] == ASC_IS_ISA &&
4419 (AscGetChipVersion(iop, ASC_IS_ISA) &
4420 ASC_CHIP_VER_ISA_BIT) == 0) {
4422 * Don't clear 'asc_ioport[ioport]'. Try
4423 * this board again for VL. Increment
4424 * 'ioport' past this board.
4427 goto ioport_try_again;
4431 * This board appears good, don't try the I/O port
4432 * again by clearing its value. Increment 'ioport'
4433 * for the next iteration.
4435 asc_ioport[ioport++] = 0;
4438 #endif /* CONFIG_ISA */
4443 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4444 #endif /* CONFIG_ISA */
4449 if (pci_init_search == 0) {
4452 pci_init_search = 1;
4454 /* Find all PCI cards. */
4455 while (pci_device_id_cnt < ASC_PCI_DEVICE_ID_CNT) {
4456 if ((pci_devp = pci_find_device(PCI_VENDOR_ID_ASP,
4457 pci_device_id[pci_device_id_cnt], pci_devp)) ==
4459 pci_device_id_cnt++;
4461 if (pci_enable_device(pci_devp) == 0) {
4462 pci_devicep[pci_card_cnt_max++] = pci_devp;
4468 * Sort PCI cards in ascending order by PCI Bus, Slot,
4469 * and Device Number.
4471 for (i = 0; i < pci_card_cnt_max - 1; i++)
4473 for (j = i + 1; j < pci_card_cnt_max; j++) {
4474 if ((pci_devicep[j]->bus->number <
4475 pci_devicep[i]->bus->number) ||
4476 ((pci_devicep[j]->bus->number ==
4477 pci_devicep[i]->bus->number) &&
4478 (pci_devicep[j]->devfn <
4479 pci_devicep[i]->devfn))) {
4480 pci_devp = pci_devicep[i];
4481 pci_devicep[i] = pci_devicep[j];
4482 pci_devicep[j] = pci_devp;
4492 if (pci_card_cnt == pci_card_cnt_max) {
4495 pci_devp = pci_devicep[pci_card_cnt];
4498 "advansys_detect: devfn %d, bus number %d\n",
4499 pci_devp->devfn, pci_devp->bus->number);
4500 iop = pci_resource_start(pci_devp, 0);
4502 "advansys_detect: vendorID %X, deviceID %X\n",
4503 pci_devp->vendor, pci_devp->device);
4504 ASC_DBG2(2, "advansys_detect: iop %X, irqLine %d\n",
4505 iop, pci_devp->irq);
4508 dev = &pci_devp->dev;
4510 #endif /* CONFIG_PCI */
4514 ASC_PRINT1("advansys_detect: unknown bus type: %d\n",
4518 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
4521 * Adapter not found, try next bus type.
4530 * Register the adapter, get its configuration, and
4533 ASC_DBG(2, "advansys_detect: scsi_register()\n");
4534 shp = scsi_register(tpnt, sizeof(asc_board_t));
4540 /* Save a pointer to the Scsi_Host of each board found. */
4541 asc_host[asc_board_count++] = shp;
4543 /* Initialize private per board data */
4544 boardp = ASC_BOARDP(shp);
4545 memset(boardp, 0, sizeof(asc_board_t));
4546 boardp->id = asc_board_count - 1;
4548 /* Initialize spinlock. */
4549 spin_lock_init(&boardp->lock);
4552 * Handle both narrow and wide boards.
4554 * If a Wide board was detected, set the board structure
4555 * wide board flag. Set-up the board structure based on
4559 if (asc_bus[bus] == ASC_IS_PCI &&
4560 (pci_devp->device == PCI_DEVICE_ID_ASP_ABP940UW ||
4561 pci_devp->device == PCI_DEVICE_ID_38C0800_REV1 ||
4562 pci_devp->device == PCI_DEVICE_ID_38C1600_REV1))
4564 boardp->flags |= ASC_IS_WIDE_BOARD;
4566 #endif /* CONFIG_PCI */
4568 if (ASC_NARROW_BOARD(boardp)) {
4569 ASC_DBG(1, "advansys_detect: narrow board\n");
4570 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4571 asc_dvc_varp->bus_type = asc_bus[bus];
4572 asc_dvc_varp->drv_ptr = boardp;
4573 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
4574 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
4575 asc_dvc_varp->iop_base = iop;
4576 asc_dvc_varp->isr_callback = asc_isr_callback;
4578 ASC_DBG(1, "advansys_detect: wide board\n");
4579 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4580 adv_dvc_varp->drv_ptr = boardp;
4581 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
4582 adv_dvc_varp->isr_callback = adv_isr_callback;
4583 adv_dvc_varp->async_callback = adv_async_callback;
4585 if (pci_devp->device == PCI_DEVICE_ID_ASP_ABP940UW)
4587 ASC_DBG(1, "advansys_detect: ASC-3550\n");
4588 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
4589 } else if (pci_devp->device == PCI_DEVICE_ID_38C0800_REV1)
4591 ASC_DBG(1, "advansys_detect: ASC-38C0800\n");
4592 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
4595 ASC_DBG(1, "advansys_detect: ASC-38C1600\n");
4596 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
4598 #endif /* CONFIG_PCI */
4601 * Map the board's registers into virtual memory for
4602 * PCI slave access. Only memory accesses are used to
4603 * access the board's registers.
4605 * Note: The PCI register base address is not always
4606 * page aligned, but the address passed to ioremap()
4607 * must be page aligned. It is guaranteed that the
4608 * PCI register base address will not cross a page
4611 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4613 iolen = ADV_3550_IOLEN;
4614 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4616 iolen = ADV_38C0800_IOLEN;
4619 iolen = ADV_38C1600_IOLEN;
4622 pci_memory_address = pci_resource_start(pci_devp, 1);
4623 ASC_DBG1(1, "advansys_detect: pci_memory_address: 0x%lx\n",
4624 (ulong) pci_memory_address);
4625 if ((boardp->ioremap_addr =
4626 ioremap(pci_memory_address & PAGE_MASK,
4629 "advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
4630 boardp->id, pci_memory_address, iolen);
4631 scsi_unregister(shp);
4635 ASC_DBG1(1, "advansys_detect: ioremap_addr: 0x%lx\n",
4636 (ulong) boardp->ioremap_addr);
4637 adv_dvc_varp->iop_base = (AdvPortAddr)
4638 (boardp->ioremap_addr +
4639 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
4640 ASC_DBG1(1, "advansys_detect: iop_base: 0x%lx\n",
4641 adv_dvc_varp->iop_base);
4642 #endif /* CONFIG_PCI */
4645 * Even though it isn't used to access wide boards, other
4646 * than for the debug line below, save I/O Port address so
4647 * that it can be reported.
4649 boardp->ioport = iop;
4652 "advansys_detect: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
4653 (ushort) inp(iop + 1), (ushort) inpw(iop));
4656 #ifdef CONFIG_PROC_FS
4658 * Allocate buffer for printing information from
4659 * /proc/scsi/advansys/[0...].
4661 if ((boardp->prtbuf =
4662 kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
4664 "advansys_detect: board %d: kmalloc(%d, %d) returned NULL\n",
4665 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
4666 scsi_unregister(shp);
4670 #endif /* CONFIG_PROC_FS */
4672 if (ASC_NARROW_BOARD(boardp)) {
4673 asc_dvc_varp->cfg->dev = dev;
4675 * Set the board bus type and PCI IRQ before
4676 * calling AscInitGetConfig().
4678 switch (asc_dvc_varp->bus_type) {
4681 shp->unchecked_isa_dma = TRUE;
4685 shp->unchecked_isa_dma = FALSE;
4689 shp->unchecked_isa_dma = FALSE;
4692 #endif /* CONFIG_ISA */
4695 shp->irq = asc_dvc_varp->irq_no = pci_devp->irq;
4696 asc_dvc_varp->cfg->pci_slot_info =
4697 ASC_PCI_MKID(pci_devp->bus->number,
4698 PCI_SLOT(pci_devp->devfn),
4699 PCI_FUNC(pci_devp->devfn));
4700 shp->unchecked_isa_dma = FALSE;
4703 #endif /* CONFIG_PCI */
4706 "advansys_detect: board %d: unknown adapter type: %d\n",
4707 boardp->id, asc_dvc_varp->bus_type);
4708 shp->unchecked_isa_dma = TRUE;
4713 adv_dvc_varp->cfg->dev = dev;
4715 * For Wide boards set PCI information before calling
4716 * AdvInitGetConfig().
4719 shp->irq = adv_dvc_varp->irq_no = pci_devp->irq;
4720 adv_dvc_varp->cfg->pci_slot_info =
4721 ASC_PCI_MKID(pci_devp->bus->number,
4722 PCI_SLOT(pci_devp->devfn),
4723 PCI_FUNC(pci_devp->devfn));
4724 shp->unchecked_isa_dma = FALSE;
4726 #endif /* CONFIG_PCI */
4730 * Read the board configuration.
4732 if (ASC_NARROW_BOARD(boardp)) {
4734 * NOTE: AscInitGetConfig() may change the board's
4735 * bus_type value. The asc_bus[bus] value should no
4736 * longer be used. If the bus_type field must be
4737 * referenced only use the bit-wise AND operator "&".
4739 ASC_DBG(2, "advansys_detect: AscInitGetConfig()\n");
4740 switch(ret = AscInitGetConfig(asc_dvc_varp)) {
4741 case 0: /* No error */
4743 case ASC_WARN_IO_PORT_ROTATE:
4745 "AscInitGetConfig: board %d: I/O port address modified\n",
4748 case ASC_WARN_AUTO_CONFIG:
4750 "AscInitGetConfig: board %d: I/O port increment switch enabled\n",
4753 case ASC_WARN_EEPROM_CHKSUM:
4755 "AscInitGetConfig: board %d: EEPROM checksum error\n",
4758 case ASC_WARN_IRQ_MODIFIED:
4760 "AscInitGetConfig: board %d: IRQ modified\n",
4763 case ASC_WARN_CMD_QNG_CONFLICT:
4765 "AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
4770 "AscInitGetConfig: board %d: unknown warning: 0x%x\n",
4774 if ((err_code = asc_dvc_varp->err_code) != 0) {
4776 "AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4777 boardp->id, asc_dvc_varp->init_state,
4778 asc_dvc_varp->err_code);
4781 ASC_DBG(2, "advansys_detect: AdvInitGetConfig()\n");
4782 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
4783 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
4786 if ((err_code = adv_dvc_varp->err_code) != 0) {
4788 "AdvInitGetConfig: board %d error: err_code 0x%x\n",
4789 boardp->id, adv_dvc_varp->err_code);
4793 if (err_code != 0) {
4794 #ifdef CONFIG_PROC_FS
4795 kfree(boardp->prtbuf);
4796 #endif /* CONFIG_PROC_FS */
4797 scsi_unregister(shp);
4803 * Save the EEPROM configuration so that it can be displayed
4804 * from /proc/scsi/advansys/[0...].
4806 if (ASC_NARROW_BOARD(boardp)) {
4811 * Set the adapter's target id bit in the 'init_tidmask' field.
4813 boardp->init_tidmask |=
4814 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
4817 * Save EEPROM settings for the board.
4819 ep = &boardp->eep_config.asc_eep;
4821 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
4822 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
4823 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
4824 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
4825 ep->start_motor = asc_dvc_varp->start_motor;
4826 ep->cntl = asc_dvc_varp->dvc_cntl;
4827 ep->no_scam = asc_dvc_varp->no_scam;
4828 ep->max_total_qng = asc_dvc_varp->max_total_qng;
4829 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
4830 /* 'max_tag_qng' is set to the same value for every device. */
4831 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
4832 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
4833 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
4834 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
4835 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
4836 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
4837 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
4840 * Modify board configuration.
4842 ASC_DBG(2, "advansys_detect: AscInitSetConfig()\n");
4843 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
4844 case 0: /* No error. */
4846 case ASC_WARN_IO_PORT_ROTATE:
4848 "AscInitSetConfig: board %d: I/O port address modified\n",
4851 case ASC_WARN_AUTO_CONFIG:
4853 "AscInitSetConfig: board %d: I/O port increment switch enabled\n",
4856 case ASC_WARN_EEPROM_CHKSUM:
4858 "AscInitSetConfig: board %d: EEPROM checksum error\n",
4861 case ASC_WARN_IRQ_MODIFIED:
4863 "AscInitSetConfig: board %d: IRQ modified\n",
4866 case ASC_WARN_CMD_QNG_CONFLICT:
4868 "AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
4873 "AscInitSetConfig: board %d: unknown warning: 0x%x\n",
4877 if (asc_dvc_varp->err_code != 0) {
4879 "AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4880 boardp->id, asc_dvc_varp->init_state,
4881 asc_dvc_varp->err_code);
4882 #ifdef CONFIG_PROC_FS
4883 kfree(boardp->prtbuf);
4884 #endif /* CONFIG_PROC_FS */
4885 scsi_unregister(shp);
4891 * Finish initializing the 'Scsi_Host' structure.
4893 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
4894 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
4895 shp->irq = asc_dvc_varp->irq_no;
4898 ADVEEP_3550_CONFIG *ep_3550;
4899 ADVEEP_38C0800_CONFIG *ep_38C0800;
4900 ADVEEP_38C1600_CONFIG *ep_38C1600;
4903 * Save Wide EEP Configuration Information.
4905 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4907 ep_3550 = &boardp->eep_config.adv_3550_eep;
4909 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4910 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
4911 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4912 ep_3550->termination = adv_dvc_varp->cfg->termination;
4913 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
4914 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
4915 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
4916 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
4917 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
4918 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
4919 ep_3550->start_motor = adv_dvc_varp->start_motor;
4920 ep_3550->scsi_reset_delay = adv_dvc_varp->scsi_reset_wait;
4921 ep_3550->serial_number_word1 =
4922 adv_dvc_varp->cfg->serial1;
4923 ep_3550->serial_number_word2 =
4924 adv_dvc_varp->cfg->serial2;
4925 ep_3550->serial_number_word3 =
4926 adv_dvc_varp->cfg->serial3;
4927 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4929 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4931 ep_38C0800->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4932 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
4933 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4934 ep_38C0800->termination_lvd =
4935 adv_dvc_varp->cfg->termination;
4936 ep_38C0800->disc_enable = adv_dvc_varp->cfg->disc_enable;
4937 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
4938 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
4939 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4940 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4941 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4942 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4943 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4944 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4945 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
4946 ep_38C0800->scsi_reset_delay =
4947 adv_dvc_varp->scsi_reset_wait;
4948 ep_38C0800->serial_number_word1 =
4949 adv_dvc_varp->cfg->serial1;
4950 ep_38C0800->serial_number_word2 =
4951 adv_dvc_varp->cfg->serial2;
4952 ep_38C0800->serial_number_word3 =
4953 adv_dvc_varp->cfg->serial3;
4956 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4958 ep_38C1600->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4959 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
4960 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4961 ep_38C1600->termination_lvd =
4962 adv_dvc_varp->cfg->termination;
4963 ep_38C1600->disc_enable = adv_dvc_varp->cfg->disc_enable;
4964 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
4965 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
4966 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4967 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4968 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4969 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4970 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4971 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4972 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
4973 ep_38C1600->scsi_reset_delay =
4974 adv_dvc_varp->scsi_reset_wait;
4975 ep_38C1600->serial_number_word1 =
4976 adv_dvc_varp->cfg->serial1;
4977 ep_38C1600->serial_number_word2 =
4978 adv_dvc_varp->cfg->serial2;
4979 ep_38C1600->serial_number_word3 =
4980 adv_dvc_varp->cfg->serial3;
4984 * Set the adapter's target id bit in the 'init_tidmask' field.
4986 boardp->init_tidmask |=
4987 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
4990 * Finish initializing the 'Scsi_Host' structure.
4992 shp->irq = adv_dvc_varp->irq_no;
4996 * Channels are numbered beginning with 0. For AdvanSys one host
4997 * structure supports one channel. Multi-channel boards have a
4998 * separate host structure for each channel.
5000 shp->max_channel = 0;
5001 if (ASC_NARROW_BOARD(boardp)) {
5002 shp->max_id = ASC_MAX_TID + 1;
5003 shp->max_lun = ASC_MAX_LUN + 1;
5005 shp->io_port = asc_dvc_varp->iop_base;
5006 boardp->asc_n_io_port = ASC_IOADR_GAP;
5007 shp->this_id = asc_dvc_varp->cfg->chip_scsi_id;
5009 /* Set maximum number of queues the adapter can handle. */
5010 shp->can_queue = asc_dvc_varp->max_total_qng;
5012 shp->max_id = ADV_MAX_TID + 1;
5013 shp->max_lun = ADV_MAX_LUN + 1;
5016 * Save the I/O Port address and length even though
5017 * I/O ports are not used to access Wide boards.
5018 * Instead the Wide boards are accessed with
5019 * PCI Memory Mapped I/O.
5022 boardp->asc_n_io_port = iolen;
5024 shp->this_id = adv_dvc_varp->chip_scsi_id;
5026 /* Set maximum number of queues the adapter can handle. */
5027 shp->can_queue = adv_dvc_varp->max_host_qng;
5031 * 'n_io_port' currently is one byte.
5033 * Set a value to 'n_io_port', but never referenced it because
5034 * it may be truncated.
5036 shp->n_io_port = boardp->asc_n_io_port <= 255 ?
5037 boardp->asc_n_io_port : 255;
5040 * Following v1.3.89, 'cmd_per_lun' is no longer needed
5041 * and should be set to zero.
5043 * But because of a bug introduced in v1.3.89 if the driver is
5044 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
5045 * SCSI function 'allocate_device' will panic. To allow the driver
5046 * to work as a module in these kernels set 'cmd_per_lun' to 1.
5048 * Note: This is wrong. cmd_per_lun should be set to the depth
5049 * you want on untagged devices always.
5052 shp->cmd_per_lun = 1;
5054 shp->cmd_per_lun = 0;
5058 * Set the maximum number of scatter-gather elements the
5059 * adapter can handle.
5061 if (ASC_NARROW_BOARD(boardp)) {
5063 * Allow two commands with 'sg_tablesize' scatter-gather
5064 * elements to be executed simultaneously. This value is
5065 * the theoretical hardware limit. It may be decreased
5069 (((asc_dvc_varp->max_total_qng - 2) / 2) *
5070 ASC_SG_LIST_PER_Q) + 1;
5072 shp->sg_tablesize = ADV_MAX_SG_LIST;
5076 * The value of 'sg_tablesize' can not exceed the SCSI
5077 * mid-level driver definition of SG_ALL. SG_ALL also
5078 * must not be exceeded, because it is used to define the
5079 * size of the scatter-gather table in 'struct asc_sg_head'.
5081 if (shp->sg_tablesize > SG_ALL) {
5082 shp->sg_tablesize = SG_ALL;
5085 ASC_DBG1(1, "advansys_detect: sg_tablesize: %d\n",
5088 /* BIOS start address. */
5089 if (ASC_NARROW_BOARD(boardp)) {
5091 ((ulong) AscGetChipBiosAddress(
5092 asc_dvc_varp->iop_base,
5093 asc_dvc_varp->bus_type));
5096 * Fill-in BIOS board variables. The Wide BIOS saves
5097 * information in LRAM that is used by the driver.
5099 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_SIGNATURE,
5100 boardp->bios_signature);
5101 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_VERSION,
5102 boardp->bios_version);
5103 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODESEG,
5104 boardp->bios_codeseg);
5105 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODELEN,
5106 boardp->bios_codelen);
5109 "advansys_detect: bios_signature 0x%x, bios_version 0x%x\n",
5110 boardp->bios_signature, boardp->bios_version);
5113 "advansys_detect: bios_codeseg 0x%x, bios_codelen 0x%x\n",
5114 boardp->bios_codeseg, boardp->bios_codelen);
5117 * If the BIOS saved a valid signature, then fill in
5118 * the BIOS code segment base address.
5120 if (boardp->bios_signature == 0x55AA) {
5122 * Convert x86 realmode code segment to a linear
5123 * address by shifting left 4.
5125 shp->base = ((ulong) boardp->bios_codeseg << 4);
5132 * Register Board Resources - I/O Port, DMA, IRQ
5136 * Register I/O port range.
5138 * For Wide boards the I/O ports are not used to access
5139 * the board, but request the region anyway.
5141 * 'shp->n_io_port' is not referenced, because it may be truncated.
5144 "advansys_detect: request_region port 0x%lx, len 0x%x\n",
5145 (ulong) shp->io_port, boardp->asc_n_io_port);
5146 if (request_region(shp->io_port, boardp->asc_n_io_port,
5147 "advansys") == NULL) {
5149 "advansys_detect: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
5150 boardp->id, (ulong) shp->io_port, boardp->asc_n_io_port);
5151 #ifdef CONFIG_PROC_FS
5152 kfree(boardp->prtbuf);
5153 #endif /* CONFIG_PROC_FS */
5154 scsi_unregister(shp);
5159 /* Register DMA Channel for Narrow boards. */
5160 shp->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
5162 if (ASC_NARROW_BOARD(boardp)) {
5163 /* Register DMA channel for ISA bus. */
5164 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5165 shp->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
5167 request_dma(shp->dma_channel, "advansys")) != 0) {
5169 "advansys_detect: board %d: request_dma() %d failed %d\n",
5170 boardp->id, shp->dma_channel, ret);
5171 release_region(shp->io_port, boardp->asc_n_io_port);
5172 #ifdef CONFIG_PROC_FS
5173 kfree(boardp->prtbuf);
5174 #endif /* CONFIG_PROC_FS */
5175 scsi_unregister(shp);
5179 AscEnableIsaDma(shp->dma_channel);
5182 #endif /* CONFIG_ISA */
5184 /* Register IRQ Number. */
5185 ASC_DBG1(2, "advansys_detect: request_irq() %d\n", shp->irq);
5187 * If request_irq() fails with the SA_INTERRUPT flag set,
5188 * then try again without the SA_INTERRUPT flag set. This
5189 * allows IRQ sharing to work even with other drivers that
5190 * do not set the SA_INTERRUPT flag.
5192 * If SA_INTERRUPT is not set, then interrupts are enabled
5193 * before the driver interrupt function is called.
5195 if (((ret = request_irq(shp->irq, advansys_interrupt,
5196 SA_INTERRUPT | (share_irq == TRUE ? SA_SHIRQ : 0),
5197 "advansys", boardp)) != 0) &&
5198 ((ret = request_irq(shp->irq, advansys_interrupt,
5199 (share_irq == TRUE ? SA_SHIRQ : 0),
5200 "advansys", boardp)) != 0))
5202 if (ret == -EBUSY) {
5204 "advansys_detect: board %d: request_irq(): IRQ 0x%x already in use.\n",
5205 boardp->id, shp->irq);
5206 } else if (ret == -EINVAL) {
5208 "advansys_detect: board %d: request_irq(): IRQ 0x%x not valid.\n",
5209 boardp->id, shp->irq);
5212 "advansys_detect: board %d: request_irq(): IRQ 0x%x failed with %d\n",
5213 boardp->id, shp->irq, ret);
5215 release_region(shp->io_port, boardp->asc_n_io_port);
5216 iounmap(boardp->ioremap_addr);
5217 if (shp->dma_channel != NO_ISA_DMA) {
5218 free_dma(shp->dma_channel);
5220 #ifdef CONFIG_PROC_FS
5221 kfree(boardp->prtbuf);
5222 #endif /* CONFIG_PROC_FS */
5223 scsi_unregister(shp);
5229 * Initialize board RISC chip and enable interrupts.
5231 if (ASC_NARROW_BOARD(boardp)) {
5232 ASC_DBG(2, "advansys_detect: AscInitAsc1000Driver()\n");
5233 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
5234 err_code = asc_dvc_varp->err_code;
5236 if (warn_code || err_code) {
5238 "advansys_detect: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
5239 boardp->id, asc_dvc_varp->init_state,
5240 warn_code, err_code);
5245 adv_req_t *reqp = NULL;
5249 * Allocate buffer carrier structures. The total size
5250 * is about 4 KB, so allocate all at once.
5253 (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
5254 ASC_DBG1(1, "advansys_detect: carrp 0x%lx\n", (ulong) carrp);
5256 if (carrp == NULL) {
5261 * Allocate up to 'max_host_qng' request structures for
5262 * the Wide board. The total size is about 16 KB, so
5263 * allocate all at once. If the allocation fails decrement
5266 for (req_cnt = adv_dvc_varp->max_host_qng;
5267 req_cnt > 0; req_cnt--) {
5269 reqp = (adv_req_t *)
5270 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
5273 "advansys_detect: reqp 0x%lx, req_cnt %d, bytes %lu\n",
5274 (ulong) reqp, req_cnt,
5275 (ulong) sizeof(adv_req_t) * req_cnt);
5287 * Allocate up to ADV_TOT_SG_BLOCK request structures for
5288 * the Wide board. Each structure is about 136 bytes.
5290 boardp->adv_sgblkp = NULL;
5291 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
5293 sgp = (adv_sgblk_t *)
5294 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
5300 sgp->next_sgblkp = boardp->adv_sgblkp;
5301 boardp->adv_sgblkp = sgp;
5305 "advansys_detect: sg_cnt %d * %u = %u bytes\n",
5306 sg_cnt, sizeof(adv_sgblk_t),
5307 (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
5310 * If no request structures or scatter-gather structures could
5311 * be allocated, then return an error. Otherwise continue with
5318 "advansys_detect: board %d error: failed to kmalloc() carrier buffer.\n",
5320 err_code = ADV_ERROR;
5321 } else if (reqp == NULL) {
5324 "advansys_detect: board %d error: failed to kmalloc() adv_req_t buffer.\n",
5326 err_code = ADV_ERROR;
5327 } else if (boardp->adv_sgblkp == NULL) {
5331 "advansys_detect: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
5333 err_code = ADV_ERROR;
5336 /* Save carrier buffer pointer. */
5337 boardp->orig_carrp = carrp;
5340 * Save original pointer for kfree() in case the
5341 * driver is built as a module and can be unloaded.
5343 boardp->orig_reqp = reqp;
5345 adv_dvc_varp->carrier_buf = carrp;
5348 * Point 'adv_reqp' to the request structures and
5349 * link them together.
5352 reqp[req_cnt].next_reqp = NULL;
5353 for (; req_cnt > 0; req_cnt--) {
5354 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
5356 boardp->adv_reqp = &reqp[0];
5358 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5361 "advansys_detect: AdvInitAsc3550Driver()\n");
5362 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
5363 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5365 "advansys_detect: AdvInitAsc38C0800Driver()\n");
5366 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
5369 "advansys_detect: AdvInitAsc38C1600Driver()\n");
5370 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
5372 err_code = adv_dvc_varp->err_code;
5374 if (warn_code || err_code) {
5376 "advansys_detect: board %d error: warn 0x%x, error 0x%x\n",
5377 boardp->id, warn_code, err_code);
5382 if (err_code != 0) {
5383 release_region(shp->io_port, boardp->asc_n_io_port);
5384 if (ASC_WIDE_BOARD(boardp)) {
5385 iounmap(boardp->ioremap_addr);
5386 kfree(boardp->orig_carrp);
5387 boardp->orig_carrp = NULL;
5388 if (boardp->orig_reqp) {
5389 kfree(boardp->orig_reqp);
5390 boardp->orig_reqp = boardp->adv_reqp = NULL;
5392 while ((sgp = boardp->adv_sgblkp) != NULL)
5394 boardp->adv_sgblkp = sgp->next_sgblkp;
5398 if (shp->dma_channel != NO_ISA_DMA) {
5399 free_dma(shp->dma_channel);
5401 #ifdef CONFIG_PROC_FS
5402 kfree(boardp->prtbuf);
5403 #endif /* CONFIG_PROC_FS */
5404 free_irq(shp->irq, boardp);
5405 scsi_unregister(shp);
5409 ASC_DBG_PRT_SCSI_HOST(2, shp);
5413 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n", asc_board_count);
5414 return asc_board_count;
5418 * advansys_release()
5420 * Release resources allocated for a single AdvanSys adapter.
5423 advansys_release(struct Scsi_Host *shp)
5425 asc_board_t *boardp;
5427 ASC_DBG(1, "advansys_release: begin\n");
5428 boardp = ASC_BOARDP(shp);
5429 free_irq(shp->irq, boardp);
5430 if (shp->dma_channel != NO_ISA_DMA) {
5431 ASC_DBG(1, "advansys_release: free_dma()\n");
5432 free_dma(shp->dma_channel);
5434 release_region(shp->io_port, boardp->asc_n_io_port);
5435 if (ASC_WIDE_BOARD(boardp)) {
5436 adv_sgblk_t *sgp = NULL;
5438 iounmap(boardp->ioremap_addr);
5439 kfree(boardp->orig_carrp);
5440 boardp->orig_carrp = NULL;
5441 if (boardp->orig_reqp) {
5442 kfree(boardp->orig_reqp);
5443 boardp->orig_reqp = boardp->adv_reqp = NULL;
5445 while ((sgp = boardp->adv_sgblkp) != NULL)
5447 boardp->adv_sgblkp = sgp->next_sgblkp;
5451 #ifdef CONFIG_PROC_FS
5452 ASC_ASSERT(boardp->prtbuf != NULL);
5453 kfree(boardp->prtbuf);
5454 #endif /* CONFIG_PROC_FS */
5455 scsi_unregister(shp);
5456 ASC_DBG(1, "advansys_release: end\n");
5463 * Return suitable for printing on the console with the argument
5464 * adapter's configuration information.
5466 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
5467 * otherwise the static 'info' array will be overrun.
5470 advansys_info(struct Scsi_Host *shp)
5472 static char info[ASC_INFO_SIZE];
5473 asc_board_t *boardp;
5474 ASC_DVC_VAR *asc_dvc_varp;
5475 ADV_DVC_VAR *adv_dvc_varp;
5478 char *widename = NULL;
5480 boardp = ASC_BOARDP(shp);
5481 if (ASC_NARROW_BOARD(boardp)) {
5482 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5483 ASC_DBG(1, "advansys_info: begin\n");
5484 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5485 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == ASC_IS_ISAPNP) {
5486 busname = "ISA PnP";
5490 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5492 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
5493 ASC_VERSION, busname,
5494 (ulong) shp->io_port,
5495 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5496 shp->irq, shp->dma_channel);
5498 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
5500 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
5502 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
5503 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
5504 == ASC_IS_PCI_ULTRA) {
5505 busname = "PCI Ultra";
5511 ASC_PRINT2( "advansys_info: board %d: unknown bus type %d\n",
5512 boardp->id, asc_dvc_varp->bus_type);
5514 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5516 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
5517 ASC_VERSION, busname,
5518 (ulong) shp->io_port,
5519 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5524 * Wide Adapter Information
5526 * Memory-mapped I/O is used instead of I/O space to access
5527 * the adapter, but display the I/O Port range. The Memory
5528 * I/O address is displayed through the driver /proc file.
5530 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5531 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5533 iolen = ADV_3550_IOLEN;
5534 widename = "Ultra-Wide";
5535 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
5537 iolen = ADV_38C0800_IOLEN;
5538 widename = "Ultra2-Wide";
5541 iolen = ADV_38C1600_IOLEN;
5542 widename = "Ultra3-Wide";
5544 sprintf(info, "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
5547 (ulong) adv_dvc_varp->iop_base,
5548 (ulong) adv_dvc_varp->iop_base + iolen - 1,
5551 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
5552 ASC_DBG(1, "advansys_info: end\n");
5557 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
5559 * This function always returns 0. Command return status is saved
5560 * in the 'scp' result field.
5563 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
5565 struct Scsi_Host *shp;
5566 asc_board_t *boardp;
5568 struct scsi_cmnd *done_scp;
5570 shp = scp->device->host;
5571 boardp = ASC_BOARDP(shp);
5572 ASC_STATS(shp, queuecommand);
5574 /* host_lock taken by mid-level prior to call but need to protect */
5575 /* against own ISR */
5576 spin_lock_irqsave(&boardp->lock, flags);
5579 * Block new commands while handling a reset or abort request.
5581 if (boardp->flags & ASC_HOST_IN_RESET) {
5583 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
5585 scp->result = HOST_BYTE(DID_RESET);
5588 * Add blocked requests to the board's 'done' queue. The queued
5589 * requests will be completed at the end of the abort or reset
5592 asc_enqueue(&boardp->done, scp, ASC_BACK);
5593 spin_unlock_irqrestore(&boardp->lock, flags);
5598 * Attempt to execute any waiting commands for the board.
5600 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
5602 "advansys_queuecommand: before asc_execute_queue() waiting\n");
5603 asc_execute_queue(&boardp->waiting);
5607 * Save the function pointer to Linux mid-level 'done' function
5608 * and attempt to execute the command.
5610 * If ASC_NOERROR is returned the request has been added to the
5611 * board's 'active' queue and will be completed by the interrupt
5614 * If ASC_BUSY is returned add the request to the board's per
5615 * target waiting list. This is the first time the request has
5616 * been tried. Add it to the back of the waiting list. It will be
5619 * If an error occurred, the request will have been placed on the
5620 * board's 'done' queue and must be completed before returning.
5622 scp->scsi_done = done;
5623 switch (asc_execute_scsi_cmnd(scp)) {
5627 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
5631 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
5632 /* Interrupts could be enabled here. */
5633 asc_scsi_done_list(done_scp);
5636 spin_unlock_irqrestore(&boardp->lock, flags);
5644 * Reset the bus associated with the command 'scp'.
5646 * This function runs its own thread. Interrupts must be blocked but
5647 * sleeping is allowed and no locking other than for host structures is
5648 * required. Returns SUCCESS or FAILED.
5651 advansys_reset(struct scsi_cmnd *scp)
5653 struct Scsi_Host *shp;
5654 asc_board_t *boardp;
5655 ASC_DVC_VAR *asc_dvc_varp;
5656 ADV_DVC_VAR *adv_dvc_varp;
5658 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5659 struct scsi_cmnd *tscp, *new_last_scp;
5663 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong) scp);
5665 #ifdef ADVANSYS_STATS
5666 if (scp->device->host != NULL) {
5667 ASC_STATS(scp->device->host, reset);
5669 #endif /* ADVANSYS_STATS */
5671 if ((shp = scp->device->host) == NULL) {
5672 scp->result = HOST_BYTE(DID_ERROR);
5676 boardp = ASC_BOARDP(shp);
5678 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
5681 * Check for re-entrancy.
5683 spin_lock_irqsave(&boardp->lock, flags);
5684 if (boardp->flags & ASC_HOST_IN_RESET) {
5685 spin_unlock_irqrestore(&boardp->lock, flags);
5688 boardp->flags |= ASC_HOST_IN_RESET;
5689 spin_unlock_irqrestore(&boardp->lock, flags);
5691 if (ASC_NARROW_BOARD(boardp)) {
5695 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5698 * Reset the chip and SCSI bus.
5700 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
5701 status = AscInitAsc1000Driver(asc_dvc_varp);
5703 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
5704 if (asc_dvc_varp->err_code) {
5706 "advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
5707 boardp->id, asc_dvc_varp->err_code);
5709 } else if (status) {
5711 "advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
5712 boardp->id, status);
5715 "advansys_reset: board %d: SCSI bus reset successful.\n",
5719 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
5720 spin_lock_irqsave(&boardp->lock, flags);
5726 * If the suggest reset bus flags are set, then reset the bus.
5727 * Otherwise only reset the device.
5729 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5732 * Reset the target's SCSI bus.
5734 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
5735 switch (AdvResetChipAndSB(adv_dvc_varp)) {
5737 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset successful.\n",
5742 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset error.\n",
5747 spin_lock_irqsave(&boardp->lock, flags);
5748 (void) AdvISR(adv_dvc_varp);
5750 /* Board lock is held. */
5753 * Dequeue all board 'done' requests. A pointer to the last request
5754 * is returned in 'last_scp'.
5756 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
5759 * Dequeue all board 'active' requests for all devices and set
5760 * the request status to DID_RESET. A pointer to the last request
5761 * is returned in 'last_scp'.
5763 if (done_scp == NULL) {
5764 done_scp = asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
5765 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5766 tscp->result = HOST_BYTE(DID_RESET);
5769 /* Append to 'done_scp' at the end with 'last_scp'. */
5770 ASC_ASSERT(last_scp != NULL);
5771 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5772 &boardp->active, &new_last_scp, ASC_TID_ALL);
5773 if (new_last_scp != NULL) {
5774 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5775 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5776 tscp->result = HOST_BYTE(DID_RESET);
5778 last_scp = new_last_scp;
5783 * Dequeue all 'waiting' requests and set the request status
5786 if (done_scp == NULL) {
5787 done_scp = asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
5788 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5789 tscp->result = HOST_BYTE(DID_RESET);
5792 /* Append to 'done_scp' at the end with 'last_scp'. */
5793 ASC_ASSERT(last_scp != NULL);
5794 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5795 &boardp->waiting, &new_last_scp, ASC_TID_ALL);
5796 if (new_last_scp != NULL) {
5797 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5798 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5799 tscp->result = HOST_BYTE(DID_RESET);
5801 last_scp = new_last_scp;
5805 /* Save the time of the most recently completed reset. */
5806 boardp->last_reset = jiffies;
5808 /* Clear reset flag. */
5809 boardp->flags &= ~ASC_HOST_IN_RESET;
5810 spin_unlock_irqrestore(&boardp->lock, flags);
5813 * Complete all the 'done_scp' requests.
5815 if (done_scp != NULL) {
5816 asc_scsi_done_list(done_scp);
5819 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
5825 * advansys_biosparam()
5827 * Translate disk drive geometry if the "BIOS greater than 1 GB"
5828 * support is enabled for a drive.
5830 * ip (information pointer) is an int array with the following definition:
5836 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
5837 sector_t capacity, int ip[])
5839 asc_board_t *boardp;
5841 ASC_DBG(1, "advansys_biosparam: begin\n");
5842 ASC_STATS(sdev->host, biosparam);
5843 boardp = ASC_BOARDP(sdev->host);
5844 if (ASC_NARROW_BOARD(boardp)) {
5845 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
5846 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
5854 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
5855 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
5863 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
5864 ASC_DBG(1, "advansys_biosparam: end\n");
5871 * This function is called from init/main.c at boot time.
5872 * It it passed LILO parameters that can be set from the
5873 * LILO command line or in /etc/lilo.conf.
5875 * It is used by the AdvanSys driver to either disable I/O
5876 * port scanning or to limit scanning to 1 - 4 I/O ports.
5877 * Regardless of the option setting EISA and PCI boards
5878 * will still be searched for and detected. This option
5879 * only affects searching for ISA and VL boards.
5881 * If ADVANSYS_DEBUG is defined the driver debug level may
5882 * be set using the 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port.
5885 * 1. Eliminate I/O port scanning:
5886 * boot: linux advansys=
5888 * boot: linux advansys=0x0
5889 * 2. Limit I/O port scanning to one I/O port:
5890 * boot: linux advansys=0x110
5891 * 3. Limit I/O port scanning to four I/O ports:
5892 * boot: linux advansys=0x110,0x210,0x230,0x330
5893 * 4. If ADVANSYS_DEBUG, limit I/O port scanning to four I/O ports and
5894 * set the driver debug level to 2.
5895 * boot: linux advansys=0x110,0x210,0x230,0x330,0xdeb2
5897 * ints[0] - number of arguments
5898 * ints[1] - first argument
5899 * ints[2] - second argument
5903 advansys_setup(char *str, int *ints)
5907 if (asc_iopflag == ASC_TRUE) {
5908 printk("AdvanSys SCSI: 'advansys' LILO option may appear only once\n");
5912 asc_iopflag = ASC_TRUE;
5914 if (ints[0] > ASC_NUM_IOPORT_PROBE) {
5915 #ifdef ADVANSYS_DEBUG
5916 if ((ints[0] == ASC_NUM_IOPORT_PROBE + 1) &&
5917 (ints[ASC_NUM_IOPORT_PROBE + 1] >> 4 == 0xdeb)) {
5918 asc_dbglvl = ints[ASC_NUM_IOPORT_PROBE + 1] & 0xf;
5920 #endif /* ADVANSYS_DEBUG */
5921 printk("AdvanSys SCSI: only %d I/O ports accepted\n",
5922 ASC_NUM_IOPORT_PROBE);
5923 #ifdef ADVANSYS_DEBUG
5925 #endif /* ADVANSYS_DEBUG */
5928 #ifdef ADVANSYS_DEBUG
5929 ASC_DBG1(1, "advansys_setup: ints[0] %d\n", ints[0]);
5930 for (i = 1; i < ints[0]; i++) {
5931 ASC_DBG2(1, " ints[%d] 0x%x", i, ints[i]);
5934 #endif /* ADVANSYS_DEBUG */
5936 for (i = 1; i <= ints[0] && i <= ASC_NUM_IOPORT_PROBE; i++) {
5937 asc_ioport[i-1] = ints[i];
5938 ASC_DBG2(1, "advansys_setup: asc_ioport[%d] 0x%x\n",
5939 i - 1, asc_ioport[i-1]);
5945 * --- Loadable Driver Support
5948 static struct scsi_host_template driver_template = {
5949 .proc_name = "advansys",
5950 #ifdef CONFIG_PROC_FS
5951 .proc_info = advansys_proc_info,
5954 .detect = advansys_detect,
5955 .release = advansys_release,
5956 .info = advansys_info,
5957 .queuecommand = advansys_queuecommand,
5958 .eh_bus_reset_handler = advansys_reset,
5959 .bios_param = advansys_biosparam,
5960 .slave_configure = advansys_slave_configure,
5962 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
5963 * must be set. The flag will be cleared in advansys_detect for non-ISA
5964 * adapters. Refer to the comment in scsi_module.c for more information.
5966 .unchecked_isa_dma = 1,
5968 * All adapters controlled by this driver are capable of large
5969 * scatter-gather lists. According to the mid-level SCSI documentation
5970 * this obviates any performance gain provided by setting
5971 * 'use_clustering'. But empirically while CPU utilization is increased
5972 * by enabling clustering, I/O throughput increases as well.
5974 .use_clustering = ENABLE_CLUSTERING,
5976 #include "scsi_module.c"
5980 * --- Miscellaneous Driver Functions
5984 * First-level interrupt handler.
5986 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
5987 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
5988 * is not referenced. 'dev_id' could be used to identify an interrupt passed
5989 * to the AdvanSys driver which is for a device sharing an interrupt with
5990 * an AdvanSys adapter.
5993 advansys_interrupt(int irq, void *dev_id, struct pt_regs *regs)
5997 asc_board_t *boardp;
5998 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5999 struct scsi_cmnd *new_last_scp;
6000 struct Scsi_Host *shp;
6002 ASC_DBG(1, "advansys_interrupt: begin\n");
6005 * Check for interrupts on all boards.
6006 * AscISR() will call asc_isr_callback().
6008 for (i = 0; i < asc_board_count; i++) {
6010 boardp = ASC_BOARDP(shp);
6011 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
6013 spin_lock_irqsave(&boardp->lock, flags);
6014 if (ASC_NARROW_BOARD(boardp)) {
6018 if (AscIsIntPending(shp->io_port)) {
6019 ASC_STATS(shp, interrupt);
6020 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
6021 AscISR(&boardp->dvc_var.asc_dvc_var);
6027 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
6028 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
6029 ASC_STATS(shp, interrupt);
6034 * Start waiting requests and create a list of completed requests.
6036 * If a reset request is being performed for the board, the reset
6037 * handler will complete pending requests after it has completed.
6039 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
6040 ASC_DBG2(1, "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
6041 (ulong) done_scp, (ulong) last_scp);
6043 /* Start any waiting commands for the board. */
6044 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
6045 ASC_DBG(1, "advansys_interrupt: before asc_execute_queue()\n");
6046 asc_execute_queue(&boardp->waiting);
6050 * Add to the list of requests that must be completed.
6052 * 'done_scp' will always be NULL on the first iteration
6053 * of this loop. 'last_scp' is set at the same time as
6056 if (done_scp == NULL) {
6057 done_scp = asc_dequeue_list(&boardp->done, &last_scp,
6060 ASC_ASSERT(last_scp != NULL);
6061 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
6062 &boardp->done, &new_last_scp, ASC_TID_ALL);
6063 if (new_last_scp != NULL) {
6064 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
6065 last_scp = new_last_scp;
6069 spin_unlock_irqrestore(&boardp->lock, flags);
6073 * If interrupts were enabled on entry, then they
6074 * are now enabled here.
6076 * Complete all requests on the done list.
6079 asc_scsi_done_list(done_scp);
6081 ASC_DBG(1, "advansys_interrupt: end\n");
6086 * Set the number of commands to queue per device for the
6087 * specified host adapter.
6090 advansys_slave_configure(struct scsi_device *device)
6092 asc_board_t *boardp;
6094 boardp = ASC_BOARDP(device->host);
6095 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
6097 * Save a pointer to the device and set its initial/maximum
6098 * queue depth. Only save the pointer for a lun0 dev though.
6100 if(device->lun == 0)
6101 boardp->device[device->id] = device;
6102 if(device->tagged_supported) {
6103 if (ASC_NARROW_BOARD(boardp)) {
6104 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6105 boardp->dvc_var.asc_dvc_var.max_dvc_qng[device->id]);
6107 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6108 boardp->dvc_var.adv_dvc_var.max_dvc_qng);
6111 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
6113 ASC_DBG4(1, "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
6114 (ulong) device, (ulong) boardp, device->id, device->queue_depth);
6119 * Complete all requests on the singly linked list pointed
6122 * Interrupts can be enabled on entry.
6125 asc_scsi_done_list(struct scsi_cmnd *scp)
6127 struct scsi_cmnd *tscp;
6129 ASC_DBG(2, "asc_scsi_done_list: begin\n");
6130 while (scp != NULL) {
6131 asc_board_t *boardp;
6134 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong) scp);
6135 tscp = REQPNEXT(scp);
6136 scp->host_scribble = NULL;
6138 boardp = ASC_BOARDP(scp->device->host);
6140 if (ASC_NARROW_BOARD(boardp))
6141 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6143 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6146 dma_unmap_sg(dev, (struct scatterlist *)scp->request_buffer,
6147 scp->use_sg, scp->sc_data_direction);
6148 else if (scp->request_bufflen)
6149 dma_unmap_single(dev, scp->SCp.dma_handle,
6150 scp->request_bufflen, scp->sc_data_direction);
6152 ASC_STATS(scp->device->host, done);
6153 ASC_ASSERT(scp->scsi_done != NULL);
6155 scp->scsi_done(scp);
6159 ASC_DBG(2, "asc_scsi_done_list: done\n");
6164 * Execute a single 'Scsi_Cmnd'.
6166 * The function 'done' is called when the request has been completed.
6170 * host - board controlling device
6171 * device - device to send command
6172 * target - target of device
6173 * lun - lun of device
6174 * cmd_len - length of SCSI CDB
6175 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
6176 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
6178 * if (use_sg == 0) {
6179 * request_buffer - buffer address for request
6180 * request_bufflen - length of request buffer
6182 * request_buffer - pointer to scatterlist structure
6185 * sense_buffer - sense command buffer
6187 * result (4 bytes of an int):
6189 * 0 SCSI Status Byte Code
6190 * 1 SCSI One Byte Message Code
6192 * 3 Mid-Level Error Code
6194 * host driver fields:
6195 * SCp - Scsi_Pointer used for command processing status
6196 * scsi_done - used to save caller's done function
6197 * host_scribble - used for pointer to another struct scsi_cmnd
6199 * If this function returns ASC_NOERROR the request has been enqueued
6200 * on the board's 'active' queue and will be completed from the
6201 * interrupt handler.
6203 * If this function returns ASC_NOERROR the request has been enqueued
6204 * on the board's 'done' queue and must be completed by the caller.
6206 * If ASC_BUSY is returned the request will be enqueued by the
6207 * caller on the target's waiting queue and re-tried later.
6210 asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
6212 asc_board_t *boardp;
6213 ASC_DVC_VAR *asc_dvc_varp;
6214 ADV_DVC_VAR *adv_dvc_varp;
6215 ADV_SCSI_REQ_Q *adv_scsiqp;
6216 struct scsi_device *device;
6219 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
6220 (ulong) scp, (ulong) scp->scsi_done);
6222 boardp = ASC_BOARDP(scp->device->host);
6223 device = boardp->device[scp->device->id];
6225 if (ASC_NARROW_BOARD(boardp)) {
6227 * Build and execute Narrow Board request.
6230 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6233 * Build Asc Library request structure using the
6234 * global structures 'asc_scsi_req' and 'asc_sg_head'.
6236 * If an error is returned, then the request has been
6237 * queued on the board done queue. It will be completed
6240 * asc_build_req() can not return ASC_BUSY.
6242 if (asc_build_req(boardp, scp) == ASC_ERROR) {
6243 ASC_STATS(scp->device->host, build_error);
6248 * Execute the command. If there is no error, add the command
6249 * to the active queue.
6251 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
6253 ASC_STATS(scp->device->host, exe_noerror);
6255 * Increment monotonically increasing per device successful
6256 * request counter. Wrapping doesn't matter.
6258 boardp->reqcnt[scp->device->id]++;
6259 asc_enqueue(&boardp->active, scp, ASC_BACK);
6261 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
6265 * Caller will enqueue request on the target's waiting queue
6268 ASC_STATS(scp->device->host, exe_busy);
6272 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6273 boardp->id, asc_dvc_varp->err_code);
6274 ASC_STATS(scp->device->host, exe_error);
6275 scp->result = HOST_BYTE(DID_ERROR);
6276 asc_enqueue(&boardp->done, scp, ASC_BACK);
6280 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
6281 boardp->id, asc_dvc_varp->err_code);
6282 ASC_STATS(scp->device->host, exe_unknown);
6283 scp->result = HOST_BYTE(DID_ERROR);
6284 asc_enqueue(&boardp->done, scp, ASC_BACK);
6289 * Build and execute Wide Board request.
6291 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6294 * Build and get a pointer to an Adv Library request structure.
6296 * If the request is successfully built then send it below,
6297 * otherwise return with an error.
6299 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
6301 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
6304 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
6306 * If busy is returned the request has not been enqueued.
6307 * It will be enqueued by the caller on the target's waiting
6308 * queue and retried later.
6310 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
6311 * count wide board busy conditions. They are updated in
6312 * adv_build_req and adv_get_sglist, respectively.
6317 * If an error is returned, then the request has been
6318 * queued on the board done queue. It will be completed
6322 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
6323 ASC_STATS(scp->device->host, build_error);
6328 * Execute the command. If there is no error, add the command
6329 * to the active queue.
6331 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
6333 ASC_STATS(scp->device->host, exe_noerror);
6335 * Increment monotonically increasing per device successful
6336 * request counter. Wrapping doesn't matter.
6338 boardp->reqcnt[scp->device->id]++;
6339 asc_enqueue(&boardp->active, scp, ASC_BACK);
6341 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
6345 * Caller will enqueue request on the target's waiting queue
6348 ASC_STATS(scp->device->host, exe_busy);
6352 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6353 boardp->id, adv_dvc_varp->err_code);
6354 ASC_STATS(scp->device->host, exe_error);
6355 scp->result = HOST_BYTE(DID_ERROR);
6356 asc_enqueue(&boardp->done, scp, ASC_BACK);
6360 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
6361 boardp->id, adv_dvc_varp->err_code);
6362 ASC_STATS(scp->device->host, exe_unknown);
6363 scp->result = HOST_BYTE(DID_ERROR);
6364 asc_enqueue(&boardp->done, scp, ASC_BACK);
6369 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
6374 * Build a request structure for the Asc Library (Narrow Board).
6376 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
6377 * used to build the request.
6379 * If an error occurs, then queue the request on the board done
6380 * queue and return ASC_ERROR.
6383 asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
6385 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6388 * Mutually exclusive access is required to 'asc_scsi_q' and
6389 * 'asc_sg_head' until after the request is started.
6391 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
6394 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
6396 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
6399 * Build the ASC_SCSI_Q request.
6401 * For narrow boards a CDB length maximum of 12 bytes
6404 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
6406 "asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
6407 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
6408 scp->result = HOST_BYTE(DID_ERROR);
6409 asc_enqueue(&boardp->done, scp, ASC_BACK);
6412 asc_scsi_q.cdbptr = &scp->cmnd[0];
6413 asc_scsi_q.q2.cdb_len = scp->cmd_len;
6414 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
6415 asc_scsi_q.q1.target_lun = scp->device->lun;
6416 asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
6417 asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6418 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
6421 * If there are any outstanding requests for the current target,
6422 * then every 255th request send an ORDERED request. This heuristic
6423 * tries to retain the benefit of request sorting while preventing
6424 * request starvation. 255 is the max number of tags or pending commands
6425 * a device may have outstanding.
6427 * The request count is incremented below for every successfully
6431 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
6432 (boardp->reqcnt[scp->device->id] % 255) == 0) {
6433 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
6435 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
6439 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
6442 if (scp->use_sg == 0) {
6444 * CDB request of single contiguous buffer.
6446 ASC_STATS(scp->device->host, cont_cnt);
6447 scp->SCp.dma_handle = scp->request_bufflen ?
6448 dma_map_single(dev, scp->request_buffer,
6449 scp->request_bufflen, scp->sc_data_direction) : 0;
6450 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
6451 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
6452 ASC_STATS_ADD(scp->device->host, cont_xfer,
6453 ASC_CEILING(scp->request_bufflen, 512));
6454 asc_scsi_q.q1.sg_queue_cnt = 0;
6455 asc_scsi_q.sg_head = NULL;
6458 * CDB scatter-gather request list.
6462 struct scatterlist *slp;
6464 slp = (struct scatterlist *)scp->request_buffer;
6465 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6467 if (use_sg > scp->device->host->sg_tablesize) {
6469 "asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
6470 boardp->id, use_sg, scp->device->host->sg_tablesize);
6471 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6472 scp->result = HOST_BYTE(DID_ERROR);
6473 asc_enqueue(&boardp->done, scp, ASC_BACK);
6477 ASC_STATS(scp->device->host, sg_cnt);
6480 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
6481 * structure to point to it.
6483 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
6485 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
6486 asc_scsi_q.sg_head = &asc_sg_head;
6487 asc_scsi_q.q1.data_cnt = 0;
6488 asc_scsi_q.q1.data_addr = 0;
6489 /* This is a byte value, otherwise it would need to be swapped. */
6490 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
6491 ASC_STATS_ADD(scp->device->host, sg_elem, asc_sg_head.entry_cnt);
6494 * Convert scatter-gather list into ASC_SG_HEAD list.
6496 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
6497 asc_sg_head.sg_list[sgcnt].addr = cpu_to_le32(sg_dma_address(slp));
6498 asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(sg_dma_len(slp));
6499 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6503 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
6504 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6510 * Build a request structure for the Adv Library (Wide Board).
6512 * If an adv_req_t can not be allocated to issue the request,
6513 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
6515 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
6516 * microcode for DMA addresses or math operations are byte swapped
6517 * to little-endian order.
6520 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
6521 ADV_SCSI_REQ_Q **adv_scsiqpp)
6524 ADV_SCSI_REQ_Q *scsiqp;
6527 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6530 * Allocate an adv_req_t structure from the board to execute
6533 if (boardp->adv_reqp == NULL) {
6534 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
6535 ASC_STATS(scp->device->host, adv_build_noreq);
6538 reqp = boardp->adv_reqp;
6539 boardp->adv_reqp = reqp->next_reqp;
6540 reqp->next_reqp = NULL;
6544 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
6546 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6549 * Initialize the structure.
6551 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
6554 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
6556 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
6559 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
6564 * Build the ADV_SCSI_REQ_Q request.
6568 * Set CDB length and copy it to the request structure.
6569 * For wide boards a CDB length maximum of 16 bytes
6572 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
6574 "adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
6575 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
6576 scp->result = HOST_BYTE(DID_ERROR);
6577 asc_enqueue(&boardp->done, scp, ASC_BACK);
6580 scsiqp->cdb_len = scp->cmd_len;
6581 /* Copy first 12 CDB bytes to cdb[]. */
6582 for (i = 0; i < scp->cmd_len && i < 12; i++) {
6583 scsiqp->cdb[i] = scp->cmnd[i];
6585 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
6586 for (; i < scp->cmd_len; i++) {
6587 scsiqp->cdb16[i - 12] = scp->cmnd[i];
6590 scsiqp->target_id = scp->device->id;
6591 scsiqp->target_lun = scp->device->lun;
6593 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6594 scsiqp->sense_len = sizeof(scp->sense_buffer);
6597 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
6601 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6602 scsiqp->vdata_addr = scp->request_buffer;
6603 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
6605 if (scp->use_sg == 0) {
6607 * CDB request of single contiguous buffer.
6609 reqp->sgblkp = NULL;
6610 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6611 if (scp->request_bufflen) {
6612 scsiqp->vdata_addr = scp->request_buffer;
6613 scp->SCp.dma_handle =
6614 dma_map_single(dev, scp->request_buffer,
6615 scp->request_bufflen, scp->sc_data_direction);
6617 scsiqp->vdata_addr = 0;
6618 scp->SCp.dma_handle = 0;
6620 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
6621 scsiqp->sg_list_ptr = NULL;
6622 scsiqp->sg_real_addr = 0;
6623 ASC_STATS(scp->device->host, cont_cnt);
6624 ASC_STATS_ADD(scp->device->host, cont_xfer,
6625 ASC_CEILING(scp->request_bufflen, 512));
6628 * CDB scatter-gather request list.
6630 struct scatterlist *slp;
6633 slp = (struct scatterlist *)scp->request_buffer;
6634 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6636 if (use_sg > ADV_MAX_SG_LIST) {
6638 "adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
6639 boardp->id, use_sg, scp->device->host->sg_tablesize);
6640 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6641 scp->result = HOST_BYTE(DID_ERROR);
6642 asc_enqueue(&boardp->done, scp, ASC_BACK);
6645 * Free the 'adv_req_t' structure by adding it back to the
6648 reqp->next_reqp = boardp->adv_reqp;
6649 boardp->adv_reqp = reqp;
6654 if ((ret = adv_get_sglist(boardp, reqp, scp, use_sg)) != ADV_SUCCESS) {
6656 * Free the adv_req_t structure by adding it back to the
6659 reqp->next_reqp = boardp->adv_reqp;
6660 boardp->adv_reqp = reqp;
6665 ASC_STATS(scp->device->host, sg_cnt);
6666 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
6669 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6670 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6672 *adv_scsiqpp = scsiqp;
6678 * Build scatter-gather list for Adv Library (Wide Board).
6680 * Additional ADV_SG_BLOCK structures will need to be allocated
6681 * if the total number of scatter-gather elements exceeds
6682 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
6683 * assumed to be physically contiguous.
6686 * ADV_SUCCESS(1) - SG List successfully created
6687 * ADV_ERROR(-1) - SG List creation failed
6690 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, int use_sg)
6692 adv_sgblk_t *sgblkp;
6693 ADV_SCSI_REQ_Q *scsiqp;
6694 struct scatterlist *slp;
6696 ADV_SG_BLOCK *sg_block, *prev_sg_block;
6697 ADV_PADDR sg_block_paddr;
6700 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6701 slp = (struct scatterlist *) scp->request_buffer;
6702 sg_elem_cnt = use_sg;
6703 prev_sg_block = NULL;
6704 reqp->sgblkp = NULL;
6709 * Allocate a 'adv_sgblk_t' structure from the board free
6710 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
6711 * (15) scatter-gather elements.
6713 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
6714 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
6715 ASC_STATS(scp->device->host, adv_build_nosg);
6718 * Allocation failed. Free 'adv_sgblk_t' structures already
6719 * allocated for the request.
6721 while ((sgblkp = reqp->sgblkp) != NULL)
6723 /* Remove 'sgblkp' from the request list. */
6724 reqp->sgblkp = sgblkp->next_sgblkp;
6726 /* Add 'sgblkp' to the board free list. */
6727 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6728 boardp->adv_sgblkp = sgblkp;
6732 /* Complete 'adv_sgblk_t' board allocation. */
6733 boardp->adv_sgblkp = sgblkp->next_sgblkp;
6734 sgblkp->next_sgblkp = NULL;
6737 * Get 8 byte aligned virtual and physical addresses for
6738 * the allocated ADV_SG_BLOCK structure.
6740 sg_block = (ADV_SG_BLOCK *) ADV_8BALIGN(&sgblkp->sg_block);
6741 sg_block_paddr = virt_to_bus(sg_block);
6744 * Check if this is the first 'adv_sgblk_t' for the request.
6746 if (reqp->sgblkp == NULL)
6748 /* Request's first scatter-gather block. */
6749 reqp->sgblkp = sgblkp;
6752 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
6755 scsiqp->sg_list_ptr = sg_block;
6756 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
6759 /* Request's second or later scatter-gather block. */
6760 sgblkp->next_sgblkp = reqp->sgblkp;
6761 reqp->sgblkp = sgblkp;
6764 * Point the previous ADV_SG_BLOCK structure to
6765 * the newly allocated ADV_SG_BLOCK structure.
6767 ASC_ASSERT(prev_sg_block != NULL);
6768 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
6772 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
6774 sg_block->sg_list[i].sg_addr = cpu_to_le32(sg_dma_address(slp));
6775 sg_block->sg_list[i].sg_count = cpu_to_le32(sg_dma_len(slp));
6776 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6778 if (--sg_elem_cnt == 0)
6779 { /* Last ADV_SG_BLOCK and scatter-gather entry. */
6780 sg_block->sg_cnt = i + 1;
6781 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
6786 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
6787 prev_sg_block = sg_block;
6794 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6796 * Interrupt callback function for the Narrow SCSI Asc Library.
6799 asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6801 asc_board_t *boardp;
6802 struct scsi_cmnd *scp;
6803 struct Scsi_Host *shp;
6806 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
6807 (ulong) asc_dvc_varp, (ulong) qdonep);
6808 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6811 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6812 * command that has been completed.
6814 scp = (struct scsi_cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
6815 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong) scp);
6818 ASC_PRINT("asc_isr_callback: scp is NULL\n");
6821 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6824 * If the request's host pointer is not valid, display a
6825 * message and return.
6827 shp = scp->device->host;
6828 for (i = 0; i < asc_board_count; i++) {
6829 if (asc_host[i] == shp) {
6833 if (i == asc_board_count) {
6835 "asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
6836 (ulong) scp, (ulong) shp);
6840 ASC_STATS(shp, callback);
6841 ASC_DBG1(1, "asc_isr_callback: shp 0x%lx\n", (ulong) shp);
6844 * If the request isn't found on the active queue, it may
6845 * have been removed to handle a reset request.
6846 * Display a message and return.
6848 boardp = ASC_BOARDP(shp);
6849 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
6850 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
6852 "asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
6853 boardp->id, (ulong) scp);
6858 * 'qdonep' contains the command's ending status.
6860 switch (qdonep->d3.done_stat) {
6862 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
6866 * If an INQUIRY command completed successfully, then call
6867 * the AscInquiryHandling() function to set-up the device.
6869 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
6870 (scp->request_bufflen - qdonep->remain_bytes) >= 8)
6872 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
6873 (ASC_SCSI_INQUIRY *) scp->request_buffer);
6877 * Check for an underrun condition.
6879 * If there was no error and an underrun condition, then
6880 * then return the number of underrun bytes.
6882 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
6883 qdonep->remain_bytes <= scp->request_bufflen) {
6884 ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
6885 (unsigned) qdonep->remain_bytes);
6886 scp->resid = qdonep->remain_bytes;
6891 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
6892 switch (qdonep->d3.host_stat) {
6893 case QHSTA_NO_ERROR:
6894 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6895 ASC_DBG(2, "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
6896 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6897 sizeof(scp->sense_buffer));
6899 * Note: The 'status_byte()' macro used by target drivers
6900 * defined in scsi.h shifts the status byte returned by
6901 * host drivers right by 1 bit. This is why target drivers
6902 * also use right shifted status byte definitions. For
6903 * instance target drivers use CHECK_CONDITION, defined to
6904 * 0x1, instead of the SCSI defined check condition value
6905 * of 0x2. Host drivers are supposed to return the status
6906 * byte as it is defined by SCSI.
6908 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6909 STATUS_BYTE(qdonep->d3.scsi_stat);
6911 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6916 /* QHSTA error occurred */
6917 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
6918 qdonep->d3.host_stat);
6919 scp->result = HOST_BYTE(DID_BAD_TARGET);
6924 case QD_ABORTED_BY_HOST:
6925 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
6926 scp->result = HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.scsi_msg) |
6927 STATUS_BYTE(qdonep->d3.scsi_stat);
6931 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", qdonep->d3.done_stat);
6932 scp->result = HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.scsi_msg) |
6933 STATUS_BYTE(qdonep->d3.scsi_stat);
6938 * If the 'init_tidmask' bit isn't already set for the target and the
6939 * current request finished normally, then set the bit for the target
6940 * to indicate that a device is present.
6942 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6943 qdonep->d3.done_stat == QD_NO_ERROR &&
6944 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6945 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6949 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
6950 * function, add the command to the end of the board's done queue.
6951 * The done function for the command will be called from
6952 * advansys_interrupt().
6954 asc_enqueue(&boardp->done, scp, ASC_BACK);
6960 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6962 * Callback function for the Wide SCSI Adv Library.
6965 adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6967 asc_board_t *boardp;
6969 adv_sgblk_t *sgblkp;
6970 struct scsi_cmnd *scp;
6971 struct Scsi_Host *shp;
6976 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6977 (ulong) adv_dvc_varp, (ulong) scsiqp);
6978 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6981 * Get the adv_req_t structure for the command that has been
6982 * completed. The adv_req_t structure actually contains the
6983 * completed ADV_SCSI_REQ_Q structure.
6985 reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6986 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong) reqp);
6988 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6993 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6994 * command that has been completed.
6996 * Note: The adv_req_t request structure and adv_sgblk_t structure,
6997 * if any, are dropped, because a board structure pointer can not be
7001 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong) scp);
7003 ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
7006 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7009 * If the request's host pointer is not valid, display a message
7012 shp = scp->device->host;
7013 for (i = 0; i < asc_board_count; i++) {
7014 if (asc_host[i] == shp) {
7019 * Note: If the host structure is not found, the adv_req_t request
7020 * structure and adv_sgblk_t structure, if any, is dropped.
7022 if (i == asc_board_count) {
7024 "adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
7025 (ulong) scp, (ulong) shp);
7029 ASC_STATS(shp, callback);
7030 ASC_DBG1(1, "adv_isr_callback: shp 0x%lx\n", (ulong) shp);
7033 * If the request isn't found on the active queue, it may have been
7034 * removed to handle a reset request. Display a message and return.
7036 * Note: Because the structure may still be in use don't attempt
7037 * to free the adv_req_t and adv_sgblk_t, if any, structures.
7039 boardp = ASC_BOARDP(shp);
7040 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
7041 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
7043 "adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
7044 boardp->id, (ulong) scp);
7049 * 'done_status' contains the command's ending status.
7051 switch (scsiqp->done_status) {
7053 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
7057 * Check for an underrun condition.
7059 * If there was no error and an underrun condition, then
7060 * then return the number of underrun bytes.
7062 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
7063 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
7064 resid_cnt <= scp->request_bufflen) {
7065 ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
7067 scp->resid = resid_cnt;
7072 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
7073 switch (scsiqp->host_status) {
7074 case QHSTA_NO_ERROR:
7075 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
7076 ASC_DBG(2, "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
7077 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7078 sizeof(scp->sense_buffer));
7080 * Note: The 'status_byte()' macro used by target drivers
7081 * defined in scsi.h shifts the status byte returned by
7082 * host drivers right by 1 bit. This is why target drivers
7083 * also use right shifted status byte definitions. For
7084 * instance target drivers use CHECK_CONDITION, defined to
7085 * 0x1, instead of the SCSI defined check condition value
7086 * of 0x2. Host drivers are supposed to return the status
7087 * byte as it is defined by SCSI.
7089 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7090 STATUS_BYTE(scsiqp->scsi_status);
7092 scp->result = STATUS_BYTE(scsiqp->scsi_status);
7097 /* Some other QHSTA error occurred. */
7098 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
7099 scsiqp->host_status);
7100 scp->result = HOST_BYTE(DID_BAD_TARGET);
7105 case QD_ABORTED_BY_HOST:
7106 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
7107 scp->result = HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
7111 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", scsiqp->done_status);
7112 scp->result = HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
7117 * If the 'init_tidmask' bit isn't already set for the target and the
7118 * current request finished normally, then set the bit for the target
7119 * to indicate that a device is present.
7121 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7122 scsiqp->done_status == QD_NO_ERROR &&
7123 scsiqp->host_status == QHSTA_NO_ERROR) {
7124 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7128 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
7129 * function, add the command to the end of the board's done queue.
7130 * The done function for the command will be called from
7131 * advansys_interrupt().
7133 asc_enqueue(&boardp->done, scp, ASC_BACK);
7136 * Free all 'adv_sgblk_t' structures allocated for the request.
7138 while ((sgblkp = reqp->sgblkp) != NULL)
7140 /* Remove 'sgblkp' from the request list. */
7141 reqp->sgblkp = sgblkp->next_sgblkp;
7143 /* Add 'sgblkp' to the board free list. */
7144 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7145 boardp->adv_sgblkp = sgblkp;
7149 * Free the adv_req_t structure used with the command by adding
7150 * it back to the board free list.
7152 reqp->next_reqp = boardp->adv_reqp;
7153 boardp->adv_reqp = reqp;
7155 ASC_DBG(1, "adv_isr_callback: done\n");
7161 * adv_async_callback() - Adv Library asynchronous event callback function.
7164 adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
7168 case ADV_ASYNC_SCSI_BUS_RESET_DET:
7170 * The firmware detected a SCSI Bus reset.
7172 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
7175 case ADV_ASYNC_RDMA_FAILURE:
7177 * Handle RDMA failure by resetting the SCSI Bus and
7178 * possibly the chip if it is unresponsive. Log the error
7179 * with a unique code.
7181 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
7182 AdvResetChipAndSB(adv_dvc_varp);
7185 case ADV_HOST_SCSI_BUS_RESET:
7187 * Host generated SCSI bus reset occurred.
7189 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
7193 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
7199 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
7200 * to indicate a command is queued for the device.
7202 * 'flag' may be either ASC_FRONT or ASC_BACK.
7204 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7207 asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
7211 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
7212 (ulong) ascq, (ulong) reqp, flag);
7213 ASC_ASSERT(reqp != NULL);
7214 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
7215 tid = REQPTID(reqp);
7216 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7217 if (flag == ASC_FRONT) {
7218 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
7219 ascq->q_first[tid] = reqp;
7220 /* If the queue was empty, set the last pointer. */
7221 if (ascq->q_last[tid] == NULL) {
7222 ascq->q_last[tid] = reqp;
7224 } else { /* ASC_BACK */
7225 if (ascq->q_last[tid] != NULL) {
7226 ascq->q_last[tid]->host_scribble = (unsigned char *)reqp;
7228 ascq->q_last[tid] = reqp;
7229 reqp->host_scribble = NULL;
7230 /* If the queue was empty, set the first pointer. */
7231 if (ascq->q_first[tid] == NULL) {
7232 ascq->q_first[tid] = reqp;
7235 /* The queue has at least one entry, set its bit. */
7236 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
7237 #ifdef ADVANSYS_STATS
7238 /* Maintain request queue statistics. */
7239 ascq->q_tot_cnt[tid]++;
7240 ascq->q_cur_cnt[tid]++;
7241 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
7242 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
7243 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
7244 tid, ascq->q_max_cnt[tid]);
7246 REQPTIME(reqp) = REQTIMESTAMP();
7247 #endif /* ADVANSYS_STATS */
7248 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong) reqp);
7253 * Return first queued 'REQP' on the specified queue for
7254 * the specified target device. Clear the 'tidmask' bit for
7255 * the device if no more commands are left queued for it.
7257 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7260 asc_dequeue(asc_queue_t *ascq, int tid)
7264 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7265 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7266 if ((reqp = ascq->q_first[tid]) != NULL) {
7267 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
7268 ascq->q_first[tid] = REQPNEXT(reqp);
7269 /* If the queue is empty, clear its bit and the last pointer. */
7270 if (ascq->q_first[tid] == NULL) {
7271 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7272 ASC_ASSERT(ascq->q_last[tid] == reqp);
7273 ascq->q_last[tid] = NULL;
7275 #ifdef ADVANSYS_STATS
7276 /* Maintain request queue statistics. */
7277 ascq->q_cur_cnt[tid]--;
7278 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7279 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
7280 #endif /* ADVANSYS_STATS */
7282 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong) reqp);
7287 * Return a pointer to a singly linked list of all the requests queued
7288 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
7290 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
7291 * the last request returned in the singly linked list.
7293 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
7294 * then all queued requests are concatenated into one list and
7297 * Note: If 'lastpp' is used to append a new list to the end of
7298 * an old list, only change the old list last pointer if '*lastpp'
7299 * (or the function return value) is not NULL, i.e. use a temporary
7300 * variable for 'lastpp' and check its value after the function return
7301 * before assigning it to the list last pointer.
7303 * Unfortunately collecting queuing time statistics adds overhead to
7304 * the function that isn't inherent to the function's algorithm.
7307 asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
7312 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7313 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
7316 * If 'tid' is not ASC_TID_ALL, return requests only for
7317 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
7318 * requests for all tids.
7320 if (tid != ASC_TID_ALL) {
7321 /* Return all requests for the specified 'tid'. */
7322 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
7323 /* List is empty; Set first and last return pointers to NULL. */
7324 firstp = lastp = NULL;
7326 firstp = ascq->q_first[tid];
7327 lastp = ascq->q_last[tid];
7328 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
7329 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7330 #ifdef ADVANSYS_STATS
7333 ascq->q_cur_cnt[tid] = 0;
7334 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7335 REQTIMESTAT("asc_dequeue_list", ascq, reqp, tid);
7338 #endif /* ADVANSYS_STATS */
7341 /* Return all requests for all tids. */
7342 firstp = lastp = NULL;
7343 for (i = 0; i <= ADV_MAX_TID; i++) {
7344 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
7345 if (firstp == NULL) {
7346 firstp = ascq->q_first[i];
7347 lastp = ascq->q_last[i];
7349 ASC_ASSERT(lastp != NULL);
7350 lastp->host_scribble = (unsigned char *)ascq->q_first[i];
7351 lastp = ascq->q_last[i];
7353 ascq->q_first[i] = ascq->q_last[i] = NULL;
7354 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7355 #ifdef ADVANSYS_STATS
7356 ascq->q_cur_cnt[i] = 0;
7357 #endif /* ADVANSYS_STATS */
7360 #ifdef ADVANSYS_STATS
7363 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7364 REQTIMESTAT("asc_dequeue_list", ascq, reqp, reqp->device->id);
7367 #endif /* ADVANSYS_STATS */
7372 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong) firstp);
7377 * Remove the specified 'REQP' from the specified queue for
7378 * the specified target device. Clear the 'tidmask' bit for the
7379 * device if no more commands are left queued for it.
7381 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
7383 * Return ASC_TRUE if the command was found and removed,
7384 * otherwise return ASC_FALSE.
7387 asc_rmqueue(asc_queue_t *ascq, REQP reqp)
7391 int ret = ASC_FALSE;
7393 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
7394 (ulong) ascq, (ulong) reqp);
7395 ASC_ASSERT(reqp != NULL);
7397 tid = REQPTID(reqp);
7398 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7401 * Handle the common case of 'reqp' being the first
7402 * entry on the queue.
7404 if (reqp == ascq->q_first[tid]) {
7406 ascq->q_first[tid] = REQPNEXT(reqp);
7407 /* If the queue is now empty, clear its bit and the last pointer. */
7408 if (ascq->q_first[tid] == NULL) {
7409 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7410 ASC_ASSERT(ascq->q_last[tid] == reqp);
7411 ascq->q_last[tid] = NULL;
7413 } else if (ascq->q_first[tid] != NULL) {
7414 ASC_ASSERT(ascq->q_last[tid] != NULL);
7416 * Because the case of 'reqp' being the first entry has been
7417 * handled above and it is known the queue is not empty, if
7418 * 'reqp' is found on the queue it is guaranteed the queue will
7419 * not become empty and that 'q_first[tid]' will not be changed.
7421 * Set 'prevp' to the first entry, 'currp' to the second entry,
7422 * and search for 'reqp'.
7424 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
7425 currp; prevp = currp, currp = REQPNEXT(currp)) {
7426 if (currp == reqp) {
7428 prevp->host_scribble = (unsigned char *)REQPNEXT(currp);
7429 reqp->host_scribble = NULL;
7430 if (ascq->q_last[tid] == reqp) {
7431 ascq->q_last[tid] = prevp;
7437 #ifdef ADVANSYS_STATS
7438 /* Maintain request queue statistics. */
7439 if (ret == ASC_TRUE) {
7440 ascq->q_cur_cnt[tid]--;
7441 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
7443 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7444 #endif /* ADVANSYS_STATS */
7445 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong) reqp, ret);
7450 * Execute as many queued requests as possible for the specified queue.
7452 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
7455 asc_execute_queue(asc_queue_t *ascq)
7457 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
7461 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong) ascq);
7463 * Execute queued commands for devices attached to
7464 * the current board in round-robin fashion.
7466 scan_tidmask = ascq->q_tidmask;
7468 for (i = 0; i <= ADV_MAX_TID; i++) {
7469 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
7470 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
7471 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7472 } else if (asc_execute_scsi_cmnd((struct scsi_cmnd *) reqp)
7474 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7476 * The request returned ASC_BUSY. Enqueue at the front of
7477 * target's waiting list to maintain correct ordering.
7479 asc_enqueue(ascq, reqp, ASC_FRONT);
7483 } while (scan_tidmask);
7487 #ifdef CONFIG_PROC_FS
7489 * asc_prt_board_devices()
7491 * Print driver information for devices attached to the board.
7493 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7494 * cf. asc_prt_line().
7496 * Return the number of characters copied into 'cp'. No more than
7497 * 'cplen' characters will be copied to 'cp'.
7500 asc_prt_board_devices(struct Scsi_Host *shp, char *cp, int cplen)
7502 asc_board_t *boardp;
7509 boardp = ASC_BOARDP(shp);
7513 len = asc_prt_line(cp, leftlen,
7514 "\nDevice Information for AdvanSys SCSI Host %d:\n", shp->host_no);
7517 if (ASC_NARROW_BOARD(boardp)) {
7518 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7520 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7523 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
7525 for (i = 0; i <= ADV_MAX_TID; i++) {
7526 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
7527 len = asc_prt_line(cp, leftlen, " %X,", i);
7531 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
7538 * Display Wide Board BIOS Information.
7541 asc_prt_adv_bios(struct Scsi_Host *shp, char *cp, int cplen)
7543 asc_board_t *boardp;
7547 ushort major, minor, letter;
7549 boardp = ASC_BOARDP(shp);
7553 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
7557 * If the BIOS saved a valid signature, then fill in
7558 * the BIOS code segment base address.
7560 if (boardp->bios_signature != 0x55AA) {
7561 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
7563 len = asc_prt_line(cp, leftlen,
7564 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
7566 len = asc_prt_line(cp, leftlen,
7567 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
7570 major = (boardp->bios_version >> 12) & 0xF;
7571 minor = (boardp->bios_version >> 8) & 0xF;
7572 letter = (boardp->bios_version & 0xFF);
7574 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
7575 major, minor, letter >= 26 ? '?' : letter + 'A');
7579 * Current available ROM BIOS release is 3.1I for UW
7580 * and 3.2I for U2W. This code doesn't differentiate
7581 * UW and U2W boards.
7583 if (major < 3 || (major <= 3 && minor < 1) ||
7584 (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
7585 len = asc_prt_line(cp, leftlen,
7586 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
7588 len = asc_prt_line(cp, leftlen,
7589 "ftp://ftp.connectcom.net/pub\n");
7598 * Add serial number to information bar if signature AAh
7599 * is found in at bit 15-9 (7 bits) of word 1.
7601 * Serial Number consists fo 12 alpha-numeric digits.
7603 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
7604 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
7605 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
7606 * 5 - Product revision (A-J) Word0: " "
7608 * Signature Word1: 15-9 (7 bits)
7609 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
7610 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
7612 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
7614 * Note 1: Only production cards will have a serial number.
7616 * Note 2: Signature is most significant 7 bits (0xFE).
7618 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
7621 asc_get_eeprom_string(ushort *serialnum, uchar *cp)
7625 if ((serialnum[1] & 0xFE00) != ((ushort) 0xAA << 8)) {
7629 * First word - 6 digits.
7633 /* Product type - 1st digit. */
7634 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
7635 /* Product type is P=Prototype */
7640 /* Manufacturing location - 2nd digit. */
7641 *cp++ = 'A' + ((w & 0x1C00) >> 10);
7643 /* Product ID - 3rd, 4th digits. */
7645 *cp++ = '0' + (num / 100);
7647 *cp++ = '0' + (num / 10);
7649 /* Product revision - 5th digit. */
7650 *cp++ = 'A' + (num % 10);
7660 * If bit 15 of third word is set, then the
7661 * last digit of the year is greater than 7.
7663 if (serialnum[2] & 0x8000) {
7664 *cp++ = '8' + ((w & 0x1C0) >> 6);
7666 *cp++ = '0' + ((w & 0x1C0) >> 6);
7669 /* Week of year - 7th, 8th digits. */
7671 *cp++ = '0' + num / 10;
7678 w = serialnum[2] & 0x7FFF;
7680 /* Serial number - 9th digit. */
7681 *cp++ = 'A' + (w / 1000);
7683 /* 10th, 11th, 12th digits. */
7685 *cp++ = '0' + num / 100;
7687 *cp++ = '0' + num / 10;
7691 *cp = '\0'; /* Null Terminate the string. */
7697 * asc_prt_asc_board_eeprom()
7699 * Print board EEPROM configuration.
7701 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7702 * cf. asc_prt_line().
7704 * Return the number of characters copied into 'cp'. No more than
7705 * 'cplen' characters will be copied to 'cp'.
7708 asc_prt_asc_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7710 asc_board_t *boardp;
7711 ASC_DVC_VAR *asc_dvc_varp;
7718 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
7719 #endif /* CONFIG_ISA */
7720 uchar serialstr[13];
7722 boardp = ASC_BOARDP(shp);
7723 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
7724 ep = &boardp->eep_config.asc_eep;
7729 len = asc_prt_line(cp, leftlen,
7730 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7733 if (asc_get_eeprom_string((ushort *) &ep->adapter_info[0], serialstr) ==
7735 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7738 if (ep->adapter_info[5] == 0xBB) {
7739 len = asc_prt_line(cp, leftlen,
7740 " Default Settings Used for EEPROM-less Adapter.\n");
7743 len = asc_prt_line(cp, leftlen,
7744 " Serial Number Signature Not Present.\n");
7749 len = asc_prt_line(cp, leftlen,
7750 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7751 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, ep->max_tag_qng);
7754 len = asc_prt_line(cp, leftlen,
7755 " cntl 0x%x, no_scam 0x%x\n",
7756 ep->cntl, ep->no_scam);
7759 len = asc_prt_line(cp, leftlen,
7762 for (i = 0; i <= ASC_MAX_TID; i++) {
7763 len = asc_prt_line(cp, leftlen, " %d", i);
7766 len = asc_prt_line(cp, leftlen, "\n");
7769 len = asc_prt_line(cp, leftlen,
7772 for (i = 0; i <= ASC_MAX_TID; i++) {
7773 len = asc_prt_line(cp, leftlen, " %c",
7774 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7777 len = asc_prt_line(cp, leftlen, "\n");
7780 len = asc_prt_line(cp, leftlen,
7781 " Command Queuing: ");
7783 for (i = 0; i <= ASC_MAX_TID; i++) {
7784 len = asc_prt_line(cp, leftlen, " %c",
7785 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7788 len = asc_prt_line(cp, leftlen, "\n");
7791 len = asc_prt_line(cp, leftlen,
7794 for (i = 0; i <= ASC_MAX_TID; i++) {
7795 len = asc_prt_line(cp, leftlen, " %c",
7796 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7799 len = asc_prt_line(cp, leftlen, "\n");
7802 len = asc_prt_line(cp, leftlen,
7803 " Synchronous Transfer:");
7805 for (i = 0; i <= ASC_MAX_TID; i++) {
7806 len = asc_prt_line(cp, leftlen, " %c",
7807 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7810 len = asc_prt_line(cp, leftlen, "\n");
7814 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
7815 len = asc_prt_line(cp, leftlen,
7816 " Host ISA DMA speed: %d MB/S\n",
7817 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
7820 #endif /* CONFIG_ISA */
7826 * asc_prt_adv_board_eeprom()
7828 * Print board EEPROM configuration.
7830 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7831 * cf. asc_prt_line().
7833 * Return the number of characters copied into 'cp'. No more than
7834 * 'cplen' characters will be copied to 'cp'.
7837 asc_prt_adv_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7839 asc_board_t *boardp;
7840 ADV_DVC_VAR *adv_dvc_varp;
7846 uchar serialstr[13];
7847 ADVEEP_3550_CONFIG *ep_3550 = NULL;
7848 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
7849 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
7852 ushort sdtr_speed = 0;
7854 boardp = ASC_BOARDP(shp);
7855 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
7856 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7858 ep_3550 = &boardp->eep_config.adv_3550_eep;
7859 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7861 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
7864 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
7870 len = asc_prt_line(cp, leftlen,
7871 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7874 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7876 wordp = &ep_3550->serial_number_word1;
7877 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7879 wordp = &ep_38C0800->serial_number_word1;
7882 wordp = &ep_38C1600->serial_number_word1;
7885 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
7886 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7889 len = asc_prt_line(cp, leftlen,
7890 " Serial Number Signature Not Present.\n");
7894 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7896 len = asc_prt_line(cp, leftlen,
7897 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7898 ep_3550->adapter_scsi_id, ep_3550->max_host_qng,
7899 ep_3550->max_dvc_qng);
7901 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7903 len = asc_prt_line(cp, leftlen,
7904 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7905 ep_38C0800->adapter_scsi_id, ep_38C0800->max_host_qng,
7906 ep_38C0800->max_dvc_qng);
7910 len = asc_prt_line(cp, leftlen,
7911 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7912 ep_38C1600->adapter_scsi_id, ep_38C1600->max_host_qng,
7913 ep_38C1600->max_dvc_qng);
7916 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7918 word = ep_3550->termination;
7919 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7921 word = ep_38C0800->termination_lvd;
7924 word = ep_38C1600->termination_lvd;
7928 termstr = "Low Off/High Off";
7931 termstr = "Low Off/High On";
7934 termstr = "Low On/High On";
7938 termstr = "Automatic";
7942 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7944 len = asc_prt_line(cp, leftlen,
7945 " termination: %u (%s), bios_ctrl: 0x%x\n",
7946 ep_3550->termination, termstr, ep_3550->bios_ctrl);
7948 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7950 len = asc_prt_line(cp, leftlen,
7951 " termination: %u (%s), bios_ctrl: 0x%x\n",
7952 ep_38C0800->termination_lvd, termstr, ep_38C0800->bios_ctrl);
7956 len = asc_prt_line(cp, leftlen,
7957 " termination: %u (%s), bios_ctrl: 0x%x\n",
7958 ep_38C1600->termination_lvd, termstr, ep_38C1600->bios_ctrl);
7962 len = asc_prt_line(cp, leftlen,
7965 for (i = 0; i <= ADV_MAX_TID; i++) {
7966 len = asc_prt_line(cp, leftlen, " %X", i);
7969 len = asc_prt_line(cp, leftlen, "\n");
7972 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7974 word = ep_3550->disc_enable;
7975 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7977 word = ep_38C0800->disc_enable;
7980 word = ep_38C1600->disc_enable;
7982 len = asc_prt_line(cp, leftlen,
7985 for (i = 0; i <= ADV_MAX_TID; i++) {
7986 len = asc_prt_line(cp, leftlen, " %c",
7987 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7990 len = asc_prt_line(cp, leftlen, "\n");
7993 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7995 word = ep_3550->tagqng_able;
7996 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7998 word = ep_38C0800->tagqng_able;
8001 word = ep_38C1600->tagqng_able;
8003 len = asc_prt_line(cp, leftlen,
8004 " Command Queuing: ");
8006 for (i = 0; i <= ADV_MAX_TID; i++) {
8007 len = asc_prt_line(cp, leftlen, " %c",
8008 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8011 len = asc_prt_line(cp, leftlen, "\n");
8014 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8016 word = ep_3550->start_motor;
8017 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8019 word = ep_38C0800->start_motor;
8022 word = ep_38C1600->start_motor;
8024 len = asc_prt_line(cp, leftlen,
8027 for (i = 0; i <= ADV_MAX_TID; i++) {
8028 len = asc_prt_line(cp, leftlen, " %c",
8029 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8032 len = asc_prt_line(cp, leftlen, "\n");
8035 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8037 len = asc_prt_line(cp, leftlen,
8038 " Synchronous Transfer:");
8040 for (i = 0; i <= ADV_MAX_TID; i++) {
8041 len = asc_prt_line(cp, leftlen, " %c",
8042 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8045 len = asc_prt_line(cp, leftlen, "\n");
8049 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8051 len = asc_prt_line(cp, leftlen,
8052 " Ultra Transfer: ");
8054 for (i = 0; i <= ADV_MAX_TID; i++) {
8055 len = asc_prt_line(cp, leftlen, " %c",
8056 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8059 len = asc_prt_line(cp, leftlen, "\n");
8063 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8065 word = ep_3550->wdtr_able;
8066 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8068 word = ep_38C0800->wdtr_able;
8071 word = ep_38C1600->wdtr_able;
8073 len = asc_prt_line(cp, leftlen,
8074 " Wide Transfer: ");
8076 for (i = 0; i <= ADV_MAX_TID; i++) {
8077 len = asc_prt_line(cp, leftlen, " %c",
8078 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8081 len = asc_prt_line(cp, leftlen, "\n");
8084 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
8085 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600)
8087 len = asc_prt_line(cp, leftlen,
8088 " Synchronous Transfer Speed (Mhz):\n ");
8090 for (i = 0; i <= ADV_MAX_TID; i++) {
8095 sdtr_speed = adv_dvc_varp->sdtr_speed1;
8098 sdtr_speed = adv_dvc_varp->sdtr_speed2;
8101 sdtr_speed = adv_dvc_varp->sdtr_speed3;
8104 sdtr_speed = adv_dvc_varp->sdtr_speed4;
8106 switch (sdtr_speed & ADV_MAX_TID)
8108 case 0: speed_str = "Off"; break;
8109 case 1: speed_str = " 5"; break;
8110 case 2: speed_str = " 10"; break;
8111 case 3: speed_str = " 20"; break;
8112 case 4: speed_str = " 40"; break;
8113 case 5: speed_str = " 80"; break;
8114 default: speed_str = "Unk"; break;
8116 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
8120 len = asc_prt_line(cp, leftlen, "\n ");
8125 len = asc_prt_line(cp, leftlen, "\n");
8133 * asc_prt_driver_conf()
8135 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8136 * cf. asc_prt_line().
8138 * Return the number of characters copied into 'cp'. No more than
8139 * 'cplen' characters will be copied to 'cp'.
8142 asc_prt_driver_conf(struct Scsi_Host *shp, char *cp, int cplen)
8144 asc_board_t *boardp;
8150 boardp = ASC_BOARDP(shp);
8155 len = asc_prt_line(cp, leftlen,
8156 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
8160 len = asc_prt_line(cp, leftlen,
8161 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
8162 shp->host_busy, shp->last_reset, shp->max_id, shp->max_lun,
8166 len = asc_prt_line(cp, leftlen,
8167 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
8168 shp->unique_id, shp->can_queue, shp->this_id, shp->sg_tablesize,
8172 len = asc_prt_line(cp, leftlen,
8173 " unchecked_isa_dma %d, use_clustering %d\n",
8174 shp->unchecked_isa_dma, shp->use_clustering);
8177 len = asc_prt_line(cp, leftlen,
8178 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
8179 boardp->flags, boardp->last_reset, jiffies, boardp->asc_n_io_port);
8182 /* 'shp->n_io_port' may be truncated because it is only one byte. */
8183 len = asc_prt_line(cp, leftlen,
8184 " io_port 0x%x, n_io_port 0x%x\n",
8185 shp->io_port, shp->n_io_port);
8188 if (ASC_NARROW_BOARD(boardp)) {
8189 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
8191 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
8198 * asc_prt_asc_board_info()
8200 * Print dynamic board configuration information.
8202 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8203 * cf. asc_prt_line().
8205 * Return the number of characters copied into 'cp'. No more than
8206 * 'cplen' characters will be copied to 'cp'.
8209 asc_prt_asc_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8211 asc_board_t *boardp;
8219 int renegotiate = 0;
8221 boardp = ASC_BOARDP(shp);
8222 v = &boardp->dvc_var.asc_dvc_var;
8223 c = &boardp->dvc_cfg.asc_dvc_cfg;
8224 chip_scsi_id = c->chip_scsi_id;
8229 len = asc_prt_line(cp, leftlen,
8230 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8234 len = asc_prt_line(cp, leftlen,
8235 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
8236 c->chip_version, c->lib_version, c->lib_serial_no, c->mcode_date);
8239 len = asc_prt_line(cp, leftlen,
8240 " mcode_version 0x%x, err_code %u\n",
8241 c->mcode_version, v->err_code);
8244 /* Current number of commands waiting for the host. */
8245 len = asc_prt_line(cp, leftlen,
8246 " Total Command Pending: %d\n", v->cur_total_qng);
8249 len = asc_prt_line(cp, leftlen,
8250 " Command Queuing:");
8252 for (i = 0; i <= ASC_MAX_TID; i++) {
8253 if ((chip_scsi_id == i) ||
8254 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8257 len = asc_prt_line(cp, leftlen, " %X:%c",
8258 i, (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8261 len = asc_prt_line(cp, leftlen, "\n");
8264 /* Current number of commands waiting for a device. */
8265 len = asc_prt_line(cp, leftlen,
8266 " Command Queue Pending:");
8268 for (i = 0; i <= ASC_MAX_TID; i++) {
8269 if ((chip_scsi_id == i) ||
8270 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8273 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
8276 len = asc_prt_line(cp, leftlen, "\n");
8279 /* Current limit on number of commands that can be sent to a device. */
8280 len = asc_prt_line(cp, leftlen,
8281 " Command Queue Limit:");
8283 for (i = 0; i <= ASC_MAX_TID; i++) {
8284 if ((chip_scsi_id == i) ||
8285 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8288 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
8291 len = asc_prt_line(cp, leftlen, "\n");
8294 /* Indicate whether the device has returned queue full status. */
8295 len = asc_prt_line(cp, leftlen,
8296 " Command Queue Full:");
8298 for (i = 0; i <= ASC_MAX_TID; i++) {
8299 if ((chip_scsi_id == i) ||
8300 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8303 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
8304 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
8305 i, boardp->queue_full_cnt[i]);
8307 len = asc_prt_line(cp, leftlen, " %X:N", i);
8311 len = asc_prt_line(cp, leftlen, "\n");
8314 len = asc_prt_line(cp, leftlen,
8315 " Synchronous Transfer:");
8317 for (i = 0; i <= ASC_MAX_TID; i++) {
8318 if ((chip_scsi_id == i) ||
8319 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8322 len = asc_prt_line(cp, leftlen, " %X:%c",
8323 i, (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8326 len = asc_prt_line(cp, leftlen, "\n");
8329 for (i = 0; i <= ASC_MAX_TID; i++) {
8330 uchar syn_period_ix;
8332 if ((chip_scsi_id == i) ||
8333 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8334 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
8338 len = asc_prt_line(cp, leftlen, " %X:", i);
8341 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0)
8343 len = asc_prt_line(cp, leftlen, " Asynchronous");
8348 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 1);
8350 len = asc_prt_line(cp, leftlen,
8351 " Transfer Period Factor: %d (%d.%d Mhz),",
8352 v->sdtr_period_tbl[syn_period_ix],
8353 250 / v->sdtr_period_tbl[syn_period_ix],
8354 ASC_TENTHS(250, v->sdtr_period_tbl[syn_period_ix]));
8357 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8358 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
8362 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8363 len = asc_prt_line(cp, leftlen, "*\n");
8367 len = asc_prt_line(cp, leftlen, "\n");
8374 len = asc_prt_line(cp, leftlen,
8375 " * = Re-negotiation pending before next command.\n");
8383 * asc_prt_adv_board_info()
8385 * Print dynamic board configuration information.
8387 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8388 * cf. asc_prt_line().
8390 * Return the number of characters copied into 'cp'. No more than
8391 * 'cplen' characters will be copied to 'cp'.
8394 asc_prt_adv_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8396 asc_board_t *boardp;
8403 AdvPortAddr iop_base;
8404 ushort chip_scsi_id;
8408 ushort sdtr_able, wdtr_able;
8409 ushort wdtr_done, sdtr_done;
8411 int renegotiate = 0;
8413 boardp = ASC_BOARDP(shp);
8414 v = &boardp->dvc_var.adv_dvc_var;
8415 c = &boardp->dvc_cfg.adv_dvc_cfg;
8416 iop_base = v->iop_base;
8417 chip_scsi_id = v->chip_scsi_id;
8422 len = asc_prt_line(cp, leftlen,
8423 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8427 len = asc_prt_line(cp, leftlen,
8428 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
8430 AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1) & CABLE_DETECT,
8434 len = asc_prt_line(cp, leftlen,
8435 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
8436 c->chip_version, c->lib_version, c->mcode_date, c->mcode_version);
8439 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8440 len = asc_prt_line(cp, leftlen,
8441 " Queuing Enabled:");
8443 for (i = 0; i <= ADV_MAX_TID; i++) {
8444 if ((chip_scsi_id == i) ||
8445 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8449 len = asc_prt_line(cp, leftlen, " %X:%c",
8450 i, (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8453 len = asc_prt_line(cp, leftlen, "\n");
8456 len = asc_prt_line(cp, leftlen,
8459 for (i = 0; i <= ADV_MAX_TID; i++) {
8460 if ((chip_scsi_id == i) ||
8461 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8465 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, lrambyte);
8467 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8470 len = asc_prt_line(cp, leftlen, "\n");
8473 len = asc_prt_line(cp, leftlen,
8474 " Command Pending:");
8476 for (i = 0; i <= ADV_MAX_TID; i++) {
8477 if ((chip_scsi_id == i) ||
8478 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8482 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, lrambyte);
8484 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8487 len = asc_prt_line(cp, leftlen, "\n");
8490 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8491 len = asc_prt_line(cp, leftlen,
8494 for (i = 0; i <= ADV_MAX_TID; i++) {
8495 if ((chip_scsi_id == i) ||
8496 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8500 len = asc_prt_line(cp, leftlen, " %X:%c",
8501 i, (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8504 len = asc_prt_line(cp, leftlen, "\n");
8507 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
8508 len = asc_prt_line(cp, leftlen,
8509 " Transfer Bit Width:");
8511 for (i = 0; i <= ADV_MAX_TID; i++) {
8512 if ((chip_scsi_id == i) ||
8513 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8517 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8520 len = asc_prt_line(cp, leftlen, " %X:%d",
8521 i, (lramword & 0x8000) ? 16 : 8);
8524 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
8525 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8526 len = asc_prt_line(cp, leftlen, "*");
8531 len = asc_prt_line(cp, leftlen, "\n");
8534 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8535 len = asc_prt_line(cp, leftlen,
8536 " Synchronous Enabled:");
8538 for (i = 0; i <= ADV_MAX_TID; i++) {
8539 if ((chip_scsi_id == i) ||
8540 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8544 len = asc_prt_line(cp, leftlen, " %X:%c",
8545 i, (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8548 len = asc_prt_line(cp, leftlen, "\n");
8551 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
8552 for (i = 0; i <= ADV_MAX_TID; i++) {
8554 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8556 lramword &= ~0x8000;
8558 if ((chip_scsi_id == i) ||
8559 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8560 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
8564 len = asc_prt_line(cp, leftlen, " %X:", i);
8567 if ((lramword & 0x1F) == 0) /* Check for REQ/ACK Offset 0. */
8569 len = asc_prt_line(cp, leftlen, " Asynchronous");
8573 len = asc_prt_line(cp, leftlen, " Transfer Period Factor: ");
8576 if ((lramword & 0x1F00) == 0x1100) /* 80 Mhz */
8578 len = asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
8580 } else if ((lramword & 0x1F00) == 0x1000) /* 40 Mhz */
8582 len = asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
8584 } else /* 20 Mhz or below. */
8586 period = (((lramword >> 8) * 25) + 50)/4;
8588 if (period == 0) /* Should never happen. */
8590 len = asc_prt_line(cp, leftlen, "%d (? Mhz), ");
8594 len = asc_prt_line(cp, leftlen,
8596 period, 250/period, ASC_TENTHS(250, period));
8601 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8606 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8607 len = asc_prt_line(cp, leftlen, "*\n");
8611 len = asc_prt_line(cp, leftlen, "\n");
8618 len = asc_prt_line(cp, leftlen,
8619 " * = Re-negotiation pending before next command.\n");
8629 * Copy proc information to a read buffer taking into account the current
8630 * read offset in the file and the remaining space in the read buffer.
8633 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
8634 char *cp, int cplen)
8638 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
8639 (unsigned) offset, (unsigned) advoffset, cplen);
8640 if (offset <= advoffset) {
8641 /* Read offset below current offset, copy everything. */
8642 cnt = min(cplen, leftlen);
8643 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8644 (ulong) curbuf, (ulong) cp, cnt);
8645 memcpy(curbuf, cp, cnt);
8646 } else if (offset < advoffset + cplen) {
8647 /* Read offset within current range, partial copy. */
8648 cnt = (advoffset + cplen) - offset;
8649 cp = (cp + cplen) - cnt;
8650 cnt = min(cnt, leftlen);
8651 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8652 (ulong) curbuf, (ulong) cp, cnt);
8653 memcpy(curbuf, cp, cnt);
8661 * If 'cp' is NULL print to the console, otherwise print to a buffer.
8663 * Return 0 if printing to the console, otherwise return the number of
8664 * bytes written to the buffer.
8666 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
8667 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
8670 asc_prt_line(char *buf, int buflen, char *fmt, ...)
8674 char s[ASC_PRTLINE_SIZE];
8676 va_start(args, fmt);
8677 ret = vsprintf(s, fmt, args);
8678 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
8683 ret = min(buflen, ret);
8684 memcpy(buf, s, ret);
8689 #endif /* CONFIG_PROC_FS */
8693 * --- Functions Required by the Asc Library
8697 * Delay for 'n' milliseconds. Don't use the 'jiffies'
8698 * global variable which is incremented once every 5 ms
8699 * from a timer interrupt, because this function may be
8700 * called when interrupts are disabled.
8703 DvcSleepMilliSecond(ADV_DCNT n)
8705 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
8710 * Currently and inline noop but leave as a placeholder.
8711 * Leave DvcEnterCritical() as a noop placeholder.
8714 DvcEnterCritical(void)
8720 * Critical sections are all protected by the board spinlock.
8721 * Leave DvcLeaveCritical() as a noop placeholder.
8724 DvcLeaveCritical(ulong flags)
8731 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8733 * Calling/Exit State:
8737 * Output an ASC_SCSI_Q structure to the chip
8740 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8744 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8745 AscSetChipLramAddr(iop_base, s_addr);
8746 for (i = 0; i < 2 * words; i += 2) {
8747 if (i == 4 || i == 20) {
8750 outpw(iop_base + IOP_RAM_DATA,
8751 ((ushort) outbuf[i + 1] << 8) | outbuf[i]);
8757 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8759 * Calling/Exit State:
8763 * Input an ASC_QDONE_INFO structure from the chip
8766 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8771 AscSetChipLramAddr(iop_base, s_addr);
8772 for (i = 0; i < 2 * words; i += 2) {
8776 word = inpw(iop_base + IOP_RAM_DATA);
8777 inbuf[i] = word & 0xff;
8778 inbuf[i + 1] = (word >> 8) & 0xff;
8780 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
8784 * Read a PCI configuration byte.
8787 DvcReadPCIConfigByte(
8788 ASC_DVC_VAR *asc_dvc,
8793 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8795 #else /* !defined(CONFIG_PCI) */
8797 #endif /* !defined(CONFIG_PCI) */
8801 * Write a PCI configuration byte.
8804 DvcWritePCIConfigByte(
8805 ASC_DVC_VAR *asc_dvc,
8810 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8811 #endif /* CONFIG_PCI */
8815 * Return the BIOS address of the adapter at the specified
8816 * I/O port and with the specified bus type.
8818 STATIC ushort __init
8819 AscGetChipBiosAddress(
8827 * The PCI BIOS is re-located by the motherboard BIOS. Because
8828 * of this the driver can not determine where a PCI BIOS is
8829 * loaded and executes.
8831 if (bus_type & ASC_IS_PCI)
8837 if((bus_type & ASC_IS_EISA) != 0)
8839 cfg_lsw = AscGetEisaChipCfg(iop_base);
8841 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
8842 (cfg_lsw * ASC_BIOS_BANK_SIZE));
8845 #endif /* CONFIG_ISA */
8847 cfg_lsw = AscGetChipCfgLsw(iop_base);
8850 * ISA PnP uses the top bit as the 32K BIOS flag
8852 if (bus_type == ASC_IS_ISAPNP)
8857 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
8864 * --- Functions Required by the Adv Library
8870 * Return the physical address of 'vaddr' and set '*lenp' to the
8871 * number of physically contiguous bytes that follow 'vaddr'.
8872 * 'flag' indicates the type of structure whose physical address
8873 * is being translated.
8875 * Note: Because Linux currently doesn't page the kernel and all
8876 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
8879 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
8880 uchar *vaddr, ADV_SDCNT *lenp, int flag)
8884 paddr = virt_to_bus(vaddr);
8887 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
8888 (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
8894 * Read a PCI configuration byte.
8897 DvcAdvReadPCIConfigByte(
8898 ADV_DVC_VAR *asc_dvc,
8903 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8905 #else /* CONFIG_PCI */
8907 #endif /* CONFIG_PCI */
8911 * Write a PCI configuration byte.
8914 DvcAdvWritePCIConfigByte(
8915 ADV_DVC_VAR *asc_dvc,
8920 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8921 #else /* CONFIG_PCI */
8923 #endif /* CONFIG_PCI */
8927 * --- Tracing and Debugging Functions
8930 #ifdef ADVANSYS_STATS
8931 #ifdef CONFIG_PROC_FS
8933 * asc_prt_board_stats()
8935 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8936 * cf. asc_prt_line().
8938 * Return the number of characters copied into 'cp'. No more than
8939 * 'cplen' characters will be copied to 'cp'.
8942 asc_prt_board_stats(struct Scsi_Host *shp, char *cp, int cplen)
8947 struct asc_stats *s;
8948 asc_board_t *boardp;
8953 boardp = ASC_BOARDP(shp);
8954 s = &boardp->asc_stats;
8956 len = asc_prt_line(cp, leftlen,
8957 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", shp->host_no);
8960 len = asc_prt_line(cp, leftlen,
8961 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
8962 s->queuecommand, s->reset, s->biosparam, s->interrupt);
8965 len = asc_prt_line(cp, leftlen,
8966 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
8967 s->callback, s->done, s->build_error, s->adv_build_noreq,
8971 len = asc_prt_line(cp, leftlen,
8972 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
8973 s->exe_noerror, s->exe_busy, s->exe_error, s->exe_unknown);
8977 * Display data transfer statistics.
8979 if (s->cont_cnt > 0) {
8980 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
8983 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
8985 ASC_TENTHS(s->cont_xfer, 2));
8988 /* Contiguous transfer average size */
8989 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
8990 (s->cont_xfer/2)/s->cont_cnt,
8991 ASC_TENTHS((s->cont_xfer/2), s->cont_cnt));
8995 if (s->sg_cnt > 0) {
8997 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
8998 s->sg_cnt, s->sg_elem);
9001 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
9003 ASC_TENTHS(s->sg_xfer, 2));
9006 /* Scatter gather transfer statistics */
9007 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
9008 s->sg_elem/s->sg_cnt,
9009 ASC_TENTHS(s->sg_elem, s->sg_cnt));
9012 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
9013 (s->sg_xfer/2)/s->sg_elem,
9014 ASC_TENTHS((s->sg_xfer/2), s->sg_elem));
9017 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
9018 (s->sg_xfer/2)/s->sg_cnt,
9019 ASC_TENTHS((s->sg_xfer/2), s->sg_cnt));
9024 * Display request queuing statistics.
9026 len = asc_prt_line(cp, leftlen,
9027 " Active and Waiting Request Queues (Time Unit: %d HZ):\n", HZ);
9035 * asc_prt_target_stats()
9037 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
9038 * cf. asc_prt_line().
9040 * This is separated from asc_prt_board_stats because a full set
9041 * of targets will overflow ASC_PRTBUF_SIZE.
9043 * Return the number of characters copied into 'cp'. No more than
9044 * 'cplen' characters will be copied to 'cp'.
9047 asc_prt_target_stats(struct Scsi_Host *shp, int tgt_id, char *cp, int cplen)
9052 struct asc_stats *s;
9053 ushort chip_scsi_id;
9054 asc_board_t *boardp;
9055 asc_queue_t *active;
9056 asc_queue_t *waiting;
9061 boardp = ASC_BOARDP(shp);
9062 s = &boardp->asc_stats;
9064 active = &ASC_BOARDP(shp)->active;
9065 waiting = &ASC_BOARDP(shp)->waiting;
9067 if (ASC_NARROW_BOARD(boardp)) {
9068 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
9070 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
9073 if ((chip_scsi_id == tgt_id) ||
9074 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
9079 if (active->q_tot_cnt[tgt_id] > 0 || waiting->q_tot_cnt[tgt_id] > 0) {
9080 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
9083 len = asc_prt_line(cp, leftlen,
9084 " active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
9085 active->q_cur_cnt[tgt_id], active->q_max_cnt[tgt_id],
9086 active->q_tot_cnt[tgt_id],
9087 active->q_min_tim[tgt_id], active->q_max_tim[tgt_id],
9088 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9089 (active->q_tot_tim[tgt_id]/active->q_tot_cnt[tgt_id]),
9090 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9091 ASC_TENTHS(active->q_tot_tim[tgt_id],
9092 active->q_tot_cnt[tgt_id]));
9095 len = asc_prt_line(cp, leftlen,
9096 " waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
9097 waiting->q_cur_cnt[tgt_id], waiting->q_max_cnt[tgt_id],
9098 waiting->q_tot_cnt[tgt_id],
9099 waiting->q_min_tim[tgt_id], waiting->q_max_tim[tgt_id],
9100 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9101 (waiting->q_tot_tim[tgt_id]/waiting->q_tot_cnt[tgt_id]),
9102 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9103 ASC_TENTHS(waiting->q_tot_tim[tgt_id],
9104 waiting->q_tot_cnt[tgt_id]));
9111 #endif /* CONFIG_PROC_FS */
9112 #endif /* ADVANSYS_STATS */
9114 #ifdef ADVANSYS_DEBUG
9116 * asc_prt_scsi_host()
9119 asc_prt_scsi_host(struct Scsi_Host *s)
9121 asc_board_t *boardp;
9123 boardp = ASC_BOARDP(s);
9125 printk("Scsi_Host at addr 0x%lx\n", (ulong) s);
9127 " host_busy %u, host_no %d, last_reset %d,\n",
9128 s->host_busy, s->host_no,
9129 (unsigned) s->last_reset);
9132 " base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
9133 (ulong) s->base, (ulong) s->io_port, s->n_io_port, s->irq);
9136 " dma_channel %d, this_id %d, can_queue %d,\n",
9137 s->dma_channel, s->this_id, s->can_queue);
9140 " cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
9141 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
9143 if (ASC_NARROW_BOARD(boardp)) {
9144 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
9145 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
9147 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
9148 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
9153 * asc_prt_scsi_cmnd()
9156 asc_prt_scsi_cmnd(struct scsi_cmnd *s)
9158 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong) s);
9161 " host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
9162 (ulong) s->device->host, (ulong) s->device, s->device->id, s->device->lun,
9163 s->device->channel);
9165 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
9168 "sc_data_direction %u, resid %d\n",
9169 s->sc_data_direction, s->resid);
9172 " use_sg %u, sglist_len %u\n",
9173 s->use_sg, s->sglist_len);
9176 " serial_number 0x%x, retries %d, allowed %d\n",
9177 (unsigned) s->serial_number, s->retries, s->allowed);
9180 " timeout_per_command %d\n",
9181 s->timeout_per_command);
9184 " scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
9185 (ulong) s->scsi_done, (ulong) s->done,
9186 (ulong) s->host_scribble, s->result);
9189 " tag %u, pid %u\n",
9190 (unsigned) s->tag, (unsigned) s->pid);
9194 * asc_prt_asc_dvc_var()
9197 asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
9199 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong) h);
9202 " iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
9203 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
9206 " bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
9207 h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
9208 (unsigned) h->init_sdtr);
9211 " sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
9212 (unsigned) h->sdtr_done, (unsigned) h->use_tagged_qng,
9213 (unsigned) h->unit_not_ready, (unsigned) h->chip_no);
9216 " queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
9217 (unsigned) h->queue_full_or_busy, (unsigned) h->start_motor,
9218 (unsigned) h->scsi_reset_wait);
9221 " is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
9222 (unsigned) h->is_in_int, (unsigned) h->max_total_qng,
9223 (unsigned) h->cur_total_qng, (unsigned) h->in_critical_cnt);
9226 " last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
9227 (unsigned) h->last_q_shortage, (unsigned) h->init_state,
9228 (unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
9231 " cfg 0x%lx, irq_no 0x%x\n",
9232 (ulong) h->cfg, (unsigned) h->irq_no);
9236 * asc_prt_asc_dvc_cfg()
9239 asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
9241 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong) h);
9244 " can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
9245 h->can_tagged_qng, h->cmd_qng_enabled);
9247 " disc_enable 0x%x, sdtr_enable 0x%x,\n",
9248 h->disc_enable, h->sdtr_enable);
9251 " chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
9252 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
9256 " pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
9257 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
9261 " mcode_version %d, overrun_buf 0x%lx\n",
9262 h->mcode_version, (ulong) h->overrun_buf);
9266 * asc_prt_asc_scsi_q()
9269 asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
9274 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong) q);
9277 " target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
9278 q->q2.target_ix, q->q1.target_lun,
9279 (ulong) q->q2.srb_ptr, q->q2.tag_code);
9282 " data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9283 (ulong) le32_to_cpu(q->q1.data_addr),
9284 (ulong) le32_to_cpu(q->q1.data_cnt),
9285 (ulong) le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
9288 " cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
9289 (ulong) q->cdbptr, q->q2.cdb_len,
9290 (ulong) q->sg_head, q->q1.sg_queue_cnt);
9294 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong) sgp);
9295 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
9296 for (i = 0; i < sgp->entry_cnt; i++) {
9297 printk(" [%u]: addr 0x%lx, bytes %lu\n",
9298 i, (ulong) le32_to_cpu(sgp->sg_list[i].addr),
9299 (ulong) le32_to_cpu(sgp->sg_list[i].bytes));
9306 * asc_prt_asc_qdone_info()
9309 asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
9311 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong) q);
9313 " srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
9314 (ulong) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
9317 " done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
9318 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
9322 * asc_prt_adv_dvc_var()
9324 * Display an ADV_DVC_VAR structure.
9327 asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
9329 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong) h);
9332 " iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
9333 (ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
9336 " isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
9337 (ulong) h->isr_callback, (unsigned) h->sdtr_able,
9338 (unsigned) h->wdtr_able);
9341 " start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
9342 (unsigned) h->start_motor,
9343 (unsigned) h->scsi_reset_wait, (unsigned) h->irq_no);
9346 " max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
9347 (unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
9348 (ulong) h->carr_freelist);
9351 " icq_sp 0x%lx, irq_sp 0x%lx\n",
9352 (ulong) h->icq_sp, (ulong) h->irq_sp);
9355 " no_scam 0x%x, tagqng_able 0x%x\n",
9356 (unsigned) h->no_scam, (unsigned) h->tagqng_able);
9359 " chip_scsi_id 0x%x, cfg 0x%lx\n",
9360 (unsigned) h->chip_scsi_id, (ulong) h->cfg);
9364 * asc_prt_adv_dvc_cfg()
9366 * Display an ADV_DVC_CFG structure.
9369 asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
9371 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong) h);
9374 " disc_enable 0x%x, termination 0x%x\n",
9375 h->disc_enable, h->termination);
9378 " chip_version 0x%x, mcode_date 0x%x\n",
9379 h->chip_version, h->mcode_date);
9382 " mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
9383 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
9386 " control_flag 0x%x, pci_slot_info 0x%x\n",
9387 h->control_flag, h->pci_slot_info);
9391 * asc_prt_adv_scsi_req_q()
9393 * Display an ADV_SCSI_REQ_Q structure.
9396 asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
9399 struct asc_sg_block *sg_ptr;
9401 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong) q);
9404 " target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
9405 q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
9407 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
9408 q->cntl, (ulong) le32_to_cpu(q->data_addr), (ulong) q->vdata_addr);
9411 " data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9412 (ulong) le32_to_cpu(q->data_cnt),
9413 (ulong) le32_to_cpu(q->sense_addr), q->sense_len);
9416 " cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
9417 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
9420 " sg_working_ix 0x%x, target_cmd %u\n",
9421 q->sg_working_ix, q->target_cmd);
9424 " scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
9425 (ulong) le32_to_cpu(q->scsiq_rptr),
9426 (ulong) le32_to_cpu(q->sg_real_addr), (ulong) q->sg_list_ptr);
9428 /* Display the request's ADV_SG_BLOCK structures. */
9429 if (q->sg_list_ptr != NULL)
9434 * 'sg_ptr' is a physical address. Convert it to a virtual
9435 * address by indexing 'sg_blk_cnt' into the virtual address
9436 * array 'sg_list_ptr'.
9438 * XXX - Assumes all SG physical blocks are virtually contiguous.
9440 sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
9441 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
9442 if (sg_ptr->sg_ptr == 0)
9452 * asc_prt_adv_sgblock()
9454 * Display an ADV_SG_BLOCK structure.
9457 asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
9461 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
9462 (ulong) b, sgblockno);
9463 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
9464 b->sg_cnt, (ulong) le32_to_cpu(b->sg_ptr));
9465 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
9468 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
9470 for (i = 0; i < b->sg_cnt; i++) {
9471 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
9472 i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
9479 * Print hexadecimal output in 4 byte groupings 32 bytes
9480 * or 8 double-words per line.
9483 asc_prt_hex(char *f, uchar *s, int l)
9490 printk("%s: (%d bytes)\n", f, l);
9492 for (i = 0; i < l; i += 32) {
9494 /* Display a maximum of 8 double-words per line. */
9495 if ((k = (l - i) / 4) >= 8) {
9502 for (j = 0; j < k; j++) {
9503 printk(" %2.2X%2.2X%2.2X%2.2X",
9504 (unsigned) s[i+(j*4)], (unsigned) s[i+(j*4)+1],
9505 (unsigned) s[i+(j*4)+2], (unsigned) s[i+(j*4)+3]);
9514 (unsigned) s[i+(j*4)]);
9517 printk(" %2.2X%2.2X",
9518 (unsigned) s[i+(j*4)],
9519 (unsigned) s[i+(j*4)+1]);
9522 printk(" %2.2X%2.2X%2.2X",
9523 (unsigned) s[i+(j*4)+1],
9524 (unsigned) s[i+(j*4)+2],
9525 (unsigned) s[i+(j*4)+3]);
9532 #endif /* ADVANSYS_DEBUG */
9535 * --- Asc Library Functions
9538 STATIC ushort __init
9542 PortAddr eisa_cfg_iop;
9544 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9545 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9546 return (inpw(eisa_cfg_iop));
9557 if (AscGetChipScsiID(iop_base) == new_host_id) {
9558 return (new_host_id);
9560 cfg_lsw = AscGetChipCfgLsw(iop_base);
9562 cfg_lsw |= (ushort) ((new_host_id & ASC_MAX_TID) << 8);
9563 AscSetChipCfgLsw(iop_base, cfg_lsw);
9564 return (AscGetChipScsiID(iop_base));
9573 AscSetBank(iop_base, 1);
9574 sc = inp(iop_base + IOP_REG_SC);
9575 AscSetBank(iop_base, 0);
9585 if ((bus_type & ASC_IS_EISA) != 0) {
9588 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9589 (PortAddr) ASC_EISA_REV_IOP_MASK;
9590 revision = inp(eisa_iop);
9591 return ((uchar) ((ASC_CHIP_MIN_VER_EISA - 1) + revision));
9593 return (AscGetChipVerNo(iop_base));
9596 STATIC ushort __init
9602 chip_ver = AscGetChipVerNo(iop_base);
9604 (chip_ver >= ASC_CHIP_MIN_VER_VL)
9605 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
9608 ((iop_base & 0x0C30) == 0x0C30)
9609 || ((iop_base & 0x0C50) == 0x0C50)
9611 return (ASC_IS_EISA);
9615 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
9616 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
9617 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
9618 return (ASC_IS_ISAPNP);
9620 return (ASC_IS_ISA);
9621 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
9622 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
9623 return (ASC_IS_PCI);
9637 ushort mcode_word_size;
9638 ushort mcode_chksum;
9640 /* Write the microcode buffer starting at LRAM address 0. */
9641 mcode_word_size = (ushort) (mcode_size >> 1);
9642 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
9643 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
9645 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
9646 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong) chksum);
9647 mcode_chksum = (ushort) AscMemSumLramWord(iop_base,
9648 (ushort) ASC_CODE_SEC_BEG,
9649 (ushort) ((mcode_size - s_addr - (ushort) ASC_CODE_SEC_BEG) / 2));
9650 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
9651 (ulong) mcode_chksum);
9652 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
9653 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
9664 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
9665 iop_base, AscGetChipSignatureByte(iop_base));
9666 if (AscGetChipSignatureByte(iop_base) == (uchar) ASC_1000_ID1B) {
9667 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
9668 iop_base, AscGetChipSignatureWord(iop_base));
9669 sig_word = AscGetChipSignatureWord(iop_base);
9670 if ((sig_word == (ushort) ASC_1000_ID0W) ||
9671 (sig_word == (ushort) ASC_1000_ID0W_FIX)) {
9678 STATIC PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata =
9680 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
9681 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
9685 STATIC uchar _isa_pnp_inited __initdata = 0;
9687 STATIC PortAddr __init
9688 AscSearchIOPortAddr(
9692 if (bus_type & ASC_IS_VL) {
9693 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9694 if (AscGetChipVersion(iop_beg, bus_type) <= ASC_CHIP_MAX_VER_VL) {
9700 if (bus_type & ASC_IS_ISA) {
9701 if (_isa_pnp_inited == 0) {
9702 AscSetISAPNPWaitForKey();
9705 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9706 if ((AscGetChipVersion(iop_beg, bus_type) & ASC_CHIP_VER_ISA_BIT) != 0) {
9712 if (bus_type & ASC_IS_EISA) {
9713 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
9721 STATIC PortAddr __init
9722 AscSearchIOPortAddr11(
9729 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9730 if (_asc_def_iop_base[i] > s_addr) {
9734 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9735 iop_base = _asc_def_iop_base[i];
9736 if (check_region(iop_base, ASC_IOADR_GAP) != 0) {
9738 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
9742 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n", iop_base);
9743 if (AscFindSignature(iop_base)) {
9751 AscSetISAPNPWaitForKey(void)
9753 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
9754 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
9757 #endif /* CONFIG_ISA */
9764 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
9765 AscSetChipStatus(iop_base, 0);
9777 if ((bus_type & ASC_IS_EISA) != 0) {
9778 cfg_lsw = AscGetEisaChipCfg(iop_base);
9779 chip_irq = (uchar) (((cfg_lsw >> 8) & 0x07) + 10);
9780 if ((chip_irq == 13) || (chip_irq > 15)) {
9785 if ((bus_type & ASC_IS_VL) != 0) {
9786 cfg_lsw = AscGetChipCfgLsw(iop_base);
9787 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x07));
9788 if ((chip_irq == 0) ||
9793 return ((uchar) (chip_irq + (ASC_MIN_IRQ_NO - 1)));
9795 cfg_lsw = AscGetChipCfgLsw(iop_base);
9796 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x03));
9798 chip_irq += (uchar) 2;
9799 return ((uchar) (chip_irq + ASC_MIN_IRQ_NO));
9810 if ((bus_type & ASC_IS_VL) != 0) {
9812 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) {
9815 irq_no -= (uchar) ((ASC_MIN_IRQ_NO - 1));
9818 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE3);
9819 cfg_lsw |= (ushort) 0x0010;
9820 AscSetChipCfgLsw(iop_base, cfg_lsw);
9821 AscToggleIRQAct(iop_base);
9822 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE0);
9823 cfg_lsw |= (ushort) ((irq_no & 0x07) << 2);
9824 AscSetChipCfgLsw(iop_base, cfg_lsw);
9825 AscToggleIRQAct(iop_base);
9826 return (AscGetChipIRQ(iop_base, bus_type));
9828 if ((bus_type & (ASC_IS_ISA)) != 0) {
9830 irq_no -= (uchar) 2;
9831 irq_no -= (uchar) ASC_MIN_IRQ_NO;
9832 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFF3);
9833 cfg_lsw |= (ushort) ((irq_no & 0x03) << 2);
9834 AscSetChipCfgLsw(iop_base, cfg_lsw);
9835 return (AscGetChipIRQ(iop_base, bus_type));
9845 if (dma_channel < 4) {
9846 outp(0x000B, (ushort) (0xC0 | dma_channel));
9847 outp(0x000A, dma_channel);
9848 } else if (dma_channel < 8) {
9849 outp(0x00D6, (ushort) (0xC0 | (dma_channel - 4)));
9850 outp(0x00D4, (ushort) (dma_channel - 4));
9854 #endif /* CONFIG_ISA */
9858 ASC_DVC_VAR *asc_dvc
9865 ushort int_halt_code;
9866 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9867 ASC_SCSI_BIT_ID_TYPE target_id;
9874 uchar q_cntl, tid_no;
9878 asc_board_t *boardp;
9880 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
9881 boardp = asc_dvc->drv_ptr;
9883 iop_base = asc_dvc->iop_base;
9884 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
9886 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
9887 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
9888 target_ix = AscReadLramByte(iop_base,
9889 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TARGET_IX));
9890 q_cntl = AscReadLramByte(iop_base,
9891 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL));
9892 tid_no = ASC_TIX_TO_TID(target_ix);
9893 target_id = (uchar) ASC_TID_TO_TARGET_ID(tid_no);
9894 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9895 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
9899 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
9900 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9901 AscSetChipSDTR(iop_base, 0, tid_no);
9902 boardp->sdtr_data[tid_no] = 0;
9904 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9906 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
9907 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9908 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9909 boardp->sdtr_data[tid_no] = asyn_sdtr;
9911 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9913 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
9915 AscMemWordCopyPtrFromLram(iop_base,
9918 sizeof(EXT_MSG) >> 1);
9920 if (ext_msg.msg_type == MS_EXTEND &&
9921 ext_msg.msg_req == MS_SDTR_CODE &&
9922 ext_msg.msg_len == MS_SDTR_LEN) {
9924 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
9926 sdtr_accept = FALSE;
9927 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
9929 if ((ext_msg.xfer_period <
9930 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index]) ||
9931 (ext_msg.xfer_period >
9932 asc_dvc->sdtr_period_tbl[asc_dvc->max_sdtr_index])) {
9933 sdtr_accept = FALSE;
9934 ext_msg.xfer_period =
9935 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index];
9938 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9939 ext_msg.req_ack_offset);
9940 if ((sdtr_data == 0xFF)) {
9942 q_cntl |= QC_MSG_OUT;
9943 asc_dvc->init_sdtr &= ~target_id;
9944 asc_dvc->sdtr_done &= ~target_id;
9945 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9946 boardp->sdtr_data[tid_no] = asyn_sdtr;
9949 if (ext_msg.req_ack_offset == 0) {
9951 q_cntl &= ~QC_MSG_OUT;
9952 asc_dvc->init_sdtr &= ~target_id;
9953 asc_dvc->sdtr_done &= ~target_id;
9954 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9956 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
9958 q_cntl &= ~QC_MSG_OUT;
9959 asc_dvc->sdtr_done |= target_id;
9960 asc_dvc->init_sdtr |= target_id;
9961 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9962 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9963 ext_msg.req_ack_offset);
9964 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9965 boardp->sdtr_data[tid_no] = sdtr_data;
9968 q_cntl |= QC_MSG_OUT;
9969 AscMsgOutSDTR(asc_dvc,
9970 ext_msg.xfer_period,
9971 ext_msg.req_ack_offset);
9972 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9973 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9974 ext_msg.req_ack_offset);
9975 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9976 boardp->sdtr_data[tid_no] = sdtr_data;
9977 asc_dvc->sdtr_done |= target_id;
9978 asc_dvc->init_sdtr |= target_id;
9982 AscWriteLramByte(iop_base,
9983 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
9985 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9987 } else if (ext_msg.msg_type == MS_EXTEND &&
9988 ext_msg.msg_req == MS_WDTR_CODE &&
9989 ext_msg.msg_len == MS_WDTR_LEN) {
9991 ext_msg.wdtr_width = 0;
9992 AscMemWordCopyPtrToLram(iop_base,
9995 sizeof(EXT_MSG) >> 1);
9996 q_cntl |= QC_MSG_OUT;
9997 AscWriteLramByte(iop_base,
9998 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10000 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10004 ext_msg.msg_type = MESSAGE_REJECT;
10005 AscMemWordCopyPtrToLram(iop_base,
10007 (uchar *) &ext_msg,
10008 sizeof(EXT_MSG) >> 1);
10009 q_cntl |= QC_MSG_OUT;
10010 AscWriteLramByte(iop_base,
10011 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10013 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10016 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
10018 q_cntl |= QC_REQ_SENSE;
10020 if ((asc_dvc->init_sdtr & target_id) != 0) {
10022 asc_dvc->sdtr_done &= ~target_id;
10024 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10025 q_cntl |= QC_MSG_OUT;
10026 AscMsgOutSDTR(asc_dvc,
10027 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10028 (uchar) (asc_dvc->max_sdtr_index - 1)],
10029 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10032 AscWriteLramByte(iop_base,
10033 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10036 tag_code = AscReadLramByte(iop_base,
10037 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE));
10040 (asc_dvc->pci_fix_asyn_xfer & target_id)
10041 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
10044 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
10045 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
10048 AscWriteLramByte(iop_base,
10049 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE),
10052 q_status = AscReadLramByte(iop_base,
10053 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10054 q_status |= (QS_READY | QS_BUSY);
10055 AscWriteLramByte(iop_base,
10056 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10059 scsi_busy = AscReadLramByte(iop_base,
10060 (ushort) ASCV_SCSIBUSY_B);
10061 scsi_busy &= ~target_id;
10062 AscWriteLramByte(iop_base, (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10064 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10066 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
10068 AscMemWordCopyPtrFromLram(iop_base,
10070 (uchar *) &out_msg,
10071 sizeof(EXT_MSG) >> 1);
10073 if ((out_msg.msg_type == MS_EXTEND) &&
10074 (out_msg.msg_len == MS_SDTR_LEN) &&
10075 (out_msg.msg_req == MS_SDTR_CODE)) {
10077 asc_dvc->init_sdtr &= ~target_id;
10078 asc_dvc->sdtr_done &= ~target_id;
10079 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
10080 boardp->sdtr_data[tid_no] = asyn_sdtr;
10082 q_cntl &= ~QC_MSG_OUT;
10083 AscWriteLramByte(iop_base,
10084 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10086 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10088 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
10090 scsi_status = AscReadLramByte(iop_base,
10091 (ushort) ((ushort) halt_q_addr + (ushort) ASC_SCSIQ_SCSI_STATUS));
10092 cur_dvc_qng = AscReadLramByte(iop_base,
10093 (ushort) ((ushort) ASC_QADR_BEG + (ushort) target_ix));
10094 if ((cur_dvc_qng > 0) &&
10095 (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
10097 scsi_busy = AscReadLramByte(iop_base,
10098 (ushort) ASCV_SCSIBUSY_B);
10099 scsi_busy |= target_id;
10100 AscWriteLramByte(iop_base,
10101 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10102 asc_dvc->queue_full_or_busy |= target_id;
10104 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
10105 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
10107 asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng;
10109 AscWriteLramByte(iop_base,
10110 (ushort) ((ushort) ASCV_MAX_DVC_QNG_BEG +
10115 * Set the device queue depth to the number of
10116 * active requests when the QUEUE FULL condition
10119 boardp->queue_full |= target_id;
10120 boardp->queue_full_cnt[tid_no] = cur_dvc_qng;
10124 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10127 #if CC_VERY_LONG_SG_LIST
10128 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
10133 uchar first_sg_wk_q_no;
10134 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
10135 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
10136 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
10137 ushort sg_list_dwords;
10138 ushort sg_entry_cnt;
10142 q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
10143 if (q_no == ASC_QLINK_END)
10148 q_addr = ASC_QNO_TO_QADDR(q_no);
10151 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
10152 * structure pointer using a macro provided by the driver.
10153 * The ASC_SCSI_REQ pointer provides a pointer to the
10154 * host ASC_SG_HEAD structure.
10156 /* Read request's SRB pointer. */
10157 scsiq = (ASC_SCSI_Q *)
10159 ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
10160 (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
10163 * Get request's first and working SG queue.
10165 sg_wk_q_no = AscReadLramByte(iop_base,
10166 (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
10168 first_sg_wk_q_no = AscReadLramByte(iop_base,
10169 (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
10172 * Reset request's working SG queue back to the
10175 AscWriteLramByte(iop_base,
10176 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
10179 sg_head = scsiq->sg_head;
10182 * Set sg_entry_cnt to the number of SG elements
10183 * that will be completed on this interrupt.
10185 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
10186 * SG elements. The data_cnt and data_addr fields which
10187 * add 1 to the SG element capacity are not used when
10188 * restarting SG handling after a halt.
10190 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
10192 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10195 * Keep track of remaining number of SG elements that will
10196 * need to be handled on the next interrupt.
10198 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
10201 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
10202 scsiq->remain_sg_entry_cnt = 0;
10206 * Copy SG elements into the list of allocated SG queues.
10208 * Last index completed is saved in scsiq->next_sg_index.
10210 next_qp = first_sg_wk_q_no;
10211 q_addr = ASC_QNO_TO_QADDR(next_qp);
10212 scsi_sg_q.sg_head_qp = q_no;
10213 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10214 for( i = 0; i < sg_head->queue_cnt; i++)
10216 scsi_sg_q.seq_no = i + 1;
10217 if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
10219 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
10220 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10222 * After very first SG queue RISC FW uses next
10223 * SG queue first element then checks sg_list_cnt
10224 * against zero and then decrements, so set
10225 * sg_list_cnt 1 less than number of SG elements
10226 * in each SG queue.
10228 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
10229 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
10232 * This is the last SG queue in the list of
10233 * allocated SG queues. If there are more
10234 * SG elements than will fit in the allocated
10235 * queues, then set the QCSG_SG_XFER_MORE flag.
10237 if (scsiq->remain_sg_entry_cnt != 0)
10239 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10242 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10244 /* equals sg_entry_cnt * 2 */
10245 sg_list_dwords = sg_entry_cnt << 1;
10246 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
10247 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
10251 scsi_sg_q.q_no = next_qp;
10252 AscMemWordCopyPtrToLram(iop_base,
10253 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10254 (uchar *) &scsi_sg_q,
10255 sizeof(ASC_SG_LIST_Q) >> 1);
10257 AscMemDWordCopyPtrToLram(iop_base,
10258 q_addr + ASC_SGQ_LIST_BEG,
10259 (uchar *) &sg_head->sg_list[scsiq->next_sg_index],
10262 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
10265 * If the just completed SG queue contained the
10266 * last SG element, then no more SG queues need
10269 if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
10274 next_qp = AscReadLramByte( iop_base,
10275 ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
10276 q_addr = ASC_QNO_TO_QADDR( next_qp );
10280 * Clear the halt condition so the RISC will be restarted
10281 * after the return.
10283 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10286 #endif /* CC_VERY_LONG_SG_LIST */
10291 _AscCopyLramScsiDoneQ(
10294 ASC_QDONE_INFO * scsiq,
10295 ASC_DCNT max_dma_count
10299 uchar sg_queue_cnt;
10301 DvcGetQinfo(iop_base,
10302 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
10304 (sizeof (ASC_SCSIQ_2) + sizeof (ASC_SCSIQ_3)) / 2);
10306 _val = AscReadLramWord(iop_base,
10307 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10308 scsiq->q_status = (uchar) _val;
10309 scsiq->q_no = (uchar) (_val >> 8);
10310 _val = AscReadLramWord(iop_base,
10311 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_CNTL));
10312 scsiq->cntl = (uchar) _val;
10313 sg_queue_cnt = (uchar) (_val >> 8);
10314 _val = AscReadLramWord(iop_base,
10315 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SENSE_LEN));
10316 scsiq->sense_len = (uchar) _val;
10317 scsiq->extra_bytes = (uchar) (_val >> 8);
10320 * Read high word of remain bytes from alternate location.
10322 scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
10323 (ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
10325 * Read low word of remain bytes from original location.
10327 scsiq->remain_bytes += AscReadLramWord(iop_base,
10328 (ushort) (q_addr+ (ushort) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
10330 scsiq->remain_bytes &= max_dma_count;
10331 return (sg_queue_cnt);
10336 ASC_DVC_VAR *asc_dvc
10342 uchar sg_queue_cnt;
10346 ASC_SCSI_BIT_ID_TYPE scsi_busy;
10347 ASC_SCSI_BIT_ID_TYPE target_id;
10351 uchar cur_target_qng;
10352 ASC_QDONE_INFO scsiq_buf;
10353 ASC_QDONE_INFO *scsiq;
10355 ASC_ISR_CALLBACK asc_isr_callback;
10357 iop_base = asc_dvc->iop_base;
10358 asc_isr_callback = asc_dvc->isr_callback;
10360 scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
10361 done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
10362 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
10363 next_qp = AscReadLramByte(iop_base,
10364 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_FWD));
10365 if (next_qp != ASC_QLINK_END) {
10366 AscPutVarDoneQTail(iop_base, next_qp);
10367 q_addr = ASC_QNO_TO_QADDR(next_qp);
10368 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
10369 asc_dvc->max_dma_count);
10370 AscWriteLramByte(iop_base,
10371 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10372 (uchar) (scsiq->q_status & (uchar) ~ (QS_READY | QS_ABORTED)));
10373 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
10374 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
10375 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
10376 sg_q_addr = q_addr;
10377 sg_list_qp = next_qp;
10378 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
10379 sg_list_qp = AscReadLramByte(iop_base,
10380 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_FWD));
10381 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
10382 if (sg_list_qp == ASC_QLINK_END) {
10383 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SG_Q_LINKS);
10384 scsiq->d3.done_stat = QD_WITH_ERROR;
10385 scsiq->d3.host_stat = QHSTA_D_QDONE_SG_LIST_CORRUPTED;
10386 goto FATAL_ERR_QDONE;
10388 AscWriteLramByte(iop_base,
10389 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10392 n_q_used = sg_queue_cnt + 1;
10393 AscPutVarDoneQTail(iop_base, sg_list_qp);
10395 if (asc_dvc->queue_full_or_busy & target_id) {
10396 cur_target_qng = AscReadLramByte(iop_base,
10397 (ushort) ((ushort) ASC_QADR_BEG + (ushort) scsiq->d2.target_ix));
10398 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
10399 scsi_busy = AscReadLramByte(iop_base,
10400 (ushort) ASCV_SCSIBUSY_B);
10401 scsi_busy &= ~target_id;
10402 AscWriteLramByte(iop_base,
10403 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10404 asc_dvc->queue_full_or_busy &= ~target_id;
10407 if (asc_dvc->cur_total_qng >= n_q_used) {
10408 asc_dvc->cur_total_qng -= n_q_used;
10409 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
10410 asc_dvc->cur_dvc_qng[tid_no]--;
10413 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
10414 scsiq->d3.done_stat = QD_WITH_ERROR;
10415 goto FATAL_ERR_QDONE;
10417 if ((scsiq->d2.srb_ptr == 0UL) ||
10418 ((scsiq->q_status & QS_ABORTED) != 0)) {
10420 } else if (scsiq->q_status == QS_DONE) {
10421 false_overrun = FALSE;
10422 if (scsiq->extra_bytes != 0) {
10423 scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
10425 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
10426 if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
10427 if ((scsiq->cntl & (QC_DATA_IN | QC_DATA_OUT)) == 0) {
10428 scsiq->d3.done_stat = QD_NO_ERROR;
10429 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10430 } else if (false_overrun) {
10431 scsiq->d3.done_stat = QD_NO_ERROR;
10432 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10434 } else if (scsiq->d3.host_stat ==
10435 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
10436 AscStopChip(iop_base);
10437 AscSetChipControl(iop_base,
10438 (uchar) (CC_SCSI_RESET | CC_HALT));
10439 DvcDelayNanoSecond(asc_dvc, 60000);
10440 AscSetChipControl(iop_base, CC_HALT);
10441 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10442 AscSetChipStatus(iop_base, 0);
10443 AscSetChipControl(iop_base, 0);
10446 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10447 (*asc_isr_callback) (asc_dvc, scsiq);
10449 if ((AscReadLramByte(iop_base,
10450 (ushort) (q_addr + (ushort) ASC_SCSIQ_CDB_BEG)) ==
10452 asc_dvc->unit_not_ready &= ~target_id;
10453 if (scsiq->d3.done_stat != QD_NO_ERROR) {
10454 asc_dvc->start_motor &= ~target_id;
10460 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
10462 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10463 (*asc_isr_callback) (asc_dvc, scsiq);
10473 ASC_DVC_VAR *asc_dvc
10476 ASC_CS_TYPE chipstat;
10478 ushort saved_ram_addr;
10480 uchar saved_ctrl_reg;
10485 iop_base = asc_dvc->iop_base;
10486 int_pending = FALSE;
10488 if (AscIsIntPending(iop_base) == 0)
10490 return int_pending;
10493 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
10494 || (asc_dvc->isr_callback == 0)
10498 if (asc_dvc->in_critical_cnt != 0) {
10499 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
10502 if (asc_dvc->is_in_int) {
10503 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
10506 asc_dvc->is_in_int = TRUE;
10507 ctrl_reg = AscGetChipControl(iop_base);
10508 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
10509 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
10510 chipstat = AscGetChipStatus(iop_base);
10511 if (chipstat & CSW_SCSI_RESET_LATCH) {
10512 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
10514 int_pending = TRUE;
10515 asc_dvc->sdtr_done = 0;
10516 saved_ctrl_reg &= (uchar) (~CC_HALT);
10517 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) &&
10520 DvcSleepMilliSecond(100);
10522 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
10523 AscSetChipControl(iop_base, CC_HALT);
10524 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10525 AscSetChipStatus(iop_base, 0);
10526 chipstat = AscGetChipStatus(iop_base);
10529 saved_ram_addr = AscGetChipLramAddr(iop_base);
10530 host_flag = AscReadLramByte(iop_base,
10531 ASCV_HOST_FLAG_B) & (uchar) (~ASC_HOST_FLAG_IN_ISR);
10532 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10533 (uchar) (host_flag | (uchar) ASC_HOST_FLAG_IN_ISR));
10534 if ((chipstat & CSW_INT_PENDING)
10537 AscAckInterrupt(iop_base);
10538 int_pending = TRUE;
10539 if ((chipstat & CSW_HALTED) &&
10540 (ctrl_reg & CC_SINGLE_STEP)) {
10541 if (AscIsrChipHalted(asc_dvc) == ERR) {
10542 goto ISR_REPORT_QDONE_FATAL_ERROR;
10544 saved_ctrl_reg &= (uchar) (~CC_HALT);
10547 ISR_REPORT_QDONE_FATAL_ERROR:
10548 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
10549 while (((status = AscIsrQDone(asc_dvc)) & 0x01) != 0) {
10553 if ((status = AscIsrQDone(asc_dvc)) == 1) {
10556 } while (status == 0x11);
10558 if ((status & 0x80) != 0)
10562 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10563 AscSetChipLramAddr(iop_base, saved_ram_addr);
10564 AscSetChipControl(iop_base, saved_ctrl_reg);
10565 asc_dvc->is_in_int = FALSE;
10566 return (int_pending);
10569 /* Microcode buffer is kept after initialization for error recovery. */
10570 STATIC uchar _asc_mcode_buf[] =
10572 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10573 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10574 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10576 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
10577 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10578 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
10579 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00,
10580 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
10581 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80,
10582 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80,
10583 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
10584 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D, 0x00,
10585 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1,
10586 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
10587 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, 0x84, 0x97, 0x07, 0xA6,
10588 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00,
10589 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
10590 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33,
10591 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04,
10592 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
10593 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A, 0x00,
10594 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04,
10595 0x36, 0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
10596 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, 0x3C, 0x01, 0x00, 0x05,
10597 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01,
10598 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
10599 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23,
10600 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0,
10601 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
10602 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84, 0x97,
10603 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80,
10604 0xF0, 0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
10605 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, 0x04, 0x98, 0xF0, 0x80,
10606 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6,
10607 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
10608 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02,
10609 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96,
10610 0x48, 0x82, 0x04, 0x23, 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
10611 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5, 0x01,
10612 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02,
10613 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
10614 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, 0x80, 0x63, 0x00, 0x43,
10615 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01,
10616 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
10617 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00,
10618 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6,
10619 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
10620 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE, 0x82,
10621 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8,
10622 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
10623 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, 0x3C, 0x04, 0x06, 0xA6,
10624 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83,
10625 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
10626 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03,
10627 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03,
10628 0xEC, 0x00, 0x6E, 0x00, 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
10629 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00, 0xA6,
10630 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03,
10631 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
10632 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, 0xC0, 0x83, 0x00, 0x33,
10633 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23,
10634 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
10635 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04,
10636 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84,
10637 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
10638 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00, 0x33,
10639 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC,
10640 0x00, 0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
10641 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0xA3, 0x01,
10642 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00,
10643 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
10644 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3,
10645 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23,
10646 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
10647 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8, 0x81,
10648 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81,
10649 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
10650 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, 0xF4, 0x04, 0x00, 0x33,
10651 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01,
10652 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
10653 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04,
10654 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85,
10655 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
10656 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81, 0x01,
10657 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01,
10658 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
10659 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, 0x07, 0xA4, 0xF8, 0x05,
10660 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0,
10661 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
10662 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85,
10663 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0,
10664 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
10665 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80, 0x63,
10666 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23,
10667 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
10668 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, 0x07, 0x41, 0x83, 0x03,
10669 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6,
10670 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
10671 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61,
10672 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01,
10673 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
10674 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06, 0xA6,
10675 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20,
10676 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
10677 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, 0x40, 0x0E, 0x80, 0x63,
10678 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43,
10679 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
10680 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06,
10681 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6,
10682 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
10683 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04, 0x01,
10684 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33,
10685 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
10686 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, 0x00, 0x00, 0x80, 0x67,
10687 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61,
10688 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
10689 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05,
10690 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01,
10691 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
10692 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70, 0x00,
10693 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00,
10694 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
10695 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, 0xC4, 0x07, 0x00, 0x33,
10696 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01,
10697 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
10698 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63,
10699 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02,
10700 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
10701 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3, 0x04,
10702 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08,
10703 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
10704 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, 0x5A, 0x88, 0x02, 0x01,
10705 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08,
10706 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
10707 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B,
10708 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09,
10709 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
10710 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40, 0x3A,
10711 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3,
10712 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
10713 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, 0xA1, 0x23, 0xA1, 0x01,
10714 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2,
10715 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
10718 STATIC ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
10719 STATIC ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
10721 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10722 STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
10744 ASC_DVC_VAR *asc_dvc,
10749 ulong last_int_level;
10752 int disable_syn_offset_one_fix;
10755 ASC_EXE_CALLBACK asc_exe_callback;
10756 ushort sg_entry_cnt = 0;
10757 ushort sg_entry_cnt_minus_one = 0;
10764 ASC_SG_HEAD *sg_head;
10767 iop_base = asc_dvc->iop_base;
10768 sg_head = scsiq->sg_head;
10769 asc_exe_callback = asc_dvc->exe_callback;
10770 if (asc_dvc->err_code != 0)
10772 if (scsiq == (ASC_SCSI_Q *) 0L) {
10773 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
10776 scsiq->q1.q_no = 0;
10777 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10778 scsiq->q1.extra_bytes = 0;
10781 target_ix = scsiq->q2.target_ix;
10782 tid_no = ASC_TIX_TO_TID(target_ix);
10784 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10785 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10786 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10787 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10788 AscMsgOutSDTR(asc_dvc,
10789 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10790 (uchar) (asc_dvc->max_sdtr_index - 1)],
10791 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10792 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10795 last_int_level = DvcEnterCritical();
10796 if (asc_dvc->in_critical_cnt != 0) {
10797 DvcLeaveCritical(last_int_level);
10798 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10801 asc_dvc->in_critical_cnt++;
10802 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10803 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10804 asc_dvc->in_critical_cnt--;
10805 DvcLeaveCritical(last_int_level);
10808 #if !CC_VERY_LONG_SG_LIST
10809 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10811 asc_dvc->in_critical_cnt--;
10812 DvcLeaveCritical(last_int_level);
10815 #endif /* !CC_VERY_LONG_SG_LIST */
10816 if (sg_entry_cnt == 1) {
10817 scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
10818 scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
10819 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10821 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10823 scsi_cmd = scsiq->cdbptr[0];
10824 disable_syn_offset_one_fix = FALSE;
10825 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10826 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10827 if (scsiq->q1.cntl & QC_SG_HEAD) {
10829 for (i = 0; i < sg_entry_cnt; i++) {
10830 data_cnt += (ADV_DCNT) le32_to_cpu(sg_head->sg_list[i].bytes);
10833 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10835 if (data_cnt != 0UL) {
10836 if (data_cnt < 512UL) {
10837 disable_syn_offset_one_fix = TRUE;
10839 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; i++) {
10840 disable_cmd = _syn_offset_one_disable_cmd[i];
10841 if (disable_cmd == 0xFF) {
10844 if (scsi_cmd == disable_cmd) {
10845 disable_syn_offset_one_fix = TRUE;
10852 if (disable_syn_offset_one_fix) {
10853 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10854 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10855 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10857 scsiq->q2.tag_code &= 0x27;
10859 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10860 if (asc_dvc->bug_fix_cntl) {
10861 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10862 if ((scsi_cmd == READ_6) ||
10863 (scsi_cmd == READ_10)) {
10865 (ADV_PADDR) le32_to_cpu(
10866 sg_head->sg_list[sg_entry_cnt_minus_one].addr) +
10867 (ADV_DCNT) le32_to_cpu(
10868 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10869 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10870 if ((extra_bytes != 0) &&
10871 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10873 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10874 scsiq->q1.extra_bytes = extra_bytes;
10875 data_cnt = le32_to_cpu(
10876 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10877 data_cnt -= (ASC_DCNT) extra_bytes;
10878 sg_head->sg_list[sg_entry_cnt_minus_one].bytes =
10879 cpu_to_le32(data_cnt);
10884 sg_head->entry_to_copy = sg_head->entry_cnt;
10885 #if CC_VERY_LONG_SG_LIST
10887 * Set the sg_entry_cnt to the maximum possible. The rest of
10888 * the SG elements will be copied when the RISC completes the
10889 * SG elements that fit and halts.
10891 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10893 sg_entry_cnt = ASC_MAX_SG_LIST;
10895 #endif /* CC_VERY_LONG_SG_LIST */
10896 n_q_required = AscSgListToQueue(sg_entry_cnt);
10897 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10898 (uint) n_q_required) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10899 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10900 n_q_required)) == 1) {
10901 asc_dvc->in_critical_cnt--;
10902 if (asc_exe_callback != 0) {
10903 (*asc_exe_callback) (asc_dvc, scsiq);
10905 DvcLeaveCritical(last_int_level);
10910 if (asc_dvc->bug_fix_cntl) {
10911 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10912 if ((scsi_cmd == READ_6) ||
10913 (scsi_cmd == READ_10)) {
10914 addr = le32_to_cpu(scsiq->q1.data_addr) +
10915 le32_to_cpu(scsiq->q1.data_cnt);
10916 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10917 if ((extra_bytes != 0) &&
10918 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10920 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10921 if (((ushort) data_cnt & 0x01FF) == 0) {
10922 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10923 data_cnt -= (ASC_DCNT) extra_bytes;
10924 scsiq->q1.data_cnt = cpu_to_le32(data_cnt);
10925 scsiq->q1.extra_bytes = extra_bytes;
10932 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10933 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10934 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10935 n_q_required)) == 1) {
10936 asc_dvc->in_critical_cnt--;
10937 if (asc_exe_callback != 0) {
10938 (*asc_exe_callback) (asc_dvc, scsiq);
10940 DvcLeaveCritical(last_int_level);
10945 asc_dvc->in_critical_cnt--;
10946 DvcLeaveCritical(last_int_level);
10952 ASC_DVC_VAR *asc_dvc,
10964 iop_base = asc_dvc->iop_base;
10965 target_ix = scsiq->q2.target_ix;
10966 tid_no = ASC_TIX_TO_TID(target_ix);
10968 free_q_head = (uchar) AscGetVarFreeQHead(iop_base);
10969 if (n_q_required > 1) {
10970 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
10971 free_q_head, (uchar) (n_q_required)))
10972 != (uchar) ASC_QLINK_END) {
10973 asc_dvc->last_q_shortage = 0;
10974 scsiq->sg_head->queue_cnt = n_q_required - 1;
10975 scsiq->q1.q_no = free_q_head;
10976 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10977 free_q_head)) == 1) {
10978 AscPutVarFreeQHead(iop_base, next_qp);
10979 asc_dvc->cur_total_qng += (uchar) (n_q_required);
10980 asc_dvc->cur_dvc_qng[tid_no]++;
10984 } else if (n_q_required == 1) {
10985 if ((next_qp = AscAllocFreeQueue(iop_base,
10986 free_q_head)) != ASC_QLINK_END) {
10987 scsiq->q1.q_no = free_q_head;
10988 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
10989 free_q_head)) == 1) {
10990 AscPutVarFreeQHead(iop_base, next_qp);
10991 asc_dvc->cur_total_qng++;
10992 asc_dvc->cur_dvc_qng[tid_no]++;
11007 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
11008 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
11010 return (n_sg_list_qs + 1);
11015 AscGetNumOfFreeQueue(
11016 ASC_DVC_VAR *asc_dvc,
11023 ASC_SCSI_BIT_ID_TYPE target_id;
11026 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
11027 tid_no = ASC_TIX_TO_TID(target_ix);
11028 if ((asc_dvc->unit_not_ready & target_id) ||
11029 (asc_dvc->queue_full_or_busy & target_id)) {
11033 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11034 (uint) asc_dvc->last_q_shortage +
11035 (uint) ASC_MIN_FREE_Q;
11037 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11038 (uint) ASC_MIN_FREE_Q;
11040 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
11041 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
11042 if (asc_dvc->cur_dvc_qng[tid_no] >=
11043 asc_dvc->max_dvc_qng[tid_no]) {
11046 return (cur_free_qs);
11049 if ((n_qs > asc_dvc->last_q_shortage) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
11050 asc_dvc->last_q_shortage = n_qs;
11058 ASC_DVC_VAR *asc_dvc,
11066 uchar syn_period_ix;
11070 iop_base = asc_dvc->iop_base;
11071 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
11072 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
11073 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
11074 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
11075 syn_period_ix = (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
11076 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
11077 AscMsgOutSDTR(asc_dvc,
11078 asc_dvc->sdtr_period_tbl[syn_period_ix],
11080 scsiq->q1.cntl |= QC_MSG_OUT;
11082 q_addr = ASC_QNO_TO_QADDR(q_no);
11083 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
11084 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG ;
11086 scsiq->q1.status = QS_FREE;
11087 AscMemWordCopyPtrToLram(iop_base,
11088 q_addr + ASC_SCSIQ_CDB_BEG,
11089 (uchar *) scsiq->cdbptr,
11090 scsiq->q2.cdb_len >> 1);
11092 DvcPutScsiQ(iop_base,
11093 q_addr + ASC_SCSIQ_CPY_BEG,
11094 (uchar *) &scsiq->q1.cntl,
11095 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
11096 AscWriteLramWord(iop_base,
11097 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
11098 (ushort) (((ushort) scsiq->q1.q_no << 8) | (ushort) QS_READY));
11103 AscPutReadySgListQueue(
11104 ASC_DVC_VAR *asc_dvc,
11111 ASC_SG_HEAD *sg_head;
11112 ASC_SG_LIST_Q scsi_sg_q;
11113 ASC_DCNT saved_data_addr;
11114 ASC_DCNT saved_data_cnt;
11116 ushort sg_list_dwords;
11118 ushort sg_entry_cnt;
11122 iop_base = asc_dvc->iop_base;
11123 sg_head = scsiq->sg_head;
11124 saved_data_addr = scsiq->q1.data_addr;
11125 saved_data_cnt = scsiq->q1.data_cnt;
11126 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
11127 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
11128 #if CC_VERY_LONG_SG_LIST
11130 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
11131 * then not all SG elements will fit in the allocated queues.
11132 * The rest of the SG elements will be copied when the RISC
11133 * completes the SG elements that fit and halts.
11135 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11138 * Set sg_entry_cnt to be the number of SG elements that
11139 * will fit in the allocated SG queues. It is minus 1, because
11140 * the first SG element is handled above. ASC_MAX_SG_LIST is
11141 * already inflated by 1 to account for this. For example it
11142 * may be 50 which is 1 + 7 queues * 7 SG elements.
11144 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
11147 * Keep track of remaining number of SG elements that will
11148 * need to be handled from a_isr.c.
11150 scsiq->remain_sg_entry_cnt = sg_head->entry_cnt - ASC_MAX_SG_LIST;
11153 #endif /* CC_VERY_LONG_SG_LIST */
11155 * Set sg_entry_cnt to be the number of SG elements that
11156 * will fit in the allocated SG queues. It is minus 1, because
11157 * the first SG element is handled above.
11159 sg_entry_cnt = sg_head->entry_cnt - 1;
11160 #if CC_VERY_LONG_SG_LIST
11162 #endif /* CC_VERY_LONG_SG_LIST */
11163 if (sg_entry_cnt != 0) {
11164 scsiq->q1.cntl |= QC_SG_HEAD;
11165 q_addr = ASC_QNO_TO_QADDR(q_no);
11167 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
11168 scsi_sg_q.sg_head_qp = q_no;
11169 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
11170 for (i = 0; i < sg_head->queue_cnt; i++) {
11171 scsi_sg_q.seq_no = i + 1;
11172 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
11173 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
11174 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
11176 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
11177 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
11179 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
11180 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
11183 #if CC_VERY_LONG_SG_LIST
11185 * This is the last SG queue in the list of
11186 * allocated SG queues. If there are more
11187 * SG elements than will fit in the allocated
11188 * queues, then set the QCSG_SG_XFER_MORE flag.
11190 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11192 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
11195 #endif /* CC_VERY_LONG_SG_LIST */
11196 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
11197 #if CC_VERY_LONG_SG_LIST
11199 #endif /* CC_VERY_LONG_SG_LIST */
11200 sg_list_dwords = sg_entry_cnt << 1;
11202 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
11203 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
11205 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
11206 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
11210 next_qp = AscReadLramByte(iop_base,
11211 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11212 scsi_sg_q.q_no = next_qp;
11213 q_addr = ASC_QNO_TO_QADDR(next_qp);
11214 AscMemWordCopyPtrToLram(iop_base,
11215 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
11216 (uchar *) &scsi_sg_q,
11217 sizeof(ASC_SG_LIST_Q) >> 1);
11218 AscMemDWordCopyPtrToLram(iop_base,
11219 q_addr + ASC_SGQ_LIST_BEG,
11220 (uchar *) &sg_head->sg_list[sg_index],
11222 sg_index += ASC_SG_LIST_PER_Q;
11223 scsiq->next_sg_index = sg_index;
11226 scsiq->q1.cntl &= ~QC_SG_HEAD;
11228 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
11229 scsiq->q1.data_addr = saved_data_addr;
11230 scsiq->q1.data_cnt = saved_data_cnt;
11235 AscSetRunChipSynRegAtID(
11243 if (AscHostReqRiscHalt(iop_base)) {
11244 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11245 AscStartChip(iop_base);
11252 AscSetChipSynRegAtID(
11258 ASC_SCSI_BIT_ID_TYPE org_id;
11262 AscSetBank(iop_base, 1);
11263 org_id = AscReadChipDvcID(iop_base);
11264 for (i = 0; i <= ASC_MAX_TID; i++) {
11265 if (org_id == (0x01 << i))
11268 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
11269 AscWriteChipDvcID(iop_base, id);
11270 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
11271 AscSetBank(iop_base, 0);
11272 AscSetChipSyn(iop_base, sdtr_data);
11273 if (AscGetChipSyn(iop_base) != sdtr_data) {
11279 AscSetBank(iop_base, 1);
11280 AscWriteChipDvcID(iop_base, org_id);
11281 AscSetBank(iop_base, 0);
11287 ASC_DVC_VAR *asc_dvc
11295 iop_base = asc_dvc->iop_base;
11297 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
11298 (ushort) (((int) (asc_dvc->max_total_qng + 2 + 1) * 64) >> 1)
11300 i = ASC_MIN_ACTIVE_QNO;
11301 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
11302 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11304 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11305 (uchar) (asc_dvc->max_total_qng));
11306 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11309 s_addr += ASC_QBLK_SIZE;
11310 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
11311 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11313 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11315 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11318 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11319 (uchar) ASC_QLINK_END);
11320 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11321 (uchar) (asc_dvc->max_total_qng - 1));
11322 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11323 (uchar) asc_dvc->max_total_qng);
11325 s_addr += ASC_QBLK_SIZE;
11326 for (; i <= (uchar) (asc_dvc->max_total_qng + 3);
11327 i++, s_addr += ASC_QBLK_SIZE) {
11328 AscWriteLramByte(iop_base,
11329 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_FWD), i);
11330 AscWriteLramByte(iop_base,
11331 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_BWD), i);
11332 AscWriteLramByte(iop_base,
11333 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_QNO), i);
11335 return (warn_code);
11340 ASC_DVC_VAR *asc_dvc
11347 iop_base = asc_dvc->iop_base;
11348 AscPutRiscVarFreeQHead(iop_base, 1);
11349 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11350 AscPutVarFreeQHead(iop_base, 1);
11351 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11352 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
11353 (uchar) ((int) asc_dvc->max_total_qng + 1));
11354 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
11355 (uchar) ((int) asc_dvc->max_total_qng + 2));
11356 AscWriteLramByte(iop_base, (ushort) ASCV_TOTAL_READY_Q_B,
11357 asc_dvc->max_total_qng);
11358 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
11359 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
11360 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
11361 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
11362 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
11363 AscPutQDoneInProgress(iop_base, 0);
11364 lram_addr = ASC_QADR_BEG;
11365 for (i = 0; i < 32; i++, lram_addr += 2) {
11366 AscWriteLramWord(iop_base, lram_addr, 0);
11372 AscSetLibErrorCode(
11373 ASC_DVC_VAR *asc_dvc,
11377 if (asc_dvc->err_code == 0) {
11378 asc_dvc->err_code = err_code;
11379 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
11388 ASC_DVC_VAR *asc_dvc,
11394 uchar sdtr_period_index;
11397 iop_base = asc_dvc->iop_base;
11398 sdtr_buf.msg_type = MS_EXTEND;
11399 sdtr_buf.msg_len = MS_SDTR_LEN;
11400 sdtr_buf.msg_req = MS_SDTR_CODE;
11401 sdtr_buf.xfer_period = sdtr_period;
11402 sdtr_offset &= ASC_SYN_MAX_OFFSET;
11403 sdtr_buf.req_ack_offset = sdtr_offset;
11404 if ((sdtr_period_index =
11405 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
11406 asc_dvc->max_sdtr_index) {
11407 AscMemWordCopyPtrToLram(iop_base,
11409 (uchar *) &sdtr_buf,
11410 sizeof (EXT_MSG) >> 1);
11411 return ((sdtr_period_index << 4) | sdtr_offset);
11414 sdtr_buf.req_ack_offset = 0;
11415 AscMemWordCopyPtrToLram(iop_base,
11417 (uchar *) &sdtr_buf,
11418 sizeof (EXT_MSG) >> 1);
11425 ASC_DVC_VAR *asc_dvc,
11431 uchar sdtr_period_ix;
11433 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
11435 (sdtr_period_ix > asc_dvc->max_sdtr_index)
11439 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
11450 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11451 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
11456 AscGetSynPeriodIndex(
11457 ASC_DVC_VAR *asc_dvc,
11461 uchar *period_table;
11466 period_table = asc_dvc->sdtr_period_tbl;
11467 max_index = (int) asc_dvc->max_sdtr_index;
11468 min_index = (int)asc_dvc->host_init_sdtr_index;
11469 if ((syn_time <= period_table[max_index])) {
11470 for (i = min_index; i < (max_index - 1); i++) {
11471 if (syn_time <= period_table[i]) {
11472 return ((uchar) i);
11475 return ((uchar) max_index);
11477 return ((uchar) (max_index + 1));
11491 q_addr = ASC_QNO_TO_QADDR(free_q_head);
11492 q_status = (uchar) AscReadLramByte(iop_base,
11493 (ushort) (q_addr + ASC_SCSIQ_B_STATUS));
11494 next_qp = AscReadLramByte(iop_base,
11495 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11496 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
11499 return (ASC_QLINK_END);
11503 AscAllocMultipleFreeQueue(
11511 for (i = 0; i < n_free_q; i++) {
11512 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
11513 == ASC_QLINK_END) {
11514 return (ASC_QLINK_END);
11517 return (free_q_head);
11521 AscHostReqRiscHalt(
11527 uchar saved_stop_code;
11529 if (AscIsChipHalted(iop_base))
11531 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
11532 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11533 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP
11536 if (AscIsChipHalted(iop_base)) {
11540 DvcSleepMilliSecond(100);
11541 } while (count++ < 20);
11542 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
11553 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11554 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11555 ASC_STOP_REQ_RISC_STOP);
11558 AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11559 ASC_STOP_ACK_RISC_STOP) {
11562 DvcSleepMilliSecond(100);
11563 } while (count++ < 20);
11569 DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
11575 DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
11577 udelay((nano_sec + 999)/1000);
11581 STATIC ASC_DCNT __init
11582 AscGetEisaProductID(
11586 ushort product_id_high, product_id_low;
11587 ASC_DCNT product_id;
11589 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
11590 product_id_low = inpw(eisa_iop);
11591 product_id_high = inpw(eisa_iop + 2);
11592 product_id = ((ASC_DCNT) product_id_high << 16) |
11593 (ASC_DCNT) product_id_low;
11594 return (product_id);
11597 STATIC PortAddr __init
11598 AscSearchIOPortAddrEISA(
11601 ASC_DCNT eisa_product_id;
11603 if (iop_base == 0) {
11604 iop_base = ASC_EISA_MIN_IOP_ADDR;
11606 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11608 if ((iop_base & 0x0050) == 0x0050) {
11609 iop_base += ASC_EISA_BIG_IOP_GAP;
11611 iop_base += ASC_EISA_SMALL_IOP_GAP;
11614 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
11615 eisa_product_id = AscGetEisaProductID(iop_base);
11616 if ((eisa_product_id == ASC_EISA_ID_740) ||
11617 (eisa_product_id == ASC_EISA_ID_750)) {
11618 if (AscFindSignature(iop_base)) {
11619 inpw(iop_base + 4);
11623 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11625 if ((iop_base & 0x0050) == 0x0050) {
11626 iop_base += ASC_EISA_BIG_IOP_GAP;
11628 iop_base += ASC_EISA_SMALL_IOP_GAP;
11633 #endif /* CONFIG_ISA */
11640 AscSetChipControl(iop_base, 0);
11641 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11654 cc_val = AscGetChipControl(iop_base) & (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
11655 AscSetChipControl(iop_base, (uchar) (cc_val | CC_HALT));
11656 AscSetChipIH(iop_base, INS_HALT);
11657 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11658 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
11669 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11670 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
11683 AscSetBank(iop_base, 1);
11684 AscWriteChipIH(iop_base, ins_code);
11685 AscSetBank(iop_base, 0);
11700 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
11701 if (loop++ > 0x7FFF) {
11704 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
11705 host_flag = AscReadLramByte(iop_base, ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
11706 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
11707 (uchar) (host_flag | ASC_HOST_FLAG_ACK_INT));
11708 AscSetChipStatus(iop_base, CIW_INT_ACK);
11710 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
11711 AscSetChipStatus(iop_base, CIW_INT_ACK);
11716 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
11721 AscDisableInterrupt(
11727 cfg = AscGetChipCfgLsw(iop_base);
11728 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
11733 AscEnableInterrupt(
11739 cfg = AscGetChipCfgLsw(iop_base);
11740 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
11754 val = AscGetChipControl(iop_base) &
11755 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | CC_CHIP_RESET));
11757 val |= CC_BANK_ONE;
11758 } else if (bank == 2) {
11759 val |= CC_DIAG | CC_BANK_ONE;
11761 val &= ~CC_BANK_ONE;
11763 AscSetChipControl(iop_base, val);
11768 AscResetChipAndScsiBus(
11769 ASC_DVC_VAR *asc_dvc
11775 iop_base = asc_dvc->iop_base;
11776 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) && (i-- > 0))
11778 DvcSleepMilliSecond(100);
11780 AscStopChip(iop_base);
11781 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
11782 DvcDelayNanoSecond(asc_dvc, 60000);
11783 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11784 AscSetChipIH(iop_base, INS_HALT);
11785 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
11786 AscSetChipControl(iop_base, CC_HALT);
11787 DvcSleepMilliSecond(200);
11788 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
11789 AscSetChipStatus(iop_base, 0);
11790 return (AscIsChipHalted(iop_base));
11793 STATIC ASC_DCNT __init
11797 if (bus_type & ASC_IS_ISA)
11798 return (ASC_MAX_ISA_DMA_COUNT);
11799 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11800 return (ASC_MAX_VL_DMA_COUNT);
11801 return (ASC_MAX_PCI_DMA_COUNT);
11805 STATIC ushort __init
11806 AscGetIsaDmaChannel(
11811 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11812 if (channel == 0x03)
11814 else if (channel == 0x00)
11816 return (channel + 4);
11819 STATIC ushort __init
11820 AscSetIsaDmaChannel(
11822 ushort dma_channel)
11827 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11828 if (dma_channel == 7)
11831 value = dma_channel - 4;
11832 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11834 AscSetChipCfgLsw(iop_base, cfg_lsw);
11835 return (AscGetIsaDmaChannel(iop_base));
11840 STATIC uchar __init
11845 speed_value &= 0x07;
11846 AscSetBank(iop_base, 1);
11847 AscWriteChipDmaSpeed(iop_base, speed_value);
11848 AscSetBank(iop_base, 0);
11849 return (AscGetIsaDmaSpeed(iop_base));
11852 STATIC uchar __init
11859 AscSetBank(iop_base, 1);
11860 speed_value = AscReadChipDmaSpeed(iop_base);
11861 speed_value &= 0x07;
11862 AscSetBank(iop_base, 0);
11863 return (speed_value);
11865 #endif /* CONFIG_ISA */
11867 STATIC ushort __init
11868 AscReadPCIConfigWord(
11869 ASC_DVC_VAR *asc_dvc,
11870 ushort pci_config_offset)
11874 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
11875 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
11876 return ((ushort) ((msb << 8) | lsb));
11879 STATIC ushort __init
11881 ASC_DVC_VAR *asc_dvc
11886 ushort PCIDeviceID;
11887 ushort PCIVendorID;
11888 uchar PCIRevisionID;
11889 uchar prevCmdRegBits;
11892 iop_base = asc_dvc->iop_base;
11893 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11894 if (asc_dvc->err_code != 0) {
11897 if (asc_dvc->bus_type == ASC_IS_PCI) {
11898 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
11899 AscPCIConfigVendorIDRegister);
11901 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
11902 AscPCIConfigDeviceIDRegister);
11904 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
11905 AscPCIConfigRevisionIDRegister);
11907 if (PCIVendorID != PCI_VENDOR_ID_ASP) {
11908 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11910 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
11911 AscPCIConfigCommandRegister);
11913 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
11914 AscPCICmdRegBits_IOMemBusMaster) {
11915 DvcWritePCIConfigByte(asc_dvc,
11916 AscPCIConfigCommandRegister,
11918 AscPCICmdRegBits_IOMemBusMaster));
11920 if ((DvcReadPCIConfigByte(asc_dvc,
11921 AscPCIConfigCommandRegister)
11922 & AscPCICmdRegBits_IOMemBusMaster)
11923 != AscPCICmdRegBits_IOMemBusMaster) {
11924 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11927 if ((PCIDeviceID == PCI_DEVICE_ID_ASP_1200A) ||
11928 (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940)) {
11929 DvcWritePCIConfigByte(asc_dvc,
11930 AscPCIConfigLatencyTimer, 0x00);
11931 if (DvcReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer)
11933 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11935 } else if (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940U) {
11936 if (DvcReadPCIConfigByte(asc_dvc,
11937 AscPCIConfigLatencyTimer) < 0x20) {
11938 DvcWritePCIConfigByte(asc_dvc,
11939 AscPCIConfigLatencyTimer, 0x20);
11941 if (DvcReadPCIConfigByte(asc_dvc,
11942 AscPCIConfigLatencyTimer) < 0x20) {
11943 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11949 if (AscFindSignature(iop_base)) {
11950 warn_code |= AscInitAscDvcVar(asc_dvc);
11951 warn_code |= AscInitFromEEP(asc_dvc);
11952 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11953 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
11954 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11957 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11962 STATIC ushort __init
11964 ASC_DVC_VAR *asc_dvc
11967 ushort warn_code = 0;
11969 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11970 if (asc_dvc->err_code != 0)
11972 if (AscFindSignature(asc_dvc->iop_base)) {
11973 warn_code |= AscInitFromAscDvcVar(asc_dvc);
11974 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11976 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11978 return (warn_code);
11981 STATIC ushort __init
11982 AscInitFromAscDvcVar(
11983 ASC_DVC_VAR *asc_dvc
11989 ushort pci_device_id = 0;
11991 iop_base = asc_dvc->iop_base;
11993 if (asc_dvc->cfg->dev)
11994 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
11997 cfg_msw = AscGetChipCfgMsw(iop_base);
11998 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11999 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12000 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12001 AscSetChipCfgMsw(iop_base, cfg_msw);
12003 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12004 asc_dvc->cfg->cmd_qng_enabled) {
12005 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12006 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12008 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12009 warn_code |= ASC_WARN_AUTO_CONFIG;
12011 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12012 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12013 != asc_dvc->irq_no) {
12014 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12017 if (asc_dvc->bus_type & ASC_IS_PCI) {
12019 AscSetChipCfgMsw(iop_base, cfg_msw);
12020 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12022 if ((pci_device_id == PCI_DEVICE_ID_ASP_1200A) ||
12023 (pci_device_id == PCI_DEVICE_ID_ASP_ABP940)) {
12024 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12025 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12028 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12029 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12030 == ASC_CHIP_VER_ASYN_BUG) {
12031 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12034 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12035 asc_dvc->cfg->chip_scsi_id) {
12036 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12039 if (asc_dvc->bus_type & ASC_IS_ISA) {
12040 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12041 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12043 #endif /* CONFIG_ISA */
12044 return (warn_code);
12048 AscInitAsc1000Driver(
12049 ASC_DVC_VAR *asc_dvc
12055 iop_base = asc_dvc->iop_base;
12057 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
12058 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
12059 AscResetChipAndScsiBus(asc_dvc);
12060 DvcSleepMilliSecond((ASC_DCNT)
12061 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12063 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
12064 if (asc_dvc->err_code != 0)
12066 if (!AscFindSignature(asc_dvc->iop_base)) {
12067 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12068 return (warn_code);
12070 AscDisableInterrupt(iop_base);
12071 warn_code |= AscInitLram(asc_dvc);
12072 if (asc_dvc->err_code != 0)
12074 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
12075 (ulong) _asc_mcode_chksum);
12076 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
12077 _asc_mcode_size) != _asc_mcode_chksum) {
12078 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
12079 return (warn_code);
12081 warn_code |= AscInitMicroCodeVar(asc_dvc);
12082 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
12083 AscEnableInterrupt(iop_base);
12084 return (warn_code);
12087 STATIC ushort __init
12089 ASC_DVC_VAR *asc_dvc)
12094 uchar chip_version;
12096 iop_base = asc_dvc->iop_base;
12098 asc_dvc->err_code = 0;
12099 if ((asc_dvc->bus_type &
12100 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
12101 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
12103 AscSetChipControl(iop_base, CC_HALT);
12104 AscSetChipStatus(iop_base, 0);
12105 asc_dvc->bug_fix_cntl = 0;
12106 asc_dvc->pci_fix_asyn_xfer = 0;
12107 asc_dvc->pci_fix_asyn_xfer_always = 0;
12108 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
12109 asc_dvc->sdtr_done = 0;
12110 asc_dvc->cur_total_qng = 0;
12111 asc_dvc->is_in_int = 0;
12112 asc_dvc->in_critical_cnt = 0;
12113 asc_dvc->last_q_shortage = 0;
12114 asc_dvc->use_tagged_qng = 0;
12115 asc_dvc->no_scam = 0;
12116 asc_dvc->unit_not_ready = 0;
12117 asc_dvc->queue_full_or_busy = 0;
12118 asc_dvc->redo_scam = 0;
12120 asc_dvc->host_init_sdtr_index = 0;
12121 asc_dvc->cfg->can_tagged_qng = 0;
12122 asc_dvc->cfg->cmd_qng_enabled = 0;
12123 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
12124 asc_dvc->init_sdtr = 0;
12125 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
12126 asc_dvc->scsi_reset_wait = 3;
12127 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
12128 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
12129 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
12130 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
12131 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
12132 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
12133 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
12134 ASC_LIB_VERSION_MINOR;
12135 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
12136 asc_dvc->cfg->chip_version = chip_version;
12137 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
12138 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
12139 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
12140 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
12141 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
12142 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
12143 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
12144 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
12145 asc_dvc->max_sdtr_index = 7;
12146 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
12147 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
12148 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
12149 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
12150 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
12151 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
12152 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
12153 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
12154 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
12155 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
12156 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
12157 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
12158 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
12159 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
12160 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
12161 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
12162 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
12163 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
12164 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
12165 asc_dvc->max_sdtr_index = 15;
12166 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
12168 AscSetExtraControl(iop_base,
12169 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12170 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
12171 AscSetExtraControl(iop_base,
12172 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
12175 if (asc_dvc->bus_type == ASC_IS_PCI) {
12176 AscSetExtraControl(iop_base, (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12179 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
12180 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
12181 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
12182 asc_dvc->bus_type = ASC_IS_ISAPNP;
12185 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
12186 asc_dvc->cfg->isa_dma_channel = (uchar) AscGetIsaDmaChannel(iop_base);
12188 #endif /* CONFIG_ISA */
12189 for (i = 0; i <= ASC_MAX_TID; i++) {
12190 asc_dvc->cur_dvc_qng[i] = 0;
12191 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
12192 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *) 0L;
12193 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *) 0L;
12194 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
12196 return (warn_code);
12199 STATIC ushort __init
12200 AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12202 ASCEEP_CONFIG eep_config_buf;
12203 ASCEEP_CONFIG *eep_config;
12207 ushort cfg_msw, cfg_lsw;
12211 iop_base = asc_dvc->iop_base;
12213 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12214 AscStopQueueExe(iop_base);
12215 if ((AscStopChip(iop_base) == FALSE) ||
12216 (AscGetChipScsiCtrl(iop_base) != 0)) {
12217 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12218 AscResetChipAndScsiBus(asc_dvc);
12219 DvcSleepMilliSecond((ASC_DCNT)
12220 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12222 if (AscIsChipHalted(iop_base) == FALSE) {
12223 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12224 return (warn_code);
12226 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12227 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12228 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12229 return (warn_code);
12231 eep_config = (ASCEEP_CONFIG *) &eep_config_buf;
12232 cfg_msw = AscGetChipCfgMsw(iop_base);
12233 cfg_lsw = AscGetChipCfgLsw(iop_base);
12234 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12235 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12236 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12237 AscSetChipCfgMsw(iop_base, cfg_msw);
12239 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12240 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12244 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12245 warn_code |= ASC_WARN_AUTO_CONFIG;
12246 if (asc_dvc->cfg->chip_version == 3) {
12247 if (eep_config->cfg_lsw != cfg_lsw) {
12248 warn_code |= ASC_WARN_EEPROM_RECOVER;
12249 eep_config->cfg_lsw = AscGetChipCfgLsw(iop_base);
12251 if (eep_config->cfg_msw != cfg_msw) {
12252 warn_code |= ASC_WARN_EEPROM_RECOVER;
12253 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12257 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12258 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12259 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12260 eep_config->chksum);
12261 if (chksum != eep_config->chksum) {
12262 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12263 ASC_CHIP_VER_PCI_ULTRA_3050 )
12266 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12267 eep_config->init_sdtr = 0xFF;
12268 eep_config->disc_enable = 0xFF;
12269 eep_config->start_motor = 0xFF;
12270 eep_config->use_cmd_qng = 0;
12271 eep_config->max_total_qng = 0xF0;
12272 eep_config->max_tag_qng = 0x20;
12273 eep_config->cntl = 0xBFFF;
12274 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12275 eep_config->no_scam = 0;
12276 eep_config->adapter_info[0] = 0;
12277 eep_config->adapter_info[1] = 0;
12278 eep_config->adapter_info[2] = 0;
12279 eep_config->adapter_info[3] = 0;
12280 eep_config->adapter_info[4] = 0;
12281 /* Indicate EEPROM-less board. */
12282 eep_config->adapter_info[5] = 0xBB;
12285 "AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12287 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12290 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12291 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12292 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12293 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12294 asc_dvc->start_motor = eep_config->start_motor;
12295 asc_dvc->dvc_cntl = eep_config->cntl;
12296 asc_dvc->no_scam = eep_config->no_scam;
12297 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12298 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12299 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12300 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12301 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12302 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12303 if (!AscTestExternalLram(asc_dvc)) {
12304 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
12305 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12306 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12308 eep_config->cfg_msw |= 0x0800;
12310 AscSetChipCfgMsw(iop_base, cfg_msw);
12311 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12312 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12316 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12317 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12319 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12320 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12322 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12323 eep_config->max_tag_qng = eep_config->max_total_qng;
12325 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12326 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12328 asc_dvc->max_total_qng = eep_config->max_total_qng;
12329 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12330 eep_config->use_cmd_qng) {
12331 eep_config->disc_enable = eep_config->use_cmd_qng;
12332 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12334 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12335 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12337 ASC_EEP_SET_CHIP_ID(eep_config, ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12338 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12339 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12340 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12341 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12344 for (i = 0; i <= ASC_MAX_TID; i++) {
12345 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12346 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12347 asc_dvc->cfg->sdtr_period_offset[i] =
12348 (uchar) (ASC_DEF_SDTR_OFFSET |
12349 (asc_dvc->host_init_sdtr_index << 4));
12351 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12353 if ((i = AscSetEEPConfig(iop_base, eep_config, asc_dvc->bus_type)) !=
12356 "AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", i);
12358 ASC_PRINT("AscInitFromEEP: Succesfully re-wrote EEPROM.");
12361 return (warn_code);
12365 AscInitMicroCodeVar(
12366 ASC_DVC_VAR *asc_dvc
12372 ASC_PADDR phy_addr;
12375 iop_base = asc_dvc->iop_base;
12377 for (i = 0; i <= ASC_MAX_TID; i++) {
12378 AscPutMCodeInitSDTRAtID(iop_base, i,
12379 asc_dvc->cfg->sdtr_period_offset[i]
12383 AscInitQLinkVar(asc_dvc);
12384 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
12385 asc_dvc->cfg->disc_enable);
12386 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
12387 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
12389 /* Align overrun buffer on an 8 byte boundary. */
12390 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
12391 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
12392 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
12393 (uchar *) &phy_addr, 1);
12394 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
12395 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
12396 (uchar *) &phy_size, 1);
12398 asc_dvc->cfg->mcode_date =
12399 AscReadLramWord(iop_base, (ushort) ASCV_MC_DATE_W);
12400 asc_dvc->cfg->mcode_version =
12401 AscReadLramWord(iop_base, (ushort) ASCV_MC_VER_W);
12403 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12404 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12405 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12406 return (warn_code);
12408 if (AscStartChip(iop_base) != 1) {
12409 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12410 return (warn_code);
12413 return (warn_code);
12417 AscTestExternalLram(
12418 ASC_DVC_VAR *asc_dvc)
12425 iop_base = asc_dvc->iop_base;
12427 q_addr = ASC_QNO_TO_QADDR(241);
12428 saved_word = AscReadLramWord(iop_base, q_addr);
12429 AscSetChipLramAddr(iop_base, q_addr);
12430 AscSetChipLramData(iop_base, 0x55AA);
12431 DvcSleepMilliSecond(10);
12432 AscSetChipLramAddr(iop_base, q_addr);
12433 if (AscGetChipLramData(iop_base) == 0x55AA) {
12435 AscWriteLramWord(iop_base, q_addr, saved_word);
12451 AscSetChipEEPCmd(iop_base, cmd_reg);
12452 DvcSleepMilliSecond(1);
12453 read_back = AscGetChipEEPCmd(iop_base);
12454 if (read_back == cmd_reg) {
12457 if (retry++ > ASC_EEP_MAX_RETRY) {
12464 AscWriteEEPDataReg(
12474 AscSetChipEEPData(iop_base, data_reg);
12475 DvcSleepMilliSecond(1);
12476 read_back = AscGetChipEEPData(iop_base);
12477 if (read_back == data_reg) {
12480 if (retry++ > ASC_EEP_MAX_RETRY) {
12487 AscWaitEEPRead(void)
12489 DvcSleepMilliSecond(1);
12494 AscWaitEEPWrite(void)
12496 DvcSleepMilliSecond(20);
12500 STATIC ushort __init
12508 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12510 cmd_reg = addr | ASC_EEP_CMD_READ;
12511 AscWriteEEPCmdReg(iop_base, cmd_reg);
12513 read_wval = AscGetChipEEPData(iop_base);
12515 return (read_wval);
12518 STATIC ushort __init
12526 read_wval = AscReadEEPWord(iop_base, addr);
12527 if (read_wval != word_val) {
12528 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12530 AscWriteEEPDataReg(iop_base, word_val);
12532 AscWriteEEPCmdReg(iop_base,
12533 (uchar) ((uchar) ASC_EEP_CMD_WRITE | addr));
12535 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12537 return (AscReadEEPWord(iop_base, addr));
12539 return (read_wval);
12542 STATIC ushort __init
12545 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12552 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12555 wbuf = (ushort *) cfg_buf;
12557 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
12558 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12559 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12562 if (bus_type & ASC_IS_VL) {
12563 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12564 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12566 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12567 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12569 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12570 wval = AscReadEEPWord( iop_base, ( uchar )s_addr ) ;
12571 if (s_addr <= uchar_end_in_config) {
12573 * Swap all char fields - must unswap bytes already swapped
12574 * by AscReadEEPWord().
12576 *wbuf = le16_to_cpu(wval);
12578 /* Don't swap word field at the end - cntl field. */
12581 sum += wval; /* Checksum treats all EEPROM data as words. */
12584 * Read the checksum word which will be compared against 'sum'
12585 * by the caller. Word field already swapped.
12587 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12592 AscSetEEPConfigOnce(
12594 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12603 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12606 wbuf = (ushort *) cfg_buf;
12609 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12610 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12612 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12616 if (bus_type & ASC_IS_VL) {
12617 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12618 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12620 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12621 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12623 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12624 if (s_addr <= uchar_end_in_config) {
12626 * This is a char field. Swap char fields before they are
12627 * swapped again by AscWriteEEPWord().
12629 word = cpu_to_le16(*wbuf);
12630 if (word != AscWriteEEPWord( iop_base, (uchar) s_addr, word)) {
12634 /* Don't swap word field at the end - cntl field. */
12635 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12639 sum += *wbuf; /* Checksum calculated from word values. */
12641 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12643 if (sum != AscWriteEEPWord(iop_base, (uchar) s_addr, sum)) {
12647 /* Read EEPROM back again. */
12648 wbuf = (ushort *) cfg_buf;
12650 * Read two config words; Byte-swapping done by AscReadEEPWord().
12652 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12653 if (*wbuf != AscReadEEPWord(iop_base, (uchar) s_addr)) {
12657 if (bus_type & ASC_IS_VL) {
12658 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12659 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12661 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12662 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12664 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12665 if (s_addr <= uchar_end_in_config) {
12667 * Swap all char fields. Must unswap bytes already swapped
12668 * by AscReadEEPWord().
12670 word = le16_to_cpu(AscReadEEPWord(iop_base, (uchar) s_addr));
12672 /* Don't swap word field at the end - cntl field. */
12673 word = AscReadEEPWord(iop_base, (uchar) s_addr);
12675 if (*wbuf != word) {
12679 /* Read checksum; Byte swapping not needed. */
12680 if (AscReadEEPWord(iop_base, (uchar) s_addr) != sum) {
12689 ASCEEP_CONFIG * cfg_buf, ushort bus_type
12697 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12701 if (++retry > ASC_EEP_MAX_RETRY) {
12710 ASC_DVC_VAR *asc_dvc,
12712 ASC_SCSI_INQUIRY *inq)
12715 ASC_SCSI_BIT_ID_TYPE tid_bits;
12717 dvc_type = ASC_INQ_DVC_TYPE(inq);
12718 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
12720 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)
12722 if (!(asc_dvc->init_sdtr & tid_bits))
12724 if ((dvc_type == TYPE_ROM) &&
12725 (AscCompareString((uchar *) inq->vendor_id,
12726 (uchar *) "HP ", 3) == 0))
12728 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
12730 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
12731 if ((dvc_type == TYPE_PROCESSOR) ||
12732 (dvc_type == TYPE_SCANNER) ||
12733 (dvc_type == TYPE_ROM) ||
12734 (dvc_type == TYPE_TAPE))
12736 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
12739 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
12741 AscSetRunChipSynRegAtID(asc_dvc->iop_base, tid_no,
12742 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
12750 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
12752 if ((inq->add_len >= 32) &&
12753 (AscCompareString((uchar *) inq->vendor_id,
12754 (uchar *) "QUANTUM XP34301", 15) == 0) &&
12755 (AscCompareString((uchar *) inq->product_rev_level,
12756 (uchar *) "1071", 4) == 0))
12764 AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
12765 uchar tid_no, ASC_SCSI_INQUIRY *inq)
12767 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
12768 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
12770 orig_init_sdtr = asc_dvc->init_sdtr;
12771 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
12773 asc_dvc->init_sdtr &= ~tid_bit;
12774 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
12775 asc_dvc->use_tagged_qng &= ~tid_bit;
12777 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
12778 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
12779 asc_dvc->init_sdtr |= tid_bit;
12781 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
12782 ASC_INQ_CMD_QUEUE(inq)) {
12783 if (AscTagQueuingSafe(inq)) {
12784 asc_dvc->use_tagged_qng |= tid_bit;
12785 asc_dvc->cfg->can_tagged_qng |= tid_bit;
12789 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
12790 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
12791 asc_dvc->cfg->disc_enable);
12792 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
12793 asc_dvc->use_tagged_qng);
12794 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
12795 asc_dvc->cfg->can_tagged_qng);
12797 asc_dvc->max_dvc_qng[tid_no] =
12798 asc_dvc->cfg->max_tag_qng[tid_no];
12799 AscWriteLramByte(asc_dvc->iop_base,
12800 (ushort) (ASCV_MAX_DVC_QNG_BEG + tid_no),
12801 asc_dvc->max_dvc_qng[tid_no]);
12803 if (orig_init_sdtr != asc_dvc->init_sdtr) {
12804 AscAsyncFix(asc_dvc, tid_no, inq);
12819 for (i = 0; i < len; i++) {
12820 diff = (int) (str1[i] - str2[i]);
12836 if (isodd_word(addr)) {
12837 AscSetChipLramAddr(iop_base, addr - 1);
12838 word_data = AscGetChipLramData(iop_base);
12839 byte_data = (uchar) ((word_data >> 8) & 0xFF);
12841 AscSetChipLramAddr(iop_base, addr);
12842 word_data = AscGetChipLramData(iop_base);
12843 byte_data = (uchar) (word_data & 0xFF);
12845 return (byte_data);
12855 AscSetChipLramAddr(iop_base, addr);
12856 word_data = AscGetChipLramData(iop_base);
12857 return (word_data);
12860 #if CC_VERY_LONG_SG_LIST
12867 ushort val_low, val_high;
12868 ASC_DCNT dword_data;
12870 AscSetChipLramAddr(iop_base, addr);
12871 val_low = AscGetChipLramData(iop_base);
12872 val_high = AscGetChipLramData(iop_base);
12873 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
12874 return (dword_data);
12876 #endif /* CC_VERY_LONG_SG_LIST */
12885 AscSetChipLramAddr(iop_base, addr);
12886 AscSetChipLramData(iop_base, word_val);
12899 if (isodd_word(addr)) {
12901 word_data = AscReadLramWord(iop_base, addr);
12902 word_data &= 0x00FF;
12903 word_data |= (((ushort) byte_val << 8) & 0xFF00);
12905 word_data = AscReadLramWord(iop_base, addr);
12906 word_data &= 0xFF00;
12907 word_data |= ((ushort) byte_val & 0x00FF);
12909 AscWriteLramWord(iop_base, addr, word_data);
12914 * Copy 2 bytes to LRAM.
12916 * The source data is assumed to be in little-endian order in memory
12917 * and is maintained in little-endian order when written to LRAM.
12920 AscMemWordCopyPtrToLram(
12929 AscSetChipLramAddr(iop_base, s_addr);
12930 for (i = 0; i < 2 * words; i += 2) {
12932 * On a little-endian system the second argument below
12933 * produces a little-endian ushort which is written to
12934 * LRAM in little-endian order. On a big-endian system
12935 * the second argument produces a big-endian ushort which
12936 * is "transparently" byte-swapped by outpw() and written
12937 * in little-endian order to LRAM.
12939 outpw(iop_base + IOP_RAM_DATA,
12940 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]);
12946 * Copy 4 bytes to LRAM.
12948 * The source data is assumed to be in little-endian order in memory
12949 * and is maintained in little-endian order when writen to LRAM.
12952 AscMemDWordCopyPtrToLram(
12961 AscSetChipLramAddr(iop_base, s_addr);
12962 for (i = 0; i < 4 * dwords; i += 4) {
12963 outpw(iop_base + IOP_RAM_DATA,
12964 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
12965 outpw(iop_base + IOP_RAM_DATA,
12966 ((ushort) s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
12972 * Copy 2 bytes from LRAM.
12974 * The source data is assumed to be in little-endian order in LRAM
12975 * and is maintained in little-endian order when written to memory.
12978 AscMemWordCopyPtrFromLram(
12988 AscSetChipLramAddr(iop_base, s_addr);
12989 for (i = 0; i < 2 * words; i += 2) {
12990 word = inpw(iop_base + IOP_RAM_DATA);
12991 d_buffer[i] = word & 0xff;
12992 d_buffer[i + 1] = (word >> 8) & 0xff;
13008 for (i = 0; i < words; i++, s_addr += 2) {
13009 sum += AscReadLramWord(iop_base, s_addr);
13024 AscSetChipLramAddr(iop_base, s_addr);
13025 for (i = 0; i < words; i++) {
13026 AscSetChipLramData(iop_base, set_wval);
13033 * --- Adv Library Functions
13038 /* Microcode buffer is kept after initialization for error recovery. */
13039 STATIC unsigned char _adv_asc3550_buf[] = {
13040 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, 0x01, 0x00, 0x48, 0xe4,
13041 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7,
13042 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
13043 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, 0x00, 0xec, 0x85, 0xf0,
13044 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00,
13045 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
13046 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea,
13047 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
13048 0xc0, 0x00, 0x01, 0x01, 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
13049 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00, 0x3e, 0x00, 0x80, 0x00,
13050 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
13051 0x78, 0x01, 0x62, 0x0a, 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
13052 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
13053 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00, 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15,
13054 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
13055 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
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13283 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0xfe, 0xff, 0x7f,
13284 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c,
13285 0x3d, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
13286 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, 0x03, 0x0a, 0x50, 0x01,
13287 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4,
13288 0x19, 0x48, 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
13289 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe,
13290 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60,
13291 0x89, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
13292 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, 0xcc, 0x12, 0x49, 0x04,
13293 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13,
13294 0x06, 0x17, 0xc3, 0x78, 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
13295 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, 0x13, 0x06, 0xfe, 0x56,
13296 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93,
13297 0x13, 0x06, 0xfe, 0x28, 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
13298 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, 0x01, 0xba, 0xfe, 0x4e,
13299 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe,
13300 0x04, 0xf4, 0x6c, 0xfe, 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
13301 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13302 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13303 0x19, 0x83, 0x60, 0x23, 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
13304 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x0b, 0x01,
13305 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03,
13306 0x15, 0x06, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
13307 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, 0x4a, 0x01, 0x08, 0x03,
13308 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00,
13309 0x3b, 0x72, 0x9f, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
13310 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, 0x01, 0x43, 0x1e, 0xcd,
13311 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10,
13312 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
13313 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, 0x88, 0x03, 0x0a, 0x42,
13314 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2,
13315 0xfe, 0x49, 0xe4, 0x10, 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
13316 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe,
13317 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe,
13318 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
13319 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, 0x05, 0xfe, 0x66, 0x01,
13320 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66,
13321 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
13322 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x83,
13323 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe,
13324 0x94, 0x14, 0xfe, 0x10, 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13325 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x30, 0xbc, 0xfe,
13326 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a,
13327 0x16, 0xfe, 0x5c, 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13328 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, 0xfe, 0x1d, 0xf7, 0x4f,
13329 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58,
13330 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
13331 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, 0x06, 0x37, 0x95, 0xa9,
13332 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d,
13333 0x13, 0x0d, 0x03, 0x71, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
13334 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x3c, 0x8a, 0x0a,
13335 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc,
13336 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
13337 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xf6, 0xfe, 0xd6, 0xf0,
13338 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76,
13339 0x27, 0x01, 0xda, 0x17, 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
13340 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, 0xc8, 0xfe, 0x48, 0x55,
13341 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0,
13342 0x0a, 0x40, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
13343 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, 0x0e, 0x73, 0x75, 0x03,
13344 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b,
13345 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
13346 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, 0xfe, 0x94, 0x00, 0xfe,
13347 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e,
13348 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
13349 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1b, 0xfe, 0x5a,
13350 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07,
13351 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
13352 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, 0x03, 0x25, 0xfe, 0xca,
13353 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
13356 STATIC unsigned short _adv_asc3550_size =
13357 sizeof(_adv_asc3550_buf); /* 0x13AD */
13358 STATIC ADV_DCNT _adv_asc3550_chksum =
13359 0x04D52DDDUL; /* Expanded little-endian checksum. */
13361 /* Microcode buffer is kept after initialization for error recovery. */
13362 STATIC unsigned char _adv_asc38C0800_buf[] = {
13363 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, 0x01, 0x00, 0x48, 0xe4,
13364 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6,
13365 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
13366 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0, 0x18, 0xf4, 0x08, 0x00,
13367 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0,
13368 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
13369 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13, 0xba, 0x13, 0x18, 0x40,
13370 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01,
13371 0x76, 0x01, 0xb9, 0x54, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
13372 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12, 0x08, 0x12, 0x02, 0x4a,
13373 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa,
13374 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
13375 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d, 0x06, 0x13, 0x4c, 0x1c,
13376 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00,
13377 0xbe, 0x00, 0x00, 0x01, 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
13378 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, 0x05, 0x00, 0x34, 0x00,
13379 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f,
13380 0x0c, 0x10, 0x22, 0x11, 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
13381 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0,
13382 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00,
13383 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
13384 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13, 0x12, 0x13, 0x24, 0x14,
13385 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44,
13386 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
13387 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, 0x04, 0xf8,
13388 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13389 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
13390 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08, 0x68, 0x08, 0x69, 0x08,
13391 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10,
13392 0x2a, 0x11, 0x06, 0x12, 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
13393 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18, 0xca, 0x18, 0xe6, 0x19,
13394 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe,
13395 0xac, 0x0d, 0xff, 0x10, 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
13396 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13397 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00, 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13398 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
13399 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xd6,
13400 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe, 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe,
13401 0x3d, 0xf0, 0xfe, 0x06, 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
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13631 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33,
13632 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59,
13633 0x03, 0xcd, 0x28, 0xfe, 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
13634 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, 0x30, 0xfe, 0x78, 0x10,
13635 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00,
13636 0x96, 0xf2, 0x18, 0x6d, 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
13637 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, 0x10, 0x69, 0x06, 0xfe,
13638 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06,
13639 0x88, 0x98, 0xfe, 0x90, 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
13640 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, 0x9e, 0xfe, 0xf3, 0x10,
13641 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13642 0x6e, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13643 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, 0xf4, 0x00, 0xe9, 0x91,
13644 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01,
13645 0x0b, 0x26, 0xf3, 0x16, 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
13646 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x19, 0x01, 0x0b,
13647 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76,
13648 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
13649 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01,
13650 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00,
13651 0xfe, 0x20, 0x13, 0x1d, 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
13652 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, 0x07, 0x11, 0xae, 0x09,
13653 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80,
13654 0xe7, 0x11, 0x07, 0x11, 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
13655 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xfe, 0x80, 0x4c,
13656 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87,
13657 0x04, 0x18, 0x11, 0x75, 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
13658 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, 0x17, 0xad, 0x9a, 0x1b,
13659 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10,
13660 0x18, 0x11, 0x75, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
13661 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c,
13662 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17,
13663 0xfe, 0xb6, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
13664 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x2e, 0x97, 0xfe, 0x5a,
13665 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13666 0x04, 0xb9, 0x23, 0xfe, 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
13667 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xcb, 0x97, 0xfe, 0x92,
13668 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13669 0xf6, 0x11, 0x75, 0xfe, 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
13670 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x9a, 0x5b, 0x41, 0xfe,
13671 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd,
13672 0x00, 0x6a, 0x2a, 0x04, 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
13673 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, 0xfe, 0x7e, 0x18, 0x1e,
13674 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
13675 0x7c, 0x6f, 0x4f, 0x32, 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
13676 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc,
13677 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c,
13678 0x01, 0x73, 0xfe, 0x16, 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
13679 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, 0xe7, 0x0a, 0x10, 0xfe,
13680 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37,
13681 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
13682 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, 0x13, 0xa3, 0x04, 0x09,
13683 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8,
13684 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
13685 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, 0x1c, 0x19, 0x03, 0xfe,
13686 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19,
13687 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
13688 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, 0x08, 0x10, 0x03, 0xfe,
13689 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7,
13690 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
13691 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, 0x04, 0x07, 0x7e, 0xfe,
13692 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a,
13693 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
13694 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, 0xa9, 0xb8, 0x04, 0x15,
13695 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c,
13696 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
13697 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13700 STATIC unsigned short _adv_asc38C0800_size =
13701 sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13702 STATIC ADV_DCNT _adv_asc38C0800_chksum =
13703 0x050D3FD8UL; /* Expanded little-endian checksum. */
13705 /* Microcode buffer is kept after initialization for error recovery. */
13706 STATIC unsigned char _adv_asc38C1600_buf[] = {
13707 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, 0x18, 0xe4, 0x01, 0x00,
13708 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f,
13709 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
13710 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x01, 0xe6,
13711 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0,
13712 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
13713 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01, 0x06, 0x13, 0x0c, 0x1c,
13714 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80,
13715 0x62, 0x0a, 0x5a, 0x12, 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
13716 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x04, 0x13, 0xbb, 0x55,
13717 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00,
13718 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
13719 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01,
13720 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01,
13721 0xc6, 0x0e, 0x0c, 0x10, 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
13722 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x06, 0x00,
13723 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c,
13724 0x10, 0x44, 0x00, 0x4c, 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
13725 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00,
13726 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09,
13727 0x68, 0x0d, 0x02, 0x10, 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
13728 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
13729 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00,
13730 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
13731 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x42, 0x1d, 0x08, 0x44,
13732 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59,
13733 0x31, 0xe4, 0x02, 0xe6, 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
13734 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13735 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01,
13736 0xc8, 0x01, 0xca, 0x01, 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
13737 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10, 0xf3, 0x10, 0x06, 0x12,
13738 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe,
13739 0xec, 0x0e, 0xff, 0x10, 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
13740 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13741 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13742 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
13743 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xe8,
13744 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe, 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe,
13745 0x3d, 0xf0, 0xfe, 0x0c, 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
13746 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d, 0x05, 0xfe, 0x08, 0x0f,
13747 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05, 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe,
13748 0xa6, 0x00, 0xfe, 0xd1, 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
13749 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8, 0x02, 0xfe, 0x46, 0xf0,
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14087 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
14088 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, 0xfe, 0x82, 0xf0, 0xfe,
14089 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18,
14090 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
14091 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, 0x83, 0x33, 0x0b, 0x0e,
14092 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04,
14093 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
14094 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, 0xfe, 0x99, 0x83, 0xfe,
14095 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47,
14096 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14097 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x08, 0x90, 0x04,
14098 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79,
14099 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14100 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x3c, 0x90, 0x04,
14101 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83,
14102 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
14105 STATIC unsigned short _adv_asc38C1600_size =
14106 sizeof(_adv_asc38C1600_buf); /* 0x1673 */
14107 STATIC ADV_DCNT _adv_asc38C1600_chksum =
14108 0x0604EF77UL; /* Expanded little-endian checksum. */
14112 * EEPROM Configuration.
14114 * All drivers should use this structure to set the default EEPROM
14115 * configuration. The BIOS now uses this structure when it is built.
14116 * Additional structure information can be found in a_condor.h where
14117 * the structure is defined.
14119 * The *_Field_IsChar structs are needed to correct for endianness.
14120 * These values are read from the board 16 bits at a time directly
14121 * into the structs. Because some fields are char, the values will be
14122 * in the wrong order. The *_Field_IsChar tells when to flip the
14123 * bytes. Data read and written to PCI memory is automatically swapped
14124 * on big-endian platforms so char fields read as words are actually being
14125 * unswapped on big-endian platforms.
14127 STATIC ADVEEP_3550_CONFIG
14128 Default_3550_EEPROM_Config __initdata = {
14129 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
14130 0x0000, /* cfg_msw */
14131 0xFFFF, /* disc_enable */
14132 0xFFFF, /* wdtr_able */
14133 0xFFFF, /* sdtr_able */
14134 0xFFFF, /* start_motor */
14135 0xFFFF, /* tagqng_able */
14136 0xFFFF, /* bios_scan */
14137 0, /* scam_tolerant */
14138 7, /* adapter_scsi_id */
14139 0, /* bios_boot_delay */
14140 3, /* scsi_reset_delay */
14141 0, /* bios_id_lun */
14142 0, /* termination */
14144 0xFFE7, /* bios_ctrl */
14145 0xFFFF, /* ultra_able */
14147 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
14148 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14151 0, /* serial_number_word1 */
14152 0, /* serial_number_word2 */
14153 0, /* serial_number_word3 */
14155 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */
14156 0, /* dvc_err_code */
14157 0, /* adv_err_code */
14158 0, /* adv_err_addr */
14159 0, /* saved_dvc_err_code */
14160 0, /* saved_adv_err_code */
14161 0, /* saved_adv_err_addr */
14165 STATIC ADVEEP_3550_CONFIG
14166 ADVEEP_3550_Config_Field_IsChar __initdata = {
14169 0, /* -disc_enable */
14172 0, /* start_motor */
14173 0, /* tagqng_able */
14175 0, /* scam_tolerant */
14176 1, /* adapter_scsi_id */
14177 1, /* bios_boot_delay */
14178 1, /* scsi_reset_delay */
14179 1, /* bios_id_lun */
14180 1, /* termination */
14183 0, /* ultra_able */
14185 1, /* max_host_qng */
14186 1, /* max_dvc_qng */
14189 0, /* serial_number_word1 */
14190 0, /* serial_number_word2 */
14191 0, /* serial_number_word3 */
14193 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* oem_name[16] */
14194 0, /* dvc_err_code */
14195 0, /* adv_err_code */
14196 0, /* adv_err_addr */
14197 0, /* saved_dvc_err_code */
14198 0, /* saved_adv_err_code */
14199 0, /* saved_adv_err_addr */
14203 STATIC ADVEEP_38C0800_CONFIG
14204 Default_38C0800_EEPROM_Config __initdata = {
14205 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14206 0x0000, /* 01 cfg_msw */
14207 0xFFFF, /* 02 disc_enable */
14208 0xFFFF, /* 03 wdtr_able */
14209 0x4444, /* 04 sdtr_speed1 */
14210 0xFFFF, /* 05 start_motor */
14211 0xFFFF, /* 06 tagqng_able */
14212 0xFFFF, /* 07 bios_scan */
14213 0, /* 08 scam_tolerant */
14214 7, /* 09 adapter_scsi_id */
14215 0, /* bios_boot_delay */
14216 3, /* 10 scsi_reset_delay */
14217 0, /* bios_id_lun */
14218 0, /* 11 termination_se */
14219 0, /* termination_lvd */
14220 0xFFE7, /* 12 bios_ctrl */
14221 0x4444, /* 13 sdtr_speed2 */
14222 0x4444, /* 14 sdtr_speed3 */
14223 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14224 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14225 0, /* 16 dvc_cntl */
14226 0x4444, /* 17 sdtr_speed4 */
14227 0, /* 18 serial_number_word1 */
14228 0, /* 19 serial_number_word2 */
14229 0, /* 20 serial_number_word3 */
14230 0, /* 21 check_sum */
14231 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14232 0, /* 30 dvc_err_code */
14233 0, /* 31 adv_err_code */
14234 0, /* 32 adv_err_addr */
14235 0, /* 33 saved_dvc_err_code */
14236 0, /* 34 saved_adv_err_code */
14237 0, /* 35 saved_adv_err_addr */
14238 0, /* 36 reserved */
14239 0, /* 37 reserved */
14240 0, /* 38 reserved */
14241 0, /* 39 reserved */
14242 0, /* 40 reserved */
14243 0, /* 41 reserved */
14244 0, /* 42 reserved */
14245 0, /* 43 reserved */
14246 0, /* 44 reserved */
14247 0, /* 45 reserved */
14248 0, /* 46 reserved */
14249 0, /* 47 reserved */
14250 0, /* 48 reserved */
14251 0, /* 49 reserved */
14252 0, /* 50 reserved */
14253 0, /* 51 reserved */
14254 0, /* 52 reserved */
14255 0, /* 53 reserved */
14256 0, /* 54 reserved */
14257 0, /* 55 reserved */
14258 0, /* 56 cisptr_lsw */
14259 0, /* 57 cisprt_msw */
14260 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
14261 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
14262 0, /* 60 reserved */
14263 0, /* 61 reserved */
14264 0, /* 62 reserved */
14265 0 /* 63 reserved */
14268 STATIC ADVEEP_38C0800_CONFIG
14269 ADVEEP_38C0800_Config_Field_IsChar __initdata = {
14270 0, /* 00 cfg_lsw */
14271 0, /* 01 cfg_msw */
14272 0, /* 02 disc_enable */
14273 0, /* 03 wdtr_able */
14274 0, /* 04 sdtr_speed1 */
14275 0, /* 05 start_motor */
14276 0, /* 06 tagqng_able */
14277 0, /* 07 bios_scan */
14278 0, /* 08 scam_tolerant */
14279 1, /* 09 adapter_scsi_id */
14280 1, /* bios_boot_delay */
14281 1, /* 10 scsi_reset_delay */
14282 1, /* bios_id_lun */
14283 1, /* 11 termination_se */
14284 1, /* termination_lvd */
14285 0, /* 12 bios_ctrl */
14286 0, /* 13 sdtr_speed2 */
14287 0, /* 14 sdtr_speed3 */
14288 1, /* 15 max_host_qng */
14289 1, /* max_dvc_qng */
14290 0, /* 16 dvc_cntl */
14291 0, /* 17 sdtr_speed4 */
14292 0, /* 18 serial_number_word1 */
14293 0, /* 19 serial_number_word2 */
14294 0, /* 20 serial_number_word3 */
14295 0, /* 21 check_sum */
14296 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14297 0, /* 30 dvc_err_code */
14298 0, /* 31 adv_err_code */
14299 0, /* 32 adv_err_addr */
14300 0, /* 33 saved_dvc_err_code */
14301 0, /* 34 saved_adv_err_code */
14302 0, /* 35 saved_adv_err_addr */
14303 0, /* 36 reserved */
14304 0, /* 37 reserved */
14305 0, /* 38 reserved */
14306 0, /* 39 reserved */
14307 0, /* 40 reserved */
14308 0, /* 41 reserved */
14309 0, /* 42 reserved */
14310 0, /* 43 reserved */
14311 0, /* 44 reserved */
14312 0, /* 45 reserved */
14313 0, /* 46 reserved */
14314 0, /* 47 reserved */
14315 0, /* 48 reserved */
14316 0, /* 49 reserved */
14317 0, /* 50 reserved */
14318 0, /* 51 reserved */
14319 0, /* 52 reserved */
14320 0, /* 53 reserved */
14321 0, /* 54 reserved */
14322 0, /* 55 reserved */
14323 0, /* 56 cisptr_lsw */
14324 0, /* 57 cisprt_msw */
14325 0, /* 58 subsysvid */
14326 0, /* 59 subsysid */
14327 0, /* 60 reserved */
14328 0, /* 61 reserved */
14329 0, /* 62 reserved */
14330 0 /* 63 reserved */
14333 STATIC ADVEEP_38C1600_CONFIG
14334 Default_38C1600_EEPROM_Config __initdata = {
14335 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14336 0x0000, /* 01 cfg_msw */
14337 0xFFFF, /* 02 disc_enable */
14338 0xFFFF, /* 03 wdtr_able */
14339 0x5555, /* 04 sdtr_speed1 */
14340 0xFFFF, /* 05 start_motor */
14341 0xFFFF, /* 06 tagqng_able */
14342 0xFFFF, /* 07 bios_scan */
14343 0, /* 08 scam_tolerant */
14344 7, /* 09 adapter_scsi_id */
14345 0, /* bios_boot_delay */
14346 3, /* 10 scsi_reset_delay */
14347 0, /* bios_id_lun */
14348 0, /* 11 termination_se */
14349 0, /* termination_lvd */
14350 0xFFE7, /* 12 bios_ctrl */
14351 0x5555, /* 13 sdtr_speed2 */
14352 0x5555, /* 14 sdtr_speed3 */
14353 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14354 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14355 0, /* 16 dvc_cntl */
14356 0x5555, /* 17 sdtr_speed4 */
14357 0, /* 18 serial_number_word1 */
14358 0, /* 19 serial_number_word2 */
14359 0, /* 20 serial_number_word3 */
14360 0, /* 21 check_sum */
14361 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14362 0, /* 30 dvc_err_code */
14363 0, /* 31 adv_err_code */
14364 0, /* 32 adv_err_addr */
14365 0, /* 33 saved_dvc_err_code */
14366 0, /* 34 saved_adv_err_code */
14367 0, /* 35 saved_adv_err_addr */
14368 0, /* 36 reserved */
14369 0, /* 37 reserved */
14370 0, /* 38 reserved */
14371 0, /* 39 reserved */
14372 0, /* 40 reserved */
14373 0, /* 41 reserved */
14374 0, /* 42 reserved */
14375 0, /* 43 reserved */
14376 0, /* 44 reserved */
14377 0, /* 45 reserved */
14378 0, /* 46 reserved */
14379 0, /* 47 reserved */
14380 0, /* 48 reserved */
14381 0, /* 49 reserved */
14382 0, /* 50 reserved */
14383 0, /* 51 reserved */
14384 0, /* 52 reserved */
14385 0, /* 53 reserved */
14386 0, /* 54 reserved */
14387 0, /* 55 reserved */
14388 0, /* 56 cisptr_lsw */
14389 0, /* 57 cisprt_msw */
14390 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
14391 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
14392 0, /* 60 reserved */
14393 0, /* 61 reserved */
14394 0, /* 62 reserved */
14395 0 /* 63 reserved */
14398 STATIC ADVEEP_38C1600_CONFIG
14399 ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14400 0, /* 00 cfg_lsw */
14401 0, /* 01 cfg_msw */
14402 0, /* 02 disc_enable */
14403 0, /* 03 wdtr_able */
14404 0, /* 04 sdtr_speed1 */
14405 0, /* 05 start_motor */
14406 0, /* 06 tagqng_able */
14407 0, /* 07 bios_scan */
14408 0, /* 08 scam_tolerant */
14409 1, /* 09 adapter_scsi_id */
14410 1, /* bios_boot_delay */
14411 1, /* 10 scsi_reset_delay */
14412 1, /* bios_id_lun */
14413 1, /* 11 termination_se */
14414 1, /* termination_lvd */
14415 0, /* 12 bios_ctrl */
14416 0, /* 13 sdtr_speed2 */
14417 0, /* 14 sdtr_speed3 */
14418 1, /* 15 max_host_qng */
14419 1, /* max_dvc_qng */
14420 0, /* 16 dvc_cntl */
14421 0, /* 17 sdtr_speed4 */
14422 0, /* 18 serial_number_word1 */
14423 0, /* 19 serial_number_word2 */
14424 0, /* 20 serial_number_word3 */
14425 0, /* 21 check_sum */
14426 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14427 0, /* 30 dvc_err_code */
14428 0, /* 31 adv_err_code */
14429 0, /* 32 adv_err_addr */
14430 0, /* 33 saved_dvc_err_code */
14431 0, /* 34 saved_adv_err_code */
14432 0, /* 35 saved_adv_err_addr */
14433 0, /* 36 reserved */
14434 0, /* 37 reserved */
14435 0, /* 38 reserved */
14436 0, /* 39 reserved */
14437 0, /* 40 reserved */
14438 0, /* 41 reserved */
14439 0, /* 42 reserved */
14440 0, /* 43 reserved */
14441 0, /* 44 reserved */
14442 0, /* 45 reserved */
14443 0, /* 46 reserved */
14444 0, /* 47 reserved */
14445 0, /* 48 reserved */
14446 0, /* 49 reserved */
14447 0, /* 50 reserved */
14448 0, /* 51 reserved */
14449 0, /* 52 reserved */
14450 0, /* 53 reserved */
14451 0, /* 54 reserved */
14452 0, /* 55 reserved */
14453 0, /* 56 cisptr_lsw */
14454 0, /* 57 cisprt_msw */
14455 0, /* 58 subsysvid */
14456 0, /* 59 subsysid */
14457 0, /* 60 reserved */
14458 0, /* 61 reserved */
14459 0, /* 62 reserved */
14460 0 /* 63 reserved */
14464 * Initialize the ADV_DVC_VAR structure.
14466 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14468 * For a non-fatal error return a warning code. If there are no warnings
14469 * then 0 is returned.
14472 AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14475 AdvPortAddr iop_base;
14480 asc_dvc->err_code = 0;
14481 iop_base = asc_dvc->iop_base;
14484 * PCI Command Register
14486 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14487 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14490 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14491 AscPCIConfigCommandRegister))
14492 & AscPCICmdRegBits_BusMastering)
14493 != AscPCICmdRegBits_BusMastering)
14495 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14497 DvcAdvWritePCIConfigByte(asc_dvc,
14498 AscPCIConfigCommandRegister, pci_cmd_reg);
14500 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister))
14501 & AscPCICmdRegBits_BusMastering)
14502 != AscPCICmdRegBits_BusMastering)
14504 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14509 * PCI Latency Timer
14511 * If the "latency timer" register is 0x20 or above, then we don't need
14512 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14513 * comes up less than 0x20).
14515 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14516 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer, 0x20);
14517 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20)
14519 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14524 * Save the state of the PCI Configuration Command Register
14525 * "Parity Error Response Control" Bit. If the bit is clear (0),
14526 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14527 * DMA parity errors.
14529 asc_dvc->cfg->control_flag = 0;
14530 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14531 & AscPCICmdRegBits_ParErrRespCtrl)) == 0)
14533 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14536 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14537 ADV_LIB_VERSION_MINOR;
14538 asc_dvc->cfg->chip_version =
14539 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14541 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14542 (ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14543 (ushort) ADV_CHIP_ID_BYTE);
14545 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14546 (ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14547 (ushort) ADV_CHIP_ID_WORD);
14550 * Reset the chip to start and allow register writes.
14552 if (AdvFindSignature(iop_base) == 0)
14554 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14559 * The caller must set 'chip_type' to a valid setting.
14561 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14562 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14563 asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
14565 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14572 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14573 ADV_CTRL_REG_CMD_RESET);
14574 DvcSleepMilliSecond(100);
14575 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14576 ADV_CTRL_REG_CMD_WR_IO_REG);
14578 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
14580 if ((status = AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR)
14584 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
14586 if ((status = AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR)
14592 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR)
14597 warn_code |= status;
14604 * Initialize the ASC-3550.
14606 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14608 * For a non-fatal error return a warning code. If there are no warnings
14609 * then 0 is returned.
14611 * Needed after initialization for error recovery.
14614 AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14616 AdvPortAddr iop_base;
14624 int adv_asc3550_expanded_size;
14626 ADV_DCNT contig_len;
14627 ADV_SDCNT buf_size;
14628 ADV_PADDR carr_paddr;
14632 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
14633 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14634 uchar max_cmd[ADV_MAX_TID + 1];
14636 /* If there is already an error, don't continue. */
14637 if (asc_dvc->err_code != 0)
14643 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14645 if (asc_dvc->chip_type != ADV_CHIP_ASC3550)
14647 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14652 iop_base = asc_dvc->iop_base;
14655 * Save the RISC memory BIOS region before writing the microcode.
14656 * The BIOS may already be loaded and using its RISC LRAM region
14657 * so its region must be saved and restored.
14659 * Note: This code makes the assumption, which is currently true,
14660 * that a chip reset does not clear RISC LRAM.
14662 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14664 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14668 * Save current per TID negotiated values.
14670 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
14672 ushort bios_version, major, minor;
14674 bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
14675 major = (bios_version >> 12) & 0xF;
14676 minor = (bios_version >> 8) & 0xF;
14677 if (major < 3 || (major == 3 && minor == 1))
14679 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14680 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14683 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14686 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14687 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14688 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14690 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14695 * Load the Microcode
14697 * Write the microcode image to RISC memory starting at address 0.
14699 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14700 /* Assume the following compressed format of the microcode buffer:
14702 * 254 word (508 byte) table indexed by byte code followed
14703 * by the following byte codes:
14706 * 00: Emit word 0 in table.
14707 * 01: Emit word 1 in table.
14709 * FD: Emit word 253 in table.
14712 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14713 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14716 for (i = 253 * 2; i < _adv_asc3550_size; i++)
14718 if (_adv_asc3550_buf[i] == 0xff)
14720 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
14722 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14723 _adv_asc3550_buf[i + 3] << 8) |
14724 _adv_asc3550_buf[i + 2]));
14728 } else if (_adv_asc3550_buf[i] == 0xfe)
14730 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14731 _adv_asc3550_buf[i + 2] << 8) |
14732 _adv_asc3550_buf[i + 1]));
14737 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14738 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
14739 _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14745 * Set 'word' for later use to clear the rest of memory and save
14746 * the expanded mcode size.
14749 adv_asc3550_expanded_size = word;
14752 * Clear the rest of ASC-3550 Internal RAM (8KB).
14754 for (; word < ADV_3550_MEMSIZE; word += 2)
14756 AdvWriteWordAutoIncLram(iop_base, 0);
14760 * Verify the microcode checksum.
14763 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14765 for (word = 0; word < adv_asc3550_expanded_size; word += 2)
14767 sum += AdvReadWordAutoIncLram(iop_base);
14770 if (sum != _adv_asc3550_chksum)
14772 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14777 * Restore the RISC memory BIOS region.
14779 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14781 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14785 * Calculate and write the microcode code checksum to the microcode
14786 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14788 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14789 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14791 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14792 for (word = begin_addr; word < end_addr; word += 2)
14794 code_sum += AdvReadWordAutoIncLram(iop_base);
14796 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14799 * Read and save microcode version and date.
14801 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
14802 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
14805 * Set the chip type to indicate the ASC3550.
14807 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14810 * If the PCI Configuration Command Register "Parity Error Response
14811 * Control" Bit was clear (0), then set the microcode variable
14812 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14813 * to ignore DMA parity errors.
14815 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
14817 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14818 word |= CONTROL_FLAG_IGNORE_PERR;
14819 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14823 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14824 * threshold of 128 bytes. This register is only accessible to the host.
14826 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14827 START_CTL_EMFU | READ_CMD_MRM);
14830 * Microcode operating variables for WDTR, SDTR, and command tag
14831 * queuing will be set in AdvInquiryHandling() based on what a
14832 * device reports it is capable of in Inquiry byte 7.
14834 * If SCSI Bus Resets have been disabled, then directly set
14835 * SDTR and WDTR from the EEPROM configuration. This will allow
14836 * the BIOS and warm boot to work without a SCSI bus hang on
14837 * the Inquiry caused by host and target mismatched DTR values.
14838 * Without the SCSI Bus Reset, before an Inquiry a device can't
14839 * be assumed to be in Asynchronous, Narrow mode.
14841 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
14843 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
14844 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
14848 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14849 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14850 * bitmask. These values determine the maximum SDTR speed negotiated
14853 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14854 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14855 * without determining here whether the device supports SDTR.
14857 * 4-bit speed SDTR speed name
14858 * =========== ===============
14859 * 0000b (0x0) SDTR disabled
14860 * 0001b (0x1) 5 Mhz
14861 * 0010b (0x2) 10 Mhz
14862 * 0011b (0x3) 20 Mhz (Ultra)
14863 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14864 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14865 * 0110b (0x6) Undefined
14867 * 1111b (0xF) Undefined
14870 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14872 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able)
14874 /* Set Ultra speed for TID 'tid'. */
14875 word |= (0x3 << (4 * (tid % 4)));
14878 /* Set Fast speed for TID 'tid'. */
14879 word |= (0x2 << (4 * (tid % 4)));
14881 if (tid == 3) /* Check if done with sdtr_speed1. */
14883 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14885 } else if (tid == 7) /* Check if done with sdtr_speed2. */
14887 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14889 } else if (tid == 11) /* Check if done with sdtr_speed3. */
14891 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14893 } else if (tid == 15) /* Check if done with sdtr_speed4. */
14895 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14901 * Set microcode operating variable for the disconnect per TID bitmask.
14903 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
14906 * Set SCSI_CFG0 Microcode Default Value.
14908 * The microcode will set the SCSI_CFG0 register using this value
14909 * after it is started below.
14911 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14912 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14913 asc_dvc->chip_scsi_id);
14916 * Determine SCSI_CFG1 Microcode Default Value.
14918 * The microcode will set the SCSI_CFG1 register using this value
14919 * after it is started below.
14922 /* Read current SCSI_CFG1 Register value. */
14923 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14926 * If all three connectors are in use, return an error.
14928 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14929 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0)
14931 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14936 * If the internal narrow cable is reversed all of the SCSI_CTRL
14937 * register signals will be set. Check for and return an error if
14938 * this condition is found.
14940 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
14942 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14947 * If this is a differential board and a single-ended device
14948 * is attached to one of the connectors, return an error.
14950 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0)
14952 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14957 * If automatic termination control is enabled, then set the
14958 * termination value based on a table listed in a_condor.h.
14960 * If manual termination was specified with an EEPROM setting
14961 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
14962 * is ready to be 'ored' into SCSI_CFG1.
14964 if (asc_dvc->cfg->termination == 0)
14967 * The software always controls termination by setting TERM_CTL_SEL.
14968 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
14970 asc_dvc->cfg->termination |= TERM_CTL_SEL;
14972 switch(scsi_cfg1 & CABLE_DETECT)
14974 /* TERM_CTL_H: on, TERM_CTL_L: on */
14975 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF:
14976 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
14979 /* TERM_CTL_H: on, TERM_CTL_L: off */
14980 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC:
14981 asc_dvc->cfg->termination |= TERM_CTL_H;
14984 /* TERM_CTL_H: off, TERM_CTL_L: off */
14985 case 0x2: case 0x6:
14991 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
14993 scsi_cfg1 &= ~TERM_CTL;
14996 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
14997 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
14998 * referenced, because the hardware internally inverts
14999 * the Termination High and Low bits if TERM_POL is set.
15001 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
15004 * Set SCSI_CFG1 Microcode Default Value
15006 * Set filter value and possibly modified termination control
15007 * bits in the Microcode SCSI_CFG1 Register Value.
15009 * The microcode will set the SCSI_CFG1 register using this value
15010 * after it is started below.
15012 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
15013 FLTR_DISABLE | scsi_cfg1);
15016 * Set MEM_CFG Microcode Default Value
15018 * The microcode will set the MEM_CFG register using this value
15019 * after it is started below.
15021 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15024 * ASC-3550 has 8KB internal memory.
15026 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15027 BIOS_EN | RAM_SZ_8KB);
15030 * Set SEL_MASK Microcode Default Value
15032 * The microcode will set the SEL_MASK register using this value
15033 * after it is started below.
15035 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15036 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15039 * Build carrier freelist.
15041 * Driver must have already allocated memory and set 'carrier_buf'.
15043 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15045 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15046 asc_dvc->carr_freelist = NULL;
15047 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15049 buf_size = ADV_CARRIER_BUFSIZE;
15052 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15057 * Get physical address of the carrier 'carrp'.
15059 contig_len = sizeof(ADV_CARR_T);
15060 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15061 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15063 buf_size -= sizeof(ADV_CARR_T);
15066 * If the current carrier is not physically contiguous, then
15067 * maybe there was a page crossing. Try the next carrier aligned
15070 if (contig_len < sizeof(ADV_CARR_T))
15076 carrp->carr_pa = carr_paddr;
15077 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15080 * Insert the carrier at the beginning of the freelist.
15082 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15083 asc_dvc->carr_freelist = carrp;
15087 while (buf_size > 0);
15090 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15093 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15095 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15098 asc_dvc->carr_freelist = (ADV_CARR_T *)
15099 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15102 * The first command issued will be placed in the stopper carrier.
15104 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15107 * Set RISC ICQ physical address start value.
15109 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15112 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15114 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15116 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15119 asc_dvc->carr_freelist = (ADV_CARR_T *)
15120 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15123 * The first command completed by the RISC will be placed in
15126 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15127 * completed the RISC will set the ASC_RQ_STOPPER bit.
15129 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15132 * Set RISC IRQ physical address start value.
15134 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15135 asc_dvc->carr_pending_cnt = 0;
15137 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15138 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15140 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15141 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15143 /* finally, finally, gentlemen, start your engine */
15144 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15147 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15148 * Resets should be performed. The RISC has to be running
15149 * to issue a SCSI Bus Reset.
15151 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15154 * If the BIOS Signature is present in memory, restore the
15155 * BIOS Handshake Configuration Table and do not perform
15156 * a SCSI Bus Reset.
15158 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15161 * Restore per TID negotiated values.
15163 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15164 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15165 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15166 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15168 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15173 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15175 warn_code = ASC_WARN_BUSRESET_ERROR;
15184 * Initialize the ASC-38C0800.
15186 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
15188 * For a non-fatal error return a warning code. If there are no warnings
15189 * then 0 is returned.
15191 * Needed after initialization for error recovery.
15194 AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
15196 AdvPortAddr iop_base;
15204 int adv_asc38C0800_expanded_size;
15206 ADV_DCNT contig_len;
15207 ADV_SDCNT buf_size;
15208 ADV_PADDR carr_paddr;
15213 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15214 ushort wdtr_able, sdtr_able, tagqng_able;
15215 uchar max_cmd[ADV_MAX_TID + 1];
15217 /* If there is already an error, don't continue. */
15218 if (asc_dvc->err_code != 0)
15224 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
15226 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
15228 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15233 iop_base = asc_dvc->iop_base;
15236 * Save the RISC memory BIOS region before writing the microcode.
15237 * The BIOS may already be loaded and using its RISC LRAM region
15238 * so its region must be saved and restored.
15240 * Note: This code makes the assumption, which is currently true,
15241 * that a chip reset does not clear RISC LRAM.
15243 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15245 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15249 * Save current per TID negotiated values.
15251 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15252 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15253 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15254 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15256 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15261 * RAM BIST (RAM Built-In Self Test)
15263 * Address : I/O base + offset 0x38h register (byte).
15264 * Function: Bit 7-6(RW) : RAM mode
15265 * Normal Mode : 0x00
15266 * Pre-test Mode : 0x40
15267 * RAM Test Mode : 0x80
15269 * Bit 4(RO) : Done bit
15270 * Bit 3-0(RO) : Status
15271 * Host Error : 0x08
15272 * Int_RAM Error : 0x04
15273 * RISC Error : 0x02
15274 * SCSI Error : 0x01
15277 * Note: RAM BIST code should be put right here, before loading the
15278 * microcode and after saving the RISC memory BIOS region.
15284 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15285 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15286 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15287 * to NORMAL_MODE, return an error too.
15289 for (i = 0; i < 2; i++)
15291 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15292 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15293 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15294 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15296 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15300 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15301 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15302 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15305 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15311 * LRAM Test - It takes about 1.5 ms to run through the test.
15313 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15314 * If Done bit not set or Status not 0, save register byte, set the
15315 * err_code, and return an error.
15317 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15318 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15320 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15321 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15323 /* Get here if Done bit not set or Status not 0. */
15324 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15325 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15329 /* We need to reset back to normal mode after LRAM test passes. */
15330 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15333 * Load the Microcode
15335 * Write the microcode image to RISC memory starting at address 0.
15338 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15340 /* Assume the following compressed format of the microcode buffer:
15342 * 254 word (508 byte) table indexed by byte code followed
15343 * by the following byte codes:
15346 * 00: Emit word 0 in table.
15347 * 01: Emit word 1 in table.
15349 * FD: Emit word 253 in table.
15352 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15353 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15356 for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
15358 if (_adv_asc38C0800_buf[i] == 0xff)
15360 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
15362 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15363 _adv_asc38C0800_buf[i + 3] << 8) |
15364 _adv_asc38C0800_buf[i + 2]));
15368 } else if (_adv_asc38C0800_buf[i] == 0xfe)
15370 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15371 _adv_asc38C0800_buf[i + 2] << 8) |
15372 _adv_asc38C0800_buf[i + 1]));
15377 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15378 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
15379 _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15385 * Set 'word' for later use to clear the rest of memory and save
15386 * the expanded mcode size.
15389 adv_asc38C0800_expanded_size = word;
15392 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15394 for (; word < ADV_38C0800_MEMSIZE; word += 2)
15396 AdvWriteWordAutoIncLram(iop_base, 0);
15400 * Verify the microcode checksum.
15403 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15405 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
15407 sum += AdvReadWordAutoIncLram(iop_base);
15409 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15412 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15413 (ulong) sum, (ulong) _adv_asc38C0800_chksum);
15415 if (sum != _adv_asc38C0800_chksum)
15417 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15422 * Restore the RISC memory BIOS region.
15424 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15426 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15430 * Calculate and write the microcode code checksum to the microcode
15431 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15433 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15434 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15436 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15437 for (word = begin_addr; word < end_addr; word += 2)
15439 code_sum += AdvReadWordAutoIncLram(iop_base);
15441 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15444 * Read microcode version and date.
15446 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
15447 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
15450 * Set the chip type to indicate the ASC38C0800.
15452 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15455 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15456 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15457 * cable detection and then we are able to read C_DET[3:0].
15459 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15460 * Microcode Default Value' section below.
15462 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15463 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
15466 * If the PCI Configuration Command Register "Parity Error Response
15467 * Control" Bit was clear (0), then set the microcode variable
15468 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15469 * to ignore DMA parity errors.
15471 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
15473 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15474 word |= CONTROL_FLAG_IGNORE_PERR;
15475 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15479 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15480 * bits for the default FIFO threshold.
15482 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15484 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15486 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15487 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15490 * Microcode operating variables for WDTR, SDTR, and command tag
15491 * queuing will be set in AdvInquiryHandling() based on what a
15492 * device reports it is capable of in Inquiry byte 7.
15494 * If SCSI Bus Resets have been disabled, then directly set
15495 * SDTR and WDTR from the EEPROM configuration. This will allow
15496 * the BIOS and warm boot to work without a SCSI bus hang on
15497 * the Inquiry caused by host and target mismatched DTR values.
15498 * Without the SCSI Bus Reset, before an Inquiry a device can't
15499 * be assumed to be in Asynchronous, Narrow mode.
15501 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
15503 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
15504 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
15508 * Set microcode operating variables for DISC and SDTR_SPEED1,
15509 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15510 * configuration values.
15512 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15513 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15514 * without determining here whether the device supports SDTR.
15516 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
15517 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15518 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15519 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15520 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15523 * Set SCSI_CFG0 Microcode Default Value.
15525 * The microcode will set the SCSI_CFG0 register using this value
15526 * after it is started below.
15528 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15529 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15530 asc_dvc->chip_scsi_id);
15533 * Determine SCSI_CFG1 Microcode Default Value.
15535 * The microcode will set the SCSI_CFG1 register using this value
15536 * after it is started below.
15539 /* Read current SCSI_CFG1 Register value. */
15540 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15543 * If the internal narrow cable is reversed all of the SCSI_CTRL
15544 * register signals will be set. Check for and return an error if
15545 * this condition is found.
15547 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
15549 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15554 * All kind of combinations of devices attached to one of four connectors
15555 * are acceptable except HVD device attached. For example, LVD device can
15556 * be attached to SE connector while SE device attached to LVD connector.
15557 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15559 * If an HVD device is attached to one of LVD connectors, return an error.
15560 * However, there is no way to detect HVD device attached to SE connectors.
15562 if (scsi_cfg1 & HVD)
15564 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15569 * If either SE or LVD automatic termination control is enabled, then
15570 * set the termination value based on a table listed in a_condor.h.
15572 * If manual termination was specified with an EEPROM setting then
15573 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15574 * be 'ored' into SCSI_CFG1.
15576 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
15578 /* SE automatic termination control is enabled. */
15579 switch(scsi_cfg1 & C_DET_SE)
15581 /* TERM_SE_HI: on, TERM_SE_LO: on */
15582 case 0x1: case 0x2: case 0x3:
15583 asc_dvc->cfg->termination |= TERM_SE;
15586 /* TERM_SE_HI: on, TERM_SE_LO: off */
15588 asc_dvc->cfg->termination |= TERM_SE_HI;
15593 if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
15595 /* LVD automatic termination control is enabled. */
15596 switch(scsi_cfg1 & C_DET_LVD)
15598 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15599 case 0x4: case 0x8: case 0xC:
15600 asc_dvc->cfg->termination |= TERM_LVD;
15603 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15610 * Clear any set TERM_SE and TERM_LVD bits.
15612 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15615 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15617 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15620 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15621 * and set possibly modified termination control bits in the Microcode
15622 * SCSI_CFG1 Register Value.
15624 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15627 * Set SCSI_CFG1 Microcode Default Value
15629 * Set possibly modified termination control and reset DIS_TERM_DRV
15630 * bits in the Microcode SCSI_CFG1 Register Value.
15632 * The microcode will set the SCSI_CFG1 register using this value
15633 * after it is started below.
15635 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15638 * Set MEM_CFG Microcode Default Value
15640 * The microcode will set the MEM_CFG register using this value
15641 * after it is started below.
15643 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15646 * ASC-38C0800 has 16KB internal memory.
15648 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15649 BIOS_EN | RAM_SZ_16KB);
15652 * Set SEL_MASK Microcode Default Value
15654 * The microcode will set the SEL_MASK register using this value
15655 * after it is started below.
15657 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15658 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15661 * Build the carrier freelist.
15663 * Driver must have already allocated memory and set 'carrier_buf'.
15665 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15667 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15668 asc_dvc->carr_freelist = NULL;
15669 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15671 buf_size = ADV_CARRIER_BUFSIZE;
15674 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15679 * Get physical address for the carrier 'carrp'.
15681 contig_len = sizeof(ADV_CARR_T);
15682 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15683 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15685 buf_size -= sizeof(ADV_CARR_T);
15688 * If the current carrier is not physically contiguous, then
15689 * maybe there was a page crossing. Try the next carrier aligned
15692 if (contig_len < sizeof(ADV_CARR_T))
15698 carrp->carr_pa = carr_paddr;
15699 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15702 * Insert the carrier at the beginning of the freelist.
15704 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15705 asc_dvc->carr_freelist = carrp;
15709 while (buf_size > 0);
15712 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15715 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15717 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15720 asc_dvc->carr_freelist = (ADV_CARR_T *)
15721 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15724 * The first command issued will be placed in the stopper carrier.
15726 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15729 * Set RISC ICQ physical address start value.
15730 * carr_pa is LE, must be native before write
15732 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15735 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15737 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15739 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15742 asc_dvc->carr_freelist = (ADV_CARR_T *)
15743 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15746 * The first command completed by the RISC will be placed in
15749 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15750 * completed the RISC will set the ASC_RQ_STOPPER bit.
15752 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15755 * Set RISC IRQ physical address start value.
15757 * carr_pa is LE, must be native before write *
15759 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15760 asc_dvc->carr_pending_cnt = 0;
15762 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15763 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15765 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15766 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15768 /* finally, finally, gentlemen, start your engine */
15769 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15772 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15773 * Resets should be performed. The RISC has to be running
15774 * to issue a SCSI Bus Reset.
15776 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15779 * If the BIOS Signature is present in memory, restore the
15780 * BIOS Handshake Configuration Table and do not perform
15781 * a SCSI Bus Reset.
15783 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15786 * Restore per TID negotiated values.
15788 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15789 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15790 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15791 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15793 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15798 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15800 warn_code = ASC_WARN_BUSRESET_ERROR;
15809 * Initialize the ASC-38C1600.
15811 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15813 * For a non-fatal error return a warning code. If there are no warnings
15814 * then 0 is returned.
15816 * Needed after initialization for error recovery.
15819 AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15821 AdvPortAddr iop_base;
15829 int adv_asc38C1600_expanded_size;
15831 ADV_DCNT contig_len;
15832 ADV_SDCNT buf_size;
15833 ADV_PADDR carr_paddr;
15838 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15839 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15840 uchar max_cmd[ASC_MAX_TID + 1];
15842 /* If there is already an error, don't continue. */
15843 if (asc_dvc->err_code != 0)
15849 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15851 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
15853 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15858 iop_base = asc_dvc->iop_base;
15861 * Save the RISC memory BIOS region before writing the microcode.
15862 * The BIOS may already be loaded and using its RISC LRAM region
15863 * so its region must be saved and restored.
15865 * Note: This code makes the assumption, which is currently true,
15866 * that a chip reset does not clear RISC LRAM.
15868 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15870 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15874 * Save current per TID negotiated values.
15876 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15877 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15878 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15879 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15880 for (tid = 0; tid <= ASC_MAX_TID; tid++)
15882 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15887 * RAM BIST (Built-In Self Test)
15889 * Address : I/O base + offset 0x38h register (byte).
15890 * Function: Bit 7-6(RW) : RAM mode
15891 * Normal Mode : 0x00
15892 * Pre-test Mode : 0x40
15893 * RAM Test Mode : 0x80
15895 * Bit 4(RO) : Done bit
15896 * Bit 3-0(RO) : Status
15897 * Host Error : 0x08
15898 * Int_RAM Error : 0x04
15899 * RISC Error : 0x02
15900 * SCSI Error : 0x01
15903 * Note: RAM BIST code should be put right here, before loading the
15904 * microcode and after saving the RISC memory BIOS region.
15910 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15911 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15912 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15913 * to NORMAL_MODE, return an error too.
15915 for (i = 0; i < 2; i++)
15917 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15918 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15919 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15920 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15922 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15926 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15927 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15928 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15931 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15937 * LRAM Test - It takes about 1.5 ms to run through the test.
15939 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15940 * If Done bit not set or Status not 0, save register byte, set the
15941 * err_code, and return an error.
15943 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15944 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15946 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15947 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15949 /* Get here if Done bit not set or Status not 0. */
15950 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15951 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15955 /* We need to reset back to normal mode after LRAM test passes. */
15956 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15959 * Load the Microcode
15961 * Write the microcode image to RISC memory starting at address 0.
15964 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15967 * Assume the following compressed format of the microcode buffer:
15969 * 254 word (508 byte) table indexed by byte code followed
15970 * by the following byte codes:
15973 * 00: Emit word 0 in table.
15974 * 01: Emit word 1 in table.
15976 * FD: Emit word 253 in table.
15979 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15980 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15983 for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
15985 if (_adv_asc38C1600_buf[i] == 0xff)
15987 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
15989 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15990 _adv_asc38C1600_buf[i + 3] << 8) |
15991 _adv_asc38C1600_buf[i + 2]));
15995 } else if (_adv_asc38C1600_buf[i] == 0xfe)
15997 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15998 _adv_asc38C1600_buf[i + 2] << 8) |
15999 _adv_asc38C1600_buf[i + 1]));
16004 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16005 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
16006 _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
16012 * Set 'word' for later use to clear the rest of memory and save
16013 * the expanded mcode size.
16016 adv_asc38C1600_expanded_size = word;
16019 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
16021 for (; word < ADV_38C1600_MEMSIZE; word += 2)
16023 AdvWriteWordAutoIncLram(iop_base, 0);
16027 * Verify the microcode checksum.
16030 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16032 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
16034 sum += AdvReadWordAutoIncLram(iop_base);
16037 if (sum != _adv_asc38C1600_chksum)
16039 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
16044 * Restore the RISC memory BIOS region.
16046 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
16048 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
16052 * Calculate and write the microcode code checksum to the microcode
16053 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
16055 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
16056 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
16058 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
16059 for (word = begin_addr; word < end_addr; word += 2)
16061 code_sum += AdvReadWordAutoIncLram(iop_base);
16063 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
16066 * Read microcode version and date.
16068 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
16069 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
16072 * Set the chip type to indicate the ASC38C1600.
16074 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
16077 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
16078 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
16079 * cable detection and then we are able to read C_DET[3:0].
16081 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
16082 * Microcode Default Value' section below.
16084 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16085 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
16088 * If the PCI Configuration Command Register "Parity Error Response
16089 * Control" Bit was clear (0), then set the microcode variable
16090 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
16091 * to ignore DMA parity errors.
16093 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
16095 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16096 word |= CONTROL_FLAG_IGNORE_PERR;
16097 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16101 * If the BIOS control flag AIPP (Asynchronous Information
16102 * Phase Protection) disable bit is not set, then set the firmware
16103 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
16104 * AIPP checking and encoding.
16106 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
16108 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16109 word |= CONTROL_FLAG_ENABLE_AIPP;
16110 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16114 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
16115 * and START_CTL_TH [3:2].
16117 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
16118 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
16121 * Microcode operating variables for WDTR, SDTR, and command tag
16122 * queuing will be set in AdvInquiryHandling() based on what a
16123 * device reports it is capable of in Inquiry byte 7.
16125 * If SCSI Bus Resets have been disabled, then directly set
16126 * SDTR and WDTR from the EEPROM configuration. This will allow
16127 * the BIOS and warm boot to work without a SCSI bus hang on
16128 * the Inquiry caused by host and target mismatched DTR values.
16129 * Without the SCSI Bus Reset, before an Inquiry a device can't
16130 * be assumed to be in Asynchronous, Narrow mode.
16132 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
16134 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
16135 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
16139 * Set microcode operating variables for DISC and SDTR_SPEED1,
16140 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
16141 * configuration values.
16143 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
16144 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
16145 * without determining here whether the device supports SDTR.
16147 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
16148 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
16149 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
16150 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
16151 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
16154 * Set SCSI_CFG0 Microcode Default Value.
16156 * The microcode will set the SCSI_CFG0 register using this value
16157 * after it is started below.
16159 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
16160 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
16161 asc_dvc->chip_scsi_id);
16164 * Calculate SCSI_CFG1 Microcode Default Value.
16166 * The microcode will set the SCSI_CFG1 register using this value
16167 * after it is started below.
16169 * Each ASC-38C1600 function has only two cable detect bits.
16170 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
16172 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16175 * If the cable is reversed all of the SCSI_CTRL register signals
16176 * will be set. Check for and return an error if this condition is
16179 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
16181 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
16186 * Each ASC-38C1600 function has two connectors. Only an HVD device
16187 * can not be connected to either connector. An LVD device or SE device
16188 * may be connected to either connecor. If an SE device is connected,
16189 * then at most Ultra speed (20 Mhz) can be used on both connectors.
16191 * If an HVD device is attached, return an error.
16193 if (scsi_cfg1 & HVD)
16195 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
16200 * Each function in the ASC-38C1600 uses only the SE cable detect and
16201 * termination because there are two connectors for each function. Each
16202 * function may use either LVD or SE mode. Corresponding the SE automatic
16203 * termination control EEPROM bits are used for each function. Each
16204 * function has its own EEPROM. If SE automatic control is enabled for
16205 * the function, then set the termination value based on a table listed
16208 * If manual termination is specified in the EEPROM for the function,
16209 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
16210 * ready to be 'ored' into SCSI_CFG1.
16212 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
16214 /* SE automatic termination control is enabled. */
16215 switch(scsi_cfg1 & C_DET_SE)
16217 /* TERM_SE_HI: on, TERM_SE_LO: on */
16218 case 0x1: case 0x2: case 0x3:
16219 asc_dvc->cfg->termination |= TERM_SE;
16223 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
16225 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
16229 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
16230 asc_dvc->cfg->termination |= TERM_SE_HI;
16237 * Clear any set TERM_SE bits.
16239 scsi_cfg1 &= ~TERM_SE;
16242 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
16244 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
16247 * Clear Big Endian and Terminator Polarity bits and set possibly
16248 * modified termination control bits in the Microcode SCSI_CFG1
16251 * Big Endian bit is not used even on big endian machines.
16253 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
16256 * Set SCSI_CFG1 Microcode Default Value
16258 * Set possibly modified termination control bits in the Microcode
16259 * SCSI_CFG1 Register Value.
16261 * The microcode will set the SCSI_CFG1 register using this value
16262 * after it is started below.
16264 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
16267 * Set MEM_CFG Microcode Default Value
16269 * The microcode will set the MEM_CFG register using this value
16270 * after it is started below.
16272 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
16275 * ASC-38C1600 has 32KB internal memory.
16277 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
16278 * out a special 16K Adv Library and Microcode version. After the issue
16279 * resolved, we should turn back to the 32K support. Both a_condor.h and
16280 * mcode.sas files also need to be updated.
16282 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
16283 * BIOS_EN | RAM_SZ_32KB);
16285 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
16288 * Set SEL_MASK Microcode Default Value
16290 * The microcode will set the SEL_MASK register using this value
16291 * after it is started below.
16293 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
16294 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
16297 * Build the carrier freelist.
16299 * Driver must have already allocated memory and set 'carrier_buf'.
16302 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
16304 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
16305 asc_dvc->carr_freelist = NULL;
16306 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
16308 buf_size = ADV_CARRIER_BUFSIZE;
16311 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
16316 * Get physical address for the carrier 'carrp'.
16318 contig_len = sizeof(ADV_CARR_T);
16319 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
16320 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
16322 buf_size -= sizeof(ADV_CARR_T);
16325 * If the current carrier is not physically contiguous, then
16326 * maybe there was a page crossing. Try the next carrier aligned
16329 if (contig_len < sizeof(ADV_CARR_T))
16335 carrp->carr_pa = carr_paddr;
16336 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16339 * Insert the carrier at the beginning of the freelist.
16341 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16342 asc_dvc->carr_freelist = carrp;
16346 while (buf_size > 0);
16349 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16351 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
16353 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16356 asc_dvc->carr_freelist = (ADV_CARR_T *)
16357 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16360 * The first command issued will be placed in the stopper carrier.
16362 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16365 * Set RISC ICQ physical address start value. Initialize the
16366 * COMMA register to the same value otherwise the RISC will
16367 * prematurely detect a command is available.
16369 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16370 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16371 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16374 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16376 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
16378 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16381 asc_dvc->carr_freelist = (ADV_CARR_T *)
16382 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16385 * The first command completed by the RISC will be placed in
16388 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16389 * completed the RISC will set the ASC_RQ_STOPPER bit.
16391 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16394 * Set RISC IRQ physical address start value.
16396 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16397 asc_dvc->carr_pending_cnt = 0;
16399 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16400 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
16401 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16402 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16404 /* finally, finally, gentlemen, start your engine */
16405 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16408 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16409 * Resets should be performed. The RISC has to be running
16410 * to issue a SCSI Bus Reset.
16412 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
16415 * If the BIOS Signature is present in memory, restore the
16416 * per TID microcode operating variables.
16418 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
16421 * Restore per TID negotiated values.
16423 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16424 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16425 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16426 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
16427 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16429 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
16434 if (AdvResetSB(asc_dvc) != ADV_TRUE)
16436 warn_code = ASC_WARN_BUSRESET_ERROR;
16445 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16446 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16447 * all of this is done.
16449 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16451 * For a non-fatal error return a warning code. If there are no warnings
16452 * then 0 is returned.
16454 * Note: Chip is stopped on entry.
16457 AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16459 AdvPortAddr iop_base;
16461 ADVEEP_3550_CONFIG eep_config;
16464 iop_base = asc_dvc->iop_base;
16469 * Read the board's EEPROM configuration.
16471 * Set default values if a bad checksum is found.
16473 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16475 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16478 * Set EEPROM default values.
16480 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
16482 *((uchar *) &eep_config + i) =
16483 *((uchar *) &Default_3550_EEPROM_Config + i);
16487 * Assume the 6 byte board serial number that was read
16488 * from EEPROM is correct even if the EEPROM checksum
16491 eep_config.serial_number_word3 =
16492 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16494 eep_config.serial_number_word2 =
16495 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16497 eep_config.serial_number_word1 =
16498 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16500 AdvSet3550EEPConfig(iop_base, &eep_config);
16503 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16504 * EEPROM configuration that was read.
16506 * This is the mapping of EEPROM fields to Adv Library fields.
16508 asc_dvc->wdtr_able = eep_config.wdtr_able;
16509 asc_dvc->sdtr_able = eep_config.sdtr_able;
16510 asc_dvc->ultra_able = eep_config.ultra_able;
16511 asc_dvc->tagqng_able = eep_config.tagqng_able;
16512 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16513 asc_dvc->max_host_qng = eep_config.max_host_qng;
16514 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16515 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16516 asc_dvc->start_motor = eep_config.start_motor;
16517 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16518 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16519 asc_dvc->no_scam = eep_config.scam_tolerant;
16520 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16521 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16522 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16525 * Set the host maximum queuing (max. 253, min. 16) and the per device
16526 * maximum queuing (max. 63, min. 4).
16528 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16530 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16531 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16533 /* If the value is zero, assume it is uninitialized. */
16534 if (eep_config.max_host_qng == 0)
16536 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16539 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16543 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16545 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16546 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16548 /* If the value is zero, assume it is uninitialized. */
16549 if (eep_config.max_dvc_qng == 0)
16551 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16554 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16559 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16560 * set 'max_dvc_qng' to 'max_host_qng'.
16562 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16564 eep_config.max_dvc_qng = eep_config.max_host_qng;
16568 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16569 * values based on possibly adjusted EEPROM values.
16571 asc_dvc->max_host_qng = eep_config.max_host_qng;
16572 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16576 * If the EEPROM 'termination' field is set to automatic (0), then set
16577 * the ADV_DVC_CFG 'termination' field to automatic also.
16579 * If the termination is specified with a non-zero 'termination'
16580 * value check that a legal value is set and set the ADV_DVC_CFG
16581 * 'termination' field appropriately.
16583 if (eep_config.termination == 0)
16585 asc_dvc->cfg->termination = 0; /* auto termination */
16588 /* Enable manual control with low off / high off. */
16589 if (eep_config.termination == 1)
16591 asc_dvc->cfg->termination = TERM_CTL_SEL;
16593 /* Enable manual control with low off / high on. */
16594 } else if (eep_config.termination == 2)
16596 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16598 /* Enable manual control with low on / high on. */
16599 } else if (eep_config.termination == 3)
16601 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16605 * The EEPROM 'termination' field contains a bad value. Use
16606 * automatic termination instead.
16608 asc_dvc->cfg->termination = 0;
16609 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16617 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16618 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16619 * all of this is done.
16621 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16623 * For a non-fatal error return a warning code. If there are no warnings
16624 * then 0 is returned.
16626 * Note: Chip is stopped on entry.
16629 AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16631 AdvPortAddr iop_base;
16633 ADVEEP_38C0800_CONFIG eep_config;
16635 uchar tid, termination;
16636 ushort sdtr_speed = 0;
16638 iop_base = asc_dvc->iop_base;
16643 * Read the board's EEPROM configuration.
16645 * Set default values if a bad checksum is found.
16647 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16649 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16652 * Set EEPROM default values.
16654 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
16656 *((uchar *) &eep_config + i) =
16657 *((uchar *) &Default_38C0800_EEPROM_Config + i);
16661 * Assume the 6 byte board serial number that was read
16662 * from EEPROM is correct even if the EEPROM checksum
16665 eep_config.serial_number_word3 =
16666 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16668 eep_config.serial_number_word2 =
16669 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16671 eep_config.serial_number_word1 =
16672 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16674 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16677 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16678 * EEPROM configuration that was read.
16680 * This is the mapping of EEPROM fields to Adv Library fields.
16682 asc_dvc->wdtr_able = eep_config.wdtr_able;
16683 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16684 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16685 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16686 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16687 asc_dvc->tagqng_able = eep_config.tagqng_able;
16688 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16689 asc_dvc->max_host_qng = eep_config.max_host_qng;
16690 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16691 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16692 asc_dvc->start_motor = eep_config.start_motor;
16693 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16694 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16695 asc_dvc->no_scam = eep_config.scam_tolerant;
16696 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16697 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16698 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16701 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16702 * are set, then set an 'sdtr_able' bit for it.
16704 asc_dvc->sdtr_able = 0;
16705 for (tid = 0; tid <= ADV_MAX_TID; tid++)
16709 sdtr_speed = asc_dvc->sdtr_speed1;
16710 } else if (tid == 4)
16712 sdtr_speed = asc_dvc->sdtr_speed2;
16713 } else if (tid == 8)
16715 sdtr_speed = asc_dvc->sdtr_speed3;
16716 } else if (tid == 12)
16718 sdtr_speed = asc_dvc->sdtr_speed4;
16720 if (sdtr_speed & ADV_MAX_TID)
16722 asc_dvc->sdtr_able |= (1 << tid);
16728 * Set the host maximum queuing (max. 253, min. 16) and the per device
16729 * maximum queuing (max. 63, min. 4).
16731 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16733 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16734 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16736 /* If the value is zero, assume it is uninitialized. */
16737 if (eep_config.max_host_qng == 0)
16739 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16742 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16746 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16748 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16749 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16751 /* If the value is zero, assume it is uninitialized. */
16752 if (eep_config.max_dvc_qng == 0)
16754 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16757 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16762 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16763 * set 'max_dvc_qng' to 'max_host_qng'.
16765 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16767 eep_config.max_dvc_qng = eep_config.max_host_qng;
16771 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16772 * values based on possibly adjusted EEPROM values.
16774 asc_dvc->max_host_qng = eep_config.max_host_qng;
16775 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16778 * If the EEPROM 'termination' field is set to automatic (0), then set
16779 * the ADV_DVC_CFG 'termination' field to automatic also.
16781 * If the termination is specified with a non-zero 'termination'
16782 * value check that a legal value is set and set the ADV_DVC_CFG
16783 * 'termination' field appropriately.
16785 if (eep_config.termination_se == 0)
16787 termination = 0; /* auto termination for SE */
16790 /* Enable manual control with low off / high off. */
16791 if (eep_config.termination_se == 1)
16795 /* Enable manual control with low off / high on. */
16796 } else if (eep_config.termination_se == 2)
16798 termination = TERM_SE_HI;
16800 /* Enable manual control with low on / high on. */
16801 } else if (eep_config.termination_se == 3)
16803 termination = TERM_SE;
16807 * The EEPROM 'termination_se' field contains a bad value.
16808 * Use automatic termination instead.
16811 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16815 if (eep_config.termination_lvd == 0)
16817 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16820 /* Enable manual control with low off / high off. */
16821 if (eep_config.termination_lvd == 1)
16823 asc_dvc->cfg->termination = termination;
16825 /* Enable manual control with low off / high on. */
16826 } else if (eep_config.termination_lvd == 2)
16828 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16830 /* Enable manual control with low on / high on. */
16831 } else if (eep_config.termination_lvd == 3)
16833 asc_dvc->cfg->termination =
16834 termination | TERM_LVD;
16838 * The EEPROM 'termination_lvd' field contains a bad value.
16839 * Use automatic termination instead.
16841 asc_dvc->cfg->termination = termination;
16842 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16850 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16851 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16852 * all of this is done.
16854 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16856 * For a non-fatal error return a warning code. If there are no warnings
16857 * then 0 is returned.
16859 * Note: Chip is stopped on entry.
16862 AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16864 AdvPortAddr iop_base;
16866 ADVEEP_38C1600_CONFIG eep_config;
16868 uchar tid, termination;
16869 ushort sdtr_speed = 0;
16871 iop_base = asc_dvc->iop_base;
16876 * Read the board's EEPROM configuration.
16878 * Set default values if a bad checksum is found.
16880 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16882 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16885 * Set EEPROM default values.
16887 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
16889 if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
16892 * Set Function 1 EEPROM Word 0 MSB
16894 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16897 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16898 * old Mac system booting problem. The Expansion ROM must
16899 * be disabled in Function 1 for these systems.
16902 *((uchar *) &eep_config + i) =
16903 ((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
16904 (~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
16908 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16909 * the Function 1 interrupt line is wired to INTA.
16911 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16912 * 1 - Function 1 interrupt line wired to INT A.
16913 * 0 - Function 1 interrupt line wired to INT B.
16915 * Note: Adapter boards always have Function 0 wired to INTA.
16916 * Put all 5 GPIO bits in input mode and then read
16917 * their input values.
16919 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
16920 if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
16922 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16923 *((uchar *) &eep_config + i) |=
16924 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16929 *((uchar *) &eep_config + i) =
16930 *((uchar *) &Default_38C1600_EEPROM_Config + i);
16935 * Assume the 6 byte board serial number that was read
16936 * from EEPROM is correct even if the EEPROM checksum
16939 eep_config.serial_number_word3 =
16940 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16942 eep_config.serial_number_word2 =
16943 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16945 eep_config.serial_number_word1 =
16946 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16948 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16952 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16953 * EEPROM configuration that was read.
16955 * This is the mapping of EEPROM fields to Adv Library fields.
16957 asc_dvc->wdtr_able = eep_config.wdtr_able;
16958 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16959 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16960 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16961 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16962 asc_dvc->ppr_able = 0;
16963 asc_dvc->tagqng_able = eep_config.tagqng_able;
16964 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16965 asc_dvc->max_host_qng = eep_config.max_host_qng;
16966 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16967 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
16968 asc_dvc->start_motor = eep_config.start_motor;
16969 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16970 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16971 asc_dvc->no_scam = eep_config.scam_tolerant;
16974 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16975 * are set, then set an 'sdtr_able' bit for it.
16977 asc_dvc->sdtr_able = 0;
16978 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16982 sdtr_speed = asc_dvc->sdtr_speed1;
16983 } else if (tid == 4)
16985 sdtr_speed = asc_dvc->sdtr_speed2;
16986 } else if (tid == 8)
16988 sdtr_speed = asc_dvc->sdtr_speed3;
16989 } else if (tid == 12)
16991 sdtr_speed = asc_dvc->sdtr_speed4;
16993 if (sdtr_speed & ASC_MAX_TID)
16995 asc_dvc->sdtr_able |= (1 << tid);
17001 * Set the host maximum queuing (max. 253, min. 16) and the per device
17002 * maximum queuing (max. 63, min. 4).
17004 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
17006 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17007 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
17009 /* If the value is zero, assume it is uninitialized. */
17010 if (eep_config.max_host_qng == 0)
17012 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17015 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
17019 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
17021 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17022 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
17024 /* If the value is zero, assume it is uninitialized. */
17025 if (eep_config.max_dvc_qng == 0)
17027 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17030 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
17035 * If 'max_dvc_qng' is greater than 'max_host_qng', then
17036 * set 'max_dvc_qng' to 'max_host_qng'.
17038 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
17040 eep_config.max_dvc_qng = eep_config.max_host_qng;
17044 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
17045 * values based on possibly adjusted EEPROM values.
17047 asc_dvc->max_host_qng = eep_config.max_host_qng;
17048 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17051 * If the EEPROM 'termination' field is set to automatic (0), then set
17052 * the ASC_DVC_CFG 'termination' field to automatic also.
17054 * If the termination is specified with a non-zero 'termination'
17055 * value check that a legal value is set and set the ASC_DVC_CFG
17056 * 'termination' field appropriately.
17058 if (eep_config.termination_se == 0)
17060 termination = 0; /* auto termination for SE */
17063 /* Enable manual control with low off / high off. */
17064 if (eep_config.termination_se == 1)
17068 /* Enable manual control with low off / high on. */
17069 } else if (eep_config.termination_se == 2)
17071 termination = TERM_SE_HI;
17073 /* Enable manual control with low on / high on. */
17074 } else if (eep_config.termination_se == 3)
17076 termination = TERM_SE;
17080 * The EEPROM 'termination_se' field contains a bad value.
17081 * Use automatic termination instead.
17084 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17088 if (eep_config.termination_lvd == 0)
17090 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
17093 /* Enable manual control with low off / high off. */
17094 if (eep_config.termination_lvd == 1)
17096 asc_dvc->cfg->termination = termination;
17098 /* Enable manual control with low off / high on. */
17099 } else if (eep_config.termination_lvd == 2)
17101 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
17103 /* Enable manual control with low on / high on. */
17104 } else if (eep_config.termination_lvd == 3)
17106 asc_dvc->cfg->termination =
17107 termination | TERM_LVD;
17111 * The EEPROM 'termination_lvd' field contains a bad value.
17112 * Use automatic termination instead.
17114 asc_dvc->cfg->termination = termination;
17115 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17123 * Read EEPROM configuration into the specified buffer.
17125 * Return a checksum based on the EEPROM configuration read.
17127 STATIC ushort __init
17128 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17130 ushort wval, chksum;
17133 ushort *charfields;
17135 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17136 wbuf = (ushort *) cfg_buf;
17139 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17140 eep_addr < ADV_EEP_DVC_CFG_END;
17141 eep_addr++, wbuf++)
17143 wval = AdvReadEEPWord(iop_base, eep_addr);
17144 chksum += wval; /* Checksum is calculated from word values. */
17145 if (*charfields++) {
17146 *wbuf = le16_to_cpu(wval);
17151 /* Read checksum word. */
17152 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17153 wbuf++; charfields++;
17155 /* Read rest of EEPROM not covered by the checksum. */
17156 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17157 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17158 eep_addr++, wbuf++)
17160 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17161 if (*charfields++) {
17162 *wbuf = le16_to_cpu(*wbuf);
17169 * Read EEPROM configuration into the specified buffer.
17171 * Return a checksum based on the EEPROM configuration read.
17173 STATIC ushort __init
17174 AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
17175 ADVEEP_38C0800_CONFIG *cfg_buf)
17177 ushort wval, chksum;
17180 ushort *charfields;
17182 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17183 wbuf = (ushort *) cfg_buf;
17186 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17187 eep_addr < ADV_EEP_DVC_CFG_END;
17188 eep_addr++, wbuf++)
17190 wval = AdvReadEEPWord(iop_base, eep_addr);
17191 chksum += wval; /* Checksum is calculated from word values. */
17192 if (*charfields++) {
17193 *wbuf = le16_to_cpu(wval);
17198 /* Read checksum word. */
17199 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17200 wbuf++; charfields++;
17202 /* Read rest of EEPROM not covered by the checksum. */
17203 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17204 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17205 eep_addr++, wbuf++)
17207 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17208 if (*charfields++) {
17209 *wbuf = le16_to_cpu(*wbuf);
17216 * Read EEPROM configuration into the specified buffer.
17218 * Return a checksum based on the EEPROM configuration read.
17220 STATIC ushort __init
17221 AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
17222 ADVEEP_38C1600_CONFIG *cfg_buf)
17224 ushort wval, chksum;
17227 ushort *charfields;
17229 charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
17230 wbuf = (ushort *) cfg_buf;
17233 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17234 eep_addr < ADV_EEP_DVC_CFG_END;
17235 eep_addr++, wbuf++)
17237 wval = AdvReadEEPWord(iop_base, eep_addr);
17238 chksum += wval; /* Checksum is calculated from word values. */
17239 if (*charfields++) {
17240 *wbuf = le16_to_cpu(wval);
17245 /* Read checksum word. */
17246 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17247 wbuf++; charfields++;
17249 /* Read rest of EEPROM not covered by the checksum. */
17250 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17251 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17252 eep_addr++, wbuf++)
17254 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17255 if (*charfields++) {
17256 *wbuf = le16_to_cpu(*wbuf);
17263 * Read the EEPROM from specified location
17265 STATIC ushort __init
17266 AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
17268 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17269 ASC_EEP_CMD_READ | eep_word_addr);
17270 AdvWaitEEPCmd(iop_base);
17271 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
17275 * Wait for EEPROM command to complete
17278 AdvWaitEEPCmd(AdvPortAddr iop_base)
17282 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
17284 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
17288 DvcSleepMilliSecond(1);
17290 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
17298 * Write the EEPROM from 'cfg_buf'.
17301 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17304 ushort addr, chksum;
17305 ushort *charfields;
17307 wbuf = (ushort *) cfg_buf;
17308 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17311 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17312 AdvWaitEEPCmd(iop_base);
17315 * Write EEPROM from word 0 to word 20.
17317 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17318 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17322 if (*charfields++) {
17323 word = cpu_to_le16(*wbuf);
17327 chksum += *wbuf; /* Checksum is calculated from word values. */
17328 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17329 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17330 AdvWaitEEPCmd(iop_base);
17331 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17335 * Write EEPROM checksum at word 21.
17337 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17338 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17339 AdvWaitEEPCmd(iop_base);
17340 wbuf++; charfields++;
17343 * Write EEPROM OEM name at words 22 to 29.
17345 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17346 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17350 if (*charfields++) {
17351 word = cpu_to_le16(*wbuf);
17355 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17356 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17357 AdvWaitEEPCmd(iop_base);
17359 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17360 AdvWaitEEPCmd(iop_base);
17365 * Write the EEPROM from 'cfg_buf'.
17368 AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
17369 ADVEEP_38C0800_CONFIG *cfg_buf)
17372 ushort *charfields;
17373 ushort addr, chksum;
17375 wbuf = (ushort *) cfg_buf;
17376 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17379 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17380 AdvWaitEEPCmd(iop_base);
17383 * Write EEPROM from word 0 to word 20.
17385 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17386 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17390 if (*charfields++) {
17391 word = cpu_to_le16(*wbuf);
17395 chksum += *wbuf; /* Checksum is calculated from word values. */
17396 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17397 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17398 AdvWaitEEPCmd(iop_base);
17399 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17403 * Write EEPROM checksum at word 21.
17405 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17406 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17407 AdvWaitEEPCmd(iop_base);
17408 wbuf++; charfields++;
17411 * Write EEPROM OEM name at words 22 to 29.
17413 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17414 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17418 if (*charfields++) {
17419 word = cpu_to_le16(*wbuf);
17423 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17424 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17425 AdvWaitEEPCmd(iop_base);
17427 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17428 AdvWaitEEPCmd(iop_base);
17433 * Write the EEPROM from 'cfg_buf'.
17436 AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
17437 ADVEEP_38C1600_CONFIG *cfg_buf)
17440 ushort *charfields;
17441 ushort addr, chksum;
17443 wbuf = (ushort *) cfg_buf;
17444 charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
17447 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17448 AdvWaitEEPCmd(iop_base);
17451 * Write EEPROM from word 0 to word 20.
17453 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17454 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17458 if (*charfields++) {
17459 word = cpu_to_le16(*wbuf);
17463 chksum += *wbuf; /* Checksum is calculated from word values. */
17464 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17465 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17466 AdvWaitEEPCmd(iop_base);
17467 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17471 * Write EEPROM checksum at word 21.
17473 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17474 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17475 AdvWaitEEPCmd(iop_base);
17476 wbuf++; charfields++;
17479 * Write EEPROM OEM name at words 22 to 29.
17481 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17482 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17486 if (*charfields++) {
17487 word = cpu_to_le16(*wbuf);
17491 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17492 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17493 AdvWaitEEPCmd(iop_base);
17495 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17496 AdvWaitEEPCmd(iop_base);
17502 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17504 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17505 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17506 * RISC to notify it a new command is ready to be executed.
17508 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17509 * set to SCSI_MAX_RETRY.
17511 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17512 * for DMA addresses or math operations are byte swapped to little-endian
17516 * ADV_SUCCESS(1) - The request was successfully queued.
17517 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17518 * request completes.
17519 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17523 AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
17524 ADV_SCSI_REQ_Q *scsiq)
17526 ulong last_int_level;
17527 AdvPortAddr iop_base;
17529 ADV_PADDR req_paddr;
17530 ADV_CARR_T *new_carrp;
17532 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17535 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17537 if (scsiq->target_id > ADV_MAX_TID)
17539 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17540 scsiq->done_status = QD_WITH_ERROR;
17544 iop_base = asc_dvc->iop_base;
17546 last_int_level = DvcEnterCritical();
17549 * Allocate a carrier ensuring at least one carrier always
17550 * remains on the freelist and initialize fields.
17552 if ((new_carrp = asc_dvc->carr_freelist) == NULL)
17554 DvcLeaveCritical(last_int_level);
17557 asc_dvc->carr_freelist = (ADV_CARR_T *)
17558 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17559 asc_dvc->carr_pending_cnt++;
17562 * Set the carrier to be a stopper by setting 'next_vpa'
17563 * to the stopper value. The current stopper will be changed
17564 * below to point to the new stopper.
17566 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17569 * Clear the ADV_SCSI_REQ_Q done flag.
17571 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17573 req_size = sizeof(ADV_SCSI_REQ_Q);
17574 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
17575 (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
17577 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17578 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17580 /* Wait for assertion before making little-endian */
17581 req_paddr = cpu_to_le32(req_paddr);
17583 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17584 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17585 scsiq->scsiq_rptr = req_paddr;
17587 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17589 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17590 * order during initialization.
17592 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17595 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17596 * the microcode. The newly allocated stopper will become the new
17599 asc_dvc->icq_sp->areq_vpa = req_paddr;
17602 * Set the 'next_vpa' pointer for the old stopper to be the
17603 * physical address of the new stopper. The RISC can only
17604 * follow physical addresses.
17606 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17609 * Set the host adapter stopper pointer to point to the new carrier.
17611 asc_dvc->icq_sp = new_carrp;
17613 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17614 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17617 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17619 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17620 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17623 * Clear the tickle value. In the ASC-3550 the RISC flag
17624 * command 'clr_tickle_a' does not work unless the host
17625 * value is cleared.
17627 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17629 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17632 * Notify the RISC a carrier is ready by writing the physical
17633 * address of the new carrier stopper to the COMMA register.
17635 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17636 le32_to_cpu(new_carrp->carr_pa));
17639 DvcLeaveCritical(last_int_level);
17641 return ADV_SUCCESS;
17645 * Reset SCSI Bus and purge all outstanding requests.
17648 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17649 * ADV_FALSE(0) - Microcode command failed.
17650 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17651 * may be hung which requires driver recovery.
17654 AdvResetSB(ADV_DVC_VAR *asc_dvc)
17659 * Send the SCSI Bus Reset idle start idle command which asserts
17660 * the SCSI Bus Reset signal.
17662 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
17663 if (status != ADV_TRUE)
17669 * Delay for the specified SCSI Bus Reset hold time.
17671 * The hold time delay is done on the host because the RISC has no
17672 * microsecond accurate timer.
17674 DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
17677 * Send the SCSI Bus Reset end idle command which de-asserts
17678 * the SCSI Bus Reset signal and purges any pending requests.
17680 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
17681 if (status != ADV_TRUE)
17686 DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
17692 * Reset chip and SCSI Bus.
17695 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17696 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17699 AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17702 ushort wdtr_able, sdtr_able, tagqng_able;
17703 ushort ppr_able = 0;
17704 uchar tid, max_cmd[ADV_MAX_TID + 1];
17705 AdvPortAddr iop_base;
17708 iop_base = asc_dvc->iop_base;
17711 * Save current per TID negotiated values.
17713 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17714 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17715 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17717 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17719 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17720 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17722 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17727 * Force the AdvInitAsc3550/38C0800Driver() function to
17728 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17729 * The initialization functions assumes a SCSI Bus Reset is not
17730 * needed if the BIOS signature word is present.
17732 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17733 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17736 * Stop chip and reset it.
17738 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17739 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17740 DvcSleepMilliSecond(100);
17741 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
17744 * Reset Adv Library error code, if any, and try
17745 * re-initializing the chip.
17747 asc_dvc->err_code = 0;
17748 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17750 status = AdvInitAsc38C1600Driver(asc_dvc);
17752 else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17754 status = AdvInitAsc38C0800Driver(asc_dvc);
17757 status = AdvInitAsc3550Driver(asc_dvc);
17760 /* Translate initialization return value to status value. */
17766 status = ADV_FALSE;
17770 * Restore the BIOS signature word.
17772 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17775 * Restore per TID negotiated values.
17777 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17778 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17779 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17781 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17783 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17784 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17786 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17794 * Adv Library Interrupt Service Routine
17796 * This function is called by a driver's interrupt service routine.
17797 * The function disables and re-enables interrupts.
17799 * When a microcode idle command is completed, the ADV_DVC_VAR
17800 * 'idle_cmd_done' field is set to ADV_TRUE.
17802 * Note: AdvISR() can be called when interrupts are disabled or even
17803 * when there is no hardware interrupt condition present. It will
17804 * always check for completed idle commands and microcode requests.
17805 * This is an important feature that shouldn't be changed because it
17806 * allows commands to be completed from polling mode loops.
17809 * ADV_TRUE(1) - interrupt was pending
17810 * ADV_FALSE(0) - no interrupt was pending
17813 AdvISR(ADV_DVC_VAR *asc_dvc)
17815 AdvPortAddr iop_base;
17818 ADV_CARR_T *free_carrp;
17819 ADV_VADDR irq_next_vpa;
17821 ADV_SCSI_REQ_Q *scsiq;
17823 flags = DvcEnterCritical();
17825 iop_base = asc_dvc->iop_base;
17827 /* Reading the register clears the interrupt. */
17828 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17830 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17831 ADV_INTR_STATUS_INTRC)) == 0)
17833 DvcLeaveCritical(flags);
17838 * Notify the driver of an asynchronous microcode condition by
17839 * calling the ADV_DVC_VAR.async_callback function. The function
17840 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17842 if (int_stat & ADV_INTR_STATUS_INTRB)
17846 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17848 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17849 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17851 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17852 asc_dvc->carr_pending_cnt != 0)
17854 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17855 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17857 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17862 if (asc_dvc->async_callback != 0)
17864 (*asc_dvc->async_callback)(asc_dvc, intrb_code);
17869 * Check if the IRQ stopper carrier contains a completed request.
17871 while (((irq_next_vpa =
17872 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
17875 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17876 * The RISC will have set 'areq_vpa' to a virtual address.
17878 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17879 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17880 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17881 * in AdvExeScsiQueue().
17883 scsiq = (ADV_SCSI_REQ_Q *)
17884 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17887 * Request finished with good status and the queue was not
17888 * DMAed to host memory by the firmware. Set all status fields
17889 * to indicate good status.
17891 if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
17893 scsiq->done_status = QD_NO_ERROR;
17894 scsiq->host_status = scsiq->scsi_status = 0;
17895 scsiq->data_cnt = 0L;
17899 * Advance the stopper pointer to the next carrier
17900 * ignoring the lower four bits. Free the previous
17903 free_carrp = asc_dvc->irq_sp;
17904 asc_dvc->irq_sp = (ADV_CARR_T *)
17905 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17907 free_carrp->next_vpa =
17908 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17909 asc_dvc->carr_freelist = free_carrp;
17910 asc_dvc->carr_pending_cnt--;
17912 ASC_ASSERT(scsiq != NULL);
17913 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17916 * Clear request microcode control flag.
17921 * If the command that completed was a SCSI INQUIRY and
17922 * LUN 0 was sent the command, then process the INQUIRY
17923 * command information for the device.
17925 * Note: If data returned were either VPD or CmdDt data,
17926 * don't process the INQUIRY command information for
17927 * the device, otherwise may erroneously set *_able bits.
17929 if (scsiq->done_status == QD_NO_ERROR &&
17930 scsiq->cdb[0] == INQUIRY &&
17931 scsiq->target_lun == 0 &&
17932 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17933 == ADV_INQ_RTN_STD_INQUIRY_DATA)
17935 AdvInquiryHandling(asc_dvc, scsiq);
17939 * Notify the driver of the completed request by passing
17940 * the ADV_SCSI_REQ_Q pointer to its callback function.
17942 scsiq->a_flag |= ADV_SCSIQ_DONE;
17943 (*asc_dvc->isr_callback)(asc_dvc, scsiq);
17945 * Note: After the driver callback function is called, 'scsiq'
17946 * can no longer be referenced.
17948 * Fall through and continue processing other completed
17953 * Disable interrupts again in case the driver inadvertently
17954 * enabled interrupts in its callback function.
17956 * The DvcEnterCritical() return value is ignored, because
17957 * the 'flags' saved when AdvISR() was first entered will be
17958 * used to restore the interrupt flag on exit.
17960 (void) DvcEnterCritical();
17962 DvcLeaveCritical(flags);
17967 * Send an idle command to the chip and wait for completion.
17969 * Command completion is polled for once per microsecond.
17971 * The function can be called from anywhere including an interrupt handler.
17972 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
17973 * functions to prevent reentrancy.
17976 * ADV_TRUE - command completed successfully
17977 * ADV_FALSE - command failed
17978 * ADV_ERROR - command timed out
17981 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
17983 ADV_DCNT idle_cmd_parameter)
17985 ulong last_int_level;
17988 AdvPortAddr iop_base;
17990 last_int_level = DvcEnterCritical();
17992 iop_base = asc_dvc->iop_base;
17995 * Clear the idle command status which is set by the microcode
17996 * to a non-zero value to indicate when the command is completed.
17997 * The non-zero result is one of the IDLE_CMD_STATUS_* values
17998 * defined in a_advlib.h.
18000 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
18003 * Write the idle command value after the idle command parameter
18004 * has been written to avoid a race condition. If the order is not
18005 * followed, the microcode may process the idle command before the
18006 * parameters have been written to LRAM.
18008 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
18009 cpu_to_le32(idle_cmd_parameter));
18010 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
18013 * Tickle the RISC to tell it to process the idle command.
18015 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
18016 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
18019 * Clear the tickle value. In the ASC-3550 the RISC flag
18020 * command 'clr_tickle_b' does not work unless the host
18021 * value is cleared.
18023 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
18026 /* Wait for up to 100 millisecond for the idle command to timeout. */
18027 for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
18029 /* Poll once each microsecond for command completion. */
18030 for (j = 0; j < SCSI_US_PER_MSEC; j++)
18032 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
18035 DvcLeaveCritical(last_int_level);
18038 DvcDelayMicroSecond(asc_dvc, (ushort) 1);
18042 ASC_ASSERT(0); /* The idle command should never timeout. */
18043 DvcLeaveCritical(last_int_level);
18048 * Inquiry Information Byte 7 Handling
18050 * Handle SCSI Inquiry Command information for a device by setting
18051 * microcode operating variables that affect WDTR, SDTR, and Tag
18055 AdvInquiryHandling(
18056 ADV_DVC_VAR *asc_dvc,
18057 ADV_SCSI_REQ_Q *scsiq)
18059 AdvPortAddr iop_base;
18061 ADV_SCSI_INQUIRY *inq;
18066 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
18069 * If less than 8 bytes of INQUIRY information were requested or less
18070 * than 8 bytes were transferred, then return. cdb[4] is the request
18071 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
18072 * microcode to the transfer residual count.
18075 if (scsiq->cdb[4] < 8 ||
18076 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
18081 iop_base = asc_dvc->iop_base;
18082 tid = scsiq->target_id;
18084 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
18087 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
18089 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
18095 * INQUIRY Byte 7 Handling
18097 * Use a device's INQUIRY byte 7 to determine whether it
18098 * supports WDTR, SDTR, and Tag Queuing. If the feature
18099 * is enabled in the EEPROM and the device supports the
18100 * feature, then enable it in the microcode.
18103 tidmask = ADV_TID_TO_TIDMASK(tid);
18108 * If the EEPROM enabled WDTR for the device and the device
18109 * supports wide bus (16 bit) transfers, then turn on the
18110 * device's 'wdtr_able' bit and write the new value to the
18113 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
18115 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18116 if ((cfg_word & tidmask) == 0)
18118 cfg_word |= tidmask;
18119 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18122 * Clear the microcode "SDTR negotiation" and "WDTR
18123 * negotiation" done indicators for the target to cause
18124 * it to negotiate with the new setting set above.
18125 * WDTR when accepted causes the target to enter
18126 * asynchronous mode, so SDTR must be negotiated.
18128 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18129 cfg_word &= ~tidmask;
18130 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18131 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18132 cfg_word &= ~tidmask;
18133 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18138 * Synchronous Transfers
18140 * If the EEPROM enabled SDTR for the device and the device
18141 * supports synchronous transfers, then turn on the device's
18142 * 'sdtr_able' bit. Write the new value to the microcode.
18144 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
18146 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18147 if ((cfg_word & tidmask) == 0)
18149 cfg_word |= tidmask;
18150 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18153 * Clear the microcode "SDTR negotiation" done indicator
18154 * for the target to cause it to negotiate with the new
18155 * setting set above.
18157 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18158 cfg_word &= ~tidmask;
18159 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18163 * If the Inquiry data included enough space for the SPI-3
18164 * Clocking field, then check if DT mode is supported.
18166 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
18167 (scsiq->cdb[4] >= 57 ||
18168 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
18171 * PPR (Parallel Protocol Request) Capable
18173 * If the device supports DT mode, then it must be PPR capable.
18174 * The PPR message will be used in place of the SDTR and WDTR
18175 * messages to negotiate synchronous speed and offset, transfer
18176 * width, and protocol options.
18178 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
18180 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18181 asc_dvc->ppr_able |= tidmask;
18182 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18187 * If the EEPROM enabled Tag Queuing for the device and the
18188 * device supports Tag Queueing, then turn on the device's
18189 * 'tagqng_enable' bit in the microcode and set the microcode
18190 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
18193 * Tag Queuing is disabled for the BIOS which runs in polled
18194 * mode and would see no benefit from Tag Queuing. Also by
18195 * disabling Tag Queuing in the BIOS devices with Tag Queuing
18196 * bugs will at least work with the BIOS.
18198 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
18200 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18201 cfg_word |= tidmask;
18202 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18204 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
18205 asc_dvc->max_dvc_qng);
18209 MODULE_LICENSE("Dual BSD/GPL");
18211 /* PCI Devices supported by this driver */
18212 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
18213 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
18214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18215 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
18216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18217 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
18218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18219 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
18220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18221 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
18222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18223 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
18224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18227 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);