1 #define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that redistributions of source
12 * code retain the above copyright notice and this comment without
15 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
16 * changed its name to ConnectCom Solutions, Inc.
22 Documentation for the AdvanSys Driver
24 A. Linux Kernels Supported by this Driver
25 B. Adapters Supported by this Driver
26 C. Linux source files modified by AdvanSys Driver
28 E. Driver Compile Time Options and Debugging
30 G. Tests to run before releasing new driver
32 I. Known Problems/Fix List
33 J. Credits (Chronological Order)
35 A. Linux Kernels Supported by this Driver
37 This driver has been tested in the following Linux kernels: v2.2.18
38 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
39 alpha, and PowerPC platforms.
41 B. Adapters Supported by this Driver
43 AdvanSys (Advanced System Products, Inc.) manufactures the following
44 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
45 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
46 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
47 transfer) SCSI Host Adapters for the PCI bus.
49 The CDB counts below indicate the number of SCSI CDB (Command
50 Descriptor Block) requests that can be stored in the RISC chip
51 cache and board LRAM. A CDB is a single SCSI command. The driver
52 detect routine will display the number of CDBs available for each
53 adapter detected. The number of CDBs used by the driver can be
54 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
57 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
59 Connectivity Products:
60 ABP510/5150 - Bus-Master ISA (240 CDB)
61 ABP5140 - Bus-Master ISA PnP (16 CDB)
62 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
63 ABP902/3902 - Bus-Master PCI (16 CDB)
64 ABP3905 - Bus-Master PCI (16 CDB)
65 ABP915 - Bus-Master PCI (16 CDB)
66 ABP920 - Bus-Master PCI (16 CDB)
67 ABP3922 - Bus-Master PCI (16 CDB)
68 ABP3925 - Bus-Master PCI (16 CDB)
69 ABP930 - Bus-Master PCI (16 CDB)
70 ABP930U - Bus-Master PCI Ultra (16 CDB)
71 ABP930UA - Bus-Master PCI Ultra (16 CDB)
72 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
73 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
75 Single Channel Products:
76 ABP542 - Bus-Master ISA with floppy (240 CDB)
77 ABP742 - Bus-Master EISA (240 CDB)
78 ABP842 - Bus-Master VL (240 CDB)
79 ABP940 - Bus-Master PCI (240 CDB)
80 ABP940U - Bus-Master PCI Ultra (240 CDB)
81 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
82 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
83 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
84 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
85 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
86 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
87 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
89 Multi-Channel Products:
90 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
91 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
92 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
93 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
94 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
95 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
96 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
97 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
98 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
100 C. Linux source files modified by AdvanSys Driver
102 This section for historical purposes documents the changes
103 originally made to the Linux kernel source to add the advansys
104 driver. As Linux has changed some of these files have also
107 1. linux/arch/i386/config.in:
109 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
111 2. linux/drivers/scsi/hosts.c:
113 #ifdef CONFIG_SCSI_ADVANSYS
114 #include "advansys.h"
117 and after "static struct scsi_host_template builtin_scsi_hosts[] =":
119 #ifdef CONFIG_SCSI_ADVANSYS
123 3. linux/drivers/scsi/Makefile:
125 ifdef CONFIG_SCSI_ADVANSYS
126 SCSI_SRCS := $(SCSI_SRCS) advansys.c
127 SCSI_OBJS := $(SCSI_OBJS) advansys.o
129 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
132 4. linux/init/main.c:
134 extern void advansys_setup(char *str, int *ints);
136 and add the following lines to the bootsetups[] array.
138 #ifdef CONFIG_SCSI_ADVANSYS
139 { "advansys=", advansys_setup },
144 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
146 2. This driver should be maintained in multiple files. But to make
147 it easier to include with Linux and to follow Linux conventions,
148 the whole driver is maintained in the source files advansys.h and
149 advansys.c. In this file logical sections of the driver begin with
150 a comment that contains '---'. The following are the logical sections
154 --- Linux Include File
157 --- Asc Library Constants and Macros
158 --- Adv Library Constants and Macros
159 --- Driver Constants and Macros
160 --- Driver Structures
162 --- Driver Function Prototypes
163 --- Linux 'struct scsi_host_template' and advansys_setup() Functions
164 --- Loadable Driver Support
165 --- Miscellaneous Driver Functions
166 --- Functions Required by the Asc Library
167 --- Functions Required by the Adv Library
168 --- Tracing and Debugging Functions
169 --- Asc Library Functions
170 --- Adv Library Functions
172 3. The string 'XXX' is used to flag code that needs to be re-written
173 or that contains a problem that needs to be addressed.
175 4. I have stripped comments from and reformatted the source for the
176 Asc Library and Adv Library to reduce the size of this file. This
177 source can be found under the following headings. The Asc Library
178 is used to support Narrow Boards. The Adv Library is used to
181 --- Asc Library Constants and Macros
182 --- Adv Library Constants and Macros
183 --- Asc Library Functions
184 --- Adv Library Functions
186 E. Driver Compile Time Options and Debugging
188 In this source file the following constants can be defined. They are
189 defined in the source below. Both of these options are enabled by
192 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
194 Enabling this option adds assertion logic statements to the
195 driver. If an assertion fails a message will be displayed to
196 the console, but the system will continue to operate. Any
197 assertions encountered should be reported to the person
198 responsible for the driver. Assertion statements may proactively
199 detect problems with the driver and facilitate fixing these
200 problems. Enabling assertions will add a small overhead to the
201 execution of the driver.
203 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
205 Enabling this option adds tracing functions to the driver and
206 the ability to set a driver tracing level at boot time. This
207 option will also export symbols not required outside the driver to
208 the kernel name space. This option is very useful for debugging
209 the driver, but it will add to the size of the driver execution
210 image and add overhead to the execution of the driver.
212 The amount of debugging output can be controlled with the global
213 variable 'asc_dbglvl'. The higher the number the more output. By
214 default the debug level is 0.
216 If the driver is loaded at boot time and the LILO Driver Option
217 is included in the system, the debug level can be changed by
218 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
219 first three hex digits of the pseudo I/O Port must be set to
220 'deb' and the fourth hex digit specifies the debug level: 0 - F.
221 The following command line will look for an adapter at 0x330
222 and set the debug level to 2.
224 linux advansys=0x330,0,0,0,0xdeb2
226 If the driver is built as a loadable module this variable can be
227 defined when the driver is loaded. The following insmod command
228 will set the debug level to one.
230 insmod advansys.o asc_dbglvl=1
232 Debugging Message Levels:
234 1: High-Level Tracing
237 To enable debug output to console, please make sure that:
239 a. System and kernel logging is enabled (syslogd, klogd running).
240 b. Kernel messages are routed to console output. Check
241 /etc/syslog.conf for an entry similar to this:
245 c. klogd is started with the appropriate -c parameter
248 This will cause printk() messages to be be displayed on the
249 current console. Refer to the klogd(8) and syslogd(8) man pages
252 Alternatively you can enable printk() to console with this
253 program. However, this is not the 'official' way to do this.
254 Debug output is logged in /var/log/messages.
258 syscall(103, 7, 0, 0);
261 Increasing LOG_BUF_LEN in kernel/printk.c to something like
262 40960 allows more debug messages to be buffered in the kernel
263 and written to the console or log file.
265 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
267 Enabling this option adds statistics collection and display
268 through /proc to the driver. The information is useful for
269 monitoring driver and device performance. It will add to the
270 size of the driver execution image and add minor overhead to
271 the execution of the driver.
273 Statistics are maintained on a per adapter basis. Driver entry
274 point call counts and transfer size counts are maintained.
275 Statistics are only available for kernels greater than or equal
276 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
278 AdvanSys SCSI adapter files have the following path name format:
280 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
282 This information can be displayed with cat. For example:
284 cat /proc/scsi/advansys/0
286 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
287 contain adapter and device configuration information.
289 F. Driver LILO Option
291 If init/main.c is modified as described in the 'Directions for Adding
292 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
293 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
294 This option can be used to either disable I/O port scanning or to limit
295 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
296 PCI boards will still be searched for and detected. This option only
297 affects searching for ISA and VL boards.
300 1. Eliminate I/O port scanning:
301 boot: linux advansys=
303 boot: linux advansys=0x0
304 2. Limit I/O port scanning to one I/O port:
305 boot: linux advansys=0x110
306 3. Limit I/O port scanning to four I/O ports:
307 boot: linux advansys=0x110,0x210,0x230,0x330
309 For a loadable module the same effect can be achieved by setting
310 the 'asc_iopflag' variable and 'asc_ioport' array when loading
313 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
315 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
316 I/O Port may be added to specify the driver debug level. Refer to
317 the 'Driver Compile Time Options and Debugging' section above for
320 G. Tests to run before releasing new driver
322 1. In the supported kernels verify there are no warning or compile
323 errors when the kernel is built as both a driver and as a module
324 and with the following options:
326 ADVANSYS_DEBUG - enabled and disabled
327 CONFIG_SMP - enabled and disabled
328 CONFIG_PROC_FS - enabled and disabled
330 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
331 card and one wide card attached to a hard disk and CD-ROM drive:
332 fdisk, mkfs, fsck, bonnie, copy/compare test from the
333 CD-ROM to the hard drive.
341 1. Prevent advansys_detect() from being called twice.
342 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
345 1. Prevent re-entrancy in the interrupt handler which
346 resulted in the driver hanging Linux.
347 2. Fix problem that prevented ABP-940 cards from being
348 recognized on some PCI motherboards.
349 3. Add support for the ABP-5140 PnP ISA card.
350 4. Fix check condition return status.
351 5. Add conditionally compiled code for Linux v1.3.X.
354 1. Fix problem in advansys_biosparam() that resulted in the
355 wrong drive geometry being returned for drives > 1GB with
356 extended translation enabled.
357 2. Add additional tracing during device initialization.
358 3. Change code that only applies to ISA PnP adapter.
359 4. Eliminate 'make dep' warning.
360 5. Try to fix problem with handling resets by increasing their
364 1. Change definitions to eliminate conflicts with other subsystems.
365 2. Add versioning code for the shared interrupt changes.
366 3. Eliminate problem in asc_rmqueue() with iterating after removing
368 4. Remove reset request loop problem from the "Known Problems or
369 Issues" section. This problem was isolated and fixed in the
370 mid-level SCSI driver.
373 1. Add support for ABP-940U (PCI Ultra) adapter.
374 2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
375 request_irq and supplying a dev_id pointer to both request_irq()
377 3. In AscSearchIOPortAddr11() restore a call to check_region() which
378 should be used before I/O port probing.
379 4. Fix bug in asc_prt_hex() which resulted in the displaying
381 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
382 6. Change driver versioning to be specific to each Linux sub-level.
383 7. Change statistics gathering to be per adapter instead of global
385 8. Add more information and statistics to the adapter /proc file:
386 /proc/scsi/advansys[0...].
387 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
388 This problem has been addressed with the SCSI mid-level changes
389 made in v1.3.89. The advansys_select_queue_depths() function
390 was added for the v1.3.89 changes.
393 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
396 1. Enable clustering and optimize the setting of the maximum number
397 of scatter gather elements for any particular board. Clustering
398 increases CPU utilization, but results in a relatively larger
399 increase in I/O throughput.
400 2. Improve the performance of the request queuing functions by
401 adding a last pointer to the queue structure.
402 3. Correct problems with reset and abort request handling that
403 could have hung or crashed Linux.
404 4. Add more information to the adapter /proc file:
405 /proc/scsi/advansys[0...].
406 5. Remove the request timeout issue form the driver issues list.
407 6. Miscellaneous documentation additions and changes.
410 1. Make changes to handle the new v2.1.0 kernel memory mapping
411 in which a kernel virtual address may not be equivalent to its
412 bus or DMA memory address.
413 2. Change abort and reset request handling to make it yet even
415 3. Try to mitigate request starvation by sending ordered requests
416 to heavily loaded, tag queuing enabled devices.
417 4. Maintain statistics on request response time.
418 5. Add request response time statistics and other information to
419 the adapter /proc file: /proc/scsi/advansys[0...].
422 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
423 make use of mid-level SCSI driver device queue depth flow
424 control mechanism. This will eliminate aborts caused by a
425 device being unable to keep up with requests and eliminate
426 repeat busy or QUEUE FULL status returned by a device.
427 2. Incorporate miscellaneous Asc Library bug fixes.
428 3. To allow the driver to work in kernels with broken module
429 support set 'cmd_per_lun' if the driver is compiled as a
430 module. This change affects kernels v1.3.89 to present.
431 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
432 is relocated by the motherboard BIOS and its new address can
433 not be determined by the driver.
434 5. Add mid-level SCSI queue depth information to the adapter
435 /proc file: /proc/scsi/advansys[0...].
438 1. Change allocation of global structures used for device
439 initialization to guarantee they are in DMA-able memory.
440 Previously when the driver was loaded as a module these
441 structures might not have been in DMA-able memory, causing
442 device initialization to fail.
445 1. In advansys_reset(), if the request is a synchronous reset
446 request, even if the request serial number has changed, then
447 complete the request.
448 2. Add Asc Library bug fixes including new microcode.
449 3. Clear inquiry buffer before using it.
450 4. Correct ifdef typo.
453 1. Add Asc Library bug fixes including new microcode.
454 2. Add synchronous data transfer rate information to the
455 adapter /proc file: /proc/scsi/advansys[0...].
456 3. Change ADVANSYS_DEBUG to be disabled by default. This
457 will reduce the size of the driver image, eliminate execution
458 overhead, and remove unneeded symbols from the kernel symbol
459 space that were previously added by the driver.
460 4. Add new compile-time option ADVANSYS_ASSERT for assertion
461 code that used to be defined within ADVANSYS_DEBUG. This
462 option is enabled by default.
465 1. Change version number to 2.8 to synchronize the Linux driver
466 version numbering with other AdvanSys drivers.
467 2. Reformat source files without tabs to present the same view
468 of the file to everyone regardless of the editor tab setting
470 3. Add Asc Library bug fixes.
473 1. Change version number to 3.1 to indicate that support for
474 Ultra-Wide adapters (ABP-940UW) is included in this release.
475 2. Add Asc Library (Narrow Board) bug fixes.
476 3. Report an underrun condition with the host status byte set
477 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
478 causes the underrun condition to be ignored. When Linux defines
479 its own DID_UNDERRUN the constant defined in this file can be
481 4. Add patch to AscWaitTixISRDone().
482 5. Add support for up to 16 different AdvanSys host adapter SCSI
483 channels in one system. This allows four cards with four channels
484 to be used in one system.
487 1. Handle that PCI register base addresses are not always page
488 aligned even though ioremap() requires that the address argument
492 1. Update latest BIOS version checked for from the /proc file.
493 2. Don't set microcode SDTR variable at initialization. Instead
494 wait until device capabilities have been detected from an Inquiry
498 1. Improve performance when the driver is compiled as module by
499 allowing up to 64 scatter-gather elements instead of 8.
502 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
503 2. Include SMP locking changes.
504 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
506 4. Update board serial number printing.
507 5. Try allocating an IRQ both with and without the SA_INTERRUPT
508 flag set to allow IRQ sharing with drivers that do not set
509 the SA_INTERRUPT flag. Also display a more descriptive error
510 message if request_irq() fails.
511 6. Update to latest Asc and Adv Libraries.
514 1. Update Adv Library to 4.16 which includes support for
515 the ASC38C0800 (Ultra2/LVD) IC.
518 1. Correct PCI compile time option for v2.1.93 and greater
519 kernels, advansys_info() string, and debug compile time
521 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
522 kernels. This caused an LVD detection/BIST problem problem
524 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
525 to be consistent with the BIOS.
526 4. Update to Asc Library S121 and Adv Library 5.2.
529 1. Correct PCI card detection bug introduced in 3.2B that
530 prevented PCI cards from being detected in kernels older
534 1. Correct /proc device synchronous speed information display.
535 Also when re-negotiation is pending for a target device
536 note this condition with an * and footnote.
537 2. Correct initialization problem with Ultra-Wide cards that
538 have a pre-3.2 BIOS. A microcode variable changed locations
539 in 3.2 and greater BIOSes which caused WDTR to be attempted
540 erroneously with drives that don't support WDTR.
543 1. Fix compile error caused by v2.3.13 PCI structure change.
544 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
545 checksum error for ISA cards.
546 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
547 SCSI changes that it depended on were never included in Linux.
550 1. Handle new initial function code added in v2.3.16 for all
554 1. Fix PCI board detection in v2.3.13 and greater kernels.
555 2. Fix comiple errors in v2.3.X with debugging enabled.
558 1. Add 64-bit address, long support for Alpha and UltraSPARC.
559 The driver has been verified to work on an Alpha system.
560 2. Add partial byte order handling support for Power PC and
561 other big-endian platforms. This support has not yet been
562 completed or verified.
563 3. For wide boards replace block zeroing of request and
564 scatter-gather structures with individual field initialization
565 to improve performance.
566 4. Correct and clarify ROM BIOS version detection.
569 1. Update to Adv Library 5.4.
570 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
571 adv_isr_callback(). Remove DID_UNDERRUN constant and other
572 no longer needed code that previously documented the lack
573 of underrun handling.
576 1. Eliminate compile errors for v2.0 and earlier kernels.
579 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
580 2. Update Adv Library to 5.5.
581 3. Add ifdef handling for /proc changes added in v2.3.28.
582 4. Increase Wide board scatter-gather list maximum length to
583 255 when the driver is compiled into the kernel.
586 1. Fix bug in adv_get_sglist() that caused an assertion failure
587 at line 7475. The reqp->sgblkp pointer must be initialized
588 to NULL in adv_get_sglist().
591 1. Really fix bug in adv_get_sglist().
592 2. Incorporate v2.3.29 changes into driver.
595 1. Add CONFIG_ISA ifdef code.
596 2. Include advansys_interrupts_enabled name change patch.
597 3. For >= v2.3.28 use new SCSI error handling with new function
598 advansys_eh_bus_reset(). Don't include an abort function
599 because of base library limitations.
600 4. For >= v2.3.28 use per board lock instead of io_request_lock.
601 5. For >= v2.3.28 eliminate advansys_command() and
602 advansys_command_done().
603 6. Add some changes for PowerPC (Big Endian) support, but it isn't
605 7. Fix "nonexistent resource free" problem that occurred on a module
606 unload for boards with an I/O space >= 255. The 'n_io_port' field
607 is only one byte and can not be used to hold an ioport length more
611 1. Update to Adv Library 5.8.
612 2. For wide cards add support for CDBs up to 16 bytes.
613 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
616 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
618 2. Change bitfields to shift and mask access for endian
622 1. Update for latest 2.4 kernel.
623 2. Test ABP-480 CardBus support in 2.4 kernel - works!
624 3. Update to Asc Library S123.
625 4. Update to Adv Library 5.12.
628 1. Update for latest 2.4 kernel.
629 2. Create patches for 2.2 and 2.4 kernels.
632 1. Now that 2.4 is released remove ifdef code for kernel versions
633 less than 2.2. The driver is now only supported in kernels 2.2,
635 2. Add code to release and acquire the io_request_lock in
636 the driver entrypoint functions: advansys_detect and
637 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
638 still holds the io_request_lock on entry to SCSI low-level drivers.
639 This was supposed to be removed before 2.4 was released but never
640 happened. When the mid-level SCSI driver is changed all references
641 to the io_request_lock should be removed from the driver.
642 3. Simplify error handling by removing advansys_abort(),
643 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
644 now handled by resetting the SCSI bus and fully re-initializing
645 the chip. This simple method of error recovery has proven to work
646 most reliably after attempts at different methods. Also now only
647 support the "new" error handling method and remove the obsolete
648 error handling interface.
649 4. Fix debug build errors.
652 1. Merge with ConnectCom version from Andy Kellner which
653 updates Adv Library to 5.14.
654 2. Make PowerPC (Big Endian) work for narrow cards and
655 fix problems writing EEPROM for wide cards.
656 3. Remove interrupts_enabled assertion function.
659 1. Return an error from narrow boards if passed a 16 byte
660 CDB. The wide board can already handle 16 byte CDBs.
663 1. hacks for lk 2.5 series (D. Gilbert)
666 1. change select_queue_depths to slave_configure
667 2. make cmd_per_lun be sane again
670 1. continuing cleanup for lk 2.6 series
671 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
672 3. Fix problem that oopsed ISA cards
674 I. Known Problems/Fix List (XXX)
676 1. Need to add memory mapping workaround. Test the memory mapping.
677 If it doesn't work revert to I/O port access. Can a test be done
679 2. Handle an interrupt not working. Keep an interrupt counter in
680 the interrupt handler. In the timeout function if the interrupt
681 has not occurred then print a message and run in polled mode.
682 3. Allow bus type scanning order to be changed.
683 4. Need to add support for target mode commands, cf. CAM XPT.
685 J. Credits (Chronological Order)
687 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
688 and maintained it up to 3.3F. He continues to answer questions
689 and help maintain the driver.
691 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
692 basis for the Linux v1.3.X changes which were included in the
695 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
696 in advansys_biosparam() which was fixed in the 1.3 release.
698 Erik Ratcliffe <erik@caldera.com> has done testing of the
699 AdvanSys driver in the Caldera releases.
701 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
702 AscWaitTixISRDone() which he found necessary to make the
703 driver work with a SCSI-1 disk.
705 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
706 support in the 3.1A driver.
708 Doug Gilbert <dgilbert@interlog.com> has made changes and
709 suggestions to improve the driver and done a lot of testing.
711 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
714 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
715 patch and helped with PowerPC wide and narrow board support.
717 Philip Blundell <philb@gnu.org> provided an
718 advansys_interrupts_enabled patch.
720 Dave Jones <dave@denial.force9.co.uk> reported the compiler
721 warnings generated when CONFIG_PROC_FS was not defined in
724 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
725 problems) for wide cards.
727 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
730 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
731 board support and fixed a bug in AscGetEEPConfig().
733 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
734 save_flags/restore_flags changes.
736 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
737 driver development for ConnectCom (Version > 3.3F).
739 K. ConnectCom (AdvanSys) Contact Information
741 Mail: ConnectCom Solutions, Inc.
744 Operator/Sales: 1-408-383-9400
746 Tech Support: 1-408-467-2930
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754 * --- Linux Include Files
757 #include <linux/config.h>
758 #include <linux/module.h>
760 #if defined(CONFIG_X86) && !defined(CONFIG_ISA)
762 #endif /* CONFIG_X86 && !CONFIG_ISA */
764 #include <linux/string.h>
765 #include <linux/kernel.h>
766 #include <linux/types.h>
767 #include <linux/ioport.h>
768 #include <linux/interrupt.h>
769 #include <linux/delay.h>
770 #include <linux/slab.h>
771 #include <linux/mm.h>
772 #include <linux/proc_fs.h>
773 #include <linux/init.h>
774 #include <linux/blkdev.h>
775 #include <linux/stat.h>
776 #include <linux/spinlock.h>
777 #include <linux/dma-mapping.h>
780 #include <asm/system.h>
783 /* FIXME: (by jejb@steeleye.com) This warning is present for two
786 * 1) This driver badly needs converting to the correct driver model
789 * 2) Although all of the necessary command mapping places have the
790 * appropriate dma_map.. APIs, the driver still processes its internal
791 * queue using bus_to_virt() and virt_to_bus() which are illegal under
792 * the API. The entire queue processing structure will need to be
793 * altered to fix this.
795 #warning this driver is still not properly converted to the DMA API
797 #include <scsi/scsi_cmnd.h>
798 #include <scsi/scsi_device.h>
799 #include <scsi/scsi_tcq.h>
800 #include <scsi/scsi.h>
801 #include <scsi/scsi_host.h>
802 #include "advansys.h"
804 #include <linux/pci.h>
805 #endif /* CONFIG_PCI */
812 /* Enable driver assertions. */
813 #define ADVANSYS_ASSERT
815 /* Enable driver /proc statistics. */
816 #define ADVANSYS_STATS
818 /* Enable driver tracing. */
819 /* #define ADVANSYS_DEBUG */
823 * --- Debugging Header
826 #ifdef ADVANSYS_DEBUG
828 #else /* ADVANSYS_DEBUG */
829 #define STATIC static
830 #endif /* ADVANSYS_DEBUG */
834 * --- Asc Library Constants and Macros
837 #define ASC_LIB_VERSION_MAJOR 1
838 #define ASC_LIB_VERSION_MINOR 24
839 #define ASC_LIB_SERIAL_NUMBER 123
842 * Portable Data Types
844 * Any instance where a 32-bit long or pointer type is assumed
845 * for precision or HW defined structures, the following define
846 * types must be used. In Linux the char, short, and int types
847 * are all consistent at 8, 16, and 32 bits respectively. Pointers
848 * and long types are 64 bits on Alpha and UltraSPARC.
850 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
851 #define ASC_VADDR __u32 /* Virtual address data type. */
852 #define ASC_DCNT __u32 /* Unsigned Data count type. */
853 #define ASC_SDCNT __s32 /* Signed Data count type. */
856 * These macros are used to convert a virtual address to a
857 * 32-bit value. This currently can be used on Linux Alpha
858 * which uses 64-bit virtual address but a 32-bit bus address.
859 * This is likely to break in the future, but doing this now
860 * will give us time to change the HW and FW to handle 64-bit
863 #define ASC_VADDR_TO_U32 virt_to_bus
864 #define ASC_U32_TO_VADDR bus_to_virt
866 typedef unsigned char uchar;
877 #define UW_ERR (uint)(0xFFFF)
878 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
879 #define AscPCIConfigVendorIDRegister 0x0000
880 #define AscPCIConfigDeviceIDRegister 0x0002
881 #define AscPCIConfigCommandRegister 0x0004
882 #define AscPCIConfigStatusRegister 0x0006
883 #define AscPCIConfigRevisionIDRegister 0x0008
884 #define AscPCIConfigCacheSize 0x000C
885 #define AscPCIConfigLatencyTimer 0x000D
886 #define AscPCIIOBaseRegister 0x0010
887 #define AscPCICmdRegBits_IOMemBusMaster 0x0007
888 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
889 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
890 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
891 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
892 #define ASC_PCI_REVISION_3150 0x02
893 #define ASC_PCI_REVISION_3050 0x03
895 #define ASC_DVCLIB_CALL_DONE (1)
896 #define ASC_DVCLIB_CALL_FAILED (0)
897 #define ASC_DVCLIB_CALL_ERROR (-1)
899 #define PCI_VENDOR_ID_ASP 0x10cd
900 #define PCI_DEVICE_ID_ASP_1200A 0x1100
901 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
902 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
903 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
904 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
905 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
908 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
909 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
910 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
913 #define CC_VERY_LONG_SG_LIST 0
914 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
916 #define PortAddr unsigned short /* port address size */
917 #define inp(port) inb(port)
918 #define outp(port, byte) outb((byte), (port))
920 #define inpw(port) inw(port)
921 #define outpw(port, word) outw((word), (port))
923 #define ASC_MAX_SG_QUEUE 7
924 #define ASC_MAX_SG_LIST 255
926 #define ASC_CS_TYPE unsigned short
928 #define ASC_IS_ISA (0x0001)
929 #define ASC_IS_ISAPNP (0x0081)
930 #define ASC_IS_EISA (0x0002)
931 #define ASC_IS_PCI (0x0004)
932 #define ASC_IS_PCI_ULTRA (0x0104)
933 #define ASC_IS_PCMCIA (0x0008)
934 #define ASC_IS_MCA (0x0020)
935 #define ASC_IS_VL (0x0040)
936 #define ASC_ISA_PNP_PORT_ADDR (0x279)
937 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
938 #define ASC_IS_WIDESCSI_16 (0x0100)
939 #define ASC_IS_WIDESCSI_32 (0x0200)
940 #define ASC_IS_BIG_ENDIAN (0x8000)
941 #define ASC_CHIP_MIN_VER_VL (0x01)
942 #define ASC_CHIP_MAX_VER_VL (0x07)
943 #define ASC_CHIP_MIN_VER_PCI (0x09)
944 #define ASC_CHIP_MAX_VER_PCI (0x0F)
945 #define ASC_CHIP_VER_PCI_BIT (0x08)
946 #define ASC_CHIP_MIN_VER_ISA (0x11)
947 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
948 #define ASC_CHIP_MAX_VER_ISA (0x27)
949 #define ASC_CHIP_VER_ISA_BIT (0x30)
950 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
951 #define ASC_CHIP_VER_ASYN_BUG (0x21)
952 #define ASC_CHIP_VER_PCI 0x08
953 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
954 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
955 #define ASC_CHIP_MIN_VER_EISA (0x41)
956 #define ASC_CHIP_MAX_VER_EISA (0x47)
957 #define ASC_CHIP_VER_EISA_BIT (0x40)
958 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
959 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
960 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
961 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
962 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
963 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
964 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
965 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
966 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
967 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
968 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
970 #define ASC_SCSI_ID_BITS 3
971 #define ASC_SCSI_TIX_TYPE uchar
972 #define ASC_ALL_DEVICE_BIT_SET 0xFF
973 #define ASC_SCSI_BIT_ID_TYPE uchar
974 #define ASC_MAX_TID 7
975 #define ASC_MAX_LUN 7
976 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
977 #define ASC_MAX_SENSE_LEN 32
978 #define ASC_MIN_SENSE_LEN 14
979 #define ASC_MAX_CDB_LEN 12
980 #define ASC_SCSI_RESET_HOLD_TIME_US 60
982 #define ADV_INQ_CLOCKING_ST_ONLY 0x0
983 #define ADV_INQ_CLOCKING_DT_ONLY 0x1
984 #define ADV_INQ_CLOCKING_ST_AND_DT 0x3
987 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
988 * and CmdDt (Command Support Data) field bit definitions.
990 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
991 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
992 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
993 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
995 #define ASC_SCSIDIR_NOCHK 0x00
996 #define ASC_SCSIDIR_T2H 0x08
997 #define ASC_SCSIDIR_H2T 0x10
998 #define ASC_SCSIDIR_NODATA 0x18
999 #define SCSI_ASC_NOMEDIA 0x3A
1000 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
1001 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
1002 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
1003 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
1004 #define MS_CMD_DONE 0x00
1005 #define MS_EXTEND 0x01
1006 #define MS_SDTR_LEN 0x03
1007 #define MS_SDTR_CODE 0x01
1008 #define MS_WDTR_LEN 0x02
1009 #define MS_WDTR_CODE 0x03
1010 #define MS_MDP_LEN 0x05
1011 #define MS_MDP_CODE 0x00
1014 * Inquiry data structure and bitfield macros
1016 * Only quantities of more than 1 bit are shifted, since the others are
1017 * just tested for true or false. C bitfields aren't portable between big
1018 * and little-endian platforms so they are not used.
1021 #define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1022 #define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1023 #define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1024 #define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1025 #define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1026 #define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1027 #define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1028 #define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1029 #define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1030 #define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1031 #define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1032 #define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1033 #define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1034 #define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1035 #define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1036 #define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1037 #define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1038 #define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1039 #define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1040 #define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1052 uchar product_id[16];
1053 uchar product_rev_level[4];
1056 #define ASC_SG_LIST_PER_Q 7
1057 #define QS_FREE 0x00
1058 #define QS_READY 0x01
1059 #define QS_DISC1 0x02
1060 #define QS_DISC2 0x04
1061 #define QS_BUSY 0x08
1062 #define QS_ABORTED 0x40
1063 #define QS_DONE 0x80
1064 #define QC_NO_CALLBACK 0x01
1065 #define QC_SG_SWAP_QUEUE 0x02
1066 #define QC_SG_HEAD 0x04
1067 #define QC_DATA_IN 0x08
1068 #define QC_DATA_OUT 0x10
1069 #define QC_URGENT 0x20
1070 #define QC_MSG_OUT 0x40
1071 #define QC_REQ_SENSE 0x80
1072 #define QCSG_SG_XFER_LIST 0x02
1073 #define QCSG_SG_XFER_MORE 0x04
1074 #define QCSG_SG_XFER_END 0x08
1075 #define QD_IN_PROGRESS 0x00
1076 #define QD_NO_ERROR 0x01
1077 #define QD_ABORTED_BY_HOST 0x02
1078 #define QD_WITH_ERROR 0x04
1079 #define QD_INVALID_REQUEST 0x80
1080 #define QD_INVALID_HOST_NUM 0x81
1081 #define QD_INVALID_DEVICE 0x82
1082 #define QD_ERR_INTERNAL 0xFF
1083 #define QHSTA_NO_ERROR 0x00
1084 #define QHSTA_M_SEL_TIMEOUT 0x11
1085 #define QHSTA_M_DATA_OVER_RUN 0x12
1086 #define QHSTA_M_DATA_UNDER_RUN 0x12
1087 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1088 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1089 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1090 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1091 #define QHSTA_D_HOST_ABORT_FAILED 0x23
1092 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1093 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1094 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1095 #define QHSTA_M_WTM_TIMEOUT 0x41
1096 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1097 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1098 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1099 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
1100 #define QHSTA_M_BAD_TAG_CODE 0x46
1101 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1102 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1103 #define QHSTA_D_LRAM_CMP_ERROR 0x81
1104 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1105 #define ASC_FLAG_SCSIQ_REQ 0x01
1106 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1107 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
1108 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1109 #define ASC_FLAG_WIN16 0x10
1110 #define ASC_FLAG_WIN32 0x20
1111 #define ASC_FLAG_ISA_OVER_16MB 0x40
1112 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
1113 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1114 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1115 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1116 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1117 #define ASC_SCSIQ_CPY_BEG 4
1118 #define ASC_SCSIQ_SGHD_CPY_BEG 2
1119 #define ASC_SCSIQ_B_FWD 0
1120 #define ASC_SCSIQ_B_BWD 1
1121 #define ASC_SCSIQ_B_STATUS 2
1122 #define ASC_SCSIQ_B_QNO 3
1123 #define ASC_SCSIQ_B_CNTL 4
1124 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1125 #define ASC_SCSIQ_D_DATA_ADDR 8
1126 #define ASC_SCSIQ_D_DATA_CNT 12
1127 #define ASC_SCSIQ_B_SENSE_LEN 20
1128 #define ASC_SCSIQ_DONE_INFO_BEG 22
1129 #define ASC_SCSIQ_D_SRBPTR 22
1130 #define ASC_SCSIQ_B_TARGET_IX 26
1131 #define ASC_SCSIQ_B_CDB_LEN 28
1132 #define ASC_SCSIQ_B_TAG_CODE 29
1133 #define ASC_SCSIQ_W_VM_ID 30
1134 #define ASC_SCSIQ_DONE_STATUS 32
1135 #define ASC_SCSIQ_HOST_STATUS 33
1136 #define ASC_SCSIQ_SCSI_STATUS 34
1137 #define ASC_SCSIQ_CDB_BEG 36
1138 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1139 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1140 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1141 #define ASC_SCSIQ_B_SG_WK_QP 49
1142 #define ASC_SCSIQ_B_SG_WK_IX 50
1143 #define ASC_SCSIQ_W_ALT_DC1 52
1144 #define ASC_SCSIQ_B_LIST_CNT 6
1145 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
1146 #define ASC_SGQ_B_SG_CNTL 4
1147 #define ASC_SGQ_B_SG_HEAD_QP 5
1148 #define ASC_SGQ_B_SG_LIST_CNT 6
1149 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1150 #define ASC_SGQ_LIST_BEG 8
1151 #define ASC_DEF_SCSI1_QNG 4
1152 #define ASC_MAX_SCSI1_QNG 4
1153 #define ASC_DEF_SCSI2_QNG 16
1154 #define ASC_MAX_SCSI2_QNG 32
1155 #define ASC_TAG_CODE_MASK 0x23
1156 #define ASC_STOP_REQ_RISC_STOP 0x01
1157 #define ASC_STOP_ACK_RISC_STOP 0x03
1158 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1159 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1160 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1161 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1162 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1163 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1164 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1165 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1166 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1167 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1169 typedef struct asc_scsiq_1 {
1176 ASC_PADDR data_addr;
1178 ASC_PADDR sense_addr;
1183 typedef struct asc_scsiq_2 {
1192 typedef struct asc_scsiq_3 {
1199 typedef struct asc_scsiq_4 {
1200 uchar cdb[ASC_MAX_CDB_LEN];
1201 uchar y_first_sg_list_qp;
1202 uchar y_working_sg_qp;
1203 uchar y_working_sg_ix;
1206 ushort x_reconnect_rtn;
1207 ASC_PADDR x_saved_data_addr;
1208 ASC_DCNT x_saved_data_cnt;
1211 typedef struct asc_q_done_info {
1220 ASC_DCNT remain_bytes;
1223 typedef struct asc_sg_list {
1228 typedef struct asc_sg_head {
1231 ushort entry_to_copy;
1233 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1236 #define ASC_MIN_SG_LIST 2
1238 typedef struct asc_min_sg_head {
1241 ushort entry_to_copy;
1243 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1246 #define QCX_SORT (0x0001)
1247 #define QCX_COALEASE (0x0002)
1249 typedef struct asc_scsi_q {
1253 ASC_SG_HEAD *sg_head;
1254 ushort remain_sg_entry_cnt;
1255 ushort next_sg_index;
1258 typedef struct asc_scsi_req_q {
1262 ASC_SG_HEAD *sg_head;
1265 uchar cdb[ASC_MAX_CDB_LEN];
1266 uchar sense[ASC_MIN_SENSE_LEN];
1269 typedef struct asc_scsi_bios_req_q {
1273 ASC_SG_HEAD *sg_head;
1276 uchar cdb[ASC_MAX_CDB_LEN];
1277 uchar sense[ASC_MIN_SENSE_LEN];
1278 } ASC_SCSI_BIOS_REQ_Q;
1280 typedef struct asc_risc_q {
1289 typedef struct asc_sg_list_q {
1295 uchar sg_cur_list_cnt;
1298 typedef struct asc_risc_sg_list_q {
1302 ASC_SG_LIST sg_list[7];
1303 } ASC_RISC_SG_LIST_Q;
1305 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1306 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1307 #define ASCQ_ERR_NO_ERROR 0
1308 #define ASCQ_ERR_IO_NOT_FOUND 1
1309 #define ASCQ_ERR_LOCAL_MEM 2
1310 #define ASCQ_ERR_CHKSUM 3
1311 #define ASCQ_ERR_START_CHIP 4
1312 #define ASCQ_ERR_INT_TARGET_ID 5
1313 #define ASCQ_ERR_INT_LOCAL_MEM 6
1314 #define ASCQ_ERR_HALT_RISC 7
1315 #define ASCQ_ERR_GET_ASPI_ENTRY 8
1316 #define ASCQ_ERR_CLOSE_ASPI 9
1317 #define ASCQ_ERR_HOST_INQUIRY 0x0A
1318 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1319 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1320 #define ASCQ_ERR_Q_STATUS 0x0D
1321 #define ASCQ_ERR_WR_SCSIQ 0x0E
1322 #define ASCQ_ERR_PC_ADDR 0x0F
1323 #define ASCQ_ERR_SYN_OFFSET 0x10
1324 #define ASCQ_ERR_SYN_XFER_TIME 0x11
1325 #define ASCQ_ERR_LOCK_DMA 0x12
1326 #define ASCQ_ERR_UNLOCK_DMA 0x13
1327 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1328 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
1329 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
1330 #define ASCQ_ERR_CUR_QNG 0x17
1331 #define ASCQ_ERR_SG_Q_LINKS 0x18
1332 #define ASCQ_ERR_SCSIQ_PTR 0x19
1333 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1334 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1335 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1336 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1337 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1338 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1339 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1340 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1341 #define ASCQ_ERR_SEND_SCSI_Q 0x22
1342 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1343 #define ASCQ_ERR_RESET_SDTR 0x24
1346 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1348 #define ASC_WARN_NO_ERROR 0x0000
1349 #define ASC_WARN_IO_PORT_ROTATE 0x0001
1350 #define ASC_WARN_EEPROM_CHKSUM 0x0002
1351 #define ASC_WARN_IRQ_MODIFIED 0x0004
1352 #define ASC_WARN_AUTO_CONFIG 0x0008
1353 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1354 #define ASC_WARN_EEPROM_RECOVER 0x0020
1355 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
1356 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1359 * Error code values are set in ASC_DVC_VAR 'err_code'.
1361 #define ASC_IERR_WRITE_EEPROM 0x0001
1362 #define ASC_IERR_MCODE_CHKSUM 0x0002
1363 #define ASC_IERR_SET_PC_ADDR 0x0004
1364 #define ASC_IERR_START_STOP_CHIP 0x0008
1365 #define ASC_IERR_IRQ_NO 0x0010
1366 #define ASC_IERR_SET_IRQ_NO 0x0020
1367 #define ASC_IERR_CHIP_VERSION 0x0040
1368 #define ASC_IERR_SET_SCSI_ID 0x0080
1369 #define ASC_IERR_GET_PHY_ADDR 0x0100
1370 #define ASC_IERR_BAD_SIGNATURE 0x0200
1371 #define ASC_IERR_NO_BUS_TYPE 0x0400
1372 #define ASC_IERR_SCAM 0x0800
1373 #define ASC_IERR_SET_SDTR 0x1000
1374 #define ASC_IERR_RW_LRAM 0x8000
1376 #define ASC_DEF_IRQ_NO 10
1377 #define ASC_MAX_IRQ_NO 15
1378 #define ASC_MIN_IRQ_NO 10
1379 #define ASC_MIN_REMAIN_Q (0x02)
1380 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1381 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
1382 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
1383 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1384 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1385 #define ASC_MAX_TOTAL_QNG 240
1386 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1387 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1388 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1389 #define ASC_MAX_INRAM_TAG_QNG 16
1390 #define ASC_IOADR_TABLE_MAX_IX 11
1391 #define ASC_IOADR_GAP 0x10
1392 #define ASC_SEARCH_IOP_GAP 0x10
1393 #define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1394 #define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1395 #define ASC_IOADR_1 (PortAddr)0x0110
1396 #define ASC_IOADR_2 (PortAddr)0x0130
1397 #define ASC_IOADR_3 (PortAddr)0x0150
1398 #define ASC_IOADR_4 (PortAddr)0x0190
1399 #define ASC_IOADR_5 (PortAddr)0x0210
1400 #define ASC_IOADR_6 (PortAddr)0x0230
1401 #define ASC_IOADR_7 (PortAddr)0x0250
1402 #define ASC_IOADR_8 (PortAddr)0x0330
1403 #define ASC_IOADR_DEF ASC_IOADR_8
1404 #define ASC_LIB_SCSIQ_WK_SP 256
1405 #define ASC_MAX_SYN_XFER_NO 16
1406 #define ASC_SYN_MAX_OFFSET 0x0F
1407 #define ASC_DEF_SDTR_OFFSET 0x0F
1408 #define ASC_DEF_SDTR_INDEX 0x00
1409 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1410 #define SYN_XFER_NS_0 25
1411 #define SYN_XFER_NS_1 30
1412 #define SYN_XFER_NS_2 35
1413 #define SYN_XFER_NS_3 40
1414 #define SYN_XFER_NS_4 50
1415 #define SYN_XFER_NS_5 60
1416 #define SYN_XFER_NS_6 70
1417 #define SYN_XFER_NS_7 85
1418 #define SYN_ULTRA_XFER_NS_0 12
1419 #define SYN_ULTRA_XFER_NS_1 19
1420 #define SYN_ULTRA_XFER_NS_2 25
1421 #define SYN_ULTRA_XFER_NS_3 32
1422 #define SYN_ULTRA_XFER_NS_4 38
1423 #define SYN_ULTRA_XFER_NS_5 44
1424 #define SYN_ULTRA_XFER_NS_6 50
1425 #define SYN_ULTRA_XFER_NS_7 57
1426 #define SYN_ULTRA_XFER_NS_8 63
1427 #define SYN_ULTRA_XFER_NS_9 69
1428 #define SYN_ULTRA_XFER_NS_10 75
1429 #define SYN_ULTRA_XFER_NS_11 82
1430 #define SYN_ULTRA_XFER_NS_12 88
1431 #define SYN_ULTRA_XFER_NS_13 94
1432 #define SYN_ULTRA_XFER_NS_14 100
1433 #define SYN_ULTRA_XFER_NS_15 107
1435 typedef struct ext_msg {
1441 uchar sdtr_xfer_period;
1442 uchar sdtr_req_ack_offset;
1457 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1458 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1459 #define wdtr_width u_ext_msg.wdtr.wdtr_width
1460 #define mdp_b3 u_ext_msg.mdp_b3
1461 #define mdp_b2 u_ext_msg.mdp_b2
1462 #define mdp_b1 u_ext_msg.mdp_b1
1463 #define mdp_b0 u_ext_msg.mdp_b0
1465 typedef struct asc_dvc_cfg {
1466 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1467 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1468 ASC_SCSI_BIT_ID_TYPE disc_enable;
1469 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1471 uchar isa_dma_speed;
1472 uchar isa_dma_channel;
1474 ushort lib_serial_no;
1477 ushort mcode_version;
1478 uchar max_tag_qng[ASC_MAX_TID + 1];
1480 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1481 ushort pci_slot_info;
1482 uchar adapter_info[6];
1486 #define ASC_DEF_DVC_CNTL 0xFFFF
1487 #define ASC_DEF_CHIP_SCSI_ID 7
1488 #define ASC_DEF_ISA_DMA_SPEED 4
1489 #define ASC_INIT_STATE_NULL 0x0000
1490 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1491 #define ASC_INIT_STATE_END_GET_CFG 0x0002
1492 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1493 #define ASC_INIT_STATE_END_SET_CFG 0x0008
1494 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1495 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
1496 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1497 #define ASC_INIT_STATE_END_INQUIRY 0x0080
1498 #define ASC_INIT_RESET_SCSI_DONE 0x0100
1499 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1500 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1501 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1502 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1503 #define ASC_MIN_TAGGED_CMD 7
1504 #define ASC_MAX_SCSI_RESET_WAIT 30
1506 struct asc_dvc_var; /* Forward Declaration. */
1508 typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
1509 typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
1511 typedef struct asc_dvc_var {
1515 ushort bug_fix_cntl;
1517 ASC_ISR_CALLBACK isr_callback;
1518 ASC_EXE_CALLBACK exe_callback;
1519 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1520 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1521 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1522 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1523 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1524 ASC_SCSI_BIT_ID_TYPE start_motor;
1525 uchar scsi_reset_wait;
1528 uchar max_total_qng;
1529 uchar cur_total_qng;
1530 uchar in_critical_cnt;
1532 uchar last_q_shortage;
1534 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1535 uchar max_dvc_qng[ASC_MAX_TID + 1];
1536 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1537 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1538 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1540 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1543 uchar dos_int13_table[ASC_MAX_TID + 1];
1544 ASC_DCNT max_dma_count;
1545 ASC_SCSI_BIT_ID_TYPE no_scam;
1546 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1547 uchar max_sdtr_index;
1548 uchar host_init_sdtr_index;
1549 struct asc_board *drv_ptr;
1553 typedef struct asc_dvc_inq_info {
1554 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1557 typedef struct asc_cap_info {
1562 typedef struct asc_cap_info_array {
1563 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1564 } ASC_CAP_INFO_ARRAY;
1566 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1567 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1568 #define ASC_CNTL_INITIATOR (ushort)0x0001
1569 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1570 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1571 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1572 #define ASC_CNTL_NO_SCAM (ushort)0x0010
1573 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1574 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1575 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1576 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
1577 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1578 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1579 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1580 #define ASC_CNTL_BURST_MODE (ushort)0x2000
1581 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1582 #define ASC_EEP_DVC_CFG_BEG_VL 2
1583 #define ASC_EEP_MAX_DVC_ADDR_VL 15
1584 #define ASC_EEP_DVC_CFG_BEG 32
1585 #define ASC_EEP_MAX_DVC_ADDR 45
1586 #define ASC_EEP_DEFINED_WORDS 10
1587 #define ASC_EEP_MAX_ADDR 63
1588 #define ASC_EEP_RES_WORDS 0
1589 #define ASC_EEP_MAX_RETRY 20
1590 #define ASC_MAX_INIT_BUSY_RETRY 8
1591 #define ASC_EEP_ISA_PNP_WSIZE 16
1594 * These macros keep the chip SCSI id and ISA DMA speed
1595 * bitfields in board order. C bitfields aren't portable
1596 * between big and little-endian platforms so they are
1600 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1601 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1602 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1603 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1604 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1605 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1607 typedef struct asceep_config {
1614 uchar max_total_qng;
1617 uchar power_up_wait;
1619 uchar id_speed; /* low order 4 bits is chip scsi id */
1620 /* high order 4 bits is isa dma speed */
1621 uchar dos_int13_table[ASC_MAX_TID + 1];
1622 uchar adapter_info[6];
1627 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1628 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1629 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1631 #define ASC_EEP_CMD_READ 0x80
1632 #define ASC_EEP_CMD_WRITE 0x40
1633 #define ASC_EEP_CMD_WRITE_ABLE 0x30
1634 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1635 #define ASC_OVERRUN_BSIZE 0x00000048UL
1636 #define ASC_CTRL_BREAK_ONCE 0x0001
1637 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1638 #define ASCV_MSGOUT_BEG 0x0000
1639 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1640 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1641 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1642 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1643 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1644 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1645 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1646 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1647 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1648 #define ASCV_BREAK_ADDR (ushort)0x0028
1649 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1650 #define ASCV_BREAK_CONTROL (ushort)0x002C
1651 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1653 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1654 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1655 #define ASCV_MCODE_SIZE_W (ushort)0x0034
1656 #define ASCV_STOP_CODE_B (ushort)0x0036
1657 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1658 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1659 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1660 #define ASCV_HALTCODE_W (ushort)0x0040
1661 #define ASCV_CHKSUM_W (ushort)0x0042
1662 #define ASCV_MC_DATE_W (ushort)0x0044
1663 #define ASCV_MC_VER_W (ushort)0x0046
1664 #define ASCV_NEXTRDY_B (ushort)0x0048
1665 #define ASCV_DONENEXT_B (ushort)0x0049
1666 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1667 #define ASCV_SCSIBUSY_B (ushort)0x004B
1668 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1669 #define ASCV_CURCDB_B (ushort)0x004D
1670 #define ASCV_RCLUN_B (ushort)0x004E
1671 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
1672 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
1673 #define ASCV_DISC_ENABLE_B (ushort)0x0052
1674 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1675 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1676 #define ASCV_MCODE_CNTL_B (ushort)0x0056
1677 #define ASCV_NULL_TARGET_B (ushort)0x0057
1678 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1679 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1680 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1681 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1682 #define ASCV_HOST_FLAG_B (ushort)0x005D
1683 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1684 #define ASCV_VER_SERIAL_B (ushort)0x0065
1685 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1686 #define ASCV_WTM_FLAG_B (ushort)0x0068
1687 #define ASCV_RISC_FLAG_B (ushort)0x006A
1688 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1689 #define ASC_HOST_FLAG_IN_ISR 0x01
1690 #define ASC_HOST_FLAG_ACK_INT 0x02
1691 #define ASC_RISC_FLAG_GEN_INT 0x01
1692 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1693 #define IOP_CTRL (0x0F)
1694 #define IOP_STATUS (0x0E)
1695 #define IOP_INT_ACK IOP_STATUS
1696 #define IOP_REG_IFC (0x0D)
1697 #define IOP_SYN_OFFSET (0x0B)
1698 #define IOP_EXTRA_CONTROL (0x0D)
1699 #define IOP_REG_PC (0x0C)
1700 #define IOP_RAM_ADDR (0x0A)
1701 #define IOP_RAM_DATA (0x08)
1702 #define IOP_EEP_DATA (0x06)
1703 #define IOP_EEP_CMD (0x07)
1704 #define IOP_VERSION (0x03)
1705 #define IOP_CONFIG_HIGH (0x04)
1706 #define IOP_CONFIG_LOW (0x02)
1707 #define IOP_SIG_BYTE (0x01)
1708 #define IOP_SIG_WORD (0x00)
1709 #define IOP_REG_DC1 (0x0E)
1710 #define IOP_REG_DC0 (0x0C)
1711 #define IOP_REG_SB (0x0B)
1712 #define IOP_REG_DA1 (0x0A)
1713 #define IOP_REG_DA0 (0x08)
1714 #define IOP_REG_SC (0x09)
1715 #define IOP_DMA_SPEED (0x07)
1716 #define IOP_REG_FLAG (0x07)
1717 #define IOP_FIFO_H (0x06)
1718 #define IOP_FIFO_L (0x04)
1719 #define IOP_REG_ID (0x05)
1720 #define IOP_REG_QP (0x03)
1721 #define IOP_REG_IH (0x02)
1722 #define IOP_REG_IX (0x01)
1723 #define IOP_REG_AX (0x00)
1724 #define IFC_REG_LOCK (0x00)
1725 #define IFC_REG_UNLOCK (0x09)
1726 #define IFC_WR_EN_FILTER (0x10)
1727 #define IFC_RD_NO_EEPROM (0x10)
1728 #define IFC_SLEW_RATE (0x20)
1729 #define IFC_ACT_NEG (0x40)
1730 #define IFC_INP_FILTER (0x80)
1731 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1732 #define SC_SEL (uchar)(0x80)
1733 #define SC_BSY (uchar)(0x40)
1734 #define SC_ACK (uchar)(0x20)
1735 #define SC_REQ (uchar)(0x10)
1736 #define SC_ATN (uchar)(0x08)
1737 #define SC_IO (uchar)(0x04)
1738 #define SC_CD (uchar)(0x02)
1739 #define SC_MSG (uchar)(0x01)
1740 #define SEC_SCSI_CTL (uchar)(0x80)
1741 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
1742 #define SEC_SLEW_RATE (uchar)(0x20)
1743 #define SEC_ENABLE_FILTER (uchar)(0x10)
1744 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
1745 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
1746 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1747 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1748 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1749 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1750 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1751 #define ASC_MAX_QNO 0xF8
1752 #define ASC_DATA_SEC_BEG (ushort)0x0080
1753 #define ASC_DATA_SEC_END (ushort)0x0080
1754 #define ASC_CODE_SEC_BEG (ushort)0x0080
1755 #define ASC_CODE_SEC_END (ushort)0x0080
1756 #define ASC_QADR_BEG (0x4000)
1757 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1758 #define ASC_QADR_END (ushort)0x7FFF
1759 #define ASC_QLAST_ADR (ushort)0x7FC0
1760 #define ASC_QBLK_SIZE 0x40
1761 #define ASC_BIOS_DATA_QBEG 0xF8
1762 #define ASC_MIN_ACTIVE_QNO 0x01
1763 #define ASC_QLINK_END 0xFF
1764 #define ASC_EEPROM_WORDS 0x10
1765 #define ASC_MAX_MGS_LEN 0x10
1766 #define ASC_BIOS_ADDR_DEF 0xDC00
1767 #define ASC_BIOS_SIZE 0x3800
1768 #define ASC_BIOS_RAM_OFF 0x3800
1769 #define ASC_BIOS_RAM_SIZE 0x800
1770 #define ASC_BIOS_MIN_ADDR 0xC000
1771 #define ASC_BIOS_MAX_ADDR 0xEC00
1772 #define ASC_BIOS_BANK_SIZE 0x0400
1773 #define ASC_MCODE_START_ADDR 0x0080
1774 #define ASC_CFG0_HOST_INT_ON 0x0020
1775 #define ASC_CFG0_BIOS_ON 0x0040
1776 #define ASC_CFG0_VERA_BURST_ON 0x0080
1777 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1778 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1779 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1780 #define ASC_CFG_MSW_CLR_MASK 0x3080
1781 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
1782 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1783 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1784 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1785 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1786 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
1787 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
1788 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1789 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1790 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1791 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1792 #define CSW_HALTED (ASC_CS_TYPE)0x0010
1793 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1794 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1795 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1796 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1797 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1798 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1799 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
1800 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
1801 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1802 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1803 #define CC_CHIP_RESET (uchar)0x80
1804 #define CC_SCSI_RESET (uchar)0x40
1805 #define CC_HALT (uchar)0x20
1806 #define CC_SINGLE_STEP (uchar)0x10
1807 #define CC_DMA_ABLE (uchar)0x08
1808 #define CC_TEST (uchar)0x04
1809 #define CC_BANK_ONE (uchar)0x02
1810 #define CC_DIAG (uchar)0x01
1811 #define ASC_1000_ID0W 0x04C1
1812 #define ASC_1000_ID0W_FIX 0x00C1
1813 #define ASC_1000_ID1B 0x25
1814 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1815 #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1816 #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1817 #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1818 #define ASC_EISA_REV_IOP_MASK (0x0C83)
1819 #define ASC_EISA_PID_IOP_MASK (0x0C80)
1820 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1821 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1822 #define ASC_EISA_ID_740 0x01745004UL
1823 #define ASC_EISA_ID_750 0x01755004UL
1824 #define INS_HALTINT (ushort)0x6281
1825 #define INS_HALT (ushort)0x6280
1826 #define INS_SINT (ushort)0x6200
1827 #define INS_RFLAG_WTM (ushort)0x7380
1828 #define ASC_MC_SAVE_CODE_WSIZE 0x500
1829 #define ASC_MC_SAVE_DATA_WSIZE 0x40
1831 typedef struct asc_mc_saved {
1832 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1833 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1836 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1837 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1838 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1839 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1840 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1841 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1842 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1843 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1844 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1845 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1846 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1847 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1848 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1849 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1850 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1851 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1852 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1853 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1854 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1855 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1856 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1857 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1858 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1859 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1860 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1861 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1862 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1863 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1864 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1865 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1866 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1867 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1868 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1869 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1870 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1871 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1872 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1873 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1874 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1875 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1876 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1877 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1878 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1879 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1880 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1881 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1882 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1883 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1884 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1885 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1886 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1887 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1888 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1889 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1890 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1891 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1892 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1893 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1894 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1895 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1896 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1897 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1898 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1899 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1900 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1901 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1902 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1903 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1905 STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1906 STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1907 STATIC void AscWaitEEPRead(void);
1908 STATIC void AscWaitEEPWrite(void);
1909 STATIC ushort AscReadEEPWord(PortAddr, uchar);
1910 STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1911 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1912 STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1913 STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1914 STATIC int AscStartChip(PortAddr);
1915 STATIC int AscStopChip(PortAddr);
1916 STATIC void AscSetChipIH(PortAddr, ushort);
1917 STATIC int AscIsChipHalted(PortAddr);
1918 STATIC void AscAckInterrupt(PortAddr);
1919 STATIC void AscDisableInterrupt(PortAddr);
1920 STATIC void AscEnableInterrupt(PortAddr);
1921 STATIC void AscSetBank(PortAddr, uchar);
1922 STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1924 STATIC ushort AscGetIsaDmaChannel(PortAddr);
1925 STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
1926 STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1927 STATIC uchar AscGetIsaDmaSpeed(PortAddr);
1928 #endif /* CONFIG_ISA */
1929 STATIC uchar AscReadLramByte(PortAddr, ushort);
1930 STATIC ushort AscReadLramWord(PortAddr, ushort);
1931 #if CC_VERY_LONG_SG_LIST
1932 STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1933 #endif /* CC_VERY_LONG_SG_LIST */
1934 STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
1935 STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
1936 STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1937 STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1938 STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1939 STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1940 STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1941 STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1942 STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
1943 STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1944 STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1945 STATIC int AscTestExternalLram(ASC_DVC_VAR *);
1946 STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1947 STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1948 STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
1949 STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1950 STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
1951 STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1952 STATIC int AscHostReqRiscHalt(PortAddr);
1953 STATIC int AscStopQueueExe(PortAddr);
1954 STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
1956 uchar n_q_required);
1957 STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
1958 ASC_SCSI_Q *, uchar);
1959 STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
1960 ASC_SCSI_Q *, uchar);
1961 STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1962 STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1963 STATIC ushort AscInitLram(ASC_DVC_VAR *);
1964 STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
1965 STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1966 STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
1967 STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1968 ASC_QDONE_INFO *, ASC_DCNT);
1969 STATIC int AscIsrQDone(ASC_DVC_VAR *);
1970 STATIC int AscCompareString(uchar *, uchar *, int);
1972 STATIC ushort AscGetEisaChipCfg(PortAddr);
1973 STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
1974 STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
1975 STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
1976 STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1977 STATIC void AscSetISAPNPWaitForKey(void);
1978 #endif /* CONFIG_ISA */
1979 STATIC uchar AscGetChipScsiCtrl(PortAddr);
1980 STATIC uchar AscSetChipScsiID(PortAddr, uchar);
1981 STATIC uchar AscGetChipVersion(PortAddr, ushort);
1982 STATIC ushort AscGetChipBusType(PortAddr);
1983 STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1984 STATIC int AscFindSignature(PortAddr);
1985 STATIC void AscToggleIRQAct(PortAddr);
1986 STATIC uchar AscGetChipIRQ(PortAddr, ushort);
1987 STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1988 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1989 STATIC inline ulong DvcEnterCritical(void);
1990 STATIC inline void DvcLeaveCritical(ulong);
1992 STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
1993 STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
1995 #endif /* CONFIG_PCI */
1996 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1997 STATIC void DvcSleepMilliSecond(ASC_DCNT);
1998 STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
1999 STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
2000 STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
2001 STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
2002 STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
2003 STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
2004 STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
2005 ASC_SCSI_INQUIRY *);
2006 STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
2007 STATIC void AscInquiryHandling(ASC_DVC_VAR *,
2008 uchar, ASC_SCSI_INQUIRY *);
2009 STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
2010 STATIC int AscISR(ASC_DVC_VAR *);
2011 STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
2013 STATIC int AscSgListToQueue(int);
2015 STATIC void AscEnableIsaDma(uchar);
2016 #endif /* CONFIG_ISA */
2017 STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
2021 * --- Adv Library Constants and Macros
2024 #define ADV_LIB_VERSION_MAJOR 5
2025 #define ADV_LIB_VERSION_MINOR 14
2028 * Define Adv Library required special types.
2032 * Portable Data Types
2034 * Any instance where a 32-bit long or pointer type is assumed
2035 * for precision or HW defined structures, the following define
2036 * types must be used. In Linux the char, short, and int types
2037 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2038 * and long types are 64 bits on Alpha and UltraSPARC.
2040 #define ADV_PADDR __u32 /* Physical address data type. */
2041 #define ADV_VADDR __u32 /* Virtual address data type. */
2042 #define ADV_DCNT __u32 /* Unsigned Data count type. */
2043 #define ADV_SDCNT __s32 /* Signed Data count type. */
2046 * These macros are used to convert a virtual address to a
2047 * 32-bit value. This currently can be used on Linux Alpha
2048 * which uses 64-bit virtual address but a 32-bit bus address.
2049 * This is likely to break in the future, but doing this now
2050 * will give us time to change the HW and FW to handle 64-bit
2053 #define ADV_VADDR_TO_U32 virt_to_bus
2054 #define ADV_U32_TO_VADDR bus_to_virt
2056 #define AdvPortAddr void __iomem * /* Virtual memory address size */
2059 * Define Adv Library required memory access macros.
2061 #define ADV_MEM_READB(addr) readb(addr)
2062 #define ADV_MEM_READW(addr) readw(addr)
2063 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2064 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2065 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2067 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2070 * For wide boards a CDB length maximum of 16 bytes
2073 #define ADV_MAX_CDB_LEN 16
2076 * Define total number of simultaneous maximum element scatter-gather
2077 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2078 * maximum number of outstanding commands per wide host adapter. Each
2079 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2080 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2081 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2082 * structures or 255 scatter-gather elements.
2085 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2088 * Define Adv Library required maximum number of scatter-gather
2089 * elements per request.
2091 #define ADV_MAX_SG_LIST 255
2093 /* Number of SG blocks needed. */
2094 #define ADV_NUM_SG_BLOCK \
2095 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2097 /* Total contiguous memory needed for SG blocks. */
2098 #define ADV_SG_TOTAL_MEM_SIZE \
2099 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2101 #define ADV_PAGE_SIZE PAGE_SIZE
2103 #define ADV_NUM_PAGE_CROSSING \
2104 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2106 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
2107 #define ADV_EEP_DVC_CFG_END (0x15)
2108 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2109 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
2111 #define ADV_EEP_DELAY_MS 100
2113 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2114 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2116 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2117 * For later ICs Bit 13 controls whether the CIS (Card Information
2118 * Service Section) is loaded from EEPROM.
2120 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2121 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2125 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2126 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2127 * Function 0 will specify INT B.
2129 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2130 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2131 * Function 1 will specify INT A.
2133 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2135 typedef struct adveep_3550_config
2137 /* Word Offset, Description */
2139 ushort cfg_lsw; /* 00 power up initialization */
2140 /* bit 13 set - Term Polarity Control */
2141 /* bit 14 set - BIOS Enable */
2142 /* bit 15 set - Big Endian Mode */
2143 ushort cfg_msw; /* 01 unused */
2144 ushort disc_enable; /* 02 disconnect enable */
2145 ushort wdtr_able; /* 03 Wide DTR able */
2146 ushort sdtr_able; /* 04 Synchronous DTR able */
2147 ushort start_motor; /* 05 send start up motor */
2148 ushort tagqng_able; /* 06 tag queuing able */
2149 ushort bios_scan; /* 07 BIOS device control */
2150 ushort scam_tolerant; /* 08 no scam */
2152 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2153 uchar bios_boot_delay; /* power up wait */
2155 uchar scsi_reset_delay; /* 10 reset delay */
2156 uchar bios_id_lun; /* first boot device scsi id & lun */
2157 /* high nibble is lun */
2158 /* low nibble is scsi id */
2160 uchar termination; /* 11 0 - automatic */
2161 /* 1 - low off / high off */
2162 /* 2 - low off / high on */
2163 /* 3 - low on / high on */
2164 /* There is no low on / high off */
2166 uchar reserved1; /* reserved byte (not used) */
2168 ushort bios_ctrl; /* 12 BIOS control bits */
2169 /* bit 0 BIOS don't act as initiator. */
2170 /* bit 1 BIOS > 1 GB support */
2171 /* bit 2 BIOS > 2 Disk Support */
2172 /* bit 3 BIOS don't support removables */
2173 /* bit 4 BIOS support bootable CD */
2174 /* bit 5 BIOS scan enabled */
2175 /* bit 6 BIOS support multiple LUNs */
2176 /* bit 7 BIOS display of message */
2177 /* bit 8 SCAM disabled */
2178 /* bit 9 Reset SCSI bus during init. */
2180 /* bit 11 No verbose initialization. */
2181 /* bit 12 SCSI parity enabled */
2185 ushort ultra_able; /* 13 ULTRA speed able */
2186 ushort reserved2; /* 14 reserved */
2187 uchar max_host_qng; /* 15 maximum host queuing */
2188 uchar max_dvc_qng; /* maximum per device queuing */
2189 ushort dvc_cntl; /* 16 control bit for driver */
2190 ushort bug_fix; /* 17 control bit for bug fix */
2191 ushort serial_number_word1; /* 18 Board serial number word 1 */
2192 ushort serial_number_word2; /* 19 Board serial number word 2 */
2193 ushort serial_number_word3; /* 20 Board serial number word 3 */
2194 ushort check_sum; /* 21 EEP check sum */
2195 uchar oem_name[16]; /* 22 OEM name */
2196 ushort dvc_err_code; /* 30 last device driver error code */
2197 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2198 ushort adv_err_addr; /* 32 last uc error address */
2199 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2200 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2201 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2202 ushort num_of_err; /* 36 number of error */
2203 } ADVEEP_3550_CONFIG;
2205 typedef struct adveep_38C0800_config
2207 /* Word Offset, Description */
2209 ushort cfg_lsw; /* 00 power up initialization */
2210 /* bit 13 set - Load CIS */
2211 /* bit 14 set - BIOS Enable */
2212 /* bit 15 set - Big Endian Mode */
2213 ushort cfg_msw; /* 01 unused */
2214 ushort disc_enable; /* 02 disconnect enable */
2215 ushort wdtr_able; /* 03 Wide DTR able */
2216 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2217 ushort start_motor; /* 05 send start up motor */
2218 ushort tagqng_able; /* 06 tag queuing able */
2219 ushort bios_scan; /* 07 BIOS device control */
2220 ushort scam_tolerant; /* 08 no scam */
2222 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2223 uchar bios_boot_delay; /* power up wait */
2225 uchar scsi_reset_delay; /* 10 reset delay */
2226 uchar bios_id_lun; /* first boot device scsi id & lun */
2227 /* high nibble is lun */
2228 /* low nibble is scsi id */
2230 uchar termination_se; /* 11 0 - automatic */
2231 /* 1 - low off / high off */
2232 /* 2 - low off / high on */
2233 /* 3 - low on / high on */
2234 /* There is no low on / high off */
2236 uchar termination_lvd; /* 11 0 - automatic */
2237 /* 1 - low off / high off */
2238 /* 2 - low off / high on */
2239 /* 3 - low on / high on */
2240 /* There is no low on / high off */
2242 ushort bios_ctrl; /* 12 BIOS control bits */
2243 /* bit 0 BIOS don't act as initiator. */
2244 /* bit 1 BIOS > 1 GB support */
2245 /* bit 2 BIOS > 2 Disk Support */
2246 /* bit 3 BIOS don't support removables */
2247 /* bit 4 BIOS support bootable CD */
2248 /* bit 5 BIOS scan enabled */
2249 /* bit 6 BIOS support multiple LUNs */
2250 /* bit 7 BIOS display of message */
2251 /* bit 8 SCAM disabled */
2252 /* bit 9 Reset SCSI bus during init. */
2254 /* bit 11 No verbose initialization. */
2255 /* bit 12 SCSI parity enabled */
2259 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2260 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2261 uchar max_host_qng; /* 15 maximum host queueing */
2262 uchar max_dvc_qng; /* maximum per device queuing */
2263 ushort dvc_cntl; /* 16 control bit for driver */
2264 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2265 ushort serial_number_word1; /* 18 Board serial number word 1 */
2266 ushort serial_number_word2; /* 19 Board serial number word 2 */
2267 ushort serial_number_word3; /* 20 Board serial number word 3 */
2268 ushort check_sum; /* 21 EEP check sum */
2269 uchar oem_name[16]; /* 22 OEM name */
2270 ushort dvc_err_code; /* 30 last device driver error code */
2271 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2272 ushort adv_err_addr; /* 32 last uc error address */
2273 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2274 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2275 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2276 ushort reserved36; /* 36 reserved */
2277 ushort reserved37; /* 37 reserved */
2278 ushort reserved38; /* 38 reserved */
2279 ushort reserved39; /* 39 reserved */
2280 ushort reserved40; /* 40 reserved */
2281 ushort reserved41; /* 41 reserved */
2282 ushort reserved42; /* 42 reserved */
2283 ushort reserved43; /* 43 reserved */
2284 ushort reserved44; /* 44 reserved */
2285 ushort reserved45; /* 45 reserved */
2286 ushort reserved46; /* 46 reserved */
2287 ushort reserved47; /* 47 reserved */
2288 ushort reserved48; /* 48 reserved */
2289 ushort reserved49; /* 49 reserved */
2290 ushort reserved50; /* 50 reserved */
2291 ushort reserved51; /* 51 reserved */
2292 ushort reserved52; /* 52 reserved */
2293 ushort reserved53; /* 53 reserved */
2294 ushort reserved54; /* 54 reserved */
2295 ushort reserved55; /* 55 reserved */
2296 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2297 ushort cisprt_msw; /* 57 CIS PTR MSW */
2298 ushort subsysvid; /* 58 SubSystem Vendor ID */
2299 ushort subsysid; /* 59 SubSystem ID */
2300 ushort reserved60; /* 60 reserved */
2301 ushort reserved61; /* 61 reserved */
2302 ushort reserved62; /* 62 reserved */
2303 ushort reserved63; /* 63 reserved */
2304 } ADVEEP_38C0800_CONFIG;
2306 typedef struct adveep_38C1600_config
2308 /* Word Offset, Description */
2310 ushort cfg_lsw; /* 00 power up initialization */
2311 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2312 /* clear - Func. 0 INTA, Func. 1 INTB */
2313 /* bit 13 set - Load CIS */
2314 /* bit 14 set - BIOS Enable */
2315 /* bit 15 set - Big Endian Mode */
2316 ushort cfg_msw; /* 01 unused */
2317 ushort disc_enable; /* 02 disconnect enable */
2318 ushort wdtr_able; /* 03 Wide DTR able */
2319 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2320 ushort start_motor; /* 05 send start up motor */
2321 ushort tagqng_able; /* 06 tag queuing able */
2322 ushort bios_scan; /* 07 BIOS device control */
2323 ushort scam_tolerant; /* 08 no scam */
2325 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2326 uchar bios_boot_delay; /* power up wait */
2328 uchar scsi_reset_delay; /* 10 reset delay */
2329 uchar bios_id_lun; /* first boot device scsi id & lun */
2330 /* high nibble is lun */
2331 /* low nibble is scsi id */
2333 uchar termination_se; /* 11 0 - automatic */
2334 /* 1 - low off / high off */
2335 /* 2 - low off / high on */
2336 /* 3 - low on / high on */
2337 /* There is no low on / high off */
2339 uchar termination_lvd; /* 11 0 - automatic */
2340 /* 1 - low off / high off */
2341 /* 2 - low off / high on */
2342 /* 3 - low on / high on */
2343 /* There is no low on / high off */
2345 ushort bios_ctrl; /* 12 BIOS control bits */
2346 /* bit 0 BIOS don't act as initiator. */
2347 /* bit 1 BIOS > 1 GB support */
2348 /* bit 2 BIOS > 2 Disk Support */
2349 /* bit 3 BIOS don't support removables */
2350 /* bit 4 BIOS support bootable CD */
2351 /* bit 5 BIOS scan enabled */
2352 /* bit 6 BIOS support multiple LUNs */
2353 /* bit 7 BIOS display of message */
2354 /* bit 8 SCAM disabled */
2355 /* bit 9 Reset SCSI bus during init. */
2356 /* bit 10 Basic Integrity Checking disabled */
2357 /* bit 11 No verbose initialization. */
2358 /* bit 12 SCSI parity enabled */
2359 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2362 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2363 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2364 uchar max_host_qng; /* 15 maximum host queueing */
2365 uchar max_dvc_qng; /* maximum per device queuing */
2366 ushort dvc_cntl; /* 16 control bit for driver */
2367 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2368 ushort serial_number_word1; /* 18 Board serial number word 1 */
2369 ushort serial_number_word2; /* 19 Board serial number word 2 */
2370 ushort serial_number_word3; /* 20 Board serial number word 3 */
2371 ushort check_sum; /* 21 EEP check sum */
2372 uchar oem_name[16]; /* 22 OEM name */
2373 ushort dvc_err_code; /* 30 last device driver error code */
2374 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2375 ushort adv_err_addr; /* 32 last uc error address */
2376 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2377 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2378 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2379 ushort reserved36; /* 36 reserved */
2380 ushort reserved37; /* 37 reserved */
2381 ushort reserved38; /* 38 reserved */
2382 ushort reserved39; /* 39 reserved */
2383 ushort reserved40; /* 40 reserved */
2384 ushort reserved41; /* 41 reserved */
2385 ushort reserved42; /* 42 reserved */
2386 ushort reserved43; /* 43 reserved */
2387 ushort reserved44; /* 44 reserved */
2388 ushort reserved45; /* 45 reserved */
2389 ushort reserved46; /* 46 reserved */
2390 ushort reserved47; /* 47 reserved */
2391 ushort reserved48; /* 48 reserved */
2392 ushort reserved49; /* 49 reserved */
2393 ushort reserved50; /* 50 reserved */
2394 ushort reserved51; /* 51 reserved */
2395 ushort reserved52; /* 52 reserved */
2396 ushort reserved53; /* 53 reserved */
2397 ushort reserved54; /* 54 reserved */
2398 ushort reserved55; /* 55 reserved */
2399 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2400 ushort cisprt_msw; /* 57 CIS PTR MSW */
2401 ushort subsysvid; /* 58 SubSystem Vendor ID */
2402 ushort subsysid; /* 59 SubSystem ID */
2403 ushort reserved60; /* 60 reserved */
2404 ushort reserved61; /* 61 reserved */
2405 ushort reserved62; /* 62 reserved */
2406 ushort reserved63; /* 63 reserved */
2407 } ADVEEP_38C1600_CONFIG;
2412 #define ASC_EEP_CMD_DONE 0x0200
2413 #define ASC_EEP_CMD_DONE_ERR 0x0001
2416 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2419 #define BIOS_CTRL_BIOS 0x0001
2420 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
2421 #define BIOS_CTRL_GT_2_DISK 0x0004
2422 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2423 #define BIOS_CTRL_BOOTABLE_CD 0x0010
2424 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
2425 #define BIOS_CTRL_DISPLAY_MSG 0x0080
2426 #define BIOS_CTRL_NO_SCAM 0x0100
2427 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2428 #define BIOS_CTRL_INIT_VERBOSE 0x0800
2429 #define BIOS_CTRL_SCSI_PARITY 0x1000
2430 #define BIOS_CTRL_AIPP_DIS 0x2000
2432 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2433 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2435 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2436 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2439 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2440 * a special 16K Adv Library and Microcode version. After the issue is
2441 * resolved, should restore 32K support.
2443 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2445 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2446 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2447 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2450 * Byte I/O register address from base of 'iop_base'.
2452 #define IOPB_INTR_STATUS_REG 0x00
2453 #define IOPB_CHIP_ID_1 0x01
2454 #define IOPB_INTR_ENABLES 0x02
2455 #define IOPB_CHIP_TYPE_REV 0x03
2456 #define IOPB_RES_ADDR_4 0x04
2457 #define IOPB_RES_ADDR_5 0x05
2458 #define IOPB_RAM_DATA 0x06
2459 #define IOPB_RES_ADDR_7 0x07
2460 #define IOPB_FLAG_REG 0x08
2461 #define IOPB_RES_ADDR_9 0x09
2462 #define IOPB_RISC_CSR 0x0A
2463 #define IOPB_RES_ADDR_B 0x0B
2464 #define IOPB_RES_ADDR_C 0x0C
2465 #define IOPB_RES_ADDR_D 0x0D
2466 #define IOPB_SOFT_OVER_WR 0x0E
2467 #define IOPB_RES_ADDR_F 0x0F
2468 #define IOPB_MEM_CFG 0x10
2469 #define IOPB_RES_ADDR_11 0x11
2470 #define IOPB_GPIO_DATA 0x12
2471 #define IOPB_RES_ADDR_13 0x13
2472 #define IOPB_FLASH_PAGE 0x14
2473 #define IOPB_RES_ADDR_15 0x15
2474 #define IOPB_GPIO_CNTL 0x16
2475 #define IOPB_RES_ADDR_17 0x17
2476 #define IOPB_FLASH_DATA 0x18
2477 #define IOPB_RES_ADDR_19 0x19
2478 #define IOPB_RES_ADDR_1A 0x1A
2479 #define IOPB_RES_ADDR_1B 0x1B
2480 #define IOPB_RES_ADDR_1C 0x1C
2481 #define IOPB_RES_ADDR_1D 0x1D
2482 #define IOPB_RES_ADDR_1E 0x1E
2483 #define IOPB_RES_ADDR_1F 0x1F
2484 #define IOPB_DMA_CFG0 0x20
2485 #define IOPB_DMA_CFG1 0x21
2486 #define IOPB_TICKLE 0x22
2487 #define IOPB_DMA_REG_WR 0x23
2488 #define IOPB_SDMA_STATUS 0x24
2489 #define IOPB_SCSI_BYTE_CNT 0x25
2490 #define IOPB_HOST_BYTE_CNT 0x26
2491 #define IOPB_BYTE_LEFT_TO_XFER 0x27
2492 #define IOPB_BYTE_TO_XFER_0 0x28
2493 #define IOPB_BYTE_TO_XFER_1 0x29
2494 #define IOPB_BYTE_TO_XFER_2 0x2A
2495 #define IOPB_BYTE_TO_XFER_3 0x2B
2496 #define IOPB_ACC_GRP 0x2C
2497 #define IOPB_RES_ADDR_2D 0x2D
2498 #define IOPB_DEV_ID 0x2E
2499 #define IOPB_RES_ADDR_2F 0x2F
2500 #define IOPB_SCSI_DATA 0x30
2501 #define IOPB_RES_ADDR_31 0x31
2502 #define IOPB_RES_ADDR_32 0x32
2503 #define IOPB_SCSI_DATA_HSHK 0x33
2504 #define IOPB_SCSI_CTRL 0x34
2505 #define IOPB_RES_ADDR_35 0x35
2506 #define IOPB_RES_ADDR_36 0x36
2507 #define IOPB_RES_ADDR_37 0x37
2508 #define IOPB_RAM_BIST 0x38
2509 #define IOPB_PLL_TEST 0x39
2510 #define IOPB_PCI_INT_CFG 0x3A
2511 #define IOPB_RES_ADDR_3B 0x3B
2512 #define IOPB_RFIFO_CNT 0x3C
2513 #define IOPB_RES_ADDR_3D 0x3D
2514 #define IOPB_RES_ADDR_3E 0x3E
2515 #define IOPB_RES_ADDR_3F 0x3F
2518 * Word I/O register address from base of 'iop_base'.
2520 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
2521 #define IOPW_CTRL_REG 0x02 /* CC */
2522 #define IOPW_RAM_ADDR 0x04 /* LA */
2523 #define IOPW_RAM_DATA 0x06 /* LD */
2524 #define IOPW_RES_ADDR_08 0x08
2525 #define IOPW_RISC_CSR 0x0A /* CSR */
2526 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2527 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2528 #define IOPW_RES_ADDR_10 0x10
2529 #define IOPW_SEL_MASK 0x12 /* SM */
2530 #define IOPW_RES_ADDR_14 0x14
2531 #define IOPW_FLASH_ADDR 0x16 /* FA */
2532 #define IOPW_RES_ADDR_18 0x18
2533 #define IOPW_EE_CMD 0x1A /* EC */
2534 #define IOPW_EE_DATA 0x1C /* ED */
2535 #define IOPW_SFIFO_CNT 0x1E /* SFC */
2536 #define IOPW_RES_ADDR_20 0x20
2537 #define IOPW_Q_BASE 0x22 /* QB */
2538 #define IOPW_QP 0x24 /* QP */
2539 #define IOPW_IX 0x26 /* IX */
2540 #define IOPW_SP 0x28 /* SP */
2541 #define IOPW_PC 0x2A /* PC */
2542 #define IOPW_RES_ADDR_2C 0x2C
2543 #define IOPW_RES_ADDR_2E 0x2E
2544 #define IOPW_SCSI_DATA 0x30 /* SD */
2545 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2546 #define IOPW_SCSI_CTRL 0x34 /* SC */
2547 #define IOPW_HSHK_CFG 0x36 /* HCFG */
2548 #define IOPW_SXFR_STATUS 0x36 /* SXS */
2549 #define IOPW_SXFR_CNTL 0x38 /* SXL */
2550 #define IOPW_SXFR_CNTH 0x3A /* SXH */
2551 #define IOPW_RES_ADDR_3C 0x3C
2552 #define IOPW_RFIFO_DATA 0x3E /* RFD */
2555 * Doubleword I/O register address from base of 'iop_base'.
2557 #define IOPDW_RES_ADDR_0 0x00
2558 #define IOPDW_RAM_DATA 0x04
2559 #define IOPDW_RES_ADDR_8 0x08
2560 #define IOPDW_RES_ADDR_C 0x0C
2561 #define IOPDW_RES_ADDR_10 0x10
2562 #define IOPDW_COMMA 0x14
2563 #define IOPDW_COMMB 0x18
2564 #define IOPDW_RES_ADDR_1C 0x1C
2565 #define IOPDW_SDMA_ADDR0 0x20
2566 #define IOPDW_SDMA_ADDR1 0x24
2567 #define IOPDW_SDMA_COUNT 0x28
2568 #define IOPDW_SDMA_ERROR 0x2C
2569 #define IOPDW_RDMA_ADDR0 0x30
2570 #define IOPDW_RDMA_ADDR1 0x34
2571 #define IOPDW_RDMA_COUNT 0x38
2572 #define IOPDW_RDMA_ERROR 0x3C
2574 #define ADV_CHIP_ID_BYTE 0x25
2575 #define ADV_CHIP_ID_WORD 0x04C1
2577 #define ADV_SC_SCSI_BUS_RESET 0x2000
2579 #define ADV_INTR_ENABLE_HOST_INTR 0x01
2580 #define ADV_INTR_ENABLE_SEL_INTR 0x02
2581 #define ADV_INTR_ENABLE_DPR_INTR 0x04
2582 #define ADV_INTR_ENABLE_RTA_INTR 0x08
2583 #define ADV_INTR_ENABLE_RMA_INTR 0x10
2584 #define ADV_INTR_ENABLE_RST_INTR 0x20
2585 #define ADV_INTR_ENABLE_DPE_INTR 0x40
2586 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2588 #define ADV_INTR_STATUS_INTRA 0x01
2589 #define ADV_INTR_STATUS_INTRB 0x02
2590 #define ADV_INTR_STATUS_INTRC 0x04
2592 #define ADV_RISC_CSR_STOP (0x0000)
2593 #define ADV_RISC_TEST_COND (0x2000)
2594 #define ADV_RISC_CSR_RUN (0x4000)
2595 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2597 #define ADV_CTRL_REG_HOST_INTR 0x0100
2598 #define ADV_CTRL_REG_SEL_INTR 0x0200
2599 #define ADV_CTRL_REG_DPR_INTR 0x0400
2600 #define ADV_CTRL_REG_RTA_INTR 0x0800
2601 #define ADV_CTRL_REG_RMA_INTR 0x1000
2602 #define ADV_CTRL_REG_RES_BIT14 0x2000
2603 #define ADV_CTRL_REG_DPE_INTR 0x4000
2604 #define ADV_CTRL_REG_POWER_DONE 0x8000
2605 #define ADV_CTRL_REG_ANY_INTR 0xFF00
2607 #define ADV_CTRL_REG_CMD_RESET 0x00C6
2608 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2609 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2610 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2611 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2613 #define ADV_TICKLE_NOP 0x00
2614 #define ADV_TICKLE_A 0x01
2615 #define ADV_TICKLE_B 0x02
2616 #define ADV_TICKLE_C 0x03
2618 #define ADV_SCSI_CTRL_RSTOUT 0x2000
2620 #define AdvIsIntPending(port) \
2621 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2624 * SCSI_CFG0 Register bit definitions
2626 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2627 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2628 #define EVEN_PARITY 0x1000 /* Select Even Parity */
2629 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2630 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2631 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2632 #define SCAM_EN 0x0080 /* Enable SCAM selection */
2633 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2634 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2635 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2636 #define OUR_ID 0x000F /* SCSI ID */
2639 * SCSI_CFG1 Register bit definitions
2641 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2642 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2643 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2644 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
2645 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2646 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2647 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2648 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2649 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2650 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2651 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2652 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2653 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2654 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2655 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2658 * Addendum for ASC-38C0800 Chip
2660 * The ASC-38C1600 Chip uses the same definitions except that the
2661 * bus mode override bits [12:10] have been moved to byte register
2662 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2663 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2664 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2665 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2666 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2668 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2669 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2670 #define HVD 0x1000 /* HVD Device Detect */
2671 #define LVD 0x0800 /* LVD Device Detect */
2672 #define SE 0x0400 /* SE Device Detect */
2673 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
2674 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2675 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2676 #define TERM_SE 0x0030 /* SE Termination Bits */
2677 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2678 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2679 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2680 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2681 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2682 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2683 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2684 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2687 #define CABLE_ILLEGAL_A 0x7
2688 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2690 #define CABLE_ILLEGAL_B 0xB
2691 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2694 * MEM_CFG Register bit definitions
2696 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2697 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2698 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2699 #define RAM_SZ_2KB 0x00 /* 2 KB */
2700 #define RAM_SZ_4KB 0x04 /* 4 KB */
2701 #define RAM_SZ_8KB 0x08 /* 8 KB */
2702 #define RAM_SZ_16KB 0x0C /* 16 KB */
2703 #define RAM_SZ_32KB 0x10 /* 32 KB */
2704 #define RAM_SZ_64KB 0x14 /* 64 KB */
2707 * DMA_CFG0 Register bit definitions
2709 * This register is only accessible to the host.
2711 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2712 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2713 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
2714 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
2715 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
2716 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
2717 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2718 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
2719 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
2720 #define START_CTL 0x0C /* DMA start conditions */
2721 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
2722 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2723 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2724 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2725 #define READ_CMD 0x03 /* Memory Read Method */
2726 #define READ_CMD_MR 0x00 /* Memory Read */
2727 #define READ_CMD_MRL 0x02 /* Memory Read Long */
2728 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2731 * ASC-38C0800 RAM BIST Register bit definitions
2733 #define RAM_TEST_MODE 0x80
2734 #define PRE_TEST_MODE 0x40
2735 #define NORMAL_MODE 0x00
2736 #define RAM_TEST_DONE 0x10
2737 #define RAM_TEST_STATUS 0x0F
2738 #define RAM_TEST_HOST_ERROR 0x08
2739 #define RAM_TEST_INTRAM_ERROR 0x04
2740 #define RAM_TEST_RISC_ERROR 0x02
2741 #define RAM_TEST_SCSI_ERROR 0x01
2742 #define RAM_TEST_SUCCESS 0x00
2743 #define PRE_TEST_VALUE 0x05
2744 #define NORMAL_VALUE 0x00
2747 * ASC38C1600 Definitions
2749 * IOPB_PCI_INT_CFG Bit Field Definitions
2752 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2755 * Bit 1 can be set to change the interrupt for the Function to operate in
2756 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2757 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2758 * mode, otherwise the operating mode is undefined.
2760 #define TOTEMPOLE 0x02
2763 * Bit 0 can be used to change the Int Pin for the Function. The value is
2764 * 0 by default for both Functions with Function 0 using INT A and Function
2765 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2768 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2769 * value specified in the PCI Configuration Space.
2776 * Adv Library Status Definitions
2780 #define ADV_NOERROR 1
2781 #define ADV_SUCCESS 1
2783 #define ADV_ERROR (-1)
2787 * ADV_DVC_VAR 'warn_code' values
2789 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2790 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2791 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2792 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2793 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2795 #define ADV_MAX_TID 15 /* max. target identifier */
2796 #define ADV_MAX_LUN 7 /* max. logical unit number */
2799 * Error code values are set in ADV_DVC_VAR 'err_code'.
2801 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2802 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2803 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2804 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2805 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2806 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2807 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2808 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2809 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2810 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2811 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2812 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2813 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2814 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2817 * Fixed locations of microcode operating variables.
2819 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2820 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2821 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2822 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2823 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2824 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2825 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2826 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2827 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2828 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2829 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2830 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2831 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2832 #define ASC_MC_CHIP_TYPE 0x009A
2833 #define ASC_MC_INTRB_CODE 0x009B
2834 #define ASC_MC_WDTR_ABLE 0x009C
2835 #define ASC_MC_SDTR_ABLE 0x009E
2836 #define ASC_MC_TAGQNG_ABLE 0x00A0
2837 #define ASC_MC_DISC_ENABLE 0x00A2
2838 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
2839 #define ASC_MC_IDLE_CMD 0x00A6
2840 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2841 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2842 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2843 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2844 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2845 #define ASC_MC_SDTR_DONE 0x00B6
2846 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2847 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2848 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2849 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2850 #define ASC_MC_WDTR_DONE 0x0124
2851 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2852 #define ASC_MC_ICQ 0x0160
2853 #define ASC_MC_IRQ 0x0164
2854 #define ASC_MC_PPR_ABLE 0x017A
2857 * BIOS LRAM variable absolute offsets.
2859 #define BIOS_CODESEG 0x54
2860 #define BIOS_CODELEN 0x56
2861 #define BIOS_SIGNATURE 0x58
2862 #define BIOS_VERSION 0x5A
2865 * Microcode Control Flags
2867 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2868 * and handled by the microcode.
2870 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2871 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2874 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2876 #define HSHK_CFG_WIDE_XFR 0x8000
2877 #define HSHK_CFG_RATE 0x0F00
2878 #define HSHK_CFG_OFFSET 0x001F
2880 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2881 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2882 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2883 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2885 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2886 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2887 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2888 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2889 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2891 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2892 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2893 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2894 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2895 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2897 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2898 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2900 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2901 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2904 * All fields here are accessed by the board microcode and need to be
2907 typedef struct adv_carr_t
2909 ADV_VADDR carr_va; /* Carrier Virtual Address */
2910 ADV_PADDR carr_pa; /* Carrier Physical Address */
2911 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2913 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2915 * next_vpa [3:1] Reserved Bits
2916 * next_vpa [0] Done Flag set in Response Queue.
2922 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2924 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2926 #define ASC_RQ_DONE 0x00000001
2927 #define ASC_RQ_GOOD 0x00000002
2928 #define ASC_CQ_STOPPER 0x00000000
2930 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2932 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2933 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2934 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2936 #define ADV_CARRIER_BUFSIZE \
2937 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2940 * ASC_SCSI_REQ_Q 'a_flag' definitions
2942 * The Adv Library should limit use to the lower nibble (4 bits) of
2943 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2945 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2946 #define ADV_SCSIQ_DONE 0x02 /* request done */
2947 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2949 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2950 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2951 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2954 * Adapter temporary configuration structure
2956 * This structure can be discarded after initialization. Don't add
2957 * fields here needed after initialization.
2959 * Field naming convention:
2961 * *_enable indicates the field enables or disables a feature. The
2962 * value of the field is never reset.
2964 typedef struct adv_dvc_cfg {
2965 ushort disc_enable; /* enable disconnection */
2966 uchar chip_version; /* chip version */
2967 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2968 ushort lib_version; /* Adv Library version number */
2969 ushort control_flag; /* Microcode Control Flag */
2970 ushort mcode_date; /* Microcode date */
2971 ushort mcode_version; /* Microcode version */
2972 ushort pci_slot_info; /* high byte device/function number */
2973 /* bits 7-3 device num., bits 2-0 function num. */
2974 /* low byte bus num. */
2975 ushort serial1; /* EEPROM serial number word 1 */
2976 ushort serial2; /* EEPROM serial number word 2 */
2977 ushort serial3; /* EEPROM serial number word 3 */
2978 struct device *dev; /* pointer to the pci dev structure for this board */
2982 struct adv_scsi_req_q;
2984 typedef void (* ADV_ISR_CALLBACK)
2985 (struct adv_dvc_var *, struct adv_scsi_req_q *);
2987 typedef void (* ADV_ASYNC_CALLBACK)
2988 (struct adv_dvc_var *, uchar);
2991 * Adapter operation variable structure.
2993 * One structure is required per host adapter.
2995 * Field naming convention:
2997 * *_able indicates both whether a feature should be enabled or disabled
2998 * and whether a device isi capable of the feature. At initialization
2999 * this field may be set, but later if a device is found to be incapable
3000 * of the feature, the field is cleared.
3002 typedef struct adv_dvc_var {
3003 AdvPortAddr iop_base; /* I/O port address */
3004 ushort err_code; /* fatal error code */
3005 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
3006 ADV_ISR_CALLBACK isr_callback;
3007 ADV_ASYNC_CALLBACK async_callback;
3008 ushort wdtr_able; /* try WDTR for a device */
3009 ushort sdtr_able; /* try SDTR for a device */
3010 ushort ultra_able; /* try SDTR Ultra speed for a device */
3011 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
3012 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
3013 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
3014 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
3015 ushort tagqng_able; /* try tagged queuing with a device */
3016 ushort ppr_able; /* PPR message capable per TID bitmask. */
3017 uchar max_dvc_qng; /* maximum number of tagged commands per device */
3018 ushort start_motor; /* start motor command allowed */
3019 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
3020 uchar chip_no; /* should be assigned by caller */
3021 uchar max_host_qng; /* maximum number of Q'ed command allowed */
3022 uchar irq_no; /* IRQ number */
3023 ushort no_scam; /* scam_tolerant of EEPROM */
3024 struct asc_board *drv_ptr; /* driver pointer to private structure */
3025 uchar chip_scsi_id; /* chip SCSI target ID */
3027 uchar bist_err_code;
3028 ADV_CARR_T *carrier_buf;
3029 ADV_CARR_T *carr_freelist; /* Carrier free list. */
3030 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
3031 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
3032 ushort carr_pending_cnt; /* Count of pending carriers. */
3034 * Note: The following fields will not be used after initialization. The
3035 * driver may discard the buffer after initialization is done.
3037 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3040 #define NO_OF_SG_PER_BLOCK 15
3042 typedef struct asc_sg_block {
3046 uchar sg_cnt; /* Valid entries in block. */
3047 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3049 ADV_PADDR sg_addr; /* SG element address. */
3050 ADV_DCNT sg_count; /* SG element count. */
3051 } sg_list[NO_OF_SG_PER_BLOCK];
3055 * ADV_SCSI_REQ_Q - microcode request structure
3057 * All fields in this structure up to byte 60 are used by the microcode.
3058 * The microcode makes assumptions about the size and ordering of fields
3059 * in this structure. Do not change the structure definition here without
3060 * coordinating the change with the microcode.
3062 * All fields accessed by microcode must be maintained in little_endian
3065 typedef struct adv_scsi_req_q {
3066 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3068 uchar target_id; /* Device target identifier. */
3069 uchar target_lun; /* Device target logical unit number. */
3070 ADV_PADDR data_addr; /* Data buffer physical address. */
3071 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3072 ADV_PADDR sense_addr;
3076 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3078 uchar done_status; /* Completion status. */
3079 uchar scsi_status; /* SCSI status byte. */
3080 uchar host_status; /* Ucode host status. */
3081 uchar sg_working_ix;
3082 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3083 ADV_PADDR sg_real_addr; /* SG list physical address. */
3084 ADV_PADDR scsiq_rptr;
3085 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3086 ADV_VADDR scsiq_ptr;
3089 * End of microcode structure - 60 bytes. The rest of the structure
3090 * is used by the Adv Library and ignored by the microcode.
3093 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3094 char *vdata_addr; /* Data buffer virtual address. */
3096 uchar pad[2]; /* Pad out to a word boundary. */
3100 * Microcode idle loop commands
3102 #define IDLE_CMD_COMPLETED 0
3103 #define IDLE_CMD_STOP_CHIP 0x0001
3104 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3105 #define IDLE_CMD_SEND_INT 0x0004
3106 #define IDLE_CMD_ABORT 0x0008
3107 #define IDLE_CMD_DEVICE_RESET 0x0010
3108 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3109 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3110 #define IDLE_CMD_SCSIREQ 0x0080
3112 #define IDLE_CMD_STATUS_SUCCESS 0x0001
3113 #define IDLE_CMD_STATUS_FAILURE 0x0002
3116 * AdvSendIdleCmd() flag definitions.
3118 #define ADV_NOWAIT 0x01
3121 * Wait loop time out values.
3123 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3124 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3125 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3126 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3127 #define SCSI_MAX_RETRY 10 /* retry count */
3129 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3130 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3131 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3132 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3135 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3138 * Device drivers must define the following functions.
3140 STATIC inline ulong DvcEnterCritical(void);
3141 STATIC inline void DvcLeaveCritical(ulong);
3142 STATIC void DvcSleepMilliSecond(ADV_DCNT);
3143 STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3144 STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3145 STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3146 uchar *, ASC_SDCNT *, int);
3147 STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3150 * Adv Library functions available to drivers.
3152 STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3153 STATIC int AdvISR(ADV_DVC_VAR *);
3154 STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
3155 STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3156 STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3157 STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3158 STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
3159 STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3162 * Internal Adv Library functions.
3164 STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3165 STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3166 STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3167 STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3168 STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3169 STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3170 STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3171 STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3172 STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3173 STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3174 STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3175 STATIC void AdvWaitEEPCmd(AdvPortAddr);
3176 STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
3179 * PCI Bus Definitions
3181 #define AscPCICmdRegBits_BusMastering 0x0007
3182 #define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3184 /* Read byte from a register. */
3185 #define AdvReadByteRegister(iop_base, reg_off) \
3186 (ADV_MEM_READB((iop_base) + (reg_off)))
3188 /* Write byte to a register. */
3189 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
3190 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3192 /* Read word (2 bytes) from a register. */
3193 #define AdvReadWordRegister(iop_base, reg_off) \
3194 (ADV_MEM_READW((iop_base) + (reg_off)))
3196 /* Write word (2 bytes) to a register. */
3197 #define AdvWriteWordRegister(iop_base, reg_off, word) \
3198 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3200 /* Write dword (4 bytes) to a register. */
3201 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3202 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3204 /* Read byte from LRAM. */
3205 #define AdvReadByteLram(iop_base, addr, byte) \
3207 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3208 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3211 /* Write byte to LRAM. */
3212 #define AdvWriteByteLram(iop_base, addr, byte) \
3213 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3214 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3216 /* Read word (2 bytes) from LRAM. */
3217 #define AdvReadWordLram(iop_base, addr, word) \
3219 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3220 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3223 /* Write word (2 bytes) to LRAM. */
3224 #define AdvWriteWordLram(iop_base, addr, word) \
3225 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3226 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3228 /* Write little-endian double word (4 bytes) to LRAM */
3229 /* Because of unspecified C language ordering don't use auto-increment. */
3230 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3231 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3232 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3233 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3234 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3235 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3236 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3238 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
3239 #define AdvReadWordAutoIncLram(iop_base) \
3240 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3242 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
3243 #define AdvWriteWordAutoIncLram(iop_base, word) \
3244 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3248 * Define macro to check for Condor signature.
3250 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3251 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3253 #define AdvFindSignature(iop_base) \
3254 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3255 ADV_CHIP_ID_BYTE) && \
3256 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3257 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3260 * Define macro to Return the version number of the chip at 'iop_base'.
3262 * The second parameter 'bus_type' is currently unused.
3264 #define AdvGetChipVersion(iop_base, bus_type) \
3265 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3268 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3269 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3271 * If the request has not yet been sent to the device it will simply be
3272 * aborted from RISC memory. If the request is disconnected it will be
3273 * aborted on reselection by sending an Abort Message to the target ID.
3276 * ADV_TRUE(1) - Queue was successfully aborted.
3277 * ADV_FALSE(0) - Queue was not found on the active queue list.
3279 #define AdvAbortQueue(asc_dvc, scsiq) \
3280 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3284 * Send a Bus Device Reset Message to the specified target ID.
3286 * All outstanding commands will be purged if sending the
3287 * Bus Device Reset Message is successful.
3290 * ADV_TRUE(1) - All requests on the target are purged.
3291 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3294 #define AdvResetDevice(asc_dvc, target_id) \
3295 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3296 (ADV_DCNT) (target_id))
3299 * SCSI Wide Type definition.
3301 #define ADV_SCSI_BIT_ID_TYPE ushort
3304 * AdvInitScsiTarget() 'cntl_flag' options.
3306 #define ADV_SCAN_LUN 0x01
3307 #define ADV_CAPINFO_NOLUN 0x02
3310 * Convert target id to target id bit mask.
3312 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3315 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3318 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
3319 #define QD_NO_ERROR 0x01
3320 #define QD_ABORTED_BY_HOST 0x02
3321 #define QD_WITH_ERROR 0x04
3323 #define QHSTA_NO_ERROR 0x00
3324 #define QHSTA_M_SEL_TIMEOUT 0x11
3325 #define QHSTA_M_DATA_OVER_RUN 0x12
3326 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3327 #define QHSTA_M_QUEUE_ABORTED 0x15
3328 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3329 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3330 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3331 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3332 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3333 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3334 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3335 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3336 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3337 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3338 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3339 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3340 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3341 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3342 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3343 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3344 #define QHSTA_M_WTM_TIMEOUT 0x41
3345 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3346 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3347 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3348 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3349 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3350 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3354 * Default EEPROM Configuration structure defined in a_init.c.
3356 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3357 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3358 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3361 * DvcGetPhyAddr() flag arguments
3363 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3364 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3365 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3366 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3367 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3368 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3370 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
3371 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3372 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3373 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3376 * Total contiguous memory needed for driver SG blocks.
3378 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3379 * number of scatter-gather elements the driver supports in a
3383 #define ADV_SG_LIST_MAX_BYTE_SIZE \
3384 (sizeof(ADV_SG_BLOCK) * \
3385 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3388 * Inquiry data structure and bitfield macros
3390 * Using bitfields to access the subchar data isn't portable across
3391 * endianness, so instead mask and shift. Only quantities of more
3392 * than 1 bit are shifted, since the others are just tested for true
3396 #define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3397 #define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3398 #define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3399 #define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3400 #define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3401 #define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3402 #define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3403 #define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3404 #define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3405 #define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3406 #define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3407 #define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3408 #define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3409 #define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3410 #define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3411 #define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3412 #define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3413 #define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3414 #define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3415 #define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3418 uchar periph; /* peripheral device type [0:4] */
3419 /* peripheral qualifier [5:7] */
3420 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3421 /* RMB - removable medium bit [7] */
3422 uchar ver; /* ANSI approved version [0:2] */
3423 /* ECMA version [3:5] */
3424 /* ISO version [6:7] */
3425 uchar byte3; /* response data format [0:3] */
3430 /* reserved [4:5] */
3431 /* terminate I/O process bit (see 5.6.22) [6] */
3432 /* asynch. event notification (processor) [7] */
3433 uchar add_len; /* additional length */
3434 uchar res1; /* reserved */
3435 uchar res2; /* reserved */
3436 uchar flags; /* soft reset implemented [0] */
3437 /* command queuing [1] */
3439 /* linked command for this logical unit [3] */
3440 /* synchronous data transfer [4] */
3441 /* wide bus 16 bit data transfer [5] */
3442 /* wide bus 32 bit data transfer [6] */
3443 /* relative addressing mode [7] */
3444 uchar vendor_id[8]; /* vendor identification */
3445 uchar product_id[16]; /* product identification */
3446 uchar product_rev_level[4]; /* product revision level */
3447 uchar vendor_specific[20]; /* vendor specific */
3448 uchar info; /* information unit supported [0] */
3449 /* quick arbitrate supported [1] */
3450 /* clocking field [2:3] */
3451 /* reserved [4:7] */
3452 uchar res3; /* reserved */
3453 } ADV_SCSI_INQUIRY; /* 58 bytes */
3457 * --- Driver Constants and Macros
3460 #define ASC_NUM_BOARD_SUPPORTED 16
3461 #define ASC_NUM_IOPORT_PROBE 4
3462 #define ASC_NUM_BUS 4
3464 /* Reference Scsi_Host hostdata */
3465 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3467 /* asc_board_t flags */
3468 #define ASC_HOST_IN_RESET 0x01
3469 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3470 #define ASC_SELECT_QUEUE_DEPTHS 0x08
3472 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3473 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3475 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3477 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
3479 #ifdef CONFIG_PROC_FS
3480 /* /proc/scsi/advansys/[0...] related definitions */
3481 #define ASC_PRTBUF_SIZE 2048
3482 #define ASC_PRTLINE_SIZE 160
3484 #define ASC_PRT_NEXT() \
3488 if (leftlen == 0) { \
3493 #endif /* CONFIG_PROC_FS */
3495 /* Asc Library return codes */
3498 #define ASC_NOERROR 1
3500 #define ASC_ERROR (-1)
3502 /* struct scsi_cmnd function return codes */
3503 #define STATUS_BYTE(byte) (byte)
3504 #define MSG_BYTE(byte) ((byte) << 8)
3505 #define HOST_BYTE(byte) ((byte) << 16)
3506 #define DRIVER_BYTE(byte) ((byte) << 24)
3509 * The following definitions and macros are OS independent interfaces to
3510 * the queue functions:
3511 * REQ - SCSI request structure
3512 * REQP - pointer to SCSI request structure
3513 * REQPTID(reqp) - reqp's target id
3514 * REQPNEXT(reqp) - reqp's next pointer
3515 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3516 * REQPTIME(reqp) - reqp's time stamp value
3517 * REQTIMESTAMP() - system time stamp value
3519 typedef struct scsi_cmnd REQ, *REQP;
3520 #define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3521 #define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3522 #define REQPTID(reqp) ((reqp)->device->id)
3523 #define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3524 #define REQTIMESTAMP() (jiffies)
3526 #define REQTIMESTAT(function, ascq, reqp, tid) \
3529 * If the request time stamp is less than the system time stamp, then \
3530 * maybe the system time stamp wrapped. Set the request time to zero.\
3532 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3533 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3535 /* Indicate an error occurred with the assertion. */ \
3536 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3537 REQPTIME(reqp) = 0; \
3539 /* Handle first minimum time case without external initialization. */ \
3540 if (((ascq)->q_tot_cnt[tid] == 1) || \
3541 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3542 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3543 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3544 (function), (tid), (ascq)->q_min_tim[tid]); \
3546 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3547 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3548 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3549 (function), tid, (ascq)->q_max_tim[tid]); \
3551 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3552 /* Reset the time stamp field. */ \
3553 REQPTIME(reqp) = 0; \
3556 /* asc_enqueue() flags */
3560 /* asc_dequeue_list() argument */
3561 #define ASC_TID_ALL (-1)
3563 /* Return non-zero, if the queue is empty. */
3564 #define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3566 #define PCI_MAX_SLOT 0x1F
3567 #define PCI_MAX_BUS 0xFF
3568 #define PCI_IOADDRESS_MASK 0xFFFE
3569 #define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3571 #ifndef ADVANSYS_STATS
3572 #define ASC_STATS(shp, counter)
3573 #define ASC_STATS_ADD(shp, counter, count)
3574 #else /* ADVANSYS_STATS */
3575 #define ASC_STATS(shp, counter) \
3576 (ASC_BOARDP(shp)->asc_stats.counter++)
3578 #define ASC_STATS_ADD(shp, counter, count) \
3579 (ASC_BOARDP(shp)->asc_stats.counter += (count))
3580 #endif /* ADVANSYS_STATS */
3582 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3584 /* If the result wraps when calculating tenths, return 0. */
3585 #define ASC_TENTHS(num, den) \
3586 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3587 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3590 * Display a message to the console.
3592 #define ASC_PRINT(s) \
3594 printk("advansys: "); \
3598 #define ASC_PRINT1(s, a1) \
3600 printk("advansys: "); \
3601 printk((s), (a1)); \
3604 #define ASC_PRINT2(s, a1, a2) \
3606 printk("advansys: "); \
3607 printk((s), (a1), (a2)); \
3610 #define ASC_PRINT3(s, a1, a2, a3) \
3612 printk("advansys: "); \
3613 printk((s), (a1), (a2), (a3)); \
3616 #define ASC_PRINT4(s, a1, a2, a3, a4) \
3618 printk("advansys: "); \
3619 printk((s), (a1), (a2), (a3), (a4)); \
3623 #ifndef ADVANSYS_DEBUG
3625 #define ASC_DBG(lvl, s)
3626 #define ASC_DBG1(lvl, s, a1)
3627 #define ASC_DBG2(lvl, s, a1, a2)
3628 #define ASC_DBG3(lvl, s, a1, a2, a3)
3629 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3630 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3631 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3632 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3633 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3634 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3635 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3636 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
3637 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
3638 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
3639 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3641 #else /* ADVANSYS_DEBUG */
3644 * Debugging Message Levels:
3646 * 1: High-Level Tracing
3647 * 2-N: Verbose Tracing
3650 #define ASC_DBG(lvl, s) \
3652 if (asc_dbglvl >= (lvl)) { \
3657 #define ASC_DBG1(lvl, s, a1) \
3659 if (asc_dbglvl >= (lvl)) { \
3660 printk((s), (a1)); \
3664 #define ASC_DBG2(lvl, s, a1, a2) \
3666 if (asc_dbglvl >= (lvl)) { \
3667 printk((s), (a1), (a2)); \
3671 #define ASC_DBG3(lvl, s, a1, a2, a3) \
3673 if (asc_dbglvl >= (lvl)) { \
3674 printk((s), (a1), (a2), (a3)); \
3678 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3680 if (asc_dbglvl >= (lvl)) { \
3681 printk((s), (a1), (a2), (a3), (a4)); \
3685 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3687 if (asc_dbglvl >= (lvl)) { \
3688 asc_prt_scsi_host(s); \
3692 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3694 if (asc_dbglvl >= (lvl)) { \
3695 asc_prt_scsi_cmnd(s); \
3699 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3701 if (asc_dbglvl >= (lvl)) { \
3702 asc_prt_asc_scsi_q(scsiqp); \
3706 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3708 if (asc_dbglvl >= (lvl)) { \
3709 asc_prt_asc_qdone_info(qdone); \
3713 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3715 if (asc_dbglvl >= (lvl)) { \
3716 asc_prt_adv_scsi_req_q(scsiqp); \
3720 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3722 if (asc_dbglvl >= (lvl)) { \
3723 asc_prt_hex((name), (start), (length)); \
3727 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3728 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3730 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3731 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3733 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3734 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3735 #endif /* ADVANSYS_DEBUG */
3737 #ifndef ADVANSYS_ASSERT
3738 #define ASC_ASSERT(a)
3739 #else /* ADVANSYS_ASSERT */
3741 #define ASC_ASSERT(a) \
3744 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3745 __FILE__, __LINE__); \
3749 #endif /* ADVANSYS_ASSERT */
3753 * --- Driver Structures
3756 #ifdef ADVANSYS_STATS
3758 /* Per board statistics structure */
3760 /* Driver Entrypoint Statistics */
3761 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3762 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3763 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3764 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3765 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3766 ADV_DCNT done; /* # calls to request's scsi_done function */
3767 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3768 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3769 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3770 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3771 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3772 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3773 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3774 ADV_DCNT exe_unknown; /* # unknown returns. */
3775 /* Data Transfer Statistics */
3776 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3777 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3778 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3779 ADV_DCNT sg_elem; /* # scatter-gather elements */
3780 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3782 #endif /* ADVANSYS_STATS */
3785 * Request queuing structure
3787 typedef struct asc_queue {
3788 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3789 REQP q_first[ADV_MAX_TID+1]; /* first queued request */
3790 REQP q_last[ADV_MAX_TID+1]; /* last queued request */
3791 #ifdef ADVANSYS_STATS
3792 short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
3793 short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
3794 ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
3795 ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
3796 ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
3797 ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
3798 #endif /* ADVANSYS_STATS */
3802 * Adv Library Request Structures
3804 * The following two structures are used to process Wide Board requests.
3806 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3807 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3808 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3809 * Mid-Level SCSI request structure.
3811 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3812 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3813 * up to 255 scatter-gather elements may be used per request or
3816 * Both structures must be 32 byte aligned.
3818 typedef struct adv_sgblk {
3819 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3820 uchar align[32]; /* Sgblock structure padding. */
3821 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3824 typedef struct adv_req {
3825 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3826 uchar align[32]; /* Request structure padding. */
3827 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3828 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3829 struct adv_req *next_reqp; /* Next Request Structure. */
3833 * Structure allocated for each board.
3835 * This structure is allocated by scsi_register() at the end
3836 * of the 'Scsi_Host' structure starting at the 'hostdata'
3837 * field. It is guaranteed to be allocated from DMA-able memory.
3839 typedef struct asc_board {
3840 int id; /* Board Id */
3841 uint flags; /* Board flags */
3843 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3844 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3847 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3848 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3850 ushort asc_n_io_port; /* Number I/O ports. */
3851 asc_queue_t active; /* Active command queue */
3852 asc_queue_t waiting; /* Waiting command queue */
3853 asc_queue_t done; /* Done command queue */
3854 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3855 struct scsi_device *device[ADV_MAX_TID+1]; /* Mid-Level Scsi Device */
3856 ushort reqcnt[ADV_MAX_TID+1]; /* Starvation request count */
3857 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3858 ushort queue_full_cnt[ADV_MAX_TID+1]; /* Queue full count */
3860 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3861 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3862 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3863 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3865 ulong last_reset; /* Saved last reset time */
3866 spinlock_t lock; /* Board spinlock */
3867 #ifdef CONFIG_PROC_FS
3868 /* /proc/scsi/advansys/[0...] */
3869 char *prtbuf; /* /proc print buffer */
3870 #endif /* CONFIG_PROC_FS */
3871 #ifdef ADVANSYS_STATS
3872 struct asc_stats asc_stats; /* Board statistics */
3873 #endif /* ADVANSYS_STATS */
3875 * The following fields are used only for Narrow Boards.
3877 /* The following three structures must be in DMA-able memory. */
3878 ASC_SCSI_REQ_Q scsireqq;
3879 ASC_CAP_INFO cap_info;
3880 ASC_SCSI_INQUIRY inquiry;
3881 uchar sdtr_data[ASC_MAX_TID+1]; /* SDTR information */
3883 * The following fields are used only for Wide Boards.
3885 void *ioremap_addr; /* I/O Memory remap address. */
3886 ushort ioport; /* I/O Port address. */
3887 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3888 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3889 adv_req_t *adv_reqp; /* Request structures. */
3890 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3891 ushort bios_signature; /* BIOS Signature. */
3892 ushort bios_version; /* BIOS Version. */
3893 ushort bios_codeseg; /* BIOS Code Segment. */
3894 ushort bios_codelen; /* BIOS Code Segment Length. */
3898 * PCI configuration structures
3900 typedef struct _PCI_DATA_
3909 typedef struct _PCI_DEVICE_
3924 typedef struct _PCI_CONFIG_SPACE_
3936 ADV_PADDR baseAddress[6];
3938 ADV_PADDR optionRomAddr;
3939 ushort reserved2[4];
3951 /* Note: All driver global data should be initialized. */
3953 /* Number of boards detected in system. */
3954 STATIC int asc_board_count = 0;
3955 STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
3957 /* Overrun buffer used by all narrow boards. */
3958 STATIC uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3961 * Global structures required to issue a command.
3963 STATIC ASC_SCSI_Q asc_scsi_q = { { 0 } };
3964 STATIC ASC_SG_HEAD asc_sg_head = { 0 };
3966 /* List of supported bus types. */
3967 STATIC ushort asc_bus[ASC_NUM_BUS] __initdata = {
3975 * Used with the LILO 'advansys' option to eliminate or
3976 * limit I/O port probing at boot time, cf. advansys_setup().
3978 STATIC int asc_iopflag = ASC_FALSE;
3979 STATIC int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
3981 #ifdef ADVANSYS_DEBUG
3983 asc_bus_name[ASC_NUM_BUS] = {
3990 STATIC int asc_dbglvl = 3;
3991 #endif /* ADVANSYS_DEBUG */
3993 /* Declaration for Asc Library internal data referenced by driver. */
3994 STATIC PortAddr _asc_def_iop_base[];
3998 * --- Driver Function Prototypes
4000 * advansys.h contains function prototypes for functions global to Linux.
4003 STATIC irqreturn_t advansys_interrupt(int, void *, struct pt_regs *);
4004 STATIC int advansys_slave_configure(struct scsi_device *);
4005 STATIC void asc_scsi_done_list(struct scsi_cmnd *);
4006 STATIC int asc_execute_scsi_cmnd(struct scsi_cmnd *);
4007 STATIC int asc_build_req(asc_board_t *, struct scsi_cmnd *);
4008 STATIC int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
4009 STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
4010 STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
4011 STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
4012 STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
4013 STATIC void asc_enqueue(asc_queue_t *, REQP, int);
4014 STATIC REQP asc_dequeue(asc_queue_t *, int);
4015 STATIC REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
4016 STATIC int asc_rmqueue(asc_queue_t *, REQP);
4017 STATIC void asc_execute_queue(asc_queue_t *);
4018 #ifdef CONFIG_PROC_FS
4019 STATIC int asc_proc_copy(off_t, off_t, char *, int , char *, int);
4020 STATIC int asc_prt_board_devices(struct Scsi_Host *, char *, int);
4021 STATIC int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
4022 STATIC int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
4023 STATIC int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
4024 STATIC int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
4025 STATIC int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
4026 STATIC int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
4027 STATIC int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
4028 STATIC int asc_prt_line(char *, int, char *fmt, ...);
4029 #endif /* CONFIG_PROC_FS */
4031 /* Declaration for Asc Library internal functions referenced by driver. */
4032 STATIC int AscFindSignature(PortAddr);
4033 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
4035 /* Statistics function prototypes. */
4036 #ifdef ADVANSYS_STATS
4037 #ifdef CONFIG_PROC_FS
4038 STATIC int asc_prt_board_stats(struct Scsi_Host *, char *, int);
4039 STATIC int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
4040 #endif /* CONFIG_PROC_FS */
4041 #endif /* ADVANSYS_STATS */
4043 /* Debug function prototypes. */
4044 #ifdef ADVANSYS_DEBUG
4045 STATIC void asc_prt_scsi_host(struct Scsi_Host *);
4046 STATIC void asc_prt_scsi_cmnd(struct scsi_cmnd *);
4047 STATIC void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
4048 STATIC void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4049 STATIC void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4050 STATIC void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4051 STATIC void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4052 STATIC void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4053 STATIC void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4054 STATIC void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4055 STATIC void asc_prt_hex(char *f, uchar *, int);
4056 #endif /* ADVANSYS_DEBUG */
4060 * --- Linux 'struct scsi_host_template' and advansys_setup() Functions
4063 #ifdef CONFIG_PROC_FS
4065 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4067 * *buffer: I/O buffer
4068 * **start: if inout == FALSE pointer into buffer where user read should start
4069 * offset: current offset into a /proc/scsi/advansys/[0...] file
4070 * length: length of buffer
4071 * hostno: Scsi_Host host_no
4072 * inout: TRUE - user is writing; FALSE - user is reading
4074 * Return the number of bytes read from or written to a
4075 * /proc/scsi/advansys/[0...] file.
4077 * Note: This function uses the per board buffer 'prtbuf' which is
4078 * allocated when the board is initialized in advansys_detect(). The
4079 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4080 * used to write to the buffer. The way asc_proc_copy() is written
4081 * if 'prtbuf' is too small it will not be overwritten. Instead the
4082 * user just won't get all the available statistics.
4085 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4086 off_t offset, int length, int inout)
4088 struct Scsi_Host *shp;
4089 asc_board_t *boardp;
4098 #ifdef ADVANSYS_STATS
4100 #endif /* ADVANSYS_STATS */
4102 ASC_DBG(1, "advansys_proc_info: begin\n");
4105 * User write not supported.
4107 if (inout == TRUE) {
4112 * User read of /proc/scsi/advansys/[0...] file.
4115 /* Find the specified board. */
4116 for (i = 0; i < asc_board_count; i++) {
4117 if (asc_host[i]->host_no == shost->host_no) {
4121 if (i == asc_board_count) {
4126 boardp = ASC_BOARDP(shp);
4128 /* Copy read data starting at the beginning of the buffer. */
4136 * Get board configuration information.
4138 * advansys_info() returns the board string from its own static buffer.
4140 cp = (char *) advansys_info(shp);
4143 /* Copy board information. */
4144 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4148 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4155 * Display Wide Board BIOS Information.
4157 if (ASC_WIDE_BOARD(boardp)) {
4158 cp = boardp->prtbuf;
4159 cplen = asc_prt_adv_bios(shp, cp, ASC_PRTBUF_SIZE);
4160 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4161 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4165 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4173 * Display driver information for each device attached to the board.
4175 cp = boardp->prtbuf;
4176 cplen = asc_prt_board_devices(shp, cp, ASC_PRTBUF_SIZE);
4177 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4178 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4182 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4189 * Display EEPROM configuration for the board.
4191 cp = boardp->prtbuf;
4192 if (ASC_NARROW_BOARD(boardp)) {
4193 cplen = asc_prt_asc_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4195 cplen = asc_prt_adv_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4197 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4198 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4202 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4209 * Display driver configuration and information for the board.
4211 cp = boardp->prtbuf;
4212 cplen = asc_prt_driver_conf(shp, cp, ASC_PRTBUF_SIZE);
4213 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4214 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4218 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4224 #ifdef ADVANSYS_STATS
4226 * Display driver statistics for the board.
4228 cp = boardp->prtbuf;
4229 cplen = asc_prt_board_stats(shp, cp, ASC_PRTBUF_SIZE);
4230 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4231 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4235 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4242 * Display driver statistics for each target.
4244 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4245 cp = boardp->prtbuf;
4246 cplen = asc_prt_target_stats(shp, tgt_id, cp, ASC_PRTBUF_SIZE);
4247 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4248 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4252 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4258 #endif /* ADVANSYS_STATS */
4261 * Display Asc Library dynamic configuration information
4264 cp = boardp->prtbuf;
4265 if (ASC_NARROW_BOARD(boardp)) {
4266 cplen = asc_prt_asc_board_info(shp, cp, ASC_PRTBUF_SIZE);
4268 cplen = asc_prt_adv_board_info(shp, cp, ASC_PRTBUF_SIZE);
4270 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4271 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4275 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4281 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4285 #endif /* CONFIG_PROC_FS */
4290 * Detect function for AdvanSys adapters.
4292 * Argument is a pointer to the host driver's scsi_hosts entry.
4294 * Return number of adapters found.
4296 * Note: Because this function is called during system initialization
4297 * it must not call SCSI mid-level functions including scsi_malloc()
4301 advansys_detect(struct scsi_host_template *tpnt)
4303 static int detect_called = ASC_FALSE;
4306 struct Scsi_Host *shp = NULL;
4307 asc_board_t *boardp = NULL;
4308 ASC_DVC_VAR *asc_dvc_varp = NULL;
4309 ADV_DVC_VAR *adv_dvc_varp = NULL;
4310 adv_sgblk_t *sgp = NULL;
4312 int share_irq = FALSE;
4314 struct device *dev = NULL;
4316 int pci_init_search = 0;
4317 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
4318 int pci_card_cnt_max = 0;
4319 int pci_card_cnt = 0;
4320 struct pci_dev *pci_devp = NULL;
4321 int pci_device_id_cnt = 0;
4322 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
4323 PCI_DEVICE_ID_ASP_1200A,
4324 PCI_DEVICE_ID_ASP_ABP940,
4325 PCI_DEVICE_ID_ASP_ABP940U,
4326 PCI_DEVICE_ID_ASP_ABP940UW,
4327 PCI_DEVICE_ID_38C0800_REV1,
4328 PCI_DEVICE_ID_38C1600_REV1
4330 ADV_PADDR pci_memory_address;
4331 #endif /* CONFIG_PCI */
4332 int warn_code, err_code;
4335 if (detect_called == ASC_FALSE) {
4336 detect_called = ASC_TRUE;
4338 printk("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
4342 ASC_DBG(1, "advansys_detect: begin\n");
4344 asc_board_count = 0;
4347 * If I/O port probing has been modified, then verify and
4348 * clean-up the 'asc_ioport' list.
4350 if (asc_iopflag == ASC_TRUE) {
4351 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4352 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
4353 ioport, asc_ioport[ioport]);
4354 if (asc_ioport[ioport] != 0) {
4355 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX; iop++) {
4356 if (_asc_def_iop_base[iop] == asc_ioport[ioport]) {
4360 if (iop == ASC_IOADR_TABLE_MAX_IX) {
4362 "AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
4363 asc_ioport[ioport]);
4364 asc_ioport[ioport] = 0;
4371 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
4373 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
4374 bus, asc_bus_name[bus]);
4377 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
4379 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
4382 switch (asc_bus[bus]) {
4386 if (asc_iopflag == ASC_FALSE) {
4387 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4390 * ISA and VL I/O port scanning has either been
4391 * eliminated or limited to selected ports on
4392 * the LILO command line, /etc/lilo.conf, or
4393 * by setting variables when the module was loaded.
4395 ASC_DBG(1, "advansys_detect: I/O port scanning modified\n");
4398 for (; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4399 if ((iop = asc_ioport[ioport]) != 0) {
4405 "advansys_detect: probing I/O port 0x%x...\n",
4407 if (check_region(iop, ASC_IOADR_GAP) != 0) {
4409 "AdvanSys SCSI: specified I/O Port 0x%X is busy\n", iop);
4410 /* Don't try this I/O port twice. */
4411 asc_ioport[ioport] = 0;
4412 goto ioport_try_again;
4413 } else if (AscFindSignature(iop) == ASC_FALSE) {
4415 "AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n", iop);
4416 /* Don't try this I/O port twice. */
4417 asc_ioport[ioport] = 0;
4418 goto ioport_try_again;
4421 * If this isn't an ISA board, then it must be
4422 * a VL board. If currently looking an ISA
4423 * board is being looked for then try for
4424 * another ISA board in 'asc_ioport'.
4426 if (asc_bus[bus] == ASC_IS_ISA &&
4427 (AscGetChipVersion(iop, ASC_IS_ISA) &
4428 ASC_CHIP_VER_ISA_BIT) == 0) {
4430 * Don't clear 'asc_ioport[ioport]'. Try
4431 * this board again for VL. Increment
4432 * 'ioport' past this board.
4435 goto ioport_try_again;
4439 * This board appears good, don't try the I/O port
4440 * again by clearing its value. Increment 'ioport'
4441 * for the next iteration.
4443 asc_ioport[ioport++] = 0;
4446 #endif /* CONFIG_ISA */
4451 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4452 #endif /* CONFIG_ISA */
4457 if (pci_init_search == 0) {
4460 pci_init_search = 1;
4462 /* Find all PCI cards. */
4463 while (pci_device_id_cnt < ASC_PCI_DEVICE_ID_CNT) {
4464 if ((pci_devp = pci_find_device(PCI_VENDOR_ID_ASP,
4465 pci_device_id[pci_device_id_cnt], pci_devp)) ==
4467 pci_device_id_cnt++;
4469 if (pci_enable_device(pci_devp) == 0) {
4470 pci_devicep[pci_card_cnt_max++] = pci_devp;
4476 * Sort PCI cards in ascending order by PCI Bus, Slot,
4477 * and Device Number.
4479 for (i = 0; i < pci_card_cnt_max - 1; i++)
4481 for (j = i + 1; j < pci_card_cnt_max; j++) {
4482 if ((pci_devicep[j]->bus->number <
4483 pci_devicep[i]->bus->number) ||
4484 ((pci_devicep[j]->bus->number ==
4485 pci_devicep[i]->bus->number) &&
4486 (pci_devicep[j]->devfn <
4487 pci_devicep[i]->devfn))) {
4488 pci_devp = pci_devicep[i];
4489 pci_devicep[i] = pci_devicep[j];
4490 pci_devicep[j] = pci_devp;
4500 if (pci_card_cnt == pci_card_cnt_max) {
4503 pci_devp = pci_devicep[pci_card_cnt];
4506 "advansys_detect: devfn %d, bus number %d\n",
4507 pci_devp->devfn, pci_devp->bus->number);
4508 iop = pci_resource_start(pci_devp, 0);
4510 "advansys_detect: vendorID %X, deviceID %X\n",
4511 pci_devp->vendor, pci_devp->device);
4512 ASC_DBG2(2, "advansys_detect: iop %X, irqLine %d\n",
4513 iop, pci_devp->irq);
4516 dev = &pci_devp->dev;
4518 #endif /* CONFIG_PCI */
4522 ASC_PRINT1("advansys_detect: unknown bus type: %d\n",
4526 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
4529 * Adapter not found, try next bus type.
4538 * Register the adapter, get its configuration, and
4541 ASC_DBG(2, "advansys_detect: scsi_register()\n");
4542 shp = scsi_register(tpnt, sizeof(asc_board_t));
4548 /* Save a pointer to the Scsi_Host of each board found. */
4549 asc_host[asc_board_count++] = shp;
4551 /* Initialize private per board data */
4552 boardp = ASC_BOARDP(shp);
4553 memset(boardp, 0, sizeof(asc_board_t));
4554 boardp->id = asc_board_count - 1;
4556 /* Initialize spinlock. */
4557 spin_lock_init(&boardp->lock);
4560 * Handle both narrow and wide boards.
4562 * If a Wide board was detected, set the board structure
4563 * wide board flag. Set-up the board structure based on
4567 if (asc_bus[bus] == ASC_IS_PCI &&
4568 (pci_devp->device == PCI_DEVICE_ID_ASP_ABP940UW ||
4569 pci_devp->device == PCI_DEVICE_ID_38C0800_REV1 ||
4570 pci_devp->device == PCI_DEVICE_ID_38C1600_REV1))
4572 boardp->flags |= ASC_IS_WIDE_BOARD;
4574 #endif /* CONFIG_PCI */
4576 if (ASC_NARROW_BOARD(boardp)) {
4577 ASC_DBG(1, "advansys_detect: narrow board\n");
4578 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4579 asc_dvc_varp->bus_type = asc_bus[bus];
4580 asc_dvc_varp->drv_ptr = boardp;
4581 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
4582 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
4583 asc_dvc_varp->iop_base = iop;
4584 asc_dvc_varp->isr_callback = asc_isr_callback;
4586 ASC_DBG(1, "advansys_detect: wide board\n");
4587 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4588 adv_dvc_varp->drv_ptr = boardp;
4589 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
4590 adv_dvc_varp->isr_callback = adv_isr_callback;
4591 adv_dvc_varp->async_callback = adv_async_callback;
4593 if (pci_devp->device == PCI_DEVICE_ID_ASP_ABP940UW)
4595 ASC_DBG(1, "advansys_detect: ASC-3550\n");
4596 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
4597 } else if (pci_devp->device == PCI_DEVICE_ID_38C0800_REV1)
4599 ASC_DBG(1, "advansys_detect: ASC-38C0800\n");
4600 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
4603 ASC_DBG(1, "advansys_detect: ASC-38C1600\n");
4604 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
4606 #endif /* CONFIG_PCI */
4609 * Map the board's registers into virtual memory for
4610 * PCI slave access. Only memory accesses are used to
4611 * access the board's registers.
4613 * Note: The PCI register base address is not always
4614 * page aligned, but the address passed to ioremap()
4615 * must be page aligned. It is guaranteed that the
4616 * PCI register base address will not cross a page
4619 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4621 iolen = ADV_3550_IOLEN;
4622 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4624 iolen = ADV_38C0800_IOLEN;
4627 iolen = ADV_38C1600_IOLEN;
4630 pci_memory_address = pci_resource_start(pci_devp, 1);
4631 ASC_DBG1(1, "advansys_detect: pci_memory_address: 0x%lx\n",
4632 (ulong) pci_memory_address);
4633 if ((boardp->ioremap_addr =
4634 ioremap(pci_memory_address & PAGE_MASK,
4637 "advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
4638 boardp->id, pci_memory_address, iolen);
4639 scsi_unregister(shp);
4643 ASC_DBG1(1, "advansys_detect: ioremap_addr: 0x%lx\n",
4644 (ulong) boardp->ioremap_addr);
4645 adv_dvc_varp->iop_base = (AdvPortAddr)
4646 (boardp->ioremap_addr +
4647 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
4648 ASC_DBG1(1, "advansys_detect: iop_base: 0x%lx\n",
4649 adv_dvc_varp->iop_base);
4650 #endif /* CONFIG_PCI */
4653 * Even though it isn't used to access wide boards, other
4654 * than for the debug line below, save I/O Port address so
4655 * that it can be reported.
4657 boardp->ioport = iop;
4660 "advansys_detect: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
4661 (ushort) inp(iop + 1), (ushort) inpw(iop));
4664 #ifdef CONFIG_PROC_FS
4666 * Allocate buffer for printing information from
4667 * /proc/scsi/advansys/[0...].
4669 if ((boardp->prtbuf =
4670 kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
4672 "advansys_detect: board %d: kmalloc(%d, %d) returned NULL\n",
4673 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
4674 scsi_unregister(shp);
4678 #endif /* CONFIG_PROC_FS */
4680 if (ASC_NARROW_BOARD(boardp)) {
4681 asc_dvc_varp->cfg->dev = dev;
4683 * Set the board bus type and PCI IRQ before
4684 * calling AscInitGetConfig().
4686 switch (asc_dvc_varp->bus_type) {
4689 shp->unchecked_isa_dma = TRUE;
4693 shp->unchecked_isa_dma = FALSE;
4697 shp->unchecked_isa_dma = FALSE;
4700 #endif /* CONFIG_ISA */
4703 shp->irq = asc_dvc_varp->irq_no = pci_devp->irq;
4704 asc_dvc_varp->cfg->pci_slot_info =
4705 ASC_PCI_MKID(pci_devp->bus->number,
4706 PCI_SLOT(pci_devp->devfn),
4707 PCI_FUNC(pci_devp->devfn));
4708 shp->unchecked_isa_dma = FALSE;
4711 #endif /* CONFIG_PCI */
4714 "advansys_detect: board %d: unknown adapter type: %d\n",
4715 boardp->id, asc_dvc_varp->bus_type);
4716 shp->unchecked_isa_dma = TRUE;
4721 adv_dvc_varp->cfg->dev = dev;
4723 * For Wide boards set PCI information before calling
4724 * AdvInitGetConfig().
4727 shp->irq = adv_dvc_varp->irq_no = pci_devp->irq;
4728 adv_dvc_varp->cfg->pci_slot_info =
4729 ASC_PCI_MKID(pci_devp->bus->number,
4730 PCI_SLOT(pci_devp->devfn),
4731 PCI_FUNC(pci_devp->devfn));
4732 shp->unchecked_isa_dma = FALSE;
4734 #endif /* CONFIG_PCI */
4738 * Read the board configuration.
4740 if (ASC_NARROW_BOARD(boardp)) {
4742 * NOTE: AscInitGetConfig() may change the board's
4743 * bus_type value. The asc_bus[bus] value should no
4744 * longer be used. If the bus_type field must be
4745 * referenced only use the bit-wise AND operator "&".
4747 ASC_DBG(2, "advansys_detect: AscInitGetConfig()\n");
4748 switch(ret = AscInitGetConfig(asc_dvc_varp)) {
4749 case 0: /* No error */
4751 case ASC_WARN_IO_PORT_ROTATE:
4753 "AscInitGetConfig: board %d: I/O port address modified\n",
4756 case ASC_WARN_AUTO_CONFIG:
4758 "AscInitGetConfig: board %d: I/O port increment switch enabled\n",
4761 case ASC_WARN_EEPROM_CHKSUM:
4763 "AscInitGetConfig: board %d: EEPROM checksum error\n",
4766 case ASC_WARN_IRQ_MODIFIED:
4768 "AscInitGetConfig: board %d: IRQ modified\n",
4771 case ASC_WARN_CMD_QNG_CONFLICT:
4773 "AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
4778 "AscInitGetConfig: board %d: unknown warning: 0x%x\n",
4782 if ((err_code = asc_dvc_varp->err_code) != 0) {
4784 "AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4785 boardp->id, asc_dvc_varp->init_state,
4786 asc_dvc_varp->err_code);
4789 ASC_DBG(2, "advansys_detect: AdvInitGetConfig()\n");
4790 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
4791 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
4794 if ((err_code = adv_dvc_varp->err_code) != 0) {
4796 "AdvInitGetConfig: board %d error: err_code 0x%x\n",
4797 boardp->id, adv_dvc_varp->err_code);
4801 if (err_code != 0) {
4802 #ifdef CONFIG_PROC_FS
4803 kfree(boardp->prtbuf);
4804 #endif /* CONFIG_PROC_FS */
4805 scsi_unregister(shp);
4811 * Save the EEPROM configuration so that it can be displayed
4812 * from /proc/scsi/advansys/[0...].
4814 if (ASC_NARROW_BOARD(boardp)) {
4819 * Set the adapter's target id bit in the 'init_tidmask' field.
4821 boardp->init_tidmask |=
4822 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
4825 * Save EEPROM settings for the board.
4827 ep = &boardp->eep_config.asc_eep;
4829 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
4830 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
4831 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
4832 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
4833 ep->start_motor = asc_dvc_varp->start_motor;
4834 ep->cntl = asc_dvc_varp->dvc_cntl;
4835 ep->no_scam = asc_dvc_varp->no_scam;
4836 ep->max_total_qng = asc_dvc_varp->max_total_qng;
4837 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
4838 /* 'max_tag_qng' is set to the same value for every device. */
4839 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
4840 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
4841 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
4842 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
4843 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
4844 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
4845 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
4848 * Modify board configuration.
4850 ASC_DBG(2, "advansys_detect: AscInitSetConfig()\n");
4851 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
4852 case 0: /* No error. */
4854 case ASC_WARN_IO_PORT_ROTATE:
4856 "AscInitSetConfig: board %d: I/O port address modified\n",
4859 case ASC_WARN_AUTO_CONFIG:
4861 "AscInitSetConfig: board %d: I/O port increment switch enabled\n",
4864 case ASC_WARN_EEPROM_CHKSUM:
4866 "AscInitSetConfig: board %d: EEPROM checksum error\n",
4869 case ASC_WARN_IRQ_MODIFIED:
4871 "AscInitSetConfig: board %d: IRQ modified\n",
4874 case ASC_WARN_CMD_QNG_CONFLICT:
4876 "AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
4881 "AscInitSetConfig: board %d: unknown warning: 0x%x\n",
4885 if (asc_dvc_varp->err_code != 0) {
4887 "AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4888 boardp->id, asc_dvc_varp->init_state,
4889 asc_dvc_varp->err_code);
4890 #ifdef CONFIG_PROC_FS
4891 kfree(boardp->prtbuf);
4892 #endif /* CONFIG_PROC_FS */
4893 scsi_unregister(shp);
4899 * Finish initializing the 'Scsi_Host' structure.
4901 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
4902 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
4903 shp->irq = asc_dvc_varp->irq_no;
4906 ADVEEP_3550_CONFIG *ep_3550;
4907 ADVEEP_38C0800_CONFIG *ep_38C0800;
4908 ADVEEP_38C1600_CONFIG *ep_38C1600;
4911 * Save Wide EEP Configuration Information.
4913 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4915 ep_3550 = &boardp->eep_config.adv_3550_eep;
4917 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4918 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
4919 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4920 ep_3550->termination = adv_dvc_varp->cfg->termination;
4921 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
4922 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
4923 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
4924 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
4925 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
4926 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
4927 ep_3550->start_motor = adv_dvc_varp->start_motor;
4928 ep_3550->scsi_reset_delay = adv_dvc_varp->scsi_reset_wait;
4929 ep_3550->serial_number_word1 =
4930 adv_dvc_varp->cfg->serial1;
4931 ep_3550->serial_number_word2 =
4932 adv_dvc_varp->cfg->serial2;
4933 ep_3550->serial_number_word3 =
4934 adv_dvc_varp->cfg->serial3;
4935 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4937 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4939 ep_38C0800->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4940 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
4941 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4942 ep_38C0800->termination_lvd =
4943 adv_dvc_varp->cfg->termination;
4944 ep_38C0800->disc_enable = adv_dvc_varp->cfg->disc_enable;
4945 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
4946 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
4947 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4948 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4949 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4950 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4951 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4952 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4953 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
4954 ep_38C0800->scsi_reset_delay =
4955 adv_dvc_varp->scsi_reset_wait;
4956 ep_38C0800->serial_number_word1 =
4957 adv_dvc_varp->cfg->serial1;
4958 ep_38C0800->serial_number_word2 =
4959 adv_dvc_varp->cfg->serial2;
4960 ep_38C0800->serial_number_word3 =
4961 adv_dvc_varp->cfg->serial3;
4964 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4966 ep_38C1600->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4967 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
4968 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4969 ep_38C1600->termination_lvd =
4970 adv_dvc_varp->cfg->termination;
4971 ep_38C1600->disc_enable = adv_dvc_varp->cfg->disc_enable;
4972 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
4973 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
4974 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4975 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4976 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4977 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4978 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4979 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4980 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
4981 ep_38C1600->scsi_reset_delay =
4982 adv_dvc_varp->scsi_reset_wait;
4983 ep_38C1600->serial_number_word1 =
4984 adv_dvc_varp->cfg->serial1;
4985 ep_38C1600->serial_number_word2 =
4986 adv_dvc_varp->cfg->serial2;
4987 ep_38C1600->serial_number_word3 =
4988 adv_dvc_varp->cfg->serial3;
4992 * Set the adapter's target id bit in the 'init_tidmask' field.
4994 boardp->init_tidmask |=
4995 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
4998 * Finish initializing the 'Scsi_Host' structure.
5000 shp->irq = adv_dvc_varp->irq_no;
5004 * Channels are numbered beginning with 0. For AdvanSys one host
5005 * structure supports one channel. Multi-channel boards have a
5006 * separate host structure for each channel.
5008 shp->max_channel = 0;
5009 if (ASC_NARROW_BOARD(boardp)) {
5010 shp->max_id = ASC_MAX_TID + 1;
5011 shp->max_lun = ASC_MAX_LUN + 1;
5013 shp->io_port = asc_dvc_varp->iop_base;
5014 boardp->asc_n_io_port = ASC_IOADR_GAP;
5015 shp->this_id = asc_dvc_varp->cfg->chip_scsi_id;
5017 /* Set maximum number of queues the adapter can handle. */
5018 shp->can_queue = asc_dvc_varp->max_total_qng;
5020 shp->max_id = ADV_MAX_TID + 1;
5021 shp->max_lun = ADV_MAX_LUN + 1;
5024 * Save the I/O Port address and length even though
5025 * I/O ports are not used to access Wide boards.
5026 * Instead the Wide boards are accessed with
5027 * PCI Memory Mapped I/O.
5030 boardp->asc_n_io_port = iolen;
5032 shp->this_id = adv_dvc_varp->chip_scsi_id;
5034 /* Set maximum number of queues the adapter can handle. */
5035 shp->can_queue = adv_dvc_varp->max_host_qng;
5039 * 'n_io_port' currently is one byte.
5041 * Set a value to 'n_io_port', but never referenced it because
5042 * it may be truncated.
5044 shp->n_io_port = boardp->asc_n_io_port <= 255 ?
5045 boardp->asc_n_io_port : 255;
5048 * Following v1.3.89, 'cmd_per_lun' is no longer needed
5049 * and should be set to zero.
5051 * But because of a bug introduced in v1.3.89 if the driver is
5052 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
5053 * SCSI function 'allocate_device' will panic. To allow the driver
5054 * to work as a module in these kernels set 'cmd_per_lun' to 1.
5056 * Note: This is wrong. cmd_per_lun should be set to the depth
5057 * you want on untagged devices always.
5060 shp->cmd_per_lun = 1;
5062 shp->cmd_per_lun = 0;
5066 * Set the maximum number of scatter-gather elements the
5067 * adapter can handle.
5069 if (ASC_NARROW_BOARD(boardp)) {
5071 * Allow two commands with 'sg_tablesize' scatter-gather
5072 * elements to be executed simultaneously. This value is
5073 * the theoretical hardware limit. It may be decreased
5077 (((asc_dvc_varp->max_total_qng - 2) / 2) *
5078 ASC_SG_LIST_PER_Q) + 1;
5080 shp->sg_tablesize = ADV_MAX_SG_LIST;
5084 * The value of 'sg_tablesize' can not exceed the SCSI
5085 * mid-level driver definition of SG_ALL. SG_ALL also
5086 * must not be exceeded, because it is used to define the
5087 * size of the scatter-gather table in 'struct asc_sg_head'.
5089 if (shp->sg_tablesize > SG_ALL) {
5090 shp->sg_tablesize = SG_ALL;
5093 ASC_DBG1(1, "advansys_detect: sg_tablesize: %d\n",
5096 /* BIOS start address. */
5097 if (ASC_NARROW_BOARD(boardp)) {
5099 ((ulong) AscGetChipBiosAddress(
5100 asc_dvc_varp->iop_base,
5101 asc_dvc_varp->bus_type));
5104 * Fill-in BIOS board variables. The Wide BIOS saves
5105 * information in LRAM that is used by the driver.
5107 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_SIGNATURE,
5108 boardp->bios_signature);
5109 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_VERSION,
5110 boardp->bios_version);
5111 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODESEG,
5112 boardp->bios_codeseg);
5113 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODELEN,
5114 boardp->bios_codelen);
5117 "advansys_detect: bios_signature 0x%x, bios_version 0x%x\n",
5118 boardp->bios_signature, boardp->bios_version);
5121 "advansys_detect: bios_codeseg 0x%x, bios_codelen 0x%x\n",
5122 boardp->bios_codeseg, boardp->bios_codelen);
5125 * If the BIOS saved a valid signature, then fill in
5126 * the BIOS code segment base address.
5128 if (boardp->bios_signature == 0x55AA) {
5130 * Convert x86 realmode code segment to a linear
5131 * address by shifting left 4.
5133 shp->base = ((ulong) boardp->bios_codeseg << 4);
5140 * Register Board Resources - I/O Port, DMA, IRQ
5144 * Register I/O port range.
5146 * For Wide boards the I/O ports are not used to access
5147 * the board, but request the region anyway.
5149 * 'shp->n_io_port' is not referenced, because it may be truncated.
5152 "advansys_detect: request_region port 0x%lx, len 0x%x\n",
5153 (ulong) shp->io_port, boardp->asc_n_io_port);
5154 if (request_region(shp->io_port, boardp->asc_n_io_port,
5155 "advansys") == NULL) {
5157 "advansys_detect: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
5158 boardp->id, (ulong) shp->io_port, boardp->asc_n_io_port);
5159 #ifdef CONFIG_PROC_FS
5160 kfree(boardp->prtbuf);
5161 #endif /* CONFIG_PROC_FS */
5162 scsi_unregister(shp);
5167 /* Register DMA Channel for Narrow boards. */
5168 shp->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
5170 if (ASC_NARROW_BOARD(boardp)) {
5171 /* Register DMA channel for ISA bus. */
5172 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5173 shp->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
5175 request_dma(shp->dma_channel, "advansys")) != 0) {
5177 "advansys_detect: board %d: request_dma() %d failed %d\n",
5178 boardp->id, shp->dma_channel, ret);
5179 release_region(shp->io_port, boardp->asc_n_io_port);
5180 #ifdef CONFIG_PROC_FS
5181 kfree(boardp->prtbuf);
5182 #endif /* CONFIG_PROC_FS */
5183 scsi_unregister(shp);
5187 AscEnableIsaDma(shp->dma_channel);
5190 #endif /* CONFIG_ISA */
5192 /* Register IRQ Number. */
5193 ASC_DBG1(2, "advansys_detect: request_irq() %d\n", shp->irq);
5195 * If request_irq() fails with the SA_INTERRUPT flag set,
5196 * then try again without the SA_INTERRUPT flag set. This
5197 * allows IRQ sharing to work even with other drivers that
5198 * do not set the SA_INTERRUPT flag.
5200 * If SA_INTERRUPT is not set, then interrupts are enabled
5201 * before the driver interrupt function is called.
5203 if (((ret = request_irq(shp->irq, advansys_interrupt,
5204 SA_INTERRUPT | (share_irq == TRUE ? SA_SHIRQ : 0),
5205 "advansys", boardp)) != 0) &&
5206 ((ret = request_irq(shp->irq, advansys_interrupt,
5207 (share_irq == TRUE ? SA_SHIRQ : 0),
5208 "advansys", boardp)) != 0))
5210 if (ret == -EBUSY) {
5212 "advansys_detect: board %d: request_irq(): IRQ 0x%x already in use.\n",
5213 boardp->id, shp->irq);
5214 } else if (ret == -EINVAL) {
5216 "advansys_detect: board %d: request_irq(): IRQ 0x%x not valid.\n",
5217 boardp->id, shp->irq);
5220 "advansys_detect: board %d: request_irq(): IRQ 0x%x failed with %d\n",
5221 boardp->id, shp->irq, ret);
5223 release_region(shp->io_port, boardp->asc_n_io_port);
5224 iounmap(boardp->ioremap_addr);
5225 if (shp->dma_channel != NO_ISA_DMA) {
5226 free_dma(shp->dma_channel);
5228 #ifdef CONFIG_PROC_FS
5229 kfree(boardp->prtbuf);
5230 #endif /* CONFIG_PROC_FS */
5231 scsi_unregister(shp);
5237 * Initialize board RISC chip and enable interrupts.
5239 if (ASC_NARROW_BOARD(boardp)) {
5240 ASC_DBG(2, "advansys_detect: AscInitAsc1000Driver()\n");
5241 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
5242 err_code = asc_dvc_varp->err_code;
5244 if (warn_code || err_code) {
5246 "advansys_detect: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
5247 boardp->id, asc_dvc_varp->init_state,
5248 warn_code, err_code);
5253 adv_req_t *reqp = NULL;
5257 * Allocate buffer carrier structures. The total size
5258 * is about 4 KB, so allocate all at once.
5261 (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
5262 ASC_DBG1(1, "advansys_detect: carrp 0x%lx\n", (ulong) carrp);
5264 if (carrp == NULL) {
5269 * Allocate up to 'max_host_qng' request structures for
5270 * the Wide board. The total size is about 16 KB, so
5271 * allocate all at once. If the allocation fails decrement
5274 for (req_cnt = adv_dvc_varp->max_host_qng;
5275 req_cnt > 0; req_cnt--) {
5277 reqp = (adv_req_t *)
5278 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
5281 "advansys_detect: reqp 0x%lx, req_cnt %d, bytes %lu\n",
5282 (ulong) reqp, req_cnt,
5283 (ulong) sizeof(adv_req_t) * req_cnt);
5295 * Allocate up to ADV_TOT_SG_BLOCK request structures for
5296 * the Wide board. Each structure is about 136 bytes.
5298 boardp->adv_sgblkp = NULL;
5299 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
5301 sgp = (adv_sgblk_t *)
5302 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
5308 sgp->next_sgblkp = boardp->adv_sgblkp;
5309 boardp->adv_sgblkp = sgp;
5313 "advansys_detect: sg_cnt %d * %u = %u bytes\n",
5314 sg_cnt, sizeof(adv_sgblk_t),
5315 (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
5318 * If no request structures or scatter-gather structures could
5319 * be allocated, then return an error. Otherwise continue with
5326 "advansys_detect: board %d error: failed to kmalloc() carrier buffer.\n",
5328 err_code = ADV_ERROR;
5329 } else if (reqp == NULL) {
5332 "advansys_detect: board %d error: failed to kmalloc() adv_req_t buffer.\n",
5334 err_code = ADV_ERROR;
5335 } else if (boardp->adv_sgblkp == NULL) {
5339 "advansys_detect: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
5341 err_code = ADV_ERROR;
5344 /* Save carrier buffer pointer. */
5345 boardp->orig_carrp = carrp;
5348 * Save original pointer for kfree() in case the
5349 * driver is built as a module and can be unloaded.
5351 boardp->orig_reqp = reqp;
5353 adv_dvc_varp->carrier_buf = carrp;
5356 * Point 'adv_reqp' to the request structures and
5357 * link them together.
5360 reqp[req_cnt].next_reqp = NULL;
5361 for (; req_cnt > 0; req_cnt--) {
5362 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
5364 boardp->adv_reqp = &reqp[0];
5366 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5369 "advansys_detect: AdvInitAsc3550Driver()\n");
5370 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
5371 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5373 "advansys_detect: AdvInitAsc38C0800Driver()\n");
5374 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
5377 "advansys_detect: AdvInitAsc38C1600Driver()\n");
5378 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
5380 err_code = adv_dvc_varp->err_code;
5382 if (warn_code || err_code) {
5384 "advansys_detect: board %d error: warn 0x%x, error 0x%x\n",
5385 boardp->id, warn_code, err_code);
5390 if (err_code != 0) {
5391 release_region(shp->io_port, boardp->asc_n_io_port);
5392 if (ASC_WIDE_BOARD(boardp)) {
5393 iounmap(boardp->ioremap_addr);
5394 kfree(boardp->orig_carrp);
5395 boardp->orig_carrp = NULL;
5396 if (boardp->orig_reqp) {
5397 kfree(boardp->orig_reqp);
5398 boardp->orig_reqp = boardp->adv_reqp = NULL;
5400 while ((sgp = boardp->adv_sgblkp) != NULL)
5402 boardp->adv_sgblkp = sgp->next_sgblkp;
5406 if (shp->dma_channel != NO_ISA_DMA) {
5407 free_dma(shp->dma_channel);
5409 #ifdef CONFIG_PROC_FS
5410 kfree(boardp->prtbuf);
5411 #endif /* CONFIG_PROC_FS */
5412 free_irq(shp->irq, boardp);
5413 scsi_unregister(shp);
5417 ASC_DBG_PRT_SCSI_HOST(2, shp);
5421 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n", asc_board_count);
5422 return asc_board_count;
5426 * advansys_release()
5428 * Release resources allocated for a single AdvanSys adapter.
5431 advansys_release(struct Scsi_Host *shp)
5433 asc_board_t *boardp;
5435 ASC_DBG(1, "advansys_release: begin\n");
5436 boardp = ASC_BOARDP(shp);
5437 free_irq(shp->irq, boardp);
5438 if (shp->dma_channel != NO_ISA_DMA) {
5439 ASC_DBG(1, "advansys_release: free_dma()\n");
5440 free_dma(shp->dma_channel);
5442 release_region(shp->io_port, boardp->asc_n_io_port);
5443 if (ASC_WIDE_BOARD(boardp)) {
5444 adv_sgblk_t *sgp = NULL;
5446 iounmap(boardp->ioremap_addr);
5447 kfree(boardp->orig_carrp);
5448 boardp->orig_carrp = NULL;
5449 if (boardp->orig_reqp) {
5450 kfree(boardp->orig_reqp);
5451 boardp->orig_reqp = boardp->adv_reqp = NULL;
5453 while ((sgp = boardp->adv_sgblkp) != NULL)
5455 boardp->adv_sgblkp = sgp->next_sgblkp;
5459 #ifdef CONFIG_PROC_FS
5460 ASC_ASSERT(boardp->prtbuf != NULL);
5461 kfree(boardp->prtbuf);
5462 #endif /* CONFIG_PROC_FS */
5463 scsi_unregister(shp);
5464 ASC_DBG(1, "advansys_release: end\n");
5471 * Return suitable for printing on the console with the argument
5472 * adapter's configuration information.
5474 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
5475 * otherwise the static 'info' array will be overrun.
5478 advansys_info(struct Scsi_Host *shp)
5480 static char info[ASC_INFO_SIZE];
5481 asc_board_t *boardp;
5482 ASC_DVC_VAR *asc_dvc_varp;
5483 ADV_DVC_VAR *adv_dvc_varp;
5486 char *widename = NULL;
5488 boardp = ASC_BOARDP(shp);
5489 if (ASC_NARROW_BOARD(boardp)) {
5490 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5491 ASC_DBG(1, "advansys_info: begin\n");
5492 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5493 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == ASC_IS_ISAPNP) {
5494 busname = "ISA PnP";
5498 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5500 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
5501 ASC_VERSION, busname,
5502 (ulong) shp->io_port,
5503 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5504 shp->irq, shp->dma_channel);
5506 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
5508 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
5510 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
5511 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
5512 == ASC_IS_PCI_ULTRA) {
5513 busname = "PCI Ultra";
5519 ASC_PRINT2( "advansys_info: board %d: unknown bus type %d\n",
5520 boardp->id, asc_dvc_varp->bus_type);
5522 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5524 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
5525 ASC_VERSION, busname,
5526 (ulong) shp->io_port,
5527 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5532 * Wide Adapter Information
5534 * Memory-mapped I/O is used instead of I/O space to access
5535 * the adapter, but display the I/O Port range. The Memory
5536 * I/O address is displayed through the driver /proc file.
5538 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5539 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5541 iolen = ADV_3550_IOLEN;
5542 widename = "Ultra-Wide";
5543 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
5545 iolen = ADV_38C0800_IOLEN;
5546 widename = "Ultra2-Wide";
5549 iolen = ADV_38C1600_IOLEN;
5550 widename = "Ultra3-Wide";
5552 sprintf(info, "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
5555 (ulong) adv_dvc_varp->iop_base,
5556 (ulong) adv_dvc_varp->iop_base + iolen - 1,
5559 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
5560 ASC_DBG(1, "advansys_info: end\n");
5565 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
5567 * This function always returns 0. Command return status is saved
5568 * in the 'scp' result field.
5571 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
5573 struct Scsi_Host *shp;
5574 asc_board_t *boardp;
5576 struct scsi_cmnd *done_scp;
5578 shp = scp->device->host;
5579 boardp = ASC_BOARDP(shp);
5580 ASC_STATS(shp, queuecommand);
5582 /* host_lock taken by mid-level prior to call but need to protect */
5583 /* against own ISR */
5584 spin_lock_irqsave(&boardp->lock, flags);
5587 * Block new commands while handling a reset or abort request.
5589 if (boardp->flags & ASC_HOST_IN_RESET) {
5591 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
5593 scp->result = HOST_BYTE(DID_RESET);
5596 * Add blocked requests to the board's 'done' queue. The queued
5597 * requests will be completed at the end of the abort or reset
5600 asc_enqueue(&boardp->done, scp, ASC_BACK);
5601 spin_unlock_irqrestore(&boardp->lock, flags);
5606 * Attempt to execute any waiting commands for the board.
5608 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
5610 "advansys_queuecommand: before asc_execute_queue() waiting\n");
5611 asc_execute_queue(&boardp->waiting);
5615 * Save the function pointer to Linux mid-level 'done' function
5616 * and attempt to execute the command.
5618 * If ASC_NOERROR is returned the request has been added to the
5619 * board's 'active' queue and will be completed by the interrupt
5622 * If ASC_BUSY is returned add the request to the board's per
5623 * target waiting list. This is the first time the request has
5624 * been tried. Add it to the back of the waiting list. It will be
5627 * If an error occurred, the request will have been placed on the
5628 * board's 'done' queue and must be completed before returning.
5630 scp->scsi_done = done;
5631 switch (asc_execute_scsi_cmnd(scp)) {
5635 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
5639 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
5640 /* Interrupts could be enabled here. */
5641 asc_scsi_done_list(done_scp);
5644 spin_unlock_irqrestore(&boardp->lock, flags);
5652 * Reset the bus associated with the command 'scp'.
5654 * This function runs its own thread. Interrupts must be blocked but
5655 * sleeping is allowed and no locking other than for host structures is
5656 * required. Returns SUCCESS or FAILED.
5659 advansys_reset(struct scsi_cmnd *scp)
5661 struct Scsi_Host *shp;
5662 asc_board_t *boardp;
5663 ASC_DVC_VAR *asc_dvc_varp;
5664 ADV_DVC_VAR *adv_dvc_varp;
5666 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5667 struct scsi_cmnd *tscp, *new_last_scp;
5671 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong) scp);
5673 #ifdef ADVANSYS_STATS
5674 if (scp->device->host != NULL) {
5675 ASC_STATS(scp->device->host, reset);
5677 #endif /* ADVANSYS_STATS */
5679 if ((shp = scp->device->host) == NULL) {
5680 scp->result = HOST_BYTE(DID_ERROR);
5684 boardp = ASC_BOARDP(shp);
5686 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
5689 * Check for re-entrancy.
5691 spin_lock_irqsave(&boardp->lock, flags);
5692 if (boardp->flags & ASC_HOST_IN_RESET) {
5693 spin_unlock_irqrestore(&boardp->lock, flags);
5696 boardp->flags |= ASC_HOST_IN_RESET;
5697 spin_unlock_irqrestore(&boardp->lock, flags);
5699 if (ASC_NARROW_BOARD(boardp)) {
5703 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5706 * Reset the chip and SCSI bus.
5708 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
5709 status = AscInitAsc1000Driver(asc_dvc_varp);
5711 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
5712 if (asc_dvc_varp->err_code) {
5714 "advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
5715 boardp->id, asc_dvc_varp->err_code);
5717 } else if (status) {
5719 "advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
5720 boardp->id, status);
5723 "advansys_reset: board %d: SCSI bus reset successful.\n",
5727 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
5728 spin_lock_irqsave(&boardp->lock, flags);
5734 * If the suggest reset bus flags are set, then reset the bus.
5735 * Otherwise only reset the device.
5737 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5740 * Reset the target's SCSI bus.
5742 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
5743 switch (AdvResetChipAndSB(adv_dvc_varp)) {
5745 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset successful.\n",
5750 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset error.\n",
5755 spin_lock_irqsave(&boardp->lock, flags);
5756 (void) AdvISR(adv_dvc_varp);
5758 /* Board lock is held. */
5761 * Dequeue all board 'done' requests. A pointer to the last request
5762 * is returned in 'last_scp'.
5764 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
5767 * Dequeue all board 'active' requests for all devices and set
5768 * the request status to DID_RESET. A pointer to the last request
5769 * is returned in 'last_scp'.
5771 if (done_scp == NULL) {
5772 done_scp = asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
5773 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5774 tscp->result = HOST_BYTE(DID_RESET);
5777 /* Append to 'done_scp' at the end with 'last_scp'. */
5778 ASC_ASSERT(last_scp != NULL);
5779 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5780 &boardp->active, &new_last_scp, ASC_TID_ALL);
5781 if (new_last_scp != NULL) {
5782 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5783 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5784 tscp->result = HOST_BYTE(DID_RESET);
5786 last_scp = new_last_scp;
5791 * Dequeue all 'waiting' requests and set the request status
5794 if (done_scp == NULL) {
5795 done_scp = asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
5796 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5797 tscp->result = HOST_BYTE(DID_RESET);
5800 /* Append to 'done_scp' at the end with 'last_scp'. */
5801 ASC_ASSERT(last_scp != NULL);
5802 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5803 &boardp->waiting, &new_last_scp, ASC_TID_ALL);
5804 if (new_last_scp != NULL) {
5805 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5806 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5807 tscp->result = HOST_BYTE(DID_RESET);
5809 last_scp = new_last_scp;
5813 /* Save the time of the most recently completed reset. */
5814 boardp->last_reset = jiffies;
5816 /* Clear reset flag. */
5817 boardp->flags &= ~ASC_HOST_IN_RESET;
5818 spin_unlock_irqrestore(&boardp->lock, flags);
5821 * Complete all the 'done_scp' requests.
5823 if (done_scp != NULL) {
5824 asc_scsi_done_list(done_scp);
5827 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
5833 * advansys_biosparam()
5835 * Translate disk drive geometry if the "BIOS greater than 1 GB"
5836 * support is enabled for a drive.
5838 * ip (information pointer) is an int array with the following definition:
5844 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
5845 sector_t capacity, int ip[])
5847 asc_board_t *boardp;
5849 ASC_DBG(1, "advansys_biosparam: begin\n");
5850 ASC_STATS(sdev->host, biosparam);
5851 boardp = ASC_BOARDP(sdev->host);
5852 if (ASC_NARROW_BOARD(boardp)) {
5853 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
5854 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
5862 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
5863 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
5871 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
5872 ASC_DBG(1, "advansys_biosparam: end\n");
5879 * This function is called from init/main.c at boot time.
5880 * It it passed LILO parameters that can be set from the
5881 * LILO command line or in /etc/lilo.conf.
5883 * It is used by the AdvanSys driver to either disable I/O
5884 * port scanning or to limit scanning to 1 - 4 I/O ports.
5885 * Regardless of the option setting EISA and PCI boards
5886 * will still be searched for and detected. This option
5887 * only affects searching for ISA and VL boards.
5889 * If ADVANSYS_DEBUG is defined the driver debug level may
5890 * be set using the 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port.
5893 * 1. Eliminate I/O port scanning:
5894 * boot: linux advansys=
5896 * boot: linux advansys=0x0
5897 * 2. Limit I/O port scanning to one I/O port:
5898 * boot: linux advansys=0x110
5899 * 3. Limit I/O port scanning to four I/O ports:
5900 * boot: linux advansys=0x110,0x210,0x230,0x330
5901 * 4. If ADVANSYS_DEBUG, limit I/O port scanning to four I/O ports and
5902 * set the driver debug level to 2.
5903 * boot: linux advansys=0x110,0x210,0x230,0x330,0xdeb2
5905 * ints[0] - number of arguments
5906 * ints[1] - first argument
5907 * ints[2] - second argument
5911 advansys_setup(char *str, int *ints)
5915 if (asc_iopflag == ASC_TRUE) {
5916 printk("AdvanSys SCSI: 'advansys' LILO option may appear only once\n");
5920 asc_iopflag = ASC_TRUE;
5922 if (ints[0] > ASC_NUM_IOPORT_PROBE) {
5923 #ifdef ADVANSYS_DEBUG
5924 if ((ints[0] == ASC_NUM_IOPORT_PROBE + 1) &&
5925 (ints[ASC_NUM_IOPORT_PROBE + 1] >> 4 == 0xdeb)) {
5926 asc_dbglvl = ints[ASC_NUM_IOPORT_PROBE + 1] & 0xf;
5928 #endif /* ADVANSYS_DEBUG */
5929 printk("AdvanSys SCSI: only %d I/O ports accepted\n",
5930 ASC_NUM_IOPORT_PROBE);
5931 #ifdef ADVANSYS_DEBUG
5933 #endif /* ADVANSYS_DEBUG */
5936 #ifdef ADVANSYS_DEBUG
5937 ASC_DBG1(1, "advansys_setup: ints[0] %d\n", ints[0]);
5938 for (i = 1; i < ints[0]; i++) {
5939 ASC_DBG2(1, " ints[%d] 0x%x", i, ints[i]);
5942 #endif /* ADVANSYS_DEBUG */
5944 for (i = 1; i <= ints[0] && i <= ASC_NUM_IOPORT_PROBE; i++) {
5945 asc_ioport[i-1] = ints[i];
5946 ASC_DBG2(1, "advansys_setup: asc_ioport[%d] 0x%x\n",
5947 i - 1, asc_ioport[i-1]);
5953 * --- Loadable Driver Support
5956 static struct scsi_host_template driver_template = {
5957 .proc_name = "advansys",
5958 #ifdef CONFIG_PROC_FS
5959 .proc_info = advansys_proc_info,
5962 .detect = advansys_detect,
5963 .release = advansys_release,
5964 .info = advansys_info,
5965 .queuecommand = advansys_queuecommand,
5966 .eh_bus_reset_handler = advansys_reset,
5967 .bios_param = advansys_biosparam,
5968 .slave_configure = advansys_slave_configure,
5970 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
5971 * must be set. The flag will be cleared in advansys_detect for non-ISA
5972 * adapters. Refer to the comment in scsi_module.c for more information.
5974 .unchecked_isa_dma = 1,
5976 * All adapters controlled by this driver are capable of large
5977 * scatter-gather lists. According to the mid-level SCSI documentation
5978 * this obviates any performance gain provided by setting
5979 * 'use_clustering'. But empirically while CPU utilization is increased
5980 * by enabling clustering, I/O throughput increases as well.
5982 .use_clustering = ENABLE_CLUSTERING,
5984 #include "scsi_module.c"
5988 * --- Miscellaneous Driver Functions
5992 * First-level interrupt handler.
5994 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
5995 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
5996 * is not referenced. 'dev_id' could be used to identify an interrupt passed
5997 * to the AdvanSys driver which is for a device sharing an interrupt with
5998 * an AdvanSys adapter.
6001 advansys_interrupt(int irq, void *dev_id, struct pt_regs *regs)
6005 asc_board_t *boardp;
6006 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
6007 struct scsi_cmnd *new_last_scp;
6008 struct Scsi_Host *shp;
6010 ASC_DBG(1, "advansys_interrupt: begin\n");
6013 * Check for interrupts on all boards.
6014 * AscISR() will call asc_isr_callback().
6016 for (i = 0; i < asc_board_count; i++) {
6018 boardp = ASC_BOARDP(shp);
6019 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
6021 spin_lock_irqsave(&boardp->lock, flags);
6022 if (ASC_NARROW_BOARD(boardp)) {
6026 if (AscIsIntPending(shp->io_port)) {
6027 ASC_STATS(shp, interrupt);
6028 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
6029 AscISR(&boardp->dvc_var.asc_dvc_var);
6035 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
6036 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
6037 ASC_STATS(shp, interrupt);
6042 * Start waiting requests and create a list of completed requests.
6044 * If a reset request is being performed for the board, the reset
6045 * handler will complete pending requests after it has completed.
6047 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
6048 ASC_DBG2(1, "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
6049 (ulong) done_scp, (ulong) last_scp);
6051 /* Start any waiting commands for the board. */
6052 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
6053 ASC_DBG(1, "advansys_interrupt: before asc_execute_queue()\n");
6054 asc_execute_queue(&boardp->waiting);
6058 * Add to the list of requests that must be completed.
6060 * 'done_scp' will always be NULL on the first iteration
6061 * of this loop. 'last_scp' is set at the same time as
6064 if (done_scp == NULL) {
6065 done_scp = asc_dequeue_list(&boardp->done, &last_scp,
6068 ASC_ASSERT(last_scp != NULL);
6069 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
6070 &boardp->done, &new_last_scp, ASC_TID_ALL);
6071 if (new_last_scp != NULL) {
6072 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
6073 last_scp = new_last_scp;
6077 spin_unlock_irqrestore(&boardp->lock, flags);
6081 * If interrupts were enabled on entry, then they
6082 * are now enabled here.
6084 * Complete all requests on the done list.
6087 asc_scsi_done_list(done_scp);
6089 ASC_DBG(1, "advansys_interrupt: end\n");
6094 * Set the number of commands to queue per device for the
6095 * specified host adapter.
6098 advansys_slave_configure(struct scsi_device *device)
6100 asc_board_t *boardp;
6102 boardp = ASC_BOARDP(device->host);
6103 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
6105 * Save a pointer to the device and set its initial/maximum
6106 * queue depth. Only save the pointer for a lun0 dev though.
6108 if(device->lun == 0)
6109 boardp->device[device->id] = device;
6110 if(device->tagged_supported) {
6111 if (ASC_NARROW_BOARD(boardp)) {
6112 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6113 boardp->dvc_var.asc_dvc_var.max_dvc_qng[device->id]);
6115 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6116 boardp->dvc_var.adv_dvc_var.max_dvc_qng);
6119 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
6121 ASC_DBG4(1, "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
6122 (ulong) device, (ulong) boardp, device->id, device->queue_depth);
6127 * Complete all requests on the singly linked list pointed
6130 * Interrupts can be enabled on entry.
6133 asc_scsi_done_list(struct scsi_cmnd *scp)
6135 struct scsi_cmnd *tscp;
6137 ASC_DBG(2, "asc_scsi_done_list: begin\n");
6138 while (scp != NULL) {
6139 asc_board_t *boardp;
6142 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong) scp);
6143 tscp = REQPNEXT(scp);
6144 scp->host_scribble = NULL;
6146 boardp = ASC_BOARDP(scp->device->host);
6148 if (ASC_NARROW_BOARD(boardp))
6149 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6151 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6154 dma_unmap_sg(dev, (struct scatterlist *)scp->request_buffer,
6155 scp->use_sg, scp->sc_data_direction);
6156 else if (scp->request_bufflen)
6157 dma_unmap_single(dev, scp->SCp.dma_handle,
6158 scp->request_bufflen, scp->sc_data_direction);
6160 ASC_STATS(scp->device->host, done);
6161 ASC_ASSERT(scp->scsi_done != NULL);
6163 scp->scsi_done(scp);
6167 ASC_DBG(2, "asc_scsi_done_list: done\n");
6172 * Execute a single 'Scsi_Cmnd'.
6174 * The function 'done' is called when the request has been completed.
6178 * host - board controlling device
6179 * device - device to send command
6180 * target - target of device
6181 * lun - lun of device
6182 * cmd_len - length of SCSI CDB
6183 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
6184 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
6186 * if (use_sg == 0) {
6187 * request_buffer - buffer address for request
6188 * request_bufflen - length of request buffer
6190 * request_buffer - pointer to scatterlist structure
6193 * sense_buffer - sense command buffer
6195 * result (4 bytes of an int):
6197 * 0 SCSI Status Byte Code
6198 * 1 SCSI One Byte Message Code
6200 * 3 Mid-Level Error Code
6202 * host driver fields:
6203 * SCp - Scsi_Pointer used for command processing status
6204 * scsi_done - used to save caller's done function
6205 * host_scribble - used for pointer to another struct scsi_cmnd
6207 * If this function returns ASC_NOERROR the request has been enqueued
6208 * on the board's 'active' queue and will be completed from the
6209 * interrupt handler.
6211 * If this function returns ASC_NOERROR the request has been enqueued
6212 * on the board's 'done' queue and must be completed by the caller.
6214 * If ASC_BUSY is returned the request will be enqueued by the
6215 * caller on the target's waiting queue and re-tried later.
6218 asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
6220 asc_board_t *boardp;
6221 ASC_DVC_VAR *asc_dvc_varp;
6222 ADV_DVC_VAR *adv_dvc_varp;
6223 ADV_SCSI_REQ_Q *adv_scsiqp;
6224 struct scsi_device *device;
6227 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
6228 (ulong) scp, (ulong) scp->scsi_done);
6230 boardp = ASC_BOARDP(scp->device->host);
6231 device = boardp->device[scp->device->id];
6233 if (ASC_NARROW_BOARD(boardp)) {
6235 * Build and execute Narrow Board request.
6238 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6241 * Build Asc Library request structure using the
6242 * global structures 'asc_scsi_req' and 'asc_sg_head'.
6244 * If an error is returned, then the request has been
6245 * queued on the board done queue. It will be completed
6248 * asc_build_req() can not return ASC_BUSY.
6250 if (asc_build_req(boardp, scp) == ASC_ERROR) {
6251 ASC_STATS(scp->device->host, build_error);
6256 * Execute the command. If there is no error, add the command
6257 * to the active queue.
6259 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
6261 ASC_STATS(scp->device->host, exe_noerror);
6263 * Increment monotonically increasing per device successful
6264 * request counter. Wrapping doesn't matter.
6266 boardp->reqcnt[scp->device->id]++;
6267 asc_enqueue(&boardp->active, scp, ASC_BACK);
6269 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
6273 * Caller will enqueue request on the target's waiting queue
6276 ASC_STATS(scp->device->host, exe_busy);
6280 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6281 boardp->id, asc_dvc_varp->err_code);
6282 ASC_STATS(scp->device->host, exe_error);
6283 scp->result = HOST_BYTE(DID_ERROR);
6284 asc_enqueue(&boardp->done, scp, ASC_BACK);
6288 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
6289 boardp->id, asc_dvc_varp->err_code);
6290 ASC_STATS(scp->device->host, exe_unknown);
6291 scp->result = HOST_BYTE(DID_ERROR);
6292 asc_enqueue(&boardp->done, scp, ASC_BACK);
6297 * Build and execute Wide Board request.
6299 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6302 * Build and get a pointer to an Adv Library request structure.
6304 * If the request is successfully built then send it below,
6305 * otherwise return with an error.
6307 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
6309 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
6312 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
6314 * If busy is returned the request has not been enqueued.
6315 * It will be enqueued by the caller on the target's waiting
6316 * queue and retried later.
6318 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
6319 * count wide board busy conditions. They are updated in
6320 * adv_build_req and adv_get_sglist, respectively.
6325 * If an error is returned, then the request has been
6326 * queued on the board done queue. It will be completed
6330 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
6331 ASC_STATS(scp->device->host, build_error);
6336 * Execute the command. If there is no error, add the command
6337 * to the active queue.
6339 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
6341 ASC_STATS(scp->device->host, exe_noerror);
6343 * Increment monotonically increasing per device successful
6344 * request counter. Wrapping doesn't matter.
6346 boardp->reqcnt[scp->device->id]++;
6347 asc_enqueue(&boardp->active, scp, ASC_BACK);
6349 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
6353 * Caller will enqueue request on the target's waiting queue
6356 ASC_STATS(scp->device->host, exe_busy);
6360 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6361 boardp->id, adv_dvc_varp->err_code);
6362 ASC_STATS(scp->device->host, exe_error);
6363 scp->result = HOST_BYTE(DID_ERROR);
6364 asc_enqueue(&boardp->done, scp, ASC_BACK);
6368 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
6369 boardp->id, adv_dvc_varp->err_code);
6370 ASC_STATS(scp->device->host, exe_unknown);
6371 scp->result = HOST_BYTE(DID_ERROR);
6372 asc_enqueue(&boardp->done, scp, ASC_BACK);
6377 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
6382 * Build a request structure for the Asc Library (Narrow Board).
6384 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
6385 * used to build the request.
6387 * If an error occurs, then queue the request on the board done
6388 * queue and return ASC_ERROR.
6391 asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
6393 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6396 * Mutually exclusive access is required to 'asc_scsi_q' and
6397 * 'asc_sg_head' until after the request is started.
6399 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
6402 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
6404 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
6407 * Build the ASC_SCSI_Q request.
6409 * For narrow boards a CDB length maximum of 12 bytes
6412 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
6414 "asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
6415 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
6416 scp->result = HOST_BYTE(DID_ERROR);
6417 asc_enqueue(&boardp->done, scp, ASC_BACK);
6420 asc_scsi_q.cdbptr = &scp->cmnd[0];
6421 asc_scsi_q.q2.cdb_len = scp->cmd_len;
6422 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
6423 asc_scsi_q.q1.target_lun = scp->device->lun;
6424 asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
6425 asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6426 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
6429 * If there are any outstanding requests for the current target,
6430 * then every 255th request send an ORDERED request. This heuristic
6431 * tries to retain the benefit of request sorting while preventing
6432 * request starvation. 255 is the max number of tags or pending commands
6433 * a device may have outstanding.
6435 * The request count is incremented below for every successfully
6439 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
6440 (boardp->reqcnt[scp->device->id] % 255) == 0) {
6441 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
6443 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
6447 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
6450 if (scp->use_sg == 0) {
6452 * CDB request of single contiguous buffer.
6454 ASC_STATS(scp->device->host, cont_cnt);
6455 scp->SCp.dma_handle = scp->request_bufflen ?
6456 dma_map_single(dev, scp->request_buffer,
6457 scp->request_bufflen, scp->sc_data_direction) : 0;
6458 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
6459 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
6460 ASC_STATS_ADD(scp->device->host, cont_xfer,
6461 ASC_CEILING(scp->request_bufflen, 512));
6462 asc_scsi_q.q1.sg_queue_cnt = 0;
6463 asc_scsi_q.sg_head = NULL;
6466 * CDB scatter-gather request list.
6470 struct scatterlist *slp;
6472 slp = (struct scatterlist *)scp->request_buffer;
6473 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6475 if (use_sg > scp->device->host->sg_tablesize) {
6477 "asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
6478 boardp->id, use_sg, scp->device->host->sg_tablesize);
6479 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6480 scp->result = HOST_BYTE(DID_ERROR);
6481 asc_enqueue(&boardp->done, scp, ASC_BACK);
6485 ASC_STATS(scp->device->host, sg_cnt);
6488 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
6489 * structure to point to it.
6491 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
6493 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
6494 asc_scsi_q.sg_head = &asc_sg_head;
6495 asc_scsi_q.q1.data_cnt = 0;
6496 asc_scsi_q.q1.data_addr = 0;
6497 /* This is a byte value, otherwise it would need to be swapped. */
6498 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
6499 ASC_STATS_ADD(scp->device->host, sg_elem, asc_sg_head.entry_cnt);
6502 * Convert scatter-gather list into ASC_SG_HEAD list.
6504 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
6505 asc_sg_head.sg_list[sgcnt].addr = cpu_to_le32(sg_dma_address(slp));
6506 asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(sg_dma_len(slp));
6507 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6511 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
6512 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6518 * Build a request structure for the Adv Library (Wide Board).
6520 * If an adv_req_t can not be allocated to issue the request,
6521 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
6523 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
6524 * microcode for DMA addresses or math operations are byte swapped
6525 * to little-endian order.
6528 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
6529 ADV_SCSI_REQ_Q **adv_scsiqpp)
6532 ADV_SCSI_REQ_Q *scsiqp;
6535 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6538 * Allocate an adv_req_t structure from the board to execute
6541 if (boardp->adv_reqp == NULL) {
6542 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
6543 ASC_STATS(scp->device->host, adv_build_noreq);
6546 reqp = boardp->adv_reqp;
6547 boardp->adv_reqp = reqp->next_reqp;
6548 reqp->next_reqp = NULL;
6552 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
6554 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6557 * Initialize the structure.
6559 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
6562 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
6564 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
6567 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
6572 * Build the ADV_SCSI_REQ_Q request.
6576 * Set CDB length and copy it to the request structure.
6577 * For wide boards a CDB length maximum of 16 bytes
6580 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
6582 "adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
6583 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
6584 scp->result = HOST_BYTE(DID_ERROR);
6585 asc_enqueue(&boardp->done, scp, ASC_BACK);
6588 scsiqp->cdb_len = scp->cmd_len;
6589 /* Copy first 12 CDB bytes to cdb[]. */
6590 for (i = 0; i < scp->cmd_len && i < 12; i++) {
6591 scsiqp->cdb[i] = scp->cmnd[i];
6593 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
6594 for (; i < scp->cmd_len; i++) {
6595 scsiqp->cdb16[i - 12] = scp->cmnd[i];
6598 scsiqp->target_id = scp->device->id;
6599 scsiqp->target_lun = scp->device->lun;
6601 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6602 scsiqp->sense_len = sizeof(scp->sense_buffer);
6605 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
6609 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6610 scsiqp->vdata_addr = scp->request_buffer;
6611 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
6613 if (scp->use_sg == 0) {
6615 * CDB request of single contiguous buffer.
6617 reqp->sgblkp = NULL;
6618 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6619 if (scp->request_bufflen) {
6620 scsiqp->vdata_addr = scp->request_buffer;
6621 scp->SCp.dma_handle =
6622 dma_map_single(dev, scp->request_buffer,
6623 scp->request_bufflen, scp->sc_data_direction);
6625 scsiqp->vdata_addr = 0;
6626 scp->SCp.dma_handle = 0;
6628 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
6629 scsiqp->sg_list_ptr = NULL;
6630 scsiqp->sg_real_addr = 0;
6631 ASC_STATS(scp->device->host, cont_cnt);
6632 ASC_STATS_ADD(scp->device->host, cont_xfer,
6633 ASC_CEILING(scp->request_bufflen, 512));
6636 * CDB scatter-gather request list.
6638 struct scatterlist *slp;
6641 slp = (struct scatterlist *)scp->request_buffer;
6642 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6644 if (use_sg > ADV_MAX_SG_LIST) {
6646 "adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
6647 boardp->id, use_sg, scp->device->host->sg_tablesize);
6648 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6649 scp->result = HOST_BYTE(DID_ERROR);
6650 asc_enqueue(&boardp->done, scp, ASC_BACK);
6653 * Free the 'adv_req_t' structure by adding it back to the
6656 reqp->next_reqp = boardp->adv_reqp;
6657 boardp->adv_reqp = reqp;
6662 if ((ret = adv_get_sglist(boardp, reqp, scp, use_sg)) != ADV_SUCCESS) {
6664 * Free the adv_req_t structure by adding it back to the
6667 reqp->next_reqp = boardp->adv_reqp;
6668 boardp->adv_reqp = reqp;
6673 ASC_STATS(scp->device->host, sg_cnt);
6674 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
6677 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6678 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6680 *adv_scsiqpp = scsiqp;
6686 * Build scatter-gather list for Adv Library (Wide Board).
6688 * Additional ADV_SG_BLOCK structures will need to be allocated
6689 * if the total number of scatter-gather elements exceeds
6690 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
6691 * assumed to be physically contiguous.
6694 * ADV_SUCCESS(1) - SG List successfully created
6695 * ADV_ERROR(-1) - SG List creation failed
6698 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, int use_sg)
6700 adv_sgblk_t *sgblkp;
6701 ADV_SCSI_REQ_Q *scsiqp;
6702 struct scatterlist *slp;
6704 ADV_SG_BLOCK *sg_block, *prev_sg_block;
6705 ADV_PADDR sg_block_paddr;
6708 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6709 slp = (struct scatterlist *) scp->request_buffer;
6710 sg_elem_cnt = use_sg;
6711 prev_sg_block = NULL;
6712 reqp->sgblkp = NULL;
6717 * Allocate a 'adv_sgblk_t' structure from the board free
6718 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
6719 * (15) scatter-gather elements.
6721 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
6722 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
6723 ASC_STATS(scp->device->host, adv_build_nosg);
6726 * Allocation failed. Free 'adv_sgblk_t' structures already
6727 * allocated for the request.
6729 while ((sgblkp = reqp->sgblkp) != NULL)
6731 /* Remove 'sgblkp' from the request list. */
6732 reqp->sgblkp = sgblkp->next_sgblkp;
6734 /* Add 'sgblkp' to the board free list. */
6735 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6736 boardp->adv_sgblkp = sgblkp;
6740 /* Complete 'adv_sgblk_t' board allocation. */
6741 boardp->adv_sgblkp = sgblkp->next_sgblkp;
6742 sgblkp->next_sgblkp = NULL;
6745 * Get 8 byte aligned virtual and physical addresses for
6746 * the allocated ADV_SG_BLOCK structure.
6748 sg_block = (ADV_SG_BLOCK *) ADV_8BALIGN(&sgblkp->sg_block);
6749 sg_block_paddr = virt_to_bus(sg_block);
6752 * Check if this is the first 'adv_sgblk_t' for the request.
6754 if (reqp->sgblkp == NULL)
6756 /* Request's first scatter-gather block. */
6757 reqp->sgblkp = sgblkp;
6760 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
6763 scsiqp->sg_list_ptr = sg_block;
6764 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
6767 /* Request's second or later scatter-gather block. */
6768 sgblkp->next_sgblkp = reqp->sgblkp;
6769 reqp->sgblkp = sgblkp;
6772 * Point the previous ADV_SG_BLOCK structure to
6773 * the newly allocated ADV_SG_BLOCK structure.
6775 ASC_ASSERT(prev_sg_block != NULL);
6776 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
6780 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
6782 sg_block->sg_list[i].sg_addr = cpu_to_le32(sg_dma_address(slp));
6783 sg_block->sg_list[i].sg_count = cpu_to_le32(sg_dma_len(slp));
6784 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6786 if (--sg_elem_cnt == 0)
6787 { /* Last ADV_SG_BLOCK and scatter-gather entry. */
6788 sg_block->sg_cnt = i + 1;
6789 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
6794 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
6795 prev_sg_block = sg_block;
6802 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6804 * Interrupt callback function for the Narrow SCSI Asc Library.
6807 asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6809 asc_board_t *boardp;
6810 struct scsi_cmnd *scp;
6811 struct Scsi_Host *shp;
6814 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
6815 (ulong) asc_dvc_varp, (ulong) qdonep);
6816 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6819 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6820 * command that has been completed.
6822 scp = (struct scsi_cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
6823 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong) scp);
6826 ASC_PRINT("asc_isr_callback: scp is NULL\n");
6829 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6832 * If the request's host pointer is not valid, display a
6833 * message and return.
6835 shp = scp->device->host;
6836 for (i = 0; i < asc_board_count; i++) {
6837 if (asc_host[i] == shp) {
6841 if (i == asc_board_count) {
6843 "asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
6844 (ulong) scp, (ulong) shp);
6848 ASC_STATS(shp, callback);
6849 ASC_DBG1(1, "asc_isr_callback: shp 0x%lx\n", (ulong) shp);
6852 * If the request isn't found on the active queue, it may
6853 * have been removed to handle a reset request.
6854 * Display a message and return.
6856 boardp = ASC_BOARDP(shp);
6857 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
6858 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
6860 "asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
6861 boardp->id, (ulong) scp);
6866 * 'qdonep' contains the command's ending status.
6868 switch (qdonep->d3.done_stat) {
6870 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
6874 * If an INQUIRY command completed successfully, then call
6875 * the AscInquiryHandling() function to set-up the device.
6877 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
6878 (scp->request_bufflen - qdonep->remain_bytes) >= 8)
6880 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
6881 (ASC_SCSI_INQUIRY *) scp->request_buffer);
6885 * Check for an underrun condition.
6887 * If there was no error and an underrun condition, then
6888 * then return the number of underrun bytes.
6890 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
6891 qdonep->remain_bytes <= scp->request_bufflen) {
6892 ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
6893 (unsigned) qdonep->remain_bytes);
6894 scp->resid = qdonep->remain_bytes;
6899 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
6900 switch (qdonep->d3.host_stat) {
6901 case QHSTA_NO_ERROR:
6902 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6903 ASC_DBG(2, "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
6904 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6905 sizeof(scp->sense_buffer));
6907 * Note: The 'status_byte()' macro used by target drivers
6908 * defined in scsi.h shifts the status byte returned by
6909 * host drivers right by 1 bit. This is why target drivers
6910 * also use right shifted status byte definitions. For
6911 * instance target drivers use CHECK_CONDITION, defined to
6912 * 0x1, instead of the SCSI defined check condition value
6913 * of 0x2. Host drivers are supposed to return the status
6914 * byte as it is defined by SCSI.
6916 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6917 STATUS_BYTE(qdonep->d3.scsi_stat);
6919 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6924 /* QHSTA error occurred */
6925 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
6926 qdonep->d3.host_stat);
6927 scp->result = HOST_BYTE(DID_BAD_TARGET);
6932 case QD_ABORTED_BY_HOST:
6933 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
6934 scp->result = HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.scsi_msg) |
6935 STATUS_BYTE(qdonep->d3.scsi_stat);
6939 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", qdonep->d3.done_stat);
6940 scp->result = HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.scsi_msg) |
6941 STATUS_BYTE(qdonep->d3.scsi_stat);
6946 * If the 'init_tidmask' bit isn't already set for the target and the
6947 * current request finished normally, then set the bit for the target
6948 * to indicate that a device is present.
6950 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6951 qdonep->d3.done_stat == QD_NO_ERROR &&
6952 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6953 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6957 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
6958 * function, add the command to the end of the board's done queue.
6959 * The done function for the command will be called from
6960 * advansys_interrupt().
6962 asc_enqueue(&boardp->done, scp, ASC_BACK);
6968 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6970 * Callback function for the Wide SCSI Adv Library.
6973 adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6975 asc_board_t *boardp;
6977 adv_sgblk_t *sgblkp;
6978 struct scsi_cmnd *scp;
6979 struct Scsi_Host *shp;
6984 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6985 (ulong) adv_dvc_varp, (ulong) scsiqp);
6986 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6989 * Get the adv_req_t structure for the command that has been
6990 * completed. The adv_req_t structure actually contains the
6991 * completed ADV_SCSI_REQ_Q structure.
6993 reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6994 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong) reqp);
6996 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
7001 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
7002 * command that has been completed.
7004 * Note: The adv_req_t request structure and adv_sgblk_t structure,
7005 * if any, are dropped, because a board structure pointer can not be
7009 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong) scp);
7011 ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
7014 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7017 * If the request's host pointer is not valid, display a message
7020 shp = scp->device->host;
7021 for (i = 0; i < asc_board_count; i++) {
7022 if (asc_host[i] == shp) {
7027 * Note: If the host structure is not found, the adv_req_t request
7028 * structure and adv_sgblk_t structure, if any, is dropped.
7030 if (i == asc_board_count) {
7032 "adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
7033 (ulong) scp, (ulong) shp);
7037 ASC_STATS(shp, callback);
7038 ASC_DBG1(1, "adv_isr_callback: shp 0x%lx\n", (ulong) shp);
7041 * If the request isn't found on the active queue, it may have been
7042 * removed to handle a reset request. Display a message and return.
7044 * Note: Because the structure may still be in use don't attempt
7045 * to free the adv_req_t and adv_sgblk_t, if any, structures.
7047 boardp = ASC_BOARDP(shp);
7048 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
7049 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
7051 "adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
7052 boardp->id, (ulong) scp);
7057 * 'done_status' contains the command's ending status.
7059 switch (scsiqp->done_status) {
7061 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
7065 * Check for an underrun condition.
7067 * If there was no error and an underrun condition, then
7068 * then return the number of underrun bytes.
7070 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
7071 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
7072 resid_cnt <= scp->request_bufflen) {
7073 ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
7075 scp->resid = resid_cnt;
7080 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
7081 switch (scsiqp->host_status) {
7082 case QHSTA_NO_ERROR:
7083 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
7084 ASC_DBG(2, "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
7085 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7086 sizeof(scp->sense_buffer));
7088 * Note: The 'status_byte()' macro used by target drivers
7089 * defined in scsi.h shifts the status byte returned by
7090 * host drivers right by 1 bit. This is why target drivers
7091 * also use right shifted status byte definitions. For
7092 * instance target drivers use CHECK_CONDITION, defined to
7093 * 0x1, instead of the SCSI defined check condition value
7094 * of 0x2. Host drivers are supposed to return the status
7095 * byte as it is defined by SCSI.
7097 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7098 STATUS_BYTE(scsiqp->scsi_status);
7100 scp->result = STATUS_BYTE(scsiqp->scsi_status);
7105 /* Some other QHSTA error occurred. */
7106 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
7107 scsiqp->host_status);
7108 scp->result = HOST_BYTE(DID_BAD_TARGET);
7113 case QD_ABORTED_BY_HOST:
7114 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
7115 scp->result = HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
7119 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", scsiqp->done_status);
7120 scp->result = HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
7125 * If the 'init_tidmask' bit isn't already set for the target and the
7126 * current request finished normally, then set the bit for the target
7127 * to indicate that a device is present.
7129 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7130 scsiqp->done_status == QD_NO_ERROR &&
7131 scsiqp->host_status == QHSTA_NO_ERROR) {
7132 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7136 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
7137 * function, add the command to the end of the board's done queue.
7138 * The done function for the command will be called from
7139 * advansys_interrupt().
7141 asc_enqueue(&boardp->done, scp, ASC_BACK);
7144 * Free all 'adv_sgblk_t' structures allocated for the request.
7146 while ((sgblkp = reqp->sgblkp) != NULL)
7148 /* Remove 'sgblkp' from the request list. */
7149 reqp->sgblkp = sgblkp->next_sgblkp;
7151 /* Add 'sgblkp' to the board free list. */
7152 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7153 boardp->adv_sgblkp = sgblkp;
7157 * Free the adv_req_t structure used with the command by adding
7158 * it back to the board free list.
7160 reqp->next_reqp = boardp->adv_reqp;
7161 boardp->adv_reqp = reqp;
7163 ASC_DBG(1, "adv_isr_callback: done\n");
7169 * adv_async_callback() - Adv Library asynchronous event callback function.
7172 adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
7176 case ADV_ASYNC_SCSI_BUS_RESET_DET:
7178 * The firmware detected a SCSI Bus reset.
7180 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
7183 case ADV_ASYNC_RDMA_FAILURE:
7185 * Handle RDMA failure by resetting the SCSI Bus and
7186 * possibly the chip if it is unresponsive. Log the error
7187 * with a unique code.
7189 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
7190 AdvResetChipAndSB(adv_dvc_varp);
7193 case ADV_HOST_SCSI_BUS_RESET:
7195 * Host generated SCSI bus reset occurred.
7197 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
7201 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
7207 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
7208 * to indicate a command is queued for the device.
7210 * 'flag' may be either ASC_FRONT or ASC_BACK.
7212 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7215 asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
7219 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
7220 (ulong) ascq, (ulong) reqp, flag);
7221 ASC_ASSERT(reqp != NULL);
7222 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
7223 tid = REQPTID(reqp);
7224 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7225 if (flag == ASC_FRONT) {
7226 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
7227 ascq->q_first[tid] = reqp;
7228 /* If the queue was empty, set the last pointer. */
7229 if (ascq->q_last[tid] == NULL) {
7230 ascq->q_last[tid] = reqp;
7232 } else { /* ASC_BACK */
7233 if (ascq->q_last[tid] != NULL) {
7234 ascq->q_last[tid]->host_scribble = (unsigned char *)reqp;
7236 ascq->q_last[tid] = reqp;
7237 reqp->host_scribble = NULL;
7238 /* If the queue was empty, set the first pointer. */
7239 if (ascq->q_first[tid] == NULL) {
7240 ascq->q_first[tid] = reqp;
7243 /* The queue has at least one entry, set its bit. */
7244 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
7245 #ifdef ADVANSYS_STATS
7246 /* Maintain request queue statistics. */
7247 ascq->q_tot_cnt[tid]++;
7248 ascq->q_cur_cnt[tid]++;
7249 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
7250 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
7251 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
7252 tid, ascq->q_max_cnt[tid]);
7254 REQPTIME(reqp) = REQTIMESTAMP();
7255 #endif /* ADVANSYS_STATS */
7256 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong) reqp);
7261 * Return first queued 'REQP' on the specified queue for
7262 * the specified target device. Clear the 'tidmask' bit for
7263 * the device if no more commands are left queued for it.
7265 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7268 asc_dequeue(asc_queue_t *ascq, int tid)
7272 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7273 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7274 if ((reqp = ascq->q_first[tid]) != NULL) {
7275 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
7276 ascq->q_first[tid] = REQPNEXT(reqp);
7277 /* If the queue is empty, clear its bit and the last pointer. */
7278 if (ascq->q_first[tid] == NULL) {
7279 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7280 ASC_ASSERT(ascq->q_last[tid] == reqp);
7281 ascq->q_last[tid] = NULL;
7283 #ifdef ADVANSYS_STATS
7284 /* Maintain request queue statistics. */
7285 ascq->q_cur_cnt[tid]--;
7286 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7287 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
7288 #endif /* ADVANSYS_STATS */
7290 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong) reqp);
7295 * Return a pointer to a singly linked list of all the requests queued
7296 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
7298 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
7299 * the last request returned in the singly linked list.
7301 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
7302 * then all queued requests are concatenated into one list and
7305 * Note: If 'lastpp' is used to append a new list to the end of
7306 * an old list, only change the old list last pointer if '*lastpp'
7307 * (or the function return value) is not NULL, i.e. use a temporary
7308 * variable for 'lastpp' and check its value after the function return
7309 * before assigning it to the list last pointer.
7311 * Unfortunately collecting queuing time statistics adds overhead to
7312 * the function that isn't inherent to the function's algorithm.
7315 asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
7320 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7321 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
7324 * If 'tid' is not ASC_TID_ALL, return requests only for
7325 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
7326 * requests for all tids.
7328 if (tid != ASC_TID_ALL) {
7329 /* Return all requests for the specified 'tid'. */
7330 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
7331 /* List is empty; Set first and last return pointers to NULL. */
7332 firstp = lastp = NULL;
7334 firstp = ascq->q_first[tid];
7335 lastp = ascq->q_last[tid];
7336 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
7337 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7338 #ifdef ADVANSYS_STATS
7341 ascq->q_cur_cnt[tid] = 0;
7342 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7343 REQTIMESTAT("asc_dequeue_list", ascq, reqp, tid);
7346 #endif /* ADVANSYS_STATS */
7349 /* Return all requests for all tids. */
7350 firstp = lastp = NULL;
7351 for (i = 0; i <= ADV_MAX_TID; i++) {
7352 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
7353 if (firstp == NULL) {
7354 firstp = ascq->q_first[i];
7355 lastp = ascq->q_last[i];
7357 ASC_ASSERT(lastp != NULL);
7358 lastp->host_scribble = (unsigned char *)ascq->q_first[i];
7359 lastp = ascq->q_last[i];
7361 ascq->q_first[i] = ascq->q_last[i] = NULL;
7362 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7363 #ifdef ADVANSYS_STATS
7364 ascq->q_cur_cnt[i] = 0;
7365 #endif /* ADVANSYS_STATS */
7368 #ifdef ADVANSYS_STATS
7371 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7372 REQTIMESTAT("asc_dequeue_list", ascq, reqp, reqp->device->id);
7375 #endif /* ADVANSYS_STATS */
7380 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong) firstp);
7385 * Remove the specified 'REQP' from the specified queue for
7386 * the specified target device. Clear the 'tidmask' bit for the
7387 * device if no more commands are left queued for it.
7389 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
7391 * Return ASC_TRUE if the command was found and removed,
7392 * otherwise return ASC_FALSE.
7395 asc_rmqueue(asc_queue_t *ascq, REQP reqp)
7399 int ret = ASC_FALSE;
7401 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
7402 (ulong) ascq, (ulong) reqp);
7403 ASC_ASSERT(reqp != NULL);
7405 tid = REQPTID(reqp);
7406 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7409 * Handle the common case of 'reqp' being the first
7410 * entry on the queue.
7412 if (reqp == ascq->q_first[tid]) {
7414 ascq->q_first[tid] = REQPNEXT(reqp);
7415 /* If the queue is now empty, clear its bit and the last pointer. */
7416 if (ascq->q_first[tid] == NULL) {
7417 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7418 ASC_ASSERT(ascq->q_last[tid] == reqp);
7419 ascq->q_last[tid] = NULL;
7421 } else if (ascq->q_first[tid] != NULL) {
7422 ASC_ASSERT(ascq->q_last[tid] != NULL);
7424 * Because the case of 'reqp' being the first entry has been
7425 * handled above and it is known the queue is not empty, if
7426 * 'reqp' is found on the queue it is guaranteed the queue will
7427 * not become empty and that 'q_first[tid]' will not be changed.
7429 * Set 'prevp' to the first entry, 'currp' to the second entry,
7430 * and search for 'reqp'.
7432 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
7433 currp; prevp = currp, currp = REQPNEXT(currp)) {
7434 if (currp == reqp) {
7436 prevp->host_scribble = (unsigned char *)REQPNEXT(currp);
7437 reqp->host_scribble = NULL;
7438 if (ascq->q_last[tid] == reqp) {
7439 ascq->q_last[tid] = prevp;
7445 #ifdef ADVANSYS_STATS
7446 /* Maintain request queue statistics. */
7447 if (ret == ASC_TRUE) {
7448 ascq->q_cur_cnt[tid]--;
7449 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
7451 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7452 #endif /* ADVANSYS_STATS */
7453 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong) reqp, ret);
7458 * Execute as many queued requests as possible for the specified queue.
7460 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
7463 asc_execute_queue(asc_queue_t *ascq)
7465 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
7469 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong) ascq);
7471 * Execute queued commands for devices attached to
7472 * the current board in round-robin fashion.
7474 scan_tidmask = ascq->q_tidmask;
7476 for (i = 0; i <= ADV_MAX_TID; i++) {
7477 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
7478 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
7479 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7480 } else if (asc_execute_scsi_cmnd((struct scsi_cmnd *) reqp)
7482 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7484 * The request returned ASC_BUSY. Enqueue at the front of
7485 * target's waiting list to maintain correct ordering.
7487 asc_enqueue(ascq, reqp, ASC_FRONT);
7491 } while (scan_tidmask);
7495 #ifdef CONFIG_PROC_FS
7497 * asc_prt_board_devices()
7499 * Print driver information for devices attached to the board.
7501 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7502 * cf. asc_prt_line().
7504 * Return the number of characters copied into 'cp'. No more than
7505 * 'cplen' characters will be copied to 'cp'.
7508 asc_prt_board_devices(struct Scsi_Host *shp, char *cp, int cplen)
7510 asc_board_t *boardp;
7517 boardp = ASC_BOARDP(shp);
7521 len = asc_prt_line(cp, leftlen,
7522 "\nDevice Information for AdvanSys SCSI Host %d:\n", shp->host_no);
7525 if (ASC_NARROW_BOARD(boardp)) {
7526 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7528 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7531 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
7533 for (i = 0; i <= ADV_MAX_TID; i++) {
7534 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
7535 len = asc_prt_line(cp, leftlen, " %X,", i);
7539 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
7546 * Display Wide Board BIOS Information.
7549 asc_prt_adv_bios(struct Scsi_Host *shp, char *cp, int cplen)
7551 asc_board_t *boardp;
7555 ushort major, minor, letter;
7557 boardp = ASC_BOARDP(shp);
7561 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
7565 * If the BIOS saved a valid signature, then fill in
7566 * the BIOS code segment base address.
7568 if (boardp->bios_signature != 0x55AA) {
7569 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
7571 len = asc_prt_line(cp, leftlen,
7572 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
7574 len = asc_prt_line(cp, leftlen,
7575 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
7578 major = (boardp->bios_version >> 12) & 0xF;
7579 minor = (boardp->bios_version >> 8) & 0xF;
7580 letter = (boardp->bios_version & 0xFF);
7582 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
7583 major, minor, letter >= 26 ? '?' : letter + 'A');
7587 * Current available ROM BIOS release is 3.1I for UW
7588 * and 3.2I for U2W. This code doesn't differentiate
7589 * UW and U2W boards.
7591 if (major < 3 || (major <= 3 && minor < 1) ||
7592 (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
7593 len = asc_prt_line(cp, leftlen,
7594 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
7596 len = asc_prt_line(cp, leftlen,
7597 "ftp://ftp.connectcom.net/pub\n");
7606 * Add serial number to information bar if signature AAh
7607 * is found in at bit 15-9 (7 bits) of word 1.
7609 * Serial Number consists fo 12 alpha-numeric digits.
7611 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
7612 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
7613 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
7614 * 5 - Product revision (A-J) Word0: " "
7616 * Signature Word1: 15-9 (7 bits)
7617 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
7618 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
7620 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
7622 * Note 1: Only production cards will have a serial number.
7624 * Note 2: Signature is most significant 7 bits (0xFE).
7626 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
7629 asc_get_eeprom_string(ushort *serialnum, uchar *cp)
7633 if ((serialnum[1] & 0xFE00) != ((ushort) 0xAA << 8)) {
7637 * First word - 6 digits.
7641 /* Product type - 1st digit. */
7642 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
7643 /* Product type is P=Prototype */
7648 /* Manufacturing location - 2nd digit. */
7649 *cp++ = 'A' + ((w & 0x1C00) >> 10);
7651 /* Product ID - 3rd, 4th digits. */
7653 *cp++ = '0' + (num / 100);
7655 *cp++ = '0' + (num / 10);
7657 /* Product revision - 5th digit. */
7658 *cp++ = 'A' + (num % 10);
7668 * If bit 15 of third word is set, then the
7669 * last digit of the year is greater than 7.
7671 if (serialnum[2] & 0x8000) {
7672 *cp++ = '8' + ((w & 0x1C0) >> 6);
7674 *cp++ = '0' + ((w & 0x1C0) >> 6);
7677 /* Week of year - 7th, 8th digits. */
7679 *cp++ = '0' + num / 10;
7686 w = serialnum[2] & 0x7FFF;
7688 /* Serial number - 9th digit. */
7689 *cp++ = 'A' + (w / 1000);
7691 /* 10th, 11th, 12th digits. */
7693 *cp++ = '0' + num / 100;
7695 *cp++ = '0' + num / 10;
7699 *cp = '\0'; /* Null Terminate the string. */
7705 * asc_prt_asc_board_eeprom()
7707 * Print board EEPROM configuration.
7709 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7710 * cf. asc_prt_line().
7712 * Return the number of characters copied into 'cp'. No more than
7713 * 'cplen' characters will be copied to 'cp'.
7716 asc_prt_asc_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7718 asc_board_t *boardp;
7719 ASC_DVC_VAR *asc_dvc_varp;
7726 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
7727 #endif /* CONFIG_ISA */
7728 uchar serialstr[13];
7730 boardp = ASC_BOARDP(shp);
7731 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
7732 ep = &boardp->eep_config.asc_eep;
7737 len = asc_prt_line(cp, leftlen,
7738 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7741 if (asc_get_eeprom_string((ushort *) &ep->adapter_info[0], serialstr) ==
7743 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7746 if (ep->adapter_info[5] == 0xBB) {
7747 len = asc_prt_line(cp, leftlen,
7748 " Default Settings Used for EEPROM-less Adapter.\n");
7751 len = asc_prt_line(cp, leftlen,
7752 " Serial Number Signature Not Present.\n");
7757 len = asc_prt_line(cp, leftlen,
7758 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7759 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, ep->max_tag_qng);
7762 len = asc_prt_line(cp, leftlen,
7763 " cntl 0x%x, no_scam 0x%x\n",
7764 ep->cntl, ep->no_scam);
7767 len = asc_prt_line(cp, leftlen,
7770 for (i = 0; i <= ASC_MAX_TID; i++) {
7771 len = asc_prt_line(cp, leftlen, " %d", i);
7774 len = asc_prt_line(cp, leftlen, "\n");
7777 len = asc_prt_line(cp, leftlen,
7780 for (i = 0; i <= ASC_MAX_TID; i++) {
7781 len = asc_prt_line(cp, leftlen, " %c",
7782 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7785 len = asc_prt_line(cp, leftlen, "\n");
7788 len = asc_prt_line(cp, leftlen,
7789 " Command Queuing: ");
7791 for (i = 0; i <= ASC_MAX_TID; i++) {
7792 len = asc_prt_line(cp, leftlen, " %c",
7793 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7796 len = asc_prt_line(cp, leftlen, "\n");
7799 len = asc_prt_line(cp, leftlen,
7802 for (i = 0; i <= ASC_MAX_TID; i++) {
7803 len = asc_prt_line(cp, leftlen, " %c",
7804 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7807 len = asc_prt_line(cp, leftlen, "\n");
7810 len = asc_prt_line(cp, leftlen,
7811 " Synchronous Transfer:");
7813 for (i = 0; i <= ASC_MAX_TID; i++) {
7814 len = asc_prt_line(cp, leftlen, " %c",
7815 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7818 len = asc_prt_line(cp, leftlen, "\n");
7822 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
7823 len = asc_prt_line(cp, leftlen,
7824 " Host ISA DMA speed: %d MB/S\n",
7825 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
7828 #endif /* CONFIG_ISA */
7834 * asc_prt_adv_board_eeprom()
7836 * Print board EEPROM configuration.
7838 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7839 * cf. asc_prt_line().
7841 * Return the number of characters copied into 'cp'. No more than
7842 * 'cplen' characters will be copied to 'cp'.
7845 asc_prt_adv_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7847 asc_board_t *boardp;
7848 ADV_DVC_VAR *adv_dvc_varp;
7854 uchar serialstr[13];
7855 ADVEEP_3550_CONFIG *ep_3550 = NULL;
7856 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
7857 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
7860 ushort sdtr_speed = 0;
7862 boardp = ASC_BOARDP(shp);
7863 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
7864 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7866 ep_3550 = &boardp->eep_config.adv_3550_eep;
7867 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7869 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
7872 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
7878 len = asc_prt_line(cp, leftlen,
7879 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7882 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7884 wordp = &ep_3550->serial_number_word1;
7885 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7887 wordp = &ep_38C0800->serial_number_word1;
7890 wordp = &ep_38C1600->serial_number_word1;
7893 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
7894 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7897 len = asc_prt_line(cp, leftlen,
7898 " Serial Number Signature Not Present.\n");
7902 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7904 len = asc_prt_line(cp, leftlen,
7905 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7906 ep_3550->adapter_scsi_id, ep_3550->max_host_qng,
7907 ep_3550->max_dvc_qng);
7909 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7911 len = asc_prt_line(cp, leftlen,
7912 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7913 ep_38C0800->adapter_scsi_id, ep_38C0800->max_host_qng,
7914 ep_38C0800->max_dvc_qng);
7918 len = asc_prt_line(cp, leftlen,
7919 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7920 ep_38C1600->adapter_scsi_id, ep_38C1600->max_host_qng,
7921 ep_38C1600->max_dvc_qng);
7924 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7926 word = ep_3550->termination;
7927 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7929 word = ep_38C0800->termination_lvd;
7932 word = ep_38C1600->termination_lvd;
7936 termstr = "Low Off/High Off";
7939 termstr = "Low Off/High On";
7942 termstr = "Low On/High On";
7946 termstr = "Automatic";
7950 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7952 len = asc_prt_line(cp, leftlen,
7953 " termination: %u (%s), bios_ctrl: 0x%x\n",
7954 ep_3550->termination, termstr, ep_3550->bios_ctrl);
7956 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7958 len = asc_prt_line(cp, leftlen,
7959 " termination: %u (%s), bios_ctrl: 0x%x\n",
7960 ep_38C0800->termination_lvd, termstr, ep_38C0800->bios_ctrl);
7964 len = asc_prt_line(cp, leftlen,
7965 " termination: %u (%s), bios_ctrl: 0x%x\n",
7966 ep_38C1600->termination_lvd, termstr, ep_38C1600->bios_ctrl);
7970 len = asc_prt_line(cp, leftlen,
7973 for (i = 0; i <= ADV_MAX_TID; i++) {
7974 len = asc_prt_line(cp, leftlen, " %X", i);
7977 len = asc_prt_line(cp, leftlen, "\n");
7980 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7982 word = ep_3550->disc_enable;
7983 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7985 word = ep_38C0800->disc_enable;
7988 word = ep_38C1600->disc_enable;
7990 len = asc_prt_line(cp, leftlen,
7993 for (i = 0; i <= ADV_MAX_TID; i++) {
7994 len = asc_prt_line(cp, leftlen, " %c",
7995 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7998 len = asc_prt_line(cp, leftlen, "\n");
8001 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8003 word = ep_3550->tagqng_able;
8004 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8006 word = ep_38C0800->tagqng_able;
8009 word = ep_38C1600->tagqng_able;
8011 len = asc_prt_line(cp, leftlen,
8012 " Command Queuing: ");
8014 for (i = 0; i <= ADV_MAX_TID; i++) {
8015 len = asc_prt_line(cp, leftlen, " %c",
8016 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8019 len = asc_prt_line(cp, leftlen, "\n");
8022 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8024 word = ep_3550->start_motor;
8025 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8027 word = ep_38C0800->start_motor;
8030 word = ep_38C1600->start_motor;
8032 len = asc_prt_line(cp, leftlen,
8035 for (i = 0; i <= ADV_MAX_TID; i++) {
8036 len = asc_prt_line(cp, leftlen, " %c",
8037 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8040 len = asc_prt_line(cp, leftlen, "\n");
8043 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8045 len = asc_prt_line(cp, leftlen,
8046 " Synchronous Transfer:");
8048 for (i = 0; i <= ADV_MAX_TID; i++) {
8049 len = asc_prt_line(cp, leftlen, " %c",
8050 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8053 len = asc_prt_line(cp, leftlen, "\n");
8057 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8059 len = asc_prt_line(cp, leftlen,
8060 " Ultra Transfer: ");
8062 for (i = 0; i <= ADV_MAX_TID; i++) {
8063 len = asc_prt_line(cp, leftlen, " %c",
8064 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8067 len = asc_prt_line(cp, leftlen, "\n");
8071 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8073 word = ep_3550->wdtr_able;
8074 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8076 word = ep_38C0800->wdtr_able;
8079 word = ep_38C1600->wdtr_able;
8081 len = asc_prt_line(cp, leftlen,
8082 " Wide Transfer: ");
8084 for (i = 0; i <= ADV_MAX_TID; i++) {
8085 len = asc_prt_line(cp, leftlen, " %c",
8086 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8089 len = asc_prt_line(cp, leftlen, "\n");
8092 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
8093 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600)
8095 len = asc_prt_line(cp, leftlen,
8096 " Synchronous Transfer Speed (Mhz):\n ");
8098 for (i = 0; i <= ADV_MAX_TID; i++) {
8103 sdtr_speed = adv_dvc_varp->sdtr_speed1;
8106 sdtr_speed = adv_dvc_varp->sdtr_speed2;
8109 sdtr_speed = adv_dvc_varp->sdtr_speed3;
8112 sdtr_speed = adv_dvc_varp->sdtr_speed4;
8114 switch (sdtr_speed & ADV_MAX_TID)
8116 case 0: speed_str = "Off"; break;
8117 case 1: speed_str = " 5"; break;
8118 case 2: speed_str = " 10"; break;
8119 case 3: speed_str = " 20"; break;
8120 case 4: speed_str = " 40"; break;
8121 case 5: speed_str = " 80"; break;
8122 default: speed_str = "Unk"; break;
8124 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
8128 len = asc_prt_line(cp, leftlen, "\n ");
8133 len = asc_prt_line(cp, leftlen, "\n");
8141 * asc_prt_driver_conf()
8143 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8144 * cf. asc_prt_line().
8146 * Return the number of characters copied into 'cp'. No more than
8147 * 'cplen' characters will be copied to 'cp'.
8150 asc_prt_driver_conf(struct Scsi_Host *shp, char *cp, int cplen)
8152 asc_board_t *boardp;
8158 boardp = ASC_BOARDP(shp);
8163 len = asc_prt_line(cp, leftlen,
8164 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
8168 len = asc_prt_line(cp, leftlen,
8169 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
8170 shp->host_busy, shp->last_reset, shp->max_id, shp->max_lun,
8174 len = asc_prt_line(cp, leftlen,
8175 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
8176 shp->unique_id, shp->can_queue, shp->this_id, shp->sg_tablesize,
8180 len = asc_prt_line(cp, leftlen,
8181 " unchecked_isa_dma %d, use_clustering %d\n",
8182 shp->unchecked_isa_dma, shp->use_clustering);
8185 len = asc_prt_line(cp, leftlen,
8186 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
8187 boardp->flags, boardp->last_reset, jiffies, boardp->asc_n_io_port);
8190 /* 'shp->n_io_port' may be truncated because it is only one byte. */
8191 len = asc_prt_line(cp, leftlen,
8192 " io_port 0x%x, n_io_port 0x%x\n",
8193 shp->io_port, shp->n_io_port);
8196 if (ASC_NARROW_BOARD(boardp)) {
8197 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
8199 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
8206 * asc_prt_asc_board_info()
8208 * Print dynamic board configuration information.
8210 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8211 * cf. asc_prt_line().
8213 * Return the number of characters copied into 'cp'. No more than
8214 * 'cplen' characters will be copied to 'cp'.
8217 asc_prt_asc_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8219 asc_board_t *boardp;
8227 int renegotiate = 0;
8229 boardp = ASC_BOARDP(shp);
8230 v = &boardp->dvc_var.asc_dvc_var;
8231 c = &boardp->dvc_cfg.asc_dvc_cfg;
8232 chip_scsi_id = c->chip_scsi_id;
8237 len = asc_prt_line(cp, leftlen,
8238 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8242 len = asc_prt_line(cp, leftlen,
8243 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
8244 c->chip_version, c->lib_version, c->lib_serial_no, c->mcode_date);
8247 len = asc_prt_line(cp, leftlen,
8248 " mcode_version 0x%x, err_code %u\n",
8249 c->mcode_version, v->err_code);
8252 /* Current number of commands waiting for the host. */
8253 len = asc_prt_line(cp, leftlen,
8254 " Total Command Pending: %d\n", v->cur_total_qng);
8257 len = asc_prt_line(cp, leftlen,
8258 " Command Queuing:");
8260 for (i = 0; i <= ASC_MAX_TID; i++) {
8261 if ((chip_scsi_id == i) ||
8262 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8265 len = asc_prt_line(cp, leftlen, " %X:%c",
8266 i, (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8269 len = asc_prt_line(cp, leftlen, "\n");
8272 /* Current number of commands waiting for a device. */
8273 len = asc_prt_line(cp, leftlen,
8274 " Command Queue Pending:");
8276 for (i = 0; i <= ASC_MAX_TID; i++) {
8277 if ((chip_scsi_id == i) ||
8278 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8281 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
8284 len = asc_prt_line(cp, leftlen, "\n");
8287 /* Current limit on number of commands that can be sent to a device. */
8288 len = asc_prt_line(cp, leftlen,
8289 " Command Queue Limit:");
8291 for (i = 0; i <= ASC_MAX_TID; i++) {
8292 if ((chip_scsi_id == i) ||
8293 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8296 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
8299 len = asc_prt_line(cp, leftlen, "\n");
8302 /* Indicate whether the device has returned queue full status. */
8303 len = asc_prt_line(cp, leftlen,
8304 " Command Queue Full:");
8306 for (i = 0; i <= ASC_MAX_TID; i++) {
8307 if ((chip_scsi_id == i) ||
8308 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8311 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
8312 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
8313 i, boardp->queue_full_cnt[i]);
8315 len = asc_prt_line(cp, leftlen, " %X:N", i);
8319 len = asc_prt_line(cp, leftlen, "\n");
8322 len = asc_prt_line(cp, leftlen,
8323 " Synchronous Transfer:");
8325 for (i = 0; i <= ASC_MAX_TID; i++) {
8326 if ((chip_scsi_id == i) ||
8327 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8330 len = asc_prt_line(cp, leftlen, " %X:%c",
8331 i, (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8334 len = asc_prt_line(cp, leftlen, "\n");
8337 for (i = 0; i <= ASC_MAX_TID; i++) {
8338 uchar syn_period_ix;
8340 if ((chip_scsi_id == i) ||
8341 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8342 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
8346 len = asc_prt_line(cp, leftlen, " %X:", i);
8349 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0)
8351 len = asc_prt_line(cp, leftlen, " Asynchronous");
8356 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 1);
8358 len = asc_prt_line(cp, leftlen,
8359 " Transfer Period Factor: %d (%d.%d Mhz),",
8360 v->sdtr_period_tbl[syn_period_ix],
8361 250 / v->sdtr_period_tbl[syn_period_ix],
8362 ASC_TENTHS(250, v->sdtr_period_tbl[syn_period_ix]));
8365 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8366 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
8370 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8371 len = asc_prt_line(cp, leftlen, "*\n");
8375 len = asc_prt_line(cp, leftlen, "\n");
8382 len = asc_prt_line(cp, leftlen,
8383 " * = Re-negotiation pending before next command.\n");
8391 * asc_prt_adv_board_info()
8393 * Print dynamic board configuration information.
8395 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8396 * cf. asc_prt_line().
8398 * Return the number of characters copied into 'cp'. No more than
8399 * 'cplen' characters will be copied to 'cp'.
8402 asc_prt_adv_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8404 asc_board_t *boardp;
8411 AdvPortAddr iop_base;
8412 ushort chip_scsi_id;
8416 ushort sdtr_able, wdtr_able;
8417 ushort wdtr_done, sdtr_done;
8419 int renegotiate = 0;
8421 boardp = ASC_BOARDP(shp);
8422 v = &boardp->dvc_var.adv_dvc_var;
8423 c = &boardp->dvc_cfg.adv_dvc_cfg;
8424 iop_base = v->iop_base;
8425 chip_scsi_id = v->chip_scsi_id;
8430 len = asc_prt_line(cp, leftlen,
8431 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8435 len = asc_prt_line(cp, leftlen,
8436 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
8438 AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1) & CABLE_DETECT,
8442 len = asc_prt_line(cp, leftlen,
8443 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
8444 c->chip_version, c->lib_version, c->mcode_date, c->mcode_version);
8447 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8448 len = asc_prt_line(cp, leftlen,
8449 " Queuing Enabled:");
8451 for (i = 0; i <= ADV_MAX_TID; i++) {
8452 if ((chip_scsi_id == i) ||
8453 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8457 len = asc_prt_line(cp, leftlen, " %X:%c",
8458 i, (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8461 len = asc_prt_line(cp, leftlen, "\n");
8464 len = asc_prt_line(cp, leftlen,
8467 for (i = 0; i <= ADV_MAX_TID; i++) {
8468 if ((chip_scsi_id == i) ||
8469 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8473 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, lrambyte);
8475 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8478 len = asc_prt_line(cp, leftlen, "\n");
8481 len = asc_prt_line(cp, leftlen,
8482 " Command Pending:");
8484 for (i = 0; i <= ADV_MAX_TID; i++) {
8485 if ((chip_scsi_id == i) ||
8486 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8490 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, lrambyte);
8492 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8495 len = asc_prt_line(cp, leftlen, "\n");
8498 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8499 len = asc_prt_line(cp, leftlen,
8502 for (i = 0; i <= ADV_MAX_TID; i++) {
8503 if ((chip_scsi_id == i) ||
8504 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8508 len = asc_prt_line(cp, leftlen, " %X:%c",
8509 i, (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8512 len = asc_prt_line(cp, leftlen, "\n");
8515 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
8516 len = asc_prt_line(cp, leftlen,
8517 " Transfer Bit Width:");
8519 for (i = 0; i <= ADV_MAX_TID; i++) {
8520 if ((chip_scsi_id == i) ||
8521 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8525 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8528 len = asc_prt_line(cp, leftlen, " %X:%d",
8529 i, (lramword & 0x8000) ? 16 : 8);
8532 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
8533 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8534 len = asc_prt_line(cp, leftlen, "*");
8539 len = asc_prt_line(cp, leftlen, "\n");
8542 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8543 len = asc_prt_line(cp, leftlen,
8544 " Synchronous Enabled:");
8546 for (i = 0; i <= ADV_MAX_TID; i++) {
8547 if ((chip_scsi_id == i) ||
8548 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8552 len = asc_prt_line(cp, leftlen, " %X:%c",
8553 i, (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8556 len = asc_prt_line(cp, leftlen, "\n");
8559 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
8560 for (i = 0; i <= ADV_MAX_TID; i++) {
8562 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8564 lramword &= ~0x8000;
8566 if ((chip_scsi_id == i) ||
8567 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8568 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
8572 len = asc_prt_line(cp, leftlen, " %X:", i);
8575 if ((lramword & 0x1F) == 0) /* Check for REQ/ACK Offset 0. */
8577 len = asc_prt_line(cp, leftlen, " Asynchronous");
8581 len = asc_prt_line(cp, leftlen, " Transfer Period Factor: ");
8584 if ((lramword & 0x1F00) == 0x1100) /* 80 Mhz */
8586 len = asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
8588 } else if ((lramword & 0x1F00) == 0x1000) /* 40 Mhz */
8590 len = asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
8592 } else /* 20 Mhz or below. */
8594 period = (((lramword >> 8) * 25) + 50)/4;
8596 if (period == 0) /* Should never happen. */
8598 len = asc_prt_line(cp, leftlen, "%d (? Mhz), ");
8602 len = asc_prt_line(cp, leftlen,
8604 period, 250/period, ASC_TENTHS(250, period));
8609 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8614 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8615 len = asc_prt_line(cp, leftlen, "*\n");
8619 len = asc_prt_line(cp, leftlen, "\n");
8626 len = asc_prt_line(cp, leftlen,
8627 " * = Re-negotiation pending before next command.\n");
8637 * Copy proc information to a read buffer taking into account the current
8638 * read offset in the file and the remaining space in the read buffer.
8641 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
8642 char *cp, int cplen)
8646 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
8647 (unsigned) offset, (unsigned) advoffset, cplen);
8648 if (offset <= advoffset) {
8649 /* Read offset below current offset, copy everything. */
8650 cnt = min(cplen, leftlen);
8651 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8652 (ulong) curbuf, (ulong) cp, cnt);
8653 memcpy(curbuf, cp, cnt);
8654 } else if (offset < advoffset + cplen) {
8655 /* Read offset within current range, partial copy. */
8656 cnt = (advoffset + cplen) - offset;
8657 cp = (cp + cplen) - cnt;
8658 cnt = min(cnt, leftlen);
8659 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8660 (ulong) curbuf, (ulong) cp, cnt);
8661 memcpy(curbuf, cp, cnt);
8669 * If 'cp' is NULL print to the console, otherwise print to a buffer.
8671 * Return 0 if printing to the console, otherwise return the number of
8672 * bytes written to the buffer.
8674 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
8675 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
8678 asc_prt_line(char *buf, int buflen, char *fmt, ...)
8682 char s[ASC_PRTLINE_SIZE];
8684 va_start(args, fmt);
8685 ret = vsprintf(s, fmt, args);
8686 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
8691 ret = min(buflen, ret);
8692 memcpy(buf, s, ret);
8697 #endif /* CONFIG_PROC_FS */
8701 * --- Functions Required by the Asc Library
8705 * Delay for 'n' milliseconds. Don't use the 'jiffies'
8706 * global variable which is incremented once every 5 ms
8707 * from a timer interrupt, because this function may be
8708 * called when interrupts are disabled.
8711 DvcSleepMilliSecond(ADV_DCNT n)
8713 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
8718 * Currently and inline noop but leave as a placeholder.
8719 * Leave DvcEnterCritical() as a noop placeholder.
8722 DvcEnterCritical(void)
8728 * Critical sections are all protected by the board spinlock.
8729 * Leave DvcLeaveCritical() as a noop placeholder.
8732 DvcLeaveCritical(ulong flags)
8739 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8741 * Calling/Exit State:
8745 * Output an ASC_SCSI_Q structure to the chip
8748 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8752 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8753 AscSetChipLramAddr(iop_base, s_addr);
8754 for (i = 0; i < 2 * words; i += 2) {
8755 if (i == 4 || i == 20) {
8758 outpw(iop_base + IOP_RAM_DATA,
8759 ((ushort) outbuf[i + 1] << 8) | outbuf[i]);
8765 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8767 * Calling/Exit State:
8771 * Input an ASC_QDONE_INFO structure from the chip
8774 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8779 AscSetChipLramAddr(iop_base, s_addr);
8780 for (i = 0; i < 2 * words; i += 2) {
8784 word = inpw(iop_base + IOP_RAM_DATA);
8785 inbuf[i] = word & 0xff;
8786 inbuf[i + 1] = (word >> 8) & 0xff;
8788 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
8792 * Read a PCI configuration byte.
8795 DvcReadPCIConfigByte(
8796 ASC_DVC_VAR *asc_dvc,
8801 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8803 #else /* !defined(CONFIG_PCI) */
8805 #endif /* !defined(CONFIG_PCI) */
8809 * Write a PCI configuration byte.
8812 DvcWritePCIConfigByte(
8813 ASC_DVC_VAR *asc_dvc,
8818 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8819 #endif /* CONFIG_PCI */
8823 * Return the BIOS address of the adapter at the specified
8824 * I/O port and with the specified bus type.
8826 STATIC ushort __init
8827 AscGetChipBiosAddress(
8835 * The PCI BIOS is re-located by the motherboard BIOS. Because
8836 * of this the driver can not determine where a PCI BIOS is
8837 * loaded and executes.
8839 if (bus_type & ASC_IS_PCI)
8845 if((bus_type & ASC_IS_EISA) != 0)
8847 cfg_lsw = AscGetEisaChipCfg(iop_base);
8849 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
8850 (cfg_lsw * ASC_BIOS_BANK_SIZE));
8853 #endif /* CONFIG_ISA */
8855 cfg_lsw = AscGetChipCfgLsw(iop_base);
8858 * ISA PnP uses the top bit as the 32K BIOS flag
8860 if (bus_type == ASC_IS_ISAPNP)
8865 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
8872 * --- Functions Required by the Adv Library
8878 * Return the physical address of 'vaddr' and set '*lenp' to the
8879 * number of physically contiguous bytes that follow 'vaddr'.
8880 * 'flag' indicates the type of structure whose physical address
8881 * is being translated.
8883 * Note: Because Linux currently doesn't page the kernel and all
8884 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
8887 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
8888 uchar *vaddr, ADV_SDCNT *lenp, int flag)
8892 paddr = virt_to_bus(vaddr);
8895 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
8896 (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
8902 * Read a PCI configuration byte.
8905 DvcAdvReadPCIConfigByte(
8906 ADV_DVC_VAR *asc_dvc,
8911 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8913 #else /* CONFIG_PCI */
8915 #endif /* CONFIG_PCI */
8919 * Write a PCI configuration byte.
8922 DvcAdvWritePCIConfigByte(
8923 ADV_DVC_VAR *asc_dvc,
8928 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8929 #else /* CONFIG_PCI */
8931 #endif /* CONFIG_PCI */
8935 * --- Tracing and Debugging Functions
8938 #ifdef ADVANSYS_STATS
8939 #ifdef CONFIG_PROC_FS
8941 * asc_prt_board_stats()
8943 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8944 * cf. asc_prt_line().
8946 * Return the number of characters copied into 'cp'. No more than
8947 * 'cplen' characters will be copied to 'cp'.
8950 asc_prt_board_stats(struct Scsi_Host *shp, char *cp, int cplen)
8955 struct asc_stats *s;
8956 asc_board_t *boardp;
8961 boardp = ASC_BOARDP(shp);
8962 s = &boardp->asc_stats;
8964 len = asc_prt_line(cp, leftlen,
8965 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", shp->host_no);
8968 len = asc_prt_line(cp, leftlen,
8969 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
8970 s->queuecommand, s->reset, s->biosparam, s->interrupt);
8973 len = asc_prt_line(cp, leftlen,
8974 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
8975 s->callback, s->done, s->build_error, s->adv_build_noreq,
8979 len = asc_prt_line(cp, leftlen,
8980 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
8981 s->exe_noerror, s->exe_busy, s->exe_error, s->exe_unknown);
8985 * Display data transfer statistics.
8987 if (s->cont_cnt > 0) {
8988 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
8991 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
8993 ASC_TENTHS(s->cont_xfer, 2));
8996 /* Contiguous transfer average size */
8997 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
8998 (s->cont_xfer/2)/s->cont_cnt,
8999 ASC_TENTHS((s->cont_xfer/2), s->cont_cnt));
9003 if (s->sg_cnt > 0) {
9005 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
9006 s->sg_cnt, s->sg_elem);
9009 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
9011 ASC_TENTHS(s->sg_xfer, 2));
9014 /* Scatter gather transfer statistics */
9015 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
9016 s->sg_elem/s->sg_cnt,
9017 ASC_TENTHS(s->sg_elem, s->sg_cnt));
9020 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
9021 (s->sg_xfer/2)/s->sg_elem,
9022 ASC_TENTHS((s->sg_xfer/2), s->sg_elem));
9025 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
9026 (s->sg_xfer/2)/s->sg_cnt,
9027 ASC_TENTHS((s->sg_xfer/2), s->sg_cnt));
9032 * Display request queuing statistics.
9034 len = asc_prt_line(cp, leftlen,
9035 " Active and Waiting Request Queues (Time Unit: %d HZ):\n", HZ);
9043 * asc_prt_target_stats()
9045 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
9046 * cf. asc_prt_line().
9048 * This is separated from asc_prt_board_stats because a full set
9049 * of targets will overflow ASC_PRTBUF_SIZE.
9051 * Return the number of characters copied into 'cp'. No more than
9052 * 'cplen' characters will be copied to 'cp'.
9055 asc_prt_target_stats(struct Scsi_Host *shp, int tgt_id, char *cp, int cplen)
9060 struct asc_stats *s;
9061 ushort chip_scsi_id;
9062 asc_board_t *boardp;
9063 asc_queue_t *active;
9064 asc_queue_t *waiting;
9069 boardp = ASC_BOARDP(shp);
9070 s = &boardp->asc_stats;
9072 active = &ASC_BOARDP(shp)->active;
9073 waiting = &ASC_BOARDP(shp)->waiting;
9075 if (ASC_NARROW_BOARD(boardp)) {
9076 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
9078 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
9081 if ((chip_scsi_id == tgt_id) ||
9082 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
9087 if (active->q_tot_cnt[tgt_id] > 0 || waiting->q_tot_cnt[tgt_id] > 0) {
9088 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
9091 len = asc_prt_line(cp, leftlen,
9092 " active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
9093 active->q_cur_cnt[tgt_id], active->q_max_cnt[tgt_id],
9094 active->q_tot_cnt[tgt_id],
9095 active->q_min_tim[tgt_id], active->q_max_tim[tgt_id],
9096 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9097 (active->q_tot_tim[tgt_id]/active->q_tot_cnt[tgt_id]),
9098 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9099 ASC_TENTHS(active->q_tot_tim[tgt_id],
9100 active->q_tot_cnt[tgt_id]));
9103 len = asc_prt_line(cp, leftlen,
9104 " waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
9105 waiting->q_cur_cnt[tgt_id], waiting->q_max_cnt[tgt_id],
9106 waiting->q_tot_cnt[tgt_id],
9107 waiting->q_min_tim[tgt_id], waiting->q_max_tim[tgt_id],
9108 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9109 (waiting->q_tot_tim[tgt_id]/waiting->q_tot_cnt[tgt_id]),
9110 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9111 ASC_TENTHS(waiting->q_tot_tim[tgt_id],
9112 waiting->q_tot_cnt[tgt_id]));
9119 #endif /* CONFIG_PROC_FS */
9120 #endif /* ADVANSYS_STATS */
9122 #ifdef ADVANSYS_DEBUG
9124 * asc_prt_scsi_host()
9127 asc_prt_scsi_host(struct Scsi_Host *s)
9129 asc_board_t *boardp;
9131 boardp = ASC_BOARDP(s);
9133 printk("Scsi_Host at addr 0x%lx\n", (ulong) s);
9135 " host_busy %u, host_no %d, last_reset %d,\n",
9136 s->host_busy, s->host_no,
9137 (unsigned) s->last_reset);
9140 " base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
9141 (ulong) s->base, (ulong) s->io_port, s->n_io_port, s->irq);
9144 " dma_channel %d, this_id %d, can_queue %d,\n",
9145 s->dma_channel, s->this_id, s->can_queue);
9148 " cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
9149 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
9151 if (ASC_NARROW_BOARD(boardp)) {
9152 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
9153 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
9155 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
9156 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
9161 * asc_prt_scsi_cmnd()
9164 asc_prt_scsi_cmnd(struct scsi_cmnd *s)
9166 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong) s);
9169 " host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
9170 (ulong) s->device->host, (ulong) s->device, s->device->id, s->device->lun,
9171 s->device->channel);
9173 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
9176 "sc_data_direction %u, resid %d\n",
9177 s->sc_data_direction, s->resid);
9180 " use_sg %u, sglist_len %u\n",
9181 s->use_sg, s->sglist_len);
9184 " serial_number 0x%x, retries %d, allowed %d\n",
9185 (unsigned) s->serial_number, s->retries, s->allowed);
9188 " timeout_per_command %d\n",
9189 s->timeout_per_command);
9192 " scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
9193 (ulong) s->scsi_done, (ulong) s->done,
9194 (ulong) s->host_scribble, s->result);
9197 " tag %u, pid %u\n",
9198 (unsigned) s->tag, (unsigned) s->pid);
9202 * asc_prt_asc_dvc_var()
9205 asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
9207 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong) h);
9210 " iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
9211 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
9214 " bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
9215 h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
9216 (unsigned) h->init_sdtr);
9219 " sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
9220 (unsigned) h->sdtr_done, (unsigned) h->use_tagged_qng,
9221 (unsigned) h->unit_not_ready, (unsigned) h->chip_no);
9224 " queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
9225 (unsigned) h->queue_full_or_busy, (unsigned) h->start_motor,
9226 (unsigned) h->scsi_reset_wait);
9229 " is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
9230 (unsigned) h->is_in_int, (unsigned) h->max_total_qng,
9231 (unsigned) h->cur_total_qng, (unsigned) h->in_critical_cnt);
9234 " last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
9235 (unsigned) h->last_q_shortage, (unsigned) h->init_state,
9236 (unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
9239 " cfg 0x%lx, irq_no 0x%x\n",
9240 (ulong) h->cfg, (unsigned) h->irq_no);
9244 * asc_prt_asc_dvc_cfg()
9247 asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
9249 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong) h);
9252 " can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
9253 h->can_tagged_qng, h->cmd_qng_enabled);
9255 " disc_enable 0x%x, sdtr_enable 0x%x,\n",
9256 h->disc_enable, h->sdtr_enable);
9259 " chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
9260 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
9264 " pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
9265 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
9269 " mcode_version %d, overrun_buf 0x%lx\n",
9270 h->mcode_version, (ulong) h->overrun_buf);
9274 * asc_prt_asc_scsi_q()
9277 asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
9282 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong) q);
9285 " target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
9286 q->q2.target_ix, q->q1.target_lun,
9287 (ulong) q->q2.srb_ptr, q->q2.tag_code);
9290 " data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9291 (ulong) le32_to_cpu(q->q1.data_addr),
9292 (ulong) le32_to_cpu(q->q1.data_cnt),
9293 (ulong) le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
9296 " cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
9297 (ulong) q->cdbptr, q->q2.cdb_len,
9298 (ulong) q->sg_head, q->q1.sg_queue_cnt);
9302 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong) sgp);
9303 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
9304 for (i = 0; i < sgp->entry_cnt; i++) {
9305 printk(" [%u]: addr 0x%lx, bytes %lu\n",
9306 i, (ulong) le32_to_cpu(sgp->sg_list[i].addr),
9307 (ulong) le32_to_cpu(sgp->sg_list[i].bytes));
9314 * asc_prt_asc_qdone_info()
9317 asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
9319 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong) q);
9321 " srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
9322 (ulong) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
9325 " done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
9326 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
9330 * asc_prt_adv_dvc_var()
9332 * Display an ADV_DVC_VAR structure.
9335 asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
9337 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong) h);
9340 " iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
9341 (ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
9344 " isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
9345 (ulong) h->isr_callback, (unsigned) h->sdtr_able,
9346 (unsigned) h->wdtr_able);
9349 " start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
9350 (unsigned) h->start_motor,
9351 (unsigned) h->scsi_reset_wait, (unsigned) h->irq_no);
9354 " max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
9355 (unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
9356 (ulong) h->carr_freelist);
9359 " icq_sp 0x%lx, irq_sp 0x%lx\n",
9360 (ulong) h->icq_sp, (ulong) h->irq_sp);
9363 " no_scam 0x%x, tagqng_able 0x%x\n",
9364 (unsigned) h->no_scam, (unsigned) h->tagqng_able);
9367 " chip_scsi_id 0x%x, cfg 0x%lx\n",
9368 (unsigned) h->chip_scsi_id, (ulong) h->cfg);
9372 * asc_prt_adv_dvc_cfg()
9374 * Display an ADV_DVC_CFG structure.
9377 asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
9379 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong) h);
9382 " disc_enable 0x%x, termination 0x%x\n",
9383 h->disc_enable, h->termination);
9386 " chip_version 0x%x, mcode_date 0x%x\n",
9387 h->chip_version, h->mcode_date);
9390 " mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
9391 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
9394 " control_flag 0x%x, pci_slot_info 0x%x\n",
9395 h->control_flag, h->pci_slot_info);
9399 * asc_prt_adv_scsi_req_q()
9401 * Display an ADV_SCSI_REQ_Q structure.
9404 asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
9407 struct asc_sg_block *sg_ptr;
9409 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong) q);
9412 " target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
9413 q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
9415 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
9416 q->cntl, (ulong) le32_to_cpu(q->data_addr), (ulong) q->vdata_addr);
9419 " data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9420 (ulong) le32_to_cpu(q->data_cnt),
9421 (ulong) le32_to_cpu(q->sense_addr), q->sense_len);
9424 " cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
9425 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
9428 " sg_working_ix 0x%x, target_cmd %u\n",
9429 q->sg_working_ix, q->target_cmd);
9432 " scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
9433 (ulong) le32_to_cpu(q->scsiq_rptr),
9434 (ulong) le32_to_cpu(q->sg_real_addr), (ulong) q->sg_list_ptr);
9436 /* Display the request's ADV_SG_BLOCK structures. */
9437 if (q->sg_list_ptr != NULL)
9442 * 'sg_ptr' is a physical address. Convert it to a virtual
9443 * address by indexing 'sg_blk_cnt' into the virtual address
9444 * array 'sg_list_ptr'.
9446 * XXX - Assumes all SG physical blocks are virtually contiguous.
9448 sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
9449 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
9450 if (sg_ptr->sg_ptr == 0)
9460 * asc_prt_adv_sgblock()
9462 * Display an ADV_SG_BLOCK structure.
9465 asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
9469 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
9470 (ulong) b, sgblockno);
9471 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
9472 b->sg_cnt, (ulong) le32_to_cpu(b->sg_ptr));
9473 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
9476 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
9478 for (i = 0; i < b->sg_cnt; i++) {
9479 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
9480 i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
9487 * Print hexadecimal output in 4 byte groupings 32 bytes
9488 * or 8 double-words per line.
9491 asc_prt_hex(char *f, uchar *s, int l)
9498 printk("%s: (%d bytes)\n", f, l);
9500 for (i = 0; i < l; i += 32) {
9502 /* Display a maximum of 8 double-words per line. */
9503 if ((k = (l - i) / 4) >= 8) {
9510 for (j = 0; j < k; j++) {
9511 printk(" %2.2X%2.2X%2.2X%2.2X",
9512 (unsigned) s[i+(j*4)], (unsigned) s[i+(j*4)+1],
9513 (unsigned) s[i+(j*4)+2], (unsigned) s[i+(j*4)+3]);
9522 (unsigned) s[i+(j*4)]);
9525 printk(" %2.2X%2.2X",
9526 (unsigned) s[i+(j*4)],
9527 (unsigned) s[i+(j*4)+1]);
9530 printk(" %2.2X%2.2X%2.2X",
9531 (unsigned) s[i+(j*4)+1],
9532 (unsigned) s[i+(j*4)+2],
9533 (unsigned) s[i+(j*4)+3]);
9540 #endif /* ADVANSYS_DEBUG */
9543 * --- Asc Library Functions
9546 STATIC ushort __init
9550 PortAddr eisa_cfg_iop;
9552 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9553 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9554 return (inpw(eisa_cfg_iop));
9565 if (AscGetChipScsiID(iop_base) == new_host_id) {
9566 return (new_host_id);
9568 cfg_lsw = AscGetChipCfgLsw(iop_base);
9570 cfg_lsw |= (ushort) ((new_host_id & ASC_MAX_TID) << 8);
9571 AscSetChipCfgLsw(iop_base, cfg_lsw);
9572 return (AscGetChipScsiID(iop_base));
9581 AscSetBank(iop_base, 1);
9582 sc = inp(iop_base + IOP_REG_SC);
9583 AscSetBank(iop_base, 0);
9593 if ((bus_type & ASC_IS_EISA) != 0) {
9596 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9597 (PortAddr) ASC_EISA_REV_IOP_MASK;
9598 revision = inp(eisa_iop);
9599 return ((uchar) ((ASC_CHIP_MIN_VER_EISA - 1) + revision));
9601 return (AscGetChipVerNo(iop_base));
9604 STATIC ushort __init
9610 chip_ver = AscGetChipVerNo(iop_base);
9612 (chip_ver >= ASC_CHIP_MIN_VER_VL)
9613 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
9616 ((iop_base & 0x0C30) == 0x0C30)
9617 || ((iop_base & 0x0C50) == 0x0C50)
9619 return (ASC_IS_EISA);
9623 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
9624 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
9625 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
9626 return (ASC_IS_ISAPNP);
9628 return (ASC_IS_ISA);
9629 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
9630 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
9631 return (ASC_IS_PCI);
9645 ushort mcode_word_size;
9646 ushort mcode_chksum;
9648 /* Write the microcode buffer starting at LRAM address 0. */
9649 mcode_word_size = (ushort) (mcode_size >> 1);
9650 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
9651 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
9653 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
9654 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong) chksum);
9655 mcode_chksum = (ushort) AscMemSumLramWord(iop_base,
9656 (ushort) ASC_CODE_SEC_BEG,
9657 (ushort) ((mcode_size - s_addr - (ushort) ASC_CODE_SEC_BEG) / 2));
9658 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
9659 (ulong) mcode_chksum);
9660 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
9661 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
9672 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
9673 iop_base, AscGetChipSignatureByte(iop_base));
9674 if (AscGetChipSignatureByte(iop_base) == (uchar) ASC_1000_ID1B) {
9675 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
9676 iop_base, AscGetChipSignatureWord(iop_base));
9677 sig_word = AscGetChipSignatureWord(iop_base);
9678 if ((sig_word == (ushort) ASC_1000_ID0W) ||
9679 (sig_word == (ushort) ASC_1000_ID0W_FIX)) {
9686 STATIC PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata =
9688 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
9689 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
9693 STATIC uchar _isa_pnp_inited __initdata = 0;
9695 STATIC PortAddr __init
9696 AscSearchIOPortAddr(
9700 if (bus_type & ASC_IS_VL) {
9701 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9702 if (AscGetChipVersion(iop_beg, bus_type) <= ASC_CHIP_MAX_VER_VL) {
9708 if (bus_type & ASC_IS_ISA) {
9709 if (_isa_pnp_inited == 0) {
9710 AscSetISAPNPWaitForKey();
9713 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9714 if ((AscGetChipVersion(iop_beg, bus_type) & ASC_CHIP_VER_ISA_BIT) != 0) {
9720 if (bus_type & ASC_IS_EISA) {
9721 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
9729 STATIC PortAddr __init
9730 AscSearchIOPortAddr11(
9737 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9738 if (_asc_def_iop_base[i] > s_addr) {
9742 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9743 iop_base = _asc_def_iop_base[i];
9744 if (check_region(iop_base, ASC_IOADR_GAP) != 0) {
9746 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
9750 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n", iop_base);
9751 if (AscFindSignature(iop_base)) {
9759 AscSetISAPNPWaitForKey(void)
9761 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
9762 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
9765 #endif /* CONFIG_ISA */
9772 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
9773 AscSetChipStatus(iop_base, 0);
9785 if ((bus_type & ASC_IS_EISA) != 0) {
9786 cfg_lsw = AscGetEisaChipCfg(iop_base);
9787 chip_irq = (uchar) (((cfg_lsw >> 8) & 0x07) + 10);
9788 if ((chip_irq == 13) || (chip_irq > 15)) {
9793 if ((bus_type & ASC_IS_VL) != 0) {
9794 cfg_lsw = AscGetChipCfgLsw(iop_base);
9795 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x07));
9796 if ((chip_irq == 0) ||
9801 return ((uchar) (chip_irq + (ASC_MIN_IRQ_NO - 1)));
9803 cfg_lsw = AscGetChipCfgLsw(iop_base);
9804 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x03));
9806 chip_irq += (uchar) 2;
9807 return ((uchar) (chip_irq + ASC_MIN_IRQ_NO));
9818 if ((bus_type & ASC_IS_VL) != 0) {
9820 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) {
9823 irq_no -= (uchar) ((ASC_MIN_IRQ_NO - 1));
9826 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE3);
9827 cfg_lsw |= (ushort) 0x0010;
9828 AscSetChipCfgLsw(iop_base, cfg_lsw);
9829 AscToggleIRQAct(iop_base);
9830 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE0);
9831 cfg_lsw |= (ushort) ((irq_no & 0x07) << 2);
9832 AscSetChipCfgLsw(iop_base, cfg_lsw);
9833 AscToggleIRQAct(iop_base);
9834 return (AscGetChipIRQ(iop_base, bus_type));
9836 if ((bus_type & (ASC_IS_ISA)) != 0) {
9838 irq_no -= (uchar) 2;
9839 irq_no -= (uchar) ASC_MIN_IRQ_NO;
9840 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFF3);
9841 cfg_lsw |= (ushort) ((irq_no & 0x03) << 2);
9842 AscSetChipCfgLsw(iop_base, cfg_lsw);
9843 return (AscGetChipIRQ(iop_base, bus_type));
9853 if (dma_channel < 4) {
9854 outp(0x000B, (ushort) (0xC0 | dma_channel));
9855 outp(0x000A, dma_channel);
9856 } else if (dma_channel < 8) {
9857 outp(0x00D6, (ushort) (0xC0 | (dma_channel - 4)));
9858 outp(0x00D4, (ushort) (dma_channel - 4));
9862 #endif /* CONFIG_ISA */
9866 ASC_DVC_VAR *asc_dvc
9873 ushort int_halt_code;
9874 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9875 ASC_SCSI_BIT_ID_TYPE target_id;
9882 uchar q_cntl, tid_no;
9886 asc_board_t *boardp;
9888 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
9889 boardp = asc_dvc->drv_ptr;
9891 iop_base = asc_dvc->iop_base;
9892 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
9894 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
9895 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
9896 target_ix = AscReadLramByte(iop_base,
9897 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TARGET_IX));
9898 q_cntl = AscReadLramByte(iop_base,
9899 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL));
9900 tid_no = ASC_TIX_TO_TID(target_ix);
9901 target_id = (uchar) ASC_TID_TO_TARGET_ID(tid_no);
9902 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9903 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
9907 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
9908 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9909 AscSetChipSDTR(iop_base, 0, tid_no);
9910 boardp->sdtr_data[tid_no] = 0;
9912 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9914 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
9915 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9916 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9917 boardp->sdtr_data[tid_no] = asyn_sdtr;
9919 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9921 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
9923 AscMemWordCopyPtrFromLram(iop_base,
9926 sizeof(EXT_MSG) >> 1);
9928 if (ext_msg.msg_type == MS_EXTEND &&
9929 ext_msg.msg_req == MS_SDTR_CODE &&
9930 ext_msg.msg_len == MS_SDTR_LEN) {
9932 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
9934 sdtr_accept = FALSE;
9935 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
9937 if ((ext_msg.xfer_period <
9938 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index]) ||
9939 (ext_msg.xfer_period >
9940 asc_dvc->sdtr_period_tbl[asc_dvc->max_sdtr_index])) {
9941 sdtr_accept = FALSE;
9942 ext_msg.xfer_period =
9943 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index];
9946 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9947 ext_msg.req_ack_offset);
9948 if ((sdtr_data == 0xFF)) {
9950 q_cntl |= QC_MSG_OUT;
9951 asc_dvc->init_sdtr &= ~target_id;
9952 asc_dvc->sdtr_done &= ~target_id;
9953 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9954 boardp->sdtr_data[tid_no] = asyn_sdtr;
9957 if (ext_msg.req_ack_offset == 0) {
9959 q_cntl &= ~QC_MSG_OUT;
9960 asc_dvc->init_sdtr &= ~target_id;
9961 asc_dvc->sdtr_done &= ~target_id;
9962 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9964 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
9966 q_cntl &= ~QC_MSG_OUT;
9967 asc_dvc->sdtr_done |= target_id;
9968 asc_dvc->init_sdtr |= target_id;
9969 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9970 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9971 ext_msg.req_ack_offset);
9972 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9973 boardp->sdtr_data[tid_no] = sdtr_data;
9976 q_cntl |= QC_MSG_OUT;
9977 AscMsgOutSDTR(asc_dvc,
9978 ext_msg.xfer_period,
9979 ext_msg.req_ack_offset);
9980 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9981 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9982 ext_msg.req_ack_offset);
9983 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9984 boardp->sdtr_data[tid_no] = sdtr_data;
9985 asc_dvc->sdtr_done |= target_id;
9986 asc_dvc->init_sdtr |= target_id;
9990 AscWriteLramByte(iop_base,
9991 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
9993 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9995 } else if (ext_msg.msg_type == MS_EXTEND &&
9996 ext_msg.msg_req == MS_WDTR_CODE &&
9997 ext_msg.msg_len == MS_WDTR_LEN) {
9999 ext_msg.wdtr_width = 0;
10000 AscMemWordCopyPtrToLram(iop_base,
10002 (uchar *) &ext_msg,
10003 sizeof(EXT_MSG) >> 1);
10004 q_cntl |= QC_MSG_OUT;
10005 AscWriteLramByte(iop_base,
10006 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10008 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10012 ext_msg.msg_type = MESSAGE_REJECT;
10013 AscMemWordCopyPtrToLram(iop_base,
10015 (uchar *) &ext_msg,
10016 sizeof(EXT_MSG) >> 1);
10017 q_cntl |= QC_MSG_OUT;
10018 AscWriteLramByte(iop_base,
10019 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10021 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10024 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
10026 q_cntl |= QC_REQ_SENSE;
10028 if ((asc_dvc->init_sdtr & target_id) != 0) {
10030 asc_dvc->sdtr_done &= ~target_id;
10032 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10033 q_cntl |= QC_MSG_OUT;
10034 AscMsgOutSDTR(asc_dvc,
10035 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10036 (uchar) (asc_dvc->max_sdtr_index - 1)],
10037 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10040 AscWriteLramByte(iop_base,
10041 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10044 tag_code = AscReadLramByte(iop_base,
10045 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE));
10048 (asc_dvc->pci_fix_asyn_xfer & target_id)
10049 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
10052 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
10053 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
10056 AscWriteLramByte(iop_base,
10057 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE),
10060 q_status = AscReadLramByte(iop_base,
10061 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10062 q_status |= (QS_READY | QS_BUSY);
10063 AscWriteLramByte(iop_base,
10064 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10067 scsi_busy = AscReadLramByte(iop_base,
10068 (ushort) ASCV_SCSIBUSY_B);
10069 scsi_busy &= ~target_id;
10070 AscWriteLramByte(iop_base, (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10072 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10074 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
10076 AscMemWordCopyPtrFromLram(iop_base,
10078 (uchar *) &out_msg,
10079 sizeof(EXT_MSG) >> 1);
10081 if ((out_msg.msg_type == MS_EXTEND) &&
10082 (out_msg.msg_len == MS_SDTR_LEN) &&
10083 (out_msg.msg_req == MS_SDTR_CODE)) {
10085 asc_dvc->init_sdtr &= ~target_id;
10086 asc_dvc->sdtr_done &= ~target_id;
10087 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
10088 boardp->sdtr_data[tid_no] = asyn_sdtr;
10090 q_cntl &= ~QC_MSG_OUT;
10091 AscWriteLramByte(iop_base,
10092 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10094 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10096 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
10098 scsi_status = AscReadLramByte(iop_base,
10099 (ushort) ((ushort) halt_q_addr + (ushort) ASC_SCSIQ_SCSI_STATUS));
10100 cur_dvc_qng = AscReadLramByte(iop_base,
10101 (ushort) ((ushort) ASC_QADR_BEG + (ushort) target_ix));
10102 if ((cur_dvc_qng > 0) &&
10103 (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
10105 scsi_busy = AscReadLramByte(iop_base,
10106 (ushort) ASCV_SCSIBUSY_B);
10107 scsi_busy |= target_id;
10108 AscWriteLramByte(iop_base,
10109 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10110 asc_dvc->queue_full_or_busy |= target_id;
10112 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
10113 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
10115 asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng;
10117 AscWriteLramByte(iop_base,
10118 (ushort) ((ushort) ASCV_MAX_DVC_QNG_BEG +
10123 * Set the device queue depth to the number of
10124 * active requests when the QUEUE FULL condition
10127 boardp->queue_full |= target_id;
10128 boardp->queue_full_cnt[tid_no] = cur_dvc_qng;
10132 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10135 #if CC_VERY_LONG_SG_LIST
10136 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
10141 uchar first_sg_wk_q_no;
10142 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
10143 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
10144 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
10145 ushort sg_list_dwords;
10146 ushort sg_entry_cnt;
10150 q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
10151 if (q_no == ASC_QLINK_END)
10156 q_addr = ASC_QNO_TO_QADDR(q_no);
10159 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
10160 * structure pointer using a macro provided by the driver.
10161 * The ASC_SCSI_REQ pointer provides a pointer to the
10162 * host ASC_SG_HEAD structure.
10164 /* Read request's SRB pointer. */
10165 scsiq = (ASC_SCSI_Q *)
10167 ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
10168 (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
10171 * Get request's first and working SG queue.
10173 sg_wk_q_no = AscReadLramByte(iop_base,
10174 (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
10176 first_sg_wk_q_no = AscReadLramByte(iop_base,
10177 (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
10180 * Reset request's working SG queue back to the
10183 AscWriteLramByte(iop_base,
10184 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
10187 sg_head = scsiq->sg_head;
10190 * Set sg_entry_cnt to the number of SG elements
10191 * that will be completed on this interrupt.
10193 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
10194 * SG elements. The data_cnt and data_addr fields which
10195 * add 1 to the SG element capacity are not used when
10196 * restarting SG handling after a halt.
10198 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
10200 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10203 * Keep track of remaining number of SG elements that will
10204 * need to be handled on the next interrupt.
10206 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
10209 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
10210 scsiq->remain_sg_entry_cnt = 0;
10214 * Copy SG elements into the list of allocated SG queues.
10216 * Last index completed is saved in scsiq->next_sg_index.
10218 next_qp = first_sg_wk_q_no;
10219 q_addr = ASC_QNO_TO_QADDR(next_qp);
10220 scsi_sg_q.sg_head_qp = q_no;
10221 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10222 for( i = 0; i < sg_head->queue_cnt; i++)
10224 scsi_sg_q.seq_no = i + 1;
10225 if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
10227 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
10228 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10230 * After very first SG queue RISC FW uses next
10231 * SG queue first element then checks sg_list_cnt
10232 * against zero and then decrements, so set
10233 * sg_list_cnt 1 less than number of SG elements
10234 * in each SG queue.
10236 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
10237 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
10240 * This is the last SG queue in the list of
10241 * allocated SG queues. If there are more
10242 * SG elements than will fit in the allocated
10243 * queues, then set the QCSG_SG_XFER_MORE flag.
10245 if (scsiq->remain_sg_entry_cnt != 0)
10247 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10250 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10252 /* equals sg_entry_cnt * 2 */
10253 sg_list_dwords = sg_entry_cnt << 1;
10254 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
10255 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
10259 scsi_sg_q.q_no = next_qp;
10260 AscMemWordCopyPtrToLram(iop_base,
10261 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10262 (uchar *) &scsi_sg_q,
10263 sizeof(ASC_SG_LIST_Q) >> 1);
10265 AscMemDWordCopyPtrToLram(iop_base,
10266 q_addr + ASC_SGQ_LIST_BEG,
10267 (uchar *) &sg_head->sg_list[scsiq->next_sg_index],
10270 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
10273 * If the just completed SG queue contained the
10274 * last SG element, then no more SG queues need
10277 if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
10282 next_qp = AscReadLramByte( iop_base,
10283 ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
10284 q_addr = ASC_QNO_TO_QADDR( next_qp );
10288 * Clear the halt condition so the RISC will be restarted
10289 * after the return.
10291 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10294 #endif /* CC_VERY_LONG_SG_LIST */
10299 _AscCopyLramScsiDoneQ(
10302 ASC_QDONE_INFO * scsiq,
10303 ASC_DCNT max_dma_count
10307 uchar sg_queue_cnt;
10309 DvcGetQinfo(iop_base,
10310 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
10312 (sizeof (ASC_SCSIQ_2) + sizeof (ASC_SCSIQ_3)) / 2);
10314 _val = AscReadLramWord(iop_base,
10315 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10316 scsiq->q_status = (uchar) _val;
10317 scsiq->q_no = (uchar) (_val >> 8);
10318 _val = AscReadLramWord(iop_base,
10319 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_CNTL));
10320 scsiq->cntl = (uchar) _val;
10321 sg_queue_cnt = (uchar) (_val >> 8);
10322 _val = AscReadLramWord(iop_base,
10323 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SENSE_LEN));
10324 scsiq->sense_len = (uchar) _val;
10325 scsiq->extra_bytes = (uchar) (_val >> 8);
10328 * Read high word of remain bytes from alternate location.
10330 scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
10331 (ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
10333 * Read low word of remain bytes from original location.
10335 scsiq->remain_bytes += AscReadLramWord(iop_base,
10336 (ushort) (q_addr+ (ushort) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
10338 scsiq->remain_bytes &= max_dma_count;
10339 return (sg_queue_cnt);
10344 ASC_DVC_VAR *asc_dvc
10350 uchar sg_queue_cnt;
10354 ASC_SCSI_BIT_ID_TYPE scsi_busy;
10355 ASC_SCSI_BIT_ID_TYPE target_id;
10359 uchar cur_target_qng;
10360 ASC_QDONE_INFO scsiq_buf;
10361 ASC_QDONE_INFO *scsiq;
10363 ASC_ISR_CALLBACK asc_isr_callback;
10365 iop_base = asc_dvc->iop_base;
10366 asc_isr_callback = asc_dvc->isr_callback;
10368 scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
10369 done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
10370 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
10371 next_qp = AscReadLramByte(iop_base,
10372 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_FWD));
10373 if (next_qp != ASC_QLINK_END) {
10374 AscPutVarDoneQTail(iop_base, next_qp);
10375 q_addr = ASC_QNO_TO_QADDR(next_qp);
10376 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
10377 asc_dvc->max_dma_count);
10378 AscWriteLramByte(iop_base,
10379 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10380 (uchar) (scsiq->q_status & (uchar) ~ (QS_READY | QS_ABORTED)));
10381 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
10382 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
10383 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
10384 sg_q_addr = q_addr;
10385 sg_list_qp = next_qp;
10386 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
10387 sg_list_qp = AscReadLramByte(iop_base,
10388 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_FWD));
10389 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
10390 if (sg_list_qp == ASC_QLINK_END) {
10391 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SG_Q_LINKS);
10392 scsiq->d3.done_stat = QD_WITH_ERROR;
10393 scsiq->d3.host_stat = QHSTA_D_QDONE_SG_LIST_CORRUPTED;
10394 goto FATAL_ERR_QDONE;
10396 AscWriteLramByte(iop_base,
10397 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10400 n_q_used = sg_queue_cnt + 1;
10401 AscPutVarDoneQTail(iop_base, sg_list_qp);
10403 if (asc_dvc->queue_full_or_busy & target_id) {
10404 cur_target_qng = AscReadLramByte(iop_base,
10405 (ushort) ((ushort) ASC_QADR_BEG + (ushort) scsiq->d2.target_ix));
10406 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
10407 scsi_busy = AscReadLramByte(iop_base,
10408 (ushort) ASCV_SCSIBUSY_B);
10409 scsi_busy &= ~target_id;
10410 AscWriteLramByte(iop_base,
10411 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10412 asc_dvc->queue_full_or_busy &= ~target_id;
10415 if (asc_dvc->cur_total_qng >= n_q_used) {
10416 asc_dvc->cur_total_qng -= n_q_used;
10417 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
10418 asc_dvc->cur_dvc_qng[tid_no]--;
10421 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
10422 scsiq->d3.done_stat = QD_WITH_ERROR;
10423 goto FATAL_ERR_QDONE;
10425 if ((scsiq->d2.srb_ptr == 0UL) ||
10426 ((scsiq->q_status & QS_ABORTED) != 0)) {
10428 } else if (scsiq->q_status == QS_DONE) {
10429 false_overrun = FALSE;
10430 if (scsiq->extra_bytes != 0) {
10431 scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
10433 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
10434 if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
10435 if ((scsiq->cntl & (QC_DATA_IN | QC_DATA_OUT)) == 0) {
10436 scsiq->d3.done_stat = QD_NO_ERROR;
10437 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10438 } else if (false_overrun) {
10439 scsiq->d3.done_stat = QD_NO_ERROR;
10440 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10442 } else if (scsiq->d3.host_stat ==
10443 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
10444 AscStopChip(iop_base);
10445 AscSetChipControl(iop_base,
10446 (uchar) (CC_SCSI_RESET | CC_HALT));
10447 DvcDelayNanoSecond(asc_dvc, 60000);
10448 AscSetChipControl(iop_base, CC_HALT);
10449 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10450 AscSetChipStatus(iop_base, 0);
10451 AscSetChipControl(iop_base, 0);
10454 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10455 (*asc_isr_callback) (asc_dvc, scsiq);
10457 if ((AscReadLramByte(iop_base,
10458 (ushort) (q_addr + (ushort) ASC_SCSIQ_CDB_BEG)) ==
10460 asc_dvc->unit_not_ready &= ~target_id;
10461 if (scsiq->d3.done_stat != QD_NO_ERROR) {
10462 asc_dvc->start_motor &= ~target_id;
10468 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
10470 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10471 (*asc_isr_callback) (asc_dvc, scsiq);
10481 ASC_DVC_VAR *asc_dvc
10484 ASC_CS_TYPE chipstat;
10486 ushort saved_ram_addr;
10488 uchar saved_ctrl_reg;
10493 iop_base = asc_dvc->iop_base;
10494 int_pending = FALSE;
10496 if (AscIsIntPending(iop_base) == 0)
10498 return int_pending;
10501 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
10502 || (asc_dvc->isr_callback == 0)
10506 if (asc_dvc->in_critical_cnt != 0) {
10507 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
10510 if (asc_dvc->is_in_int) {
10511 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
10514 asc_dvc->is_in_int = TRUE;
10515 ctrl_reg = AscGetChipControl(iop_base);
10516 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
10517 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
10518 chipstat = AscGetChipStatus(iop_base);
10519 if (chipstat & CSW_SCSI_RESET_LATCH) {
10520 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
10522 int_pending = TRUE;
10523 asc_dvc->sdtr_done = 0;
10524 saved_ctrl_reg &= (uchar) (~CC_HALT);
10525 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) &&
10528 DvcSleepMilliSecond(100);
10530 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
10531 AscSetChipControl(iop_base, CC_HALT);
10532 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10533 AscSetChipStatus(iop_base, 0);
10534 chipstat = AscGetChipStatus(iop_base);
10537 saved_ram_addr = AscGetChipLramAddr(iop_base);
10538 host_flag = AscReadLramByte(iop_base,
10539 ASCV_HOST_FLAG_B) & (uchar) (~ASC_HOST_FLAG_IN_ISR);
10540 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10541 (uchar) (host_flag | (uchar) ASC_HOST_FLAG_IN_ISR));
10542 if ((chipstat & CSW_INT_PENDING)
10545 AscAckInterrupt(iop_base);
10546 int_pending = TRUE;
10547 if ((chipstat & CSW_HALTED) &&
10548 (ctrl_reg & CC_SINGLE_STEP)) {
10549 if (AscIsrChipHalted(asc_dvc) == ERR) {
10550 goto ISR_REPORT_QDONE_FATAL_ERROR;
10552 saved_ctrl_reg &= (uchar) (~CC_HALT);
10555 ISR_REPORT_QDONE_FATAL_ERROR:
10556 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
10557 while (((status = AscIsrQDone(asc_dvc)) & 0x01) != 0) {
10561 if ((status = AscIsrQDone(asc_dvc)) == 1) {
10564 } while (status == 0x11);
10566 if ((status & 0x80) != 0)
10570 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10571 AscSetChipLramAddr(iop_base, saved_ram_addr);
10572 AscSetChipControl(iop_base, saved_ctrl_reg);
10573 asc_dvc->is_in_int = FALSE;
10574 return (int_pending);
10577 /* Microcode buffer is kept after initialization for error recovery. */
10578 STATIC uchar _asc_mcode_buf[] =
10580 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10581 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10582 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10583 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10584 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
10585 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10586 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
10587 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00,
10588 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
10589 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80,
10590 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80,
10591 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
10592 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D, 0x00,
10593 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1,
10594 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
10595 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, 0x84, 0x97, 0x07, 0xA6,
10596 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00,
10597 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
10598 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33,
10599 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04,
10600 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
10601 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A, 0x00,
10602 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04,
10603 0x36, 0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
10604 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, 0x3C, 0x01, 0x00, 0x05,
10605 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01,
10606 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
10607 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23,
10608 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0,
10609 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
10610 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84, 0x97,
10611 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80,
10612 0xF0, 0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
10613 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, 0x04, 0x98, 0xF0, 0x80,
10614 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6,
10615 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
10616 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02,
10617 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96,
10618 0x48, 0x82, 0x04, 0x23, 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
10619 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5, 0x01,
10620 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02,
10621 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
10622 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, 0x80, 0x63, 0x00, 0x43,
10623 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01,
10624 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
10625 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00,
10626 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6,
10627 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
10628 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE, 0x82,
10629 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8,
10630 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
10631 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, 0x3C, 0x04, 0x06, 0xA6,
10632 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83,
10633 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
10634 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03,
10635 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03,
10636 0xEC, 0x00, 0x6E, 0x00, 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
10637 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00, 0xA6,
10638 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03,
10639 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
10640 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, 0xC0, 0x83, 0x00, 0x33,
10641 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23,
10642 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
10643 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04,
10644 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84,
10645 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
10646 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00, 0x33,
10647 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC,
10648 0x00, 0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
10649 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0xA3, 0x01,
10650 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00,
10651 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
10652 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3,
10653 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23,
10654 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
10655 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8, 0x81,
10656 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81,
10657 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
10658 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, 0xF4, 0x04, 0x00, 0x33,
10659 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01,
10660 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
10661 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04,
10662 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85,
10663 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
10664 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81, 0x01,
10665 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01,
10666 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
10667 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, 0x07, 0xA4, 0xF8, 0x05,
10668 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0,
10669 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
10670 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85,
10671 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0,
10672 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
10673 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80, 0x63,
10674 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23,
10675 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
10676 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, 0x07, 0x41, 0x83, 0x03,
10677 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6,
10678 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
10679 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61,
10680 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01,
10681 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
10682 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06, 0xA6,
10683 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20,
10684 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
10685 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, 0x40, 0x0E, 0x80, 0x63,
10686 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43,
10687 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
10688 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06,
10689 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6,
10690 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
10691 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04, 0x01,
10692 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33,
10693 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
10694 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, 0x00, 0x00, 0x80, 0x67,
10695 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61,
10696 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
10697 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05,
10698 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01,
10699 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
10700 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70, 0x00,
10701 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00,
10702 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
10703 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, 0xC4, 0x07, 0x00, 0x33,
10704 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01,
10705 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
10706 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63,
10707 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02,
10708 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
10709 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3, 0x04,
10710 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08,
10711 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
10712 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, 0x5A, 0x88, 0x02, 0x01,
10713 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08,
10714 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
10715 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B,
10716 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09,
10717 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
10718 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40, 0x3A,
10719 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3,
10720 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
10721 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, 0xA1, 0x23, 0xA1, 0x01,
10722 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2,
10723 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
10726 STATIC ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
10727 STATIC ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
10729 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10730 STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
10752 ASC_DVC_VAR *asc_dvc,
10757 ulong last_int_level;
10760 int disable_syn_offset_one_fix;
10763 ASC_EXE_CALLBACK asc_exe_callback;
10764 ushort sg_entry_cnt = 0;
10765 ushort sg_entry_cnt_minus_one = 0;
10772 ASC_SG_HEAD *sg_head;
10775 iop_base = asc_dvc->iop_base;
10776 sg_head = scsiq->sg_head;
10777 asc_exe_callback = asc_dvc->exe_callback;
10778 if (asc_dvc->err_code != 0)
10780 if (scsiq == (ASC_SCSI_Q *) 0L) {
10781 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
10784 scsiq->q1.q_no = 0;
10785 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10786 scsiq->q1.extra_bytes = 0;
10789 target_ix = scsiq->q2.target_ix;
10790 tid_no = ASC_TIX_TO_TID(target_ix);
10792 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10793 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10794 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10795 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10796 AscMsgOutSDTR(asc_dvc,
10797 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10798 (uchar) (asc_dvc->max_sdtr_index - 1)],
10799 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10800 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10803 last_int_level = DvcEnterCritical();
10804 if (asc_dvc->in_critical_cnt != 0) {
10805 DvcLeaveCritical(last_int_level);
10806 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10809 asc_dvc->in_critical_cnt++;
10810 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10811 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10812 asc_dvc->in_critical_cnt--;
10813 DvcLeaveCritical(last_int_level);
10816 #if !CC_VERY_LONG_SG_LIST
10817 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10819 asc_dvc->in_critical_cnt--;
10820 DvcLeaveCritical(last_int_level);
10823 #endif /* !CC_VERY_LONG_SG_LIST */
10824 if (sg_entry_cnt == 1) {
10825 scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
10826 scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
10827 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10829 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10831 scsi_cmd = scsiq->cdbptr[0];
10832 disable_syn_offset_one_fix = FALSE;
10833 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10834 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10835 if (scsiq->q1.cntl & QC_SG_HEAD) {
10837 for (i = 0; i < sg_entry_cnt; i++) {
10838 data_cnt += (ADV_DCNT) le32_to_cpu(sg_head->sg_list[i].bytes);
10841 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10843 if (data_cnt != 0UL) {
10844 if (data_cnt < 512UL) {
10845 disable_syn_offset_one_fix = TRUE;
10847 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; i++) {
10848 disable_cmd = _syn_offset_one_disable_cmd[i];
10849 if (disable_cmd == 0xFF) {
10852 if (scsi_cmd == disable_cmd) {
10853 disable_syn_offset_one_fix = TRUE;
10860 if (disable_syn_offset_one_fix) {
10861 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10862 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10863 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10865 scsiq->q2.tag_code &= 0x27;
10867 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10868 if (asc_dvc->bug_fix_cntl) {
10869 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10870 if ((scsi_cmd == READ_6) ||
10871 (scsi_cmd == READ_10)) {
10873 (ADV_PADDR) le32_to_cpu(
10874 sg_head->sg_list[sg_entry_cnt_minus_one].addr) +
10875 (ADV_DCNT) le32_to_cpu(
10876 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10877 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10878 if ((extra_bytes != 0) &&
10879 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10881 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10882 scsiq->q1.extra_bytes = extra_bytes;
10883 data_cnt = le32_to_cpu(
10884 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10885 data_cnt -= (ASC_DCNT) extra_bytes;
10886 sg_head->sg_list[sg_entry_cnt_minus_one].bytes =
10887 cpu_to_le32(data_cnt);
10892 sg_head->entry_to_copy = sg_head->entry_cnt;
10893 #if CC_VERY_LONG_SG_LIST
10895 * Set the sg_entry_cnt to the maximum possible. The rest of
10896 * the SG elements will be copied when the RISC completes the
10897 * SG elements that fit and halts.
10899 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10901 sg_entry_cnt = ASC_MAX_SG_LIST;
10903 #endif /* CC_VERY_LONG_SG_LIST */
10904 n_q_required = AscSgListToQueue(sg_entry_cnt);
10905 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10906 (uint) n_q_required) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10907 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10908 n_q_required)) == 1) {
10909 asc_dvc->in_critical_cnt--;
10910 if (asc_exe_callback != 0) {
10911 (*asc_exe_callback) (asc_dvc, scsiq);
10913 DvcLeaveCritical(last_int_level);
10918 if (asc_dvc->bug_fix_cntl) {
10919 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10920 if ((scsi_cmd == READ_6) ||
10921 (scsi_cmd == READ_10)) {
10922 addr = le32_to_cpu(scsiq->q1.data_addr) +
10923 le32_to_cpu(scsiq->q1.data_cnt);
10924 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10925 if ((extra_bytes != 0) &&
10926 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10928 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10929 if (((ushort) data_cnt & 0x01FF) == 0) {
10930 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10931 data_cnt -= (ASC_DCNT) extra_bytes;
10932 scsiq->q1.data_cnt = cpu_to_le32(data_cnt);
10933 scsiq->q1.extra_bytes = extra_bytes;
10940 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10941 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10942 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10943 n_q_required)) == 1) {
10944 asc_dvc->in_critical_cnt--;
10945 if (asc_exe_callback != 0) {
10946 (*asc_exe_callback) (asc_dvc, scsiq);
10948 DvcLeaveCritical(last_int_level);
10953 asc_dvc->in_critical_cnt--;
10954 DvcLeaveCritical(last_int_level);
10960 ASC_DVC_VAR *asc_dvc,
10972 iop_base = asc_dvc->iop_base;
10973 target_ix = scsiq->q2.target_ix;
10974 tid_no = ASC_TIX_TO_TID(target_ix);
10976 free_q_head = (uchar) AscGetVarFreeQHead(iop_base);
10977 if (n_q_required > 1) {
10978 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
10979 free_q_head, (uchar) (n_q_required)))
10980 != (uchar) ASC_QLINK_END) {
10981 asc_dvc->last_q_shortage = 0;
10982 scsiq->sg_head->queue_cnt = n_q_required - 1;
10983 scsiq->q1.q_no = free_q_head;
10984 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10985 free_q_head)) == 1) {
10986 AscPutVarFreeQHead(iop_base, next_qp);
10987 asc_dvc->cur_total_qng += (uchar) (n_q_required);
10988 asc_dvc->cur_dvc_qng[tid_no]++;
10992 } else if (n_q_required == 1) {
10993 if ((next_qp = AscAllocFreeQueue(iop_base,
10994 free_q_head)) != ASC_QLINK_END) {
10995 scsiq->q1.q_no = free_q_head;
10996 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
10997 free_q_head)) == 1) {
10998 AscPutVarFreeQHead(iop_base, next_qp);
10999 asc_dvc->cur_total_qng++;
11000 asc_dvc->cur_dvc_qng[tid_no]++;
11015 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
11016 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
11018 return (n_sg_list_qs + 1);
11023 AscGetNumOfFreeQueue(
11024 ASC_DVC_VAR *asc_dvc,
11031 ASC_SCSI_BIT_ID_TYPE target_id;
11034 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
11035 tid_no = ASC_TIX_TO_TID(target_ix);
11036 if ((asc_dvc->unit_not_ready & target_id) ||
11037 (asc_dvc->queue_full_or_busy & target_id)) {
11041 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11042 (uint) asc_dvc->last_q_shortage +
11043 (uint) ASC_MIN_FREE_Q;
11045 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11046 (uint) ASC_MIN_FREE_Q;
11048 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
11049 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
11050 if (asc_dvc->cur_dvc_qng[tid_no] >=
11051 asc_dvc->max_dvc_qng[tid_no]) {
11054 return (cur_free_qs);
11057 if ((n_qs > asc_dvc->last_q_shortage) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
11058 asc_dvc->last_q_shortage = n_qs;
11066 ASC_DVC_VAR *asc_dvc,
11074 uchar syn_period_ix;
11078 iop_base = asc_dvc->iop_base;
11079 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
11080 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
11081 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
11082 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
11083 syn_period_ix = (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
11084 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
11085 AscMsgOutSDTR(asc_dvc,
11086 asc_dvc->sdtr_period_tbl[syn_period_ix],
11088 scsiq->q1.cntl |= QC_MSG_OUT;
11090 q_addr = ASC_QNO_TO_QADDR(q_no);
11091 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
11092 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG ;
11094 scsiq->q1.status = QS_FREE;
11095 AscMemWordCopyPtrToLram(iop_base,
11096 q_addr + ASC_SCSIQ_CDB_BEG,
11097 (uchar *) scsiq->cdbptr,
11098 scsiq->q2.cdb_len >> 1);
11100 DvcPutScsiQ(iop_base,
11101 q_addr + ASC_SCSIQ_CPY_BEG,
11102 (uchar *) &scsiq->q1.cntl,
11103 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
11104 AscWriteLramWord(iop_base,
11105 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
11106 (ushort) (((ushort) scsiq->q1.q_no << 8) | (ushort) QS_READY));
11111 AscPutReadySgListQueue(
11112 ASC_DVC_VAR *asc_dvc,
11119 ASC_SG_HEAD *sg_head;
11120 ASC_SG_LIST_Q scsi_sg_q;
11121 ASC_DCNT saved_data_addr;
11122 ASC_DCNT saved_data_cnt;
11124 ushort sg_list_dwords;
11126 ushort sg_entry_cnt;
11130 iop_base = asc_dvc->iop_base;
11131 sg_head = scsiq->sg_head;
11132 saved_data_addr = scsiq->q1.data_addr;
11133 saved_data_cnt = scsiq->q1.data_cnt;
11134 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
11135 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
11136 #if CC_VERY_LONG_SG_LIST
11138 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
11139 * then not all SG elements will fit in the allocated queues.
11140 * The rest of the SG elements will be copied when the RISC
11141 * completes the SG elements that fit and halts.
11143 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11146 * Set sg_entry_cnt to be the number of SG elements that
11147 * will fit in the allocated SG queues. It is minus 1, because
11148 * the first SG element is handled above. ASC_MAX_SG_LIST is
11149 * already inflated by 1 to account for this. For example it
11150 * may be 50 which is 1 + 7 queues * 7 SG elements.
11152 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
11155 * Keep track of remaining number of SG elements that will
11156 * need to be handled from a_isr.c.
11158 scsiq->remain_sg_entry_cnt = sg_head->entry_cnt - ASC_MAX_SG_LIST;
11161 #endif /* CC_VERY_LONG_SG_LIST */
11163 * Set sg_entry_cnt to be the number of SG elements that
11164 * will fit in the allocated SG queues. It is minus 1, because
11165 * the first SG element is handled above.
11167 sg_entry_cnt = sg_head->entry_cnt - 1;
11168 #if CC_VERY_LONG_SG_LIST
11170 #endif /* CC_VERY_LONG_SG_LIST */
11171 if (sg_entry_cnt != 0) {
11172 scsiq->q1.cntl |= QC_SG_HEAD;
11173 q_addr = ASC_QNO_TO_QADDR(q_no);
11175 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
11176 scsi_sg_q.sg_head_qp = q_no;
11177 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
11178 for (i = 0; i < sg_head->queue_cnt; i++) {
11179 scsi_sg_q.seq_no = i + 1;
11180 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
11181 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
11182 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
11184 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
11185 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
11187 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
11188 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
11191 #if CC_VERY_LONG_SG_LIST
11193 * This is the last SG queue in the list of
11194 * allocated SG queues. If there are more
11195 * SG elements than will fit in the allocated
11196 * queues, then set the QCSG_SG_XFER_MORE flag.
11198 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11200 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
11203 #endif /* CC_VERY_LONG_SG_LIST */
11204 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
11205 #if CC_VERY_LONG_SG_LIST
11207 #endif /* CC_VERY_LONG_SG_LIST */
11208 sg_list_dwords = sg_entry_cnt << 1;
11210 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
11211 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
11213 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
11214 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
11218 next_qp = AscReadLramByte(iop_base,
11219 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11220 scsi_sg_q.q_no = next_qp;
11221 q_addr = ASC_QNO_TO_QADDR(next_qp);
11222 AscMemWordCopyPtrToLram(iop_base,
11223 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
11224 (uchar *) &scsi_sg_q,
11225 sizeof(ASC_SG_LIST_Q) >> 1);
11226 AscMemDWordCopyPtrToLram(iop_base,
11227 q_addr + ASC_SGQ_LIST_BEG,
11228 (uchar *) &sg_head->sg_list[sg_index],
11230 sg_index += ASC_SG_LIST_PER_Q;
11231 scsiq->next_sg_index = sg_index;
11234 scsiq->q1.cntl &= ~QC_SG_HEAD;
11236 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
11237 scsiq->q1.data_addr = saved_data_addr;
11238 scsiq->q1.data_cnt = saved_data_cnt;
11243 AscSetRunChipSynRegAtID(
11251 if (AscHostReqRiscHalt(iop_base)) {
11252 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11253 AscStartChip(iop_base);
11260 AscSetChipSynRegAtID(
11266 ASC_SCSI_BIT_ID_TYPE org_id;
11270 AscSetBank(iop_base, 1);
11271 org_id = AscReadChipDvcID(iop_base);
11272 for (i = 0; i <= ASC_MAX_TID; i++) {
11273 if (org_id == (0x01 << i))
11276 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
11277 AscWriteChipDvcID(iop_base, id);
11278 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
11279 AscSetBank(iop_base, 0);
11280 AscSetChipSyn(iop_base, sdtr_data);
11281 if (AscGetChipSyn(iop_base) != sdtr_data) {
11287 AscSetBank(iop_base, 1);
11288 AscWriteChipDvcID(iop_base, org_id);
11289 AscSetBank(iop_base, 0);
11295 ASC_DVC_VAR *asc_dvc
11303 iop_base = asc_dvc->iop_base;
11305 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
11306 (ushort) (((int) (asc_dvc->max_total_qng + 2 + 1) * 64) >> 1)
11308 i = ASC_MIN_ACTIVE_QNO;
11309 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
11310 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11312 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11313 (uchar) (asc_dvc->max_total_qng));
11314 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11317 s_addr += ASC_QBLK_SIZE;
11318 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
11319 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11321 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11323 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11326 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11327 (uchar) ASC_QLINK_END);
11328 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11329 (uchar) (asc_dvc->max_total_qng - 1));
11330 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11331 (uchar) asc_dvc->max_total_qng);
11333 s_addr += ASC_QBLK_SIZE;
11334 for (; i <= (uchar) (asc_dvc->max_total_qng + 3);
11335 i++, s_addr += ASC_QBLK_SIZE) {
11336 AscWriteLramByte(iop_base,
11337 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_FWD), i);
11338 AscWriteLramByte(iop_base,
11339 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_BWD), i);
11340 AscWriteLramByte(iop_base,
11341 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_QNO), i);
11343 return (warn_code);
11348 ASC_DVC_VAR *asc_dvc
11355 iop_base = asc_dvc->iop_base;
11356 AscPutRiscVarFreeQHead(iop_base, 1);
11357 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11358 AscPutVarFreeQHead(iop_base, 1);
11359 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11360 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
11361 (uchar) ((int) asc_dvc->max_total_qng + 1));
11362 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
11363 (uchar) ((int) asc_dvc->max_total_qng + 2));
11364 AscWriteLramByte(iop_base, (ushort) ASCV_TOTAL_READY_Q_B,
11365 asc_dvc->max_total_qng);
11366 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
11367 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
11368 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
11369 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
11370 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
11371 AscPutQDoneInProgress(iop_base, 0);
11372 lram_addr = ASC_QADR_BEG;
11373 for (i = 0; i < 32; i++, lram_addr += 2) {
11374 AscWriteLramWord(iop_base, lram_addr, 0);
11380 AscSetLibErrorCode(
11381 ASC_DVC_VAR *asc_dvc,
11385 if (asc_dvc->err_code == 0) {
11386 asc_dvc->err_code = err_code;
11387 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
11396 ASC_DVC_VAR *asc_dvc,
11402 uchar sdtr_period_index;
11405 iop_base = asc_dvc->iop_base;
11406 sdtr_buf.msg_type = MS_EXTEND;
11407 sdtr_buf.msg_len = MS_SDTR_LEN;
11408 sdtr_buf.msg_req = MS_SDTR_CODE;
11409 sdtr_buf.xfer_period = sdtr_period;
11410 sdtr_offset &= ASC_SYN_MAX_OFFSET;
11411 sdtr_buf.req_ack_offset = sdtr_offset;
11412 if ((sdtr_period_index =
11413 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
11414 asc_dvc->max_sdtr_index) {
11415 AscMemWordCopyPtrToLram(iop_base,
11417 (uchar *) &sdtr_buf,
11418 sizeof (EXT_MSG) >> 1);
11419 return ((sdtr_period_index << 4) | sdtr_offset);
11422 sdtr_buf.req_ack_offset = 0;
11423 AscMemWordCopyPtrToLram(iop_base,
11425 (uchar *) &sdtr_buf,
11426 sizeof (EXT_MSG) >> 1);
11433 ASC_DVC_VAR *asc_dvc,
11439 uchar sdtr_period_ix;
11441 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
11443 (sdtr_period_ix > asc_dvc->max_sdtr_index)
11447 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
11458 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11459 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
11464 AscGetSynPeriodIndex(
11465 ASC_DVC_VAR *asc_dvc,
11469 uchar *period_table;
11474 period_table = asc_dvc->sdtr_period_tbl;
11475 max_index = (int) asc_dvc->max_sdtr_index;
11476 min_index = (int)asc_dvc->host_init_sdtr_index;
11477 if ((syn_time <= period_table[max_index])) {
11478 for (i = min_index; i < (max_index - 1); i++) {
11479 if (syn_time <= period_table[i]) {
11480 return ((uchar) i);
11483 return ((uchar) max_index);
11485 return ((uchar) (max_index + 1));
11499 q_addr = ASC_QNO_TO_QADDR(free_q_head);
11500 q_status = (uchar) AscReadLramByte(iop_base,
11501 (ushort) (q_addr + ASC_SCSIQ_B_STATUS));
11502 next_qp = AscReadLramByte(iop_base,
11503 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11504 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
11507 return (ASC_QLINK_END);
11511 AscAllocMultipleFreeQueue(
11519 for (i = 0; i < n_free_q; i++) {
11520 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
11521 == ASC_QLINK_END) {
11522 return (ASC_QLINK_END);
11525 return (free_q_head);
11529 AscHostReqRiscHalt(
11535 uchar saved_stop_code;
11537 if (AscIsChipHalted(iop_base))
11539 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
11540 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11541 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP
11544 if (AscIsChipHalted(iop_base)) {
11548 DvcSleepMilliSecond(100);
11549 } while (count++ < 20);
11550 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
11561 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11562 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11563 ASC_STOP_REQ_RISC_STOP);
11566 AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11567 ASC_STOP_ACK_RISC_STOP) {
11570 DvcSleepMilliSecond(100);
11571 } while (count++ < 20);
11577 DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
11583 DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
11585 udelay((nano_sec + 999)/1000);
11589 STATIC ASC_DCNT __init
11590 AscGetEisaProductID(
11594 ushort product_id_high, product_id_low;
11595 ASC_DCNT product_id;
11597 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
11598 product_id_low = inpw(eisa_iop);
11599 product_id_high = inpw(eisa_iop + 2);
11600 product_id = ((ASC_DCNT) product_id_high << 16) |
11601 (ASC_DCNT) product_id_low;
11602 return (product_id);
11605 STATIC PortAddr __init
11606 AscSearchIOPortAddrEISA(
11609 ASC_DCNT eisa_product_id;
11611 if (iop_base == 0) {
11612 iop_base = ASC_EISA_MIN_IOP_ADDR;
11614 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11616 if ((iop_base & 0x0050) == 0x0050) {
11617 iop_base += ASC_EISA_BIG_IOP_GAP;
11619 iop_base += ASC_EISA_SMALL_IOP_GAP;
11622 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
11623 eisa_product_id = AscGetEisaProductID(iop_base);
11624 if ((eisa_product_id == ASC_EISA_ID_740) ||
11625 (eisa_product_id == ASC_EISA_ID_750)) {
11626 if (AscFindSignature(iop_base)) {
11627 inpw(iop_base + 4);
11631 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11633 if ((iop_base & 0x0050) == 0x0050) {
11634 iop_base += ASC_EISA_BIG_IOP_GAP;
11636 iop_base += ASC_EISA_SMALL_IOP_GAP;
11641 #endif /* CONFIG_ISA */
11648 AscSetChipControl(iop_base, 0);
11649 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11662 cc_val = AscGetChipControl(iop_base) & (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
11663 AscSetChipControl(iop_base, (uchar) (cc_val | CC_HALT));
11664 AscSetChipIH(iop_base, INS_HALT);
11665 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11666 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
11677 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11678 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
11691 AscSetBank(iop_base, 1);
11692 AscWriteChipIH(iop_base, ins_code);
11693 AscSetBank(iop_base, 0);
11708 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
11709 if (loop++ > 0x7FFF) {
11712 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
11713 host_flag = AscReadLramByte(iop_base, ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
11714 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
11715 (uchar) (host_flag | ASC_HOST_FLAG_ACK_INT));
11716 AscSetChipStatus(iop_base, CIW_INT_ACK);
11718 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
11719 AscSetChipStatus(iop_base, CIW_INT_ACK);
11724 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
11729 AscDisableInterrupt(
11735 cfg = AscGetChipCfgLsw(iop_base);
11736 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
11741 AscEnableInterrupt(
11747 cfg = AscGetChipCfgLsw(iop_base);
11748 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
11762 val = AscGetChipControl(iop_base) &
11763 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | CC_CHIP_RESET));
11765 val |= CC_BANK_ONE;
11766 } else if (bank == 2) {
11767 val |= CC_DIAG | CC_BANK_ONE;
11769 val &= ~CC_BANK_ONE;
11771 AscSetChipControl(iop_base, val);
11776 AscResetChipAndScsiBus(
11777 ASC_DVC_VAR *asc_dvc
11783 iop_base = asc_dvc->iop_base;
11784 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) && (i-- > 0))
11786 DvcSleepMilliSecond(100);
11788 AscStopChip(iop_base);
11789 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
11790 DvcDelayNanoSecond(asc_dvc, 60000);
11791 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11792 AscSetChipIH(iop_base, INS_HALT);
11793 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
11794 AscSetChipControl(iop_base, CC_HALT);
11795 DvcSleepMilliSecond(200);
11796 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
11797 AscSetChipStatus(iop_base, 0);
11798 return (AscIsChipHalted(iop_base));
11801 STATIC ASC_DCNT __init
11805 if (bus_type & ASC_IS_ISA)
11806 return (ASC_MAX_ISA_DMA_COUNT);
11807 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11808 return (ASC_MAX_VL_DMA_COUNT);
11809 return (ASC_MAX_PCI_DMA_COUNT);
11813 STATIC ushort __init
11814 AscGetIsaDmaChannel(
11819 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11820 if (channel == 0x03)
11822 else if (channel == 0x00)
11824 return (channel + 4);
11827 STATIC ushort __init
11828 AscSetIsaDmaChannel(
11830 ushort dma_channel)
11835 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11836 if (dma_channel == 7)
11839 value = dma_channel - 4;
11840 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11842 AscSetChipCfgLsw(iop_base, cfg_lsw);
11843 return (AscGetIsaDmaChannel(iop_base));
11848 STATIC uchar __init
11853 speed_value &= 0x07;
11854 AscSetBank(iop_base, 1);
11855 AscWriteChipDmaSpeed(iop_base, speed_value);
11856 AscSetBank(iop_base, 0);
11857 return (AscGetIsaDmaSpeed(iop_base));
11860 STATIC uchar __init
11867 AscSetBank(iop_base, 1);
11868 speed_value = AscReadChipDmaSpeed(iop_base);
11869 speed_value &= 0x07;
11870 AscSetBank(iop_base, 0);
11871 return (speed_value);
11873 #endif /* CONFIG_ISA */
11875 STATIC ushort __init
11876 AscReadPCIConfigWord(
11877 ASC_DVC_VAR *asc_dvc,
11878 ushort pci_config_offset)
11882 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
11883 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
11884 return ((ushort) ((msb << 8) | lsb));
11887 STATIC ushort __init
11889 ASC_DVC_VAR *asc_dvc
11894 ushort PCIDeviceID;
11895 ushort PCIVendorID;
11896 uchar PCIRevisionID;
11897 uchar prevCmdRegBits;
11900 iop_base = asc_dvc->iop_base;
11901 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11902 if (asc_dvc->err_code != 0) {
11905 if (asc_dvc->bus_type == ASC_IS_PCI) {
11906 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
11907 AscPCIConfigVendorIDRegister);
11909 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
11910 AscPCIConfigDeviceIDRegister);
11912 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
11913 AscPCIConfigRevisionIDRegister);
11915 if (PCIVendorID != PCI_VENDOR_ID_ASP) {
11916 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11918 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
11919 AscPCIConfigCommandRegister);
11921 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
11922 AscPCICmdRegBits_IOMemBusMaster) {
11923 DvcWritePCIConfigByte(asc_dvc,
11924 AscPCIConfigCommandRegister,
11926 AscPCICmdRegBits_IOMemBusMaster));
11928 if ((DvcReadPCIConfigByte(asc_dvc,
11929 AscPCIConfigCommandRegister)
11930 & AscPCICmdRegBits_IOMemBusMaster)
11931 != AscPCICmdRegBits_IOMemBusMaster) {
11932 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11935 if ((PCIDeviceID == PCI_DEVICE_ID_ASP_1200A) ||
11936 (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940)) {
11937 DvcWritePCIConfigByte(asc_dvc,
11938 AscPCIConfigLatencyTimer, 0x00);
11939 if (DvcReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer)
11941 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11943 } else if (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940U) {
11944 if (DvcReadPCIConfigByte(asc_dvc,
11945 AscPCIConfigLatencyTimer) < 0x20) {
11946 DvcWritePCIConfigByte(asc_dvc,
11947 AscPCIConfigLatencyTimer, 0x20);
11949 if (DvcReadPCIConfigByte(asc_dvc,
11950 AscPCIConfigLatencyTimer) < 0x20) {
11951 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11957 if (AscFindSignature(iop_base)) {
11958 warn_code |= AscInitAscDvcVar(asc_dvc);
11959 warn_code |= AscInitFromEEP(asc_dvc);
11960 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11961 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
11962 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11965 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11970 STATIC ushort __init
11972 ASC_DVC_VAR *asc_dvc
11975 ushort warn_code = 0;
11977 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11978 if (asc_dvc->err_code != 0)
11980 if (AscFindSignature(asc_dvc->iop_base)) {
11981 warn_code |= AscInitFromAscDvcVar(asc_dvc);
11982 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11984 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11986 return (warn_code);
11989 STATIC ushort __init
11990 AscInitFromAscDvcVar(
11991 ASC_DVC_VAR *asc_dvc
11997 ushort pci_device_id = 0;
11999 iop_base = asc_dvc->iop_base;
12001 if (asc_dvc->cfg->dev)
12002 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
12005 cfg_msw = AscGetChipCfgMsw(iop_base);
12006 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12007 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12008 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12009 AscSetChipCfgMsw(iop_base, cfg_msw);
12011 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12012 asc_dvc->cfg->cmd_qng_enabled) {
12013 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12014 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12016 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12017 warn_code |= ASC_WARN_AUTO_CONFIG;
12019 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12020 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12021 != asc_dvc->irq_no) {
12022 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12025 if (asc_dvc->bus_type & ASC_IS_PCI) {
12027 AscSetChipCfgMsw(iop_base, cfg_msw);
12028 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12030 if ((pci_device_id == PCI_DEVICE_ID_ASP_1200A) ||
12031 (pci_device_id == PCI_DEVICE_ID_ASP_ABP940)) {
12032 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12033 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12036 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12037 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12038 == ASC_CHIP_VER_ASYN_BUG) {
12039 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12042 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12043 asc_dvc->cfg->chip_scsi_id) {
12044 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12047 if (asc_dvc->bus_type & ASC_IS_ISA) {
12048 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12049 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12051 #endif /* CONFIG_ISA */
12052 return (warn_code);
12056 AscInitAsc1000Driver(
12057 ASC_DVC_VAR *asc_dvc
12063 iop_base = asc_dvc->iop_base;
12065 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
12066 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
12067 AscResetChipAndScsiBus(asc_dvc);
12068 DvcSleepMilliSecond((ASC_DCNT)
12069 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12071 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
12072 if (asc_dvc->err_code != 0)
12074 if (!AscFindSignature(asc_dvc->iop_base)) {
12075 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12076 return (warn_code);
12078 AscDisableInterrupt(iop_base);
12079 warn_code |= AscInitLram(asc_dvc);
12080 if (asc_dvc->err_code != 0)
12082 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
12083 (ulong) _asc_mcode_chksum);
12084 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
12085 _asc_mcode_size) != _asc_mcode_chksum) {
12086 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
12087 return (warn_code);
12089 warn_code |= AscInitMicroCodeVar(asc_dvc);
12090 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
12091 AscEnableInterrupt(iop_base);
12092 return (warn_code);
12095 STATIC ushort __init
12097 ASC_DVC_VAR *asc_dvc)
12102 uchar chip_version;
12104 iop_base = asc_dvc->iop_base;
12106 asc_dvc->err_code = 0;
12107 if ((asc_dvc->bus_type &
12108 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
12109 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
12111 AscSetChipControl(iop_base, CC_HALT);
12112 AscSetChipStatus(iop_base, 0);
12113 asc_dvc->bug_fix_cntl = 0;
12114 asc_dvc->pci_fix_asyn_xfer = 0;
12115 asc_dvc->pci_fix_asyn_xfer_always = 0;
12116 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
12117 asc_dvc->sdtr_done = 0;
12118 asc_dvc->cur_total_qng = 0;
12119 asc_dvc->is_in_int = 0;
12120 asc_dvc->in_critical_cnt = 0;
12121 asc_dvc->last_q_shortage = 0;
12122 asc_dvc->use_tagged_qng = 0;
12123 asc_dvc->no_scam = 0;
12124 asc_dvc->unit_not_ready = 0;
12125 asc_dvc->queue_full_or_busy = 0;
12126 asc_dvc->redo_scam = 0;
12128 asc_dvc->host_init_sdtr_index = 0;
12129 asc_dvc->cfg->can_tagged_qng = 0;
12130 asc_dvc->cfg->cmd_qng_enabled = 0;
12131 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
12132 asc_dvc->init_sdtr = 0;
12133 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
12134 asc_dvc->scsi_reset_wait = 3;
12135 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
12136 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
12137 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
12138 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
12139 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
12140 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
12141 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
12142 ASC_LIB_VERSION_MINOR;
12143 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
12144 asc_dvc->cfg->chip_version = chip_version;
12145 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
12146 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
12147 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
12148 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
12149 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
12150 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
12151 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
12152 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
12153 asc_dvc->max_sdtr_index = 7;
12154 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
12155 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
12156 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
12157 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
12158 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
12159 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
12160 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
12161 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
12162 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
12163 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
12164 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
12165 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
12166 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
12167 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
12168 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
12169 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
12170 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
12171 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
12172 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
12173 asc_dvc->max_sdtr_index = 15;
12174 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
12176 AscSetExtraControl(iop_base,
12177 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12178 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
12179 AscSetExtraControl(iop_base,
12180 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
12183 if (asc_dvc->bus_type == ASC_IS_PCI) {
12184 AscSetExtraControl(iop_base, (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12187 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
12188 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
12189 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
12190 asc_dvc->bus_type = ASC_IS_ISAPNP;
12193 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
12194 asc_dvc->cfg->isa_dma_channel = (uchar) AscGetIsaDmaChannel(iop_base);
12196 #endif /* CONFIG_ISA */
12197 for (i = 0; i <= ASC_MAX_TID; i++) {
12198 asc_dvc->cur_dvc_qng[i] = 0;
12199 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
12200 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *) 0L;
12201 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *) 0L;
12202 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
12204 return (warn_code);
12207 STATIC ushort __init
12208 AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12210 ASCEEP_CONFIG eep_config_buf;
12211 ASCEEP_CONFIG *eep_config;
12215 ushort cfg_msw, cfg_lsw;
12219 iop_base = asc_dvc->iop_base;
12221 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12222 AscStopQueueExe(iop_base);
12223 if ((AscStopChip(iop_base) == FALSE) ||
12224 (AscGetChipScsiCtrl(iop_base) != 0)) {
12225 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12226 AscResetChipAndScsiBus(asc_dvc);
12227 DvcSleepMilliSecond((ASC_DCNT)
12228 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12230 if (AscIsChipHalted(iop_base) == FALSE) {
12231 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12232 return (warn_code);
12234 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12235 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12236 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12237 return (warn_code);
12239 eep_config = (ASCEEP_CONFIG *) &eep_config_buf;
12240 cfg_msw = AscGetChipCfgMsw(iop_base);
12241 cfg_lsw = AscGetChipCfgLsw(iop_base);
12242 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12243 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12244 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12245 AscSetChipCfgMsw(iop_base, cfg_msw);
12247 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12248 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12252 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12253 warn_code |= ASC_WARN_AUTO_CONFIG;
12254 if (asc_dvc->cfg->chip_version == 3) {
12255 if (eep_config->cfg_lsw != cfg_lsw) {
12256 warn_code |= ASC_WARN_EEPROM_RECOVER;
12257 eep_config->cfg_lsw = AscGetChipCfgLsw(iop_base);
12259 if (eep_config->cfg_msw != cfg_msw) {
12260 warn_code |= ASC_WARN_EEPROM_RECOVER;
12261 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12265 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12266 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12267 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12268 eep_config->chksum);
12269 if (chksum != eep_config->chksum) {
12270 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12271 ASC_CHIP_VER_PCI_ULTRA_3050 )
12274 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12275 eep_config->init_sdtr = 0xFF;
12276 eep_config->disc_enable = 0xFF;
12277 eep_config->start_motor = 0xFF;
12278 eep_config->use_cmd_qng = 0;
12279 eep_config->max_total_qng = 0xF0;
12280 eep_config->max_tag_qng = 0x20;
12281 eep_config->cntl = 0xBFFF;
12282 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12283 eep_config->no_scam = 0;
12284 eep_config->adapter_info[0] = 0;
12285 eep_config->adapter_info[1] = 0;
12286 eep_config->adapter_info[2] = 0;
12287 eep_config->adapter_info[3] = 0;
12288 eep_config->adapter_info[4] = 0;
12289 /* Indicate EEPROM-less board. */
12290 eep_config->adapter_info[5] = 0xBB;
12293 "AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12295 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12298 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12299 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12300 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12301 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12302 asc_dvc->start_motor = eep_config->start_motor;
12303 asc_dvc->dvc_cntl = eep_config->cntl;
12304 asc_dvc->no_scam = eep_config->no_scam;
12305 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12306 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12307 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12308 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12309 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12310 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12311 if (!AscTestExternalLram(asc_dvc)) {
12312 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
12313 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12314 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12316 eep_config->cfg_msw |= 0x0800;
12318 AscSetChipCfgMsw(iop_base, cfg_msw);
12319 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12320 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12324 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12325 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12327 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12328 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12330 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12331 eep_config->max_tag_qng = eep_config->max_total_qng;
12333 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12334 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12336 asc_dvc->max_total_qng = eep_config->max_total_qng;
12337 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12338 eep_config->use_cmd_qng) {
12339 eep_config->disc_enable = eep_config->use_cmd_qng;
12340 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12342 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12343 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12345 ASC_EEP_SET_CHIP_ID(eep_config, ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12346 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12347 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12348 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12349 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12352 for (i = 0; i <= ASC_MAX_TID; i++) {
12353 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12354 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12355 asc_dvc->cfg->sdtr_period_offset[i] =
12356 (uchar) (ASC_DEF_SDTR_OFFSET |
12357 (asc_dvc->host_init_sdtr_index << 4));
12359 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12361 if ((i = AscSetEEPConfig(iop_base, eep_config, asc_dvc->bus_type)) !=
12364 "AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", i);
12366 ASC_PRINT("AscInitFromEEP: Succesfully re-wrote EEPROM.");
12369 return (warn_code);
12373 AscInitMicroCodeVar(
12374 ASC_DVC_VAR *asc_dvc
12380 ASC_PADDR phy_addr;
12383 iop_base = asc_dvc->iop_base;
12385 for (i = 0; i <= ASC_MAX_TID; i++) {
12386 AscPutMCodeInitSDTRAtID(iop_base, i,
12387 asc_dvc->cfg->sdtr_period_offset[i]
12391 AscInitQLinkVar(asc_dvc);
12392 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
12393 asc_dvc->cfg->disc_enable);
12394 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
12395 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
12397 /* Align overrun buffer on an 8 byte boundary. */
12398 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
12399 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
12400 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
12401 (uchar *) &phy_addr, 1);
12402 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
12403 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
12404 (uchar *) &phy_size, 1);
12406 asc_dvc->cfg->mcode_date =
12407 AscReadLramWord(iop_base, (ushort) ASCV_MC_DATE_W);
12408 asc_dvc->cfg->mcode_version =
12409 AscReadLramWord(iop_base, (ushort) ASCV_MC_VER_W);
12411 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12412 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12413 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12414 return (warn_code);
12416 if (AscStartChip(iop_base) != 1) {
12417 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12418 return (warn_code);
12421 return (warn_code);
12425 AscTestExternalLram(
12426 ASC_DVC_VAR *asc_dvc)
12433 iop_base = asc_dvc->iop_base;
12435 q_addr = ASC_QNO_TO_QADDR(241);
12436 saved_word = AscReadLramWord(iop_base, q_addr);
12437 AscSetChipLramAddr(iop_base, q_addr);
12438 AscSetChipLramData(iop_base, 0x55AA);
12439 DvcSleepMilliSecond(10);
12440 AscSetChipLramAddr(iop_base, q_addr);
12441 if (AscGetChipLramData(iop_base) == 0x55AA) {
12443 AscWriteLramWord(iop_base, q_addr, saved_word);
12459 AscSetChipEEPCmd(iop_base, cmd_reg);
12460 DvcSleepMilliSecond(1);
12461 read_back = AscGetChipEEPCmd(iop_base);
12462 if (read_back == cmd_reg) {
12465 if (retry++ > ASC_EEP_MAX_RETRY) {
12472 AscWriteEEPDataReg(
12482 AscSetChipEEPData(iop_base, data_reg);
12483 DvcSleepMilliSecond(1);
12484 read_back = AscGetChipEEPData(iop_base);
12485 if (read_back == data_reg) {
12488 if (retry++ > ASC_EEP_MAX_RETRY) {
12495 AscWaitEEPRead(void)
12497 DvcSleepMilliSecond(1);
12502 AscWaitEEPWrite(void)
12504 DvcSleepMilliSecond(20);
12508 STATIC ushort __init
12516 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12518 cmd_reg = addr | ASC_EEP_CMD_READ;
12519 AscWriteEEPCmdReg(iop_base, cmd_reg);
12521 read_wval = AscGetChipEEPData(iop_base);
12523 return (read_wval);
12526 STATIC ushort __init
12534 read_wval = AscReadEEPWord(iop_base, addr);
12535 if (read_wval != word_val) {
12536 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12538 AscWriteEEPDataReg(iop_base, word_val);
12540 AscWriteEEPCmdReg(iop_base,
12541 (uchar) ((uchar) ASC_EEP_CMD_WRITE | addr));
12543 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12545 return (AscReadEEPWord(iop_base, addr));
12547 return (read_wval);
12550 STATIC ushort __init
12553 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12560 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12563 wbuf = (ushort *) cfg_buf;
12565 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
12566 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12567 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12570 if (bus_type & ASC_IS_VL) {
12571 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12572 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12574 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12575 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12577 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12578 wval = AscReadEEPWord( iop_base, ( uchar )s_addr ) ;
12579 if (s_addr <= uchar_end_in_config) {
12581 * Swap all char fields - must unswap bytes already swapped
12582 * by AscReadEEPWord().
12584 *wbuf = le16_to_cpu(wval);
12586 /* Don't swap word field at the end - cntl field. */
12589 sum += wval; /* Checksum treats all EEPROM data as words. */
12592 * Read the checksum word which will be compared against 'sum'
12593 * by the caller. Word field already swapped.
12595 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12600 AscSetEEPConfigOnce(
12602 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12611 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12614 wbuf = (ushort *) cfg_buf;
12617 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12618 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12620 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12624 if (bus_type & ASC_IS_VL) {
12625 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12626 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12628 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12629 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12631 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12632 if (s_addr <= uchar_end_in_config) {
12634 * This is a char field. Swap char fields before they are
12635 * swapped again by AscWriteEEPWord().
12637 word = cpu_to_le16(*wbuf);
12638 if (word != AscWriteEEPWord( iop_base, (uchar) s_addr, word)) {
12642 /* Don't swap word field at the end - cntl field. */
12643 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12647 sum += *wbuf; /* Checksum calculated from word values. */
12649 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12651 if (sum != AscWriteEEPWord(iop_base, (uchar) s_addr, sum)) {
12655 /* Read EEPROM back again. */
12656 wbuf = (ushort *) cfg_buf;
12658 * Read two config words; Byte-swapping done by AscReadEEPWord().
12660 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12661 if (*wbuf != AscReadEEPWord(iop_base, (uchar) s_addr)) {
12665 if (bus_type & ASC_IS_VL) {
12666 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12667 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12669 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12670 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12672 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12673 if (s_addr <= uchar_end_in_config) {
12675 * Swap all char fields. Must unswap bytes already swapped
12676 * by AscReadEEPWord().
12678 word = le16_to_cpu(AscReadEEPWord(iop_base, (uchar) s_addr));
12680 /* Don't swap word field at the end - cntl field. */
12681 word = AscReadEEPWord(iop_base, (uchar) s_addr);
12683 if (*wbuf != word) {
12687 /* Read checksum; Byte swapping not needed. */
12688 if (AscReadEEPWord(iop_base, (uchar) s_addr) != sum) {
12697 ASCEEP_CONFIG * cfg_buf, ushort bus_type
12705 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12709 if (++retry > ASC_EEP_MAX_RETRY) {
12718 ASC_DVC_VAR *asc_dvc,
12720 ASC_SCSI_INQUIRY *inq)
12723 ASC_SCSI_BIT_ID_TYPE tid_bits;
12725 dvc_type = ASC_INQ_DVC_TYPE(inq);
12726 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
12728 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)
12730 if (!(asc_dvc->init_sdtr & tid_bits))
12732 if ((dvc_type == TYPE_ROM) &&
12733 (AscCompareString((uchar *) inq->vendor_id,
12734 (uchar *) "HP ", 3) == 0))
12736 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
12738 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
12739 if ((dvc_type == TYPE_PROCESSOR) ||
12740 (dvc_type == TYPE_SCANNER) ||
12741 (dvc_type == TYPE_ROM) ||
12742 (dvc_type == TYPE_TAPE))
12744 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
12747 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
12749 AscSetRunChipSynRegAtID(asc_dvc->iop_base, tid_no,
12750 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
12758 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
12760 if ((inq->add_len >= 32) &&
12761 (AscCompareString((uchar *) inq->vendor_id,
12762 (uchar *) "QUANTUM XP34301", 15) == 0) &&
12763 (AscCompareString((uchar *) inq->product_rev_level,
12764 (uchar *) "1071", 4) == 0))
12772 AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
12773 uchar tid_no, ASC_SCSI_INQUIRY *inq)
12775 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
12776 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
12778 orig_init_sdtr = asc_dvc->init_sdtr;
12779 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
12781 asc_dvc->init_sdtr &= ~tid_bit;
12782 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
12783 asc_dvc->use_tagged_qng &= ~tid_bit;
12785 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
12786 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
12787 asc_dvc->init_sdtr |= tid_bit;
12789 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
12790 ASC_INQ_CMD_QUEUE(inq)) {
12791 if (AscTagQueuingSafe(inq)) {
12792 asc_dvc->use_tagged_qng |= tid_bit;
12793 asc_dvc->cfg->can_tagged_qng |= tid_bit;
12797 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
12798 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
12799 asc_dvc->cfg->disc_enable);
12800 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
12801 asc_dvc->use_tagged_qng);
12802 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
12803 asc_dvc->cfg->can_tagged_qng);
12805 asc_dvc->max_dvc_qng[tid_no] =
12806 asc_dvc->cfg->max_tag_qng[tid_no];
12807 AscWriteLramByte(asc_dvc->iop_base,
12808 (ushort) (ASCV_MAX_DVC_QNG_BEG + tid_no),
12809 asc_dvc->max_dvc_qng[tid_no]);
12811 if (orig_init_sdtr != asc_dvc->init_sdtr) {
12812 AscAsyncFix(asc_dvc, tid_no, inq);
12827 for (i = 0; i < len; i++) {
12828 diff = (int) (str1[i] - str2[i]);
12844 if (isodd_word(addr)) {
12845 AscSetChipLramAddr(iop_base, addr - 1);
12846 word_data = AscGetChipLramData(iop_base);
12847 byte_data = (uchar) ((word_data >> 8) & 0xFF);
12849 AscSetChipLramAddr(iop_base, addr);
12850 word_data = AscGetChipLramData(iop_base);
12851 byte_data = (uchar) (word_data & 0xFF);
12853 return (byte_data);
12863 AscSetChipLramAddr(iop_base, addr);
12864 word_data = AscGetChipLramData(iop_base);
12865 return (word_data);
12868 #if CC_VERY_LONG_SG_LIST
12875 ushort val_low, val_high;
12876 ASC_DCNT dword_data;
12878 AscSetChipLramAddr(iop_base, addr);
12879 val_low = AscGetChipLramData(iop_base);
12880 val_high = AscGetChipLramData(iop_base);
12881 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
12882 return (dword_data);
12884 #endif /* CC_VERY_LONG_SG_LIST */
12893 AscSetChipLramAddr(iop_base, addr);
12894 AscSetChipLramData(iop_base, word_val);
12907 if (isodd_word(addr)) {
12909 word_data = AscReadLramWord(iop_base, addr);
12910 word_data &= 0x00FF;
12911 word_data |= (((ushort) byte_val << 8) & 0xFF00);
12913 word_data = AscReadLramWord(iop_base, addr);
12914 word_data &= 0xFF00;
12915 word_data |= ((ushort) byte_val & 0x00FF);
12917 AscWriteLramWord(iop_base, addr, word_data);
12922 * Copy 2 bytes to LRAM.
12924 * The source data is assumed to be in little-endian order in memory
12925 * and is maintained in little-endian order when written to LRAM.
12928 AscMemWordCopyPtrToLram(
12937 AscSetChipLramAddr(iop_base, s_addr);
12938 for (i = 0; i < 2 * words; i += 2) {
12940 * On a little-endian system the second argument below
12941 * produces a little-endian ushort which is written to
12942 * LRAM in little-endian order. On a big-endian system
12943 * the second argument produces a big-endian ushort which
12944 * is "transparently" byte-swapped by outpw() and written
12945 * in little-endian order to LRAM.
12947 outpw(iop_base + IOP_RAM_DATA,
12948 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]);
12954 * Copy 4 bytes to LRAM.
12956 * The source data is assumed to be in little-endian order in memory
12957 * and is maintained in little-endian order when writen to LRAM.
12960 AscMemDWordCopyPtrToLram(
12969 AscSetChipLramAddr(iop_base, s_addr);
12970 for (i = 0; i < 4 * dwords; i += 4) {
12971 outpw(iop_base + IOP_RAM_DATA,
12972 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
12973 outpw(iop_base + IOP_RAM_DATA,
12974 ((ushort) s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
12980 * Copy 2 bytes from LRAM.
12982 * The source data is assumed to be in little-endian order in LRAM
12983 * and is maintained in little-endian order when written to memory.
12986 AscMemWordCopyPtrFromLram(
12996 AscSetChipLramAddr(iop_base, s_addr);
12997 for (i = 0; i < 2 * words; i += 2) {
12998 word = inpw(iop_base + IOP_RAM_DATA);
12999 d_buffer[i] = word & 0xff;
13000 d_buffer[i + 1] = (word >> 8) & 0xff;
13016 for (i = 0; i < words; i++, s_addr += 2) {
13017 sum += AscReadLramWord(iop_base, s_addr);
13032 AscSetChipLramAddr(iop_base, s_addr);
13033 for (i = 0; i < words; i++) {
13034 AscSetChipLramData(iop_base, set_wval);
13041 * --- Adv Library Functions
13046 /* Microcode buffer is kept after initialization for error recovery. */
13047 STATIC unsigned char _adv_asc3550_buf[] = {
13048 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, 0x01, 0x00, 0x48, 0xe4,
13049 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7,
13050 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
13051 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, 0x00, 0xec, 0x85, 0xf0,
13052 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00,
13053 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
13054 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea,
13055 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
13056 0xc0, 0x00, 0x01, 0x01, 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
13057 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00, 0x3e, 0x00, 0x80, 0x00,
13058 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
13059 0x78, 0x01, 0x62, 0x0a, 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
13060 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
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13288 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xd8, 0x14, 0x02, 0x5c,
13289 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe, 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72,
13290 0x03, 0x8f, 0xfe, 0xdc, 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
13291 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0xfe, 0xff, 0x7f,
13292 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c,
13293 0x3d, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
13294 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, 0x03, 0x0a, 0x50, 0x01,
13295 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4,
13296 0x19, 0x48, 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
13297 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe,
13298 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60,
13299 0x89, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
13300 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, 0xcc, 0x12, 0x49, 0x04,
13301 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13,
13302 0x06, 0x17, 0xc3, 0x78, 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
13303 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, 0x13, 0x06, 0xfe, 0x56,
13304 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93,
13305 0x13, 0x06, 0xfe, 0x28, 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
13306 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, 0x01, 0xba, 0xfe, 0x4e,
13307 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe,
13308 0x04, 0xf4, 0x6c, 0xfe, 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
13309 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13310 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13311 0x19, 0x83, 0x60, 0x23, 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
13312 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x0b, 0x01,
13313 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03,
13314 0x15, 0x06, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
13315 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, 0x4a, 0x01, 0x08, 0x03,
13316 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00,
13317 0x3b, 0x72, 0x9f, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
13318 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, 0x01, 0x43, 0x1e, 0xcd,
13319 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10,
13320 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
13321 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, 0x88, 0x03, 0x0a, 0x42,
13322 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2,
13323 0xfe, 0x49, 0xe4, 0x10, 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
13324 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe,
13325 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe,
13326 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
13327 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, 0x05, 0xfe, 0x66, 0x01,
13328 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66,
13329 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
13330 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x83,
13331 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe,
13332 0x94, 0x14, 0xfe, 0x10, 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13333 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x30, 0xbc, 0xfe,
13334 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a,
13335 0x16, 0xfe, 0x5c, 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13336 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, 0xfe, 0x1d, 0xf7, 0x4f,
13337 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58,
13338 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
13339 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, 0x06, 0x37, 0x95, 0xa9,
13340 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d,
13341 0x13, 0x0d, 0x03, 0x71, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
13342 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x3c, 0x8a, 0x0a,
13343 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc,
13344 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
13345 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xf6, 0xfe, 0xd6, 0xf0,
13346 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76,
13347 0x27, 0x01, 0xda, 0x17, 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
13348 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, 0xc8, 0xfe, 0x48, 0x55,
13349 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0,
13350 0x0a, 0x40, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
13351 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, 0x0e, 0x73, 0x75, 0x03,
13352 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b,
13353 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
13354 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, 0xfe, 0x94, 0x00, 0xfe,
13355 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e,
13356 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
13357 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1b, 0xfe, 0x5a,
13358 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07,
13359 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
13360 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, 0x03, 0x25, 0xfe, 0xca,
13361 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
13364 STATIC unsigned short _adv_asc3550_size =
13365 sizeof(_adv_asc3550_buf); /* 0x13AD */
13366 STATIC ADV_DCNT _adv_asc3550_chksum =
13367 0x04D52DDDUL; /* Expanded little-endian checksum. */
13369 /* Microcode buffer is kept after initialization for error recovery. */
13370 STATIC unsigned char _adv_asc38C0800_buf[] = {
13371 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, 0x01, 0x00, 0x48, 0xe4,
13372 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6,
13373 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
13374 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0, 0x18, 0xf4, 0x08, 0x00,
13375 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0,
13376 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
13377 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13, 0xba, 0x13, 0x18, 0x40,
13378 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01,
13379 0x76, 0x01, 0xb9, 0x54, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
13380 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12, 0x08, 0x12, 0x02, 0x4a,
13381 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa,
13382 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
13383 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d, 0x06, 0x13, 0x4c, 0x1c,
13384 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00,
13385 0xbe, 0x00, 0x00, 0x01, 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
13386 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, 0x05, 0x00, 0x34, 0x00,
13387 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f,
13388 0x0c, 0x10, 0x22, 0x11, 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
13389 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0,
13390 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00,
13391 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
13392 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13, 0x12, 0x13, 0x24, 0x14,
13393 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44,
13394 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
13395 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, 0x04, 0xf8,
13396 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13397 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
13398 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08, 0x68, 0x08, 0x69, 0x08,
13399 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10,
13400 0x2a, 0x11, 0x06, 0x12, 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
13401 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18, 0xca, 0x18, 0xe6, 0x19,
13402 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe,
13403 0xac, 0x0d, 0xff, 0x10, 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
13404 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13405 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00, 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13406 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
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13636 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52, 0xfe, 0x00, 0x7d, 0xfe,
13637 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f,
13638 0x7d, 0x40, 0x04, 0xdd, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
13639 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33,
13640 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59,
13641 0x03, 0xcd, 0x28, 0xfe, 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
13642 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, 0x30, 0xfe, 0x78, 0x10,
13643 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00,
13644 0x96, 0xf2, 0x18, 0x6d, 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
13645 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, 0x10, 0x69, 0x06, 0xfe,
13646 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06,
13647 0x88, 0x98, 0xfe, 0x90, 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
13648 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, 0x9e, 0xfe, 0xf3, 0x10,
13649 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13650 0x6e, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13651 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, 0xf4, 0x00, 0xe9, 0x91,
13652 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01,
13653 0x0b, 0x26, 0xf3, 0x16, 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
13654 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x19, 0x01, 0x0b,
13655 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76,
13656 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
13657 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01,
13658 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00,
13659 0xfe, 0x20, 0x13, 0x1d, 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
13660 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, 0x07, 0x11, 0xae, 0x09,
13661 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80,
13662 0xe7, 0x11, 0x07, 0x11, 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
13663 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xfe, 0x80, 0x4c,
13664 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87,
13665 0x04, 0x18, 0x11, 0x75, 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
13666 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, 0x17, 0xad, 0x9a, 0x1b,
13667 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10,
13668 0x18, 0x11, 0x75, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
13669 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c,
13670 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17,
13671 0xfe, 0xb6, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
13672 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x2e, 0x97, 0xfe, 0x5a,
13673 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13674 0x04, 0xb9, 0x23, 0xfe, 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
13675 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xcb, 0x97, 0xfe, 0x92,
13676 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13677 0xf6, 0x11, 0x75, 0xfe, 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
13678 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x9a, 0x5b, 0x41, 0xfe,
13679 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd,
13680 0x00, 0x6a, 0x2a, 0x04, 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
13681 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, 0xfe, 0x7e, 0x18, 0x1e,
13682 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
13683 0x7c, 0x6f, 0x4f, 0x32, 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
13684 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc,
13685 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c,
13686 0x01, 0x73, 0xfe, 0x16, 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
13687 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, 0xe7, 0x0a, 0x10, 0xfe,
13688 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37,
13689 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
13690 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, 0x13, 0xa3, 0x04, 0x09,
13691 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8,
13692 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
13693 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, 0x1c, 0x19, 0x03, 0xfe,
13694 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19,
13695 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
13696 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, 0x08, 0x10, 0x03, 0xfe,
13697 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7,
13698 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
13699 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, 0x04, 0x07, 0x7e, 0xfe,
13700 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a,
13701 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
13702 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, 0xa9, 0xb8, 0x04, 0x15,
13703 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c,
13704 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
13705 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13708 STATIC unsigned short _adv_asc38C0800_size =
13709 sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13710 STATIC ADV_DCNT _adv_asc38C0800_chksum =
13711 0x050D3FD8UL; /* Expanded little-endian checksum. */
13713 /* Microcode buffer is kept after initialization for error recovery. */
13714 STATIC unsigned char _adv_asc38C1600_buf[] = {
13715 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, 0x18, 0xe4, 0x01, 0x00,
13716 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f,
13717 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
13718 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x01, 0xe6,
13719 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0,
13720 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
13721 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01, 0x06, 0x13, 0x0c, 0x1c,
13722 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80,
13723 0x62, 0x0a, 0x5a, 0x12, 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
13724 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x04, 0x13, 0xbb, 0x55,
13725 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00,
13726 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
13727 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01,
13728 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01,
13729 0xc6, 0x0e, 0x0c, 0x10, 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
13730 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x06, 0x00,
13731 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c,
13732 0x10, 0x44, 0x00, 0x4c, 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
13733 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00,
13734 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09,
13735 0x68, 0x0d, 0x02, 0x10, 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
13736 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
13737 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00,
13738 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
13739 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x42, 0x1d, 0x08, 0x44,
13740 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59,
13741 0x31, 0xe4, 0x02, 0xe6, 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
13742 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13743 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01,
13744 0xc8, 0x01, 0xca, 0x01, 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
13745 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10, 0xf3, 0x10, 0x06, 0x12,
13746 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe,
13747 0xec, 0x0e, 0xff, 0x10, 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
13748 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13749 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13750 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
13751 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xe8,
13752 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe, 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe,
13753 0x3d, 0xf0, 0xfe, 0x0c, 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
13754 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d, 0x05, 0xfe, 0x08, 0x0f,
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14092 0xf0, 0xfe, 0xba, 0x1d, 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
14093 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe, 0x1a, 0x10, 0x09, 0x0d,
14094 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42,
14095 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
14096 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, 0xfe, 0x82, 0xf0, 0xfe,
14097 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18,
14098 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
14099 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, 0x83, 0x33, 0x0b, 0x0e,
14100 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04,
14101 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
14102 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, 0xfe, 0x99, 0x83, 0xfe,
14103 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47,
14104 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14105 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x08, 0x90, 0x04,
14106 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79,
14107 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14108 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x3c, 0x90, 0x04,
14109 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83,
14110 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
14113 STATIC unsigned short _adv_asc38C1600_size =
14114 sizeof(_adv_asc38C1600_buf); /* 0x1673 */
14115 STATIC ADV_DCNT _adv_asc38C1600_chksum =
14116 0x0604EF77UL; /* Expanded little-endian checksum. */
14120 * EEPROM Configuration.
14122 * All drivers should use this structure to set the default EEPROM
14123 * configuration. The BIOS now uses this structure when it is built.
14124 * Additional structure information can be found in a_condor.h where
14125 * the structure is defined.
14127 * The *_Field_IsChar structs are needed to correct for endianness.
14128 * These values are read from the board 16 bits at a time directly
14129 * into the structs. Because some fields are char, the values will be
14130 * in the wrong order. The *_Field_IsChar tells when to flip the
14131 * bytes. Data read and written to PCI memory is automatically swapped
14132 * on big-endian platforms so char fields read as words are actually being
14133 * unswapped on big-endian platforms.
14135 STATIC ADVEEP_3550_CONFIG
14136 Default_3550_EEPROM_Config __initdata = {
14137 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
14138 0x0000, /* cfg_msw */
14139 0xFFFF, /* disc_enable */
14140 0xFFFF, /* wdtr_able */
14141 0xFFFF, /* sdtr_able */
14142 0xFFFF, /* start_motor */
14143 0xFFFF, /* tagqng_able */
14144 0xFFFF, /* bios_scan */
14145 0, /* scam_tolerant */
14146 7, /* adapter_scsi_id */
14147 0, /* bios_boot_delay */
14148 3, /* scsi_reset_delay */
14149 0, /* bios_id_lun */
14150 0, /* termination */
14152 0xFFE7, /* bios_ctrl */
14153 0xFFFF, /* ultra_able */
14155 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
14156 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14159 0, /* serial_number_word1 */
14160 0, /* serial_number_word2 */
14161 0, /* serial_number_word3 */
14163 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */
14164 0, /* dvc_err_code */
14165 0, /* adv_err_code */
14166 0, /* adv_err_addr */
14167 0, /* saved_dvc_err_code */
14168 0, /* saved_adv_err_code */
14169 0, /* saved_adv_err_addr */
14173 STATIC ADVEEP_3550_CONFIG
14174 ADVEEP_3550_Config_Field_IsChar __initdata = {
14177 0, /* -disc_enable */
14180 0, /* start_motor */
14181 0, /* tagqng_able */
14183 0, /* scam_tolerant */
14184 1, /* adapter_scsi_id */
14185 1, /* bios_boot_delay */
14186 1, /* scsi_reset_delay */
14187 1, /* bios_id_lun */
14188 1, /* termination */
14191 0, /* ultra_able */
14193 1, /* max_host_qng */
14194 1, /* max_dvc_qng */
14197 0, /* serial_number_word1 */
14198 0, /* serial_number_word2 */
14199 0, /* serial_number_word3 */
14201 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* oem_name[16] */
14202 0, /* dvc_err_code */
14203 0, /* adv_err_code */
14204 0, /* adv_err_addr */
14205 0, /* saved_dvc_err_code */
14206 0, /* saved_adv_err_code */
14207 0, /* saved_adv_err_addr */
14211 STATIC ADVEEP_38C0800_CONFIG
14212 Default_38C0800_EEPROM_Config __initdata = {
14213 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14214 0x0000, /* 01 cfg_msw */
14215 0xFFFF, /* 02 disc_enable */
14216 0xFFFF, /* 03 wdtr_able */
14217 0x4444, /* 04 sdtr_speed1 */
14218 0xFFFF, /* 05 start_motor */
14219 0xFFFF, /* 06 tagqng_able */
14220 0xFFFF, /* 07 bios_scan */
14221 0, /* 08 scam_tolerant */
14222 7, /* 09 adapter_scsi_id */
14223 0, /* bios_boot_delay */
14224 3, /* 10 scsi_reset_delay */
14225 0, /* bios_id_lun */
14226 0, /* 11 termination_se */
14227 0, /* termination_lvd */
14228 0xFFE7, /* 12 bios_ctrl */
14229 0x4444, /* 13 sdtr_speed2 */
14230 0x4444, /* 14 sdtr_speed3 */
14231 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14232 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14233 0, /* 16 dvc_cntl */
14234 0x4444, /* 17 sdtr_speed4 */
14235 0, /* 18 serial_number_word1 */
14236 0, /* 19 serial_number_word2 */
14237 0, /* 20 serial_number_word3 */
14238 0, /* 21 check_sum */
14239 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14240 0, /* 30 dvc_err_code */
14241 0, /* 31 adv_err_code */
14242 0, /* 32 adv_err_addr */
14243 0, /* 33 saved_dvc_err_code */
14244 0, /* 34 saved_adv_err_code */
14245 0, /* 35 saved_adv_err_addr */
14246 0, /* 36 reserved */
14247 0, /* 37 reserved */
14248 0, /* 38 reserved */
14249 0, /* 39 reserved */
14250 0, /* 40 reserved */
14251 0, /* 41 reserved */
14252 0, /* 42 reserved */
14253 0, /* 43 reserved */
14254 0, /* 44 reserved */
14255 0, /* 45 reserved */
14256 0, /* 46 reserved */
14257 0, /* 47 reserved */
14258 0, /* 48 reserved */
14259 0, /* 49 reserved */
14260 0, /* 50 reserved */
14261 0, /* 51 reserved */
14262 0, /* 52 reserved */
14263 0, /* 53 reserved */
14264 0, /* 54 reserved */
14265 0, /* 55 reserved */
14266 0, /* 56 cisptr_lsw */
14267 0, /* 57 cisprt_msw */
14268 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
14269 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
14270 0, /* 60 reserved */
14271 0, /* 61 reserved */
14272 0, /* 62 reserved */
14273 0 /* 63 reserved */
14276 STATIC ADVEEP_38C0800_CONFIG
14277 ADVEEP_38C0800_Config_Field_IsChar __initdata = {
14278 0, /* 00 cfg_lsw */
14279 0, /* 01 cfg_msw */
14280 0, /* 02 disc_enable */
14281 0, /* 03 wdtr_able */
14282 0, /* 04 sdtr_speed1 */
14283 0, /* 05 start_motor */
14284 0, /* 06 tagqng_able */
14285 0, /* 07 bios_scan */
14286 0, /* 08 scam_tolerant */
14287 1, /* 09 adapter_scsi_id */
14288 1, /* bios_boot_delay */
14289 1, /* 10 scsi_reset_delay */
14290 1, /* bios_id_lun */
14291 1, /* 11 termination_se */
14292 1, /* termination_lvd */
14293 0, /* 12 bios_ctrl */
14294 0, /* 13 sdtr_speed2 */
14295 0, /* 14 sdtr_speed3 */
14296 1, /* 15 max_host_qng */
14297 1, /* max_dvc_qng */
14298 0, /* 16 dvc_cntl */
14299 0, /* 17 sdtr_speed4 */
14300 0, /* 18 serial_number_word1 */
14301 0, /* 19 serial_number_word2 */
14302 0, /* 20 serial_number_word3 */
14303 0, /* 21 check_sum */
14304 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14305 0, /* 30 dvc_err_code */
14306 0, /* 31 adv_err_code */
14307 0, /* 32 adv_err_addr */
14308 0, /* 33 saved_dvc_err_code */
14309 0, /* 34 saved_adv_err_code */
14310 0, /* 35 saved_adv_err_addr */
14311 0, /* 36 reserved */
14312 0, /* 37 reserved */
14313 0, /* 38 reserved */
14314 0, /* 39 reserved */
14315 0, /* 40 reserved */
14316 0, /* 41 reserved */
14317 0, /* 42 reserved */
14318 0, /* 43 reserved */
14319 0, /* 44 reserved */
14320 0, /* 45 reserved */
14321 0, /* 46 reserved */
14322 0, /* 47 reserved */
14323 0, /* 48 reserved */
14324 0, /* 49 reserved */
14325 0, /* 50 reserved */
14326 0, /* 51 reserved */
14327 0, /* 52 reserved */
14328 0, /* 53 reserved */
14329 0, /* 54 reserved */
14330 0, /* 55 reserved */
14331 0, /* 56 cisptr_lsw */
14332 0, /* 57 cisprt_msw */
14333 0, /* 58 subsysvid */
14334 0, /* 59 subsysid */
14335 0, /* 60 reserved */
14336 0, /* 61 reserved */
14337 0, /* 62 reserved */
14338 0 /* 63 reserved */
14341 STATIC ADVEEP_38C1600_CONFIG
14342 Default_38C1600_EEPROM_Config __initdata = {
14343 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14344 0x0000, /* 01 cfg_msw */
14345 0xFFFF, /* 02 disc_enable */
14346 0xFFFF, /* 03 wdtr_able */
14347 0x5555, /* 04 sdtr_speed1 */
14348 0xFFFF, /* 05 start_motor */
14349 0xFFFF, /* 06 tagqng_able */
14350 0xFFFF, /* 07 bios_scan */
14351 0, /* 08 scam_tolerant */
14352 7, /* 09 adapter_scsi_id */
14353 0, /* bios_boot_delay */
14354 3, /* 10 scsi_reset_delay */
14355 0, /* bios_id_lun */
14356 0, /* 11 termination_se */
14357 0, /* termination_lvd */
14358 0xFFE7, /* 12 bios_ctrl */
14359 0x5555, /* 13 sdtr_speed2 */
14360 0x5555, /* 14 sdtr_speed3 */
14361 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14362 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14363 0, /* 16 dvc_cntl */
14364 0x5555, /* 17 sdtr_speed4 */
14365 0, /* 18 serial_number_word1 */
14366 0, /* 19 serial_number_word2 */
14367 0, /* 20 serial_number_word3 */
14368 0, /* 21 check_sum */
14369 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14370 0, /* 30 dvc_err_code */
14371 0, /* 31 adv_err_code */
14372 0, /* 32 adv_err_addr */
14373 0, /* 33 saved_dvc_err_code */
14374 0, /* 34 saved_adv_err_code */
14375 0, /* 35 saved_adv_err_addr */
14376 0, /* 36 reserved */
14377 0, /* 37 reserved */
14378 0, /* 38 reserved */
14379 0, /* 39 reserved */
14380 0, /* 40 reserved */
14381 0, /* 41 reserved */
14382 0, /* 42 reserved */
14383 0, /* 43 reserved */
14384 0, /* 44 reserved */
14385 0, /* 45 reserved */
14386 0, /* 46 reserved */
14387 0, /* 47 reserved */
14388 0, /* 48 reserved */
14389 0, /* 49 reserved */
14390 0, /* 50 reserved */
14391 0, /* 51 reserved */
14392 0, /* 52 reserved */
14393 0, /* 53 reserved */
14394 0, /* 54 reserved */
14395 0, /* 55 reserved */
14396 0, /* 56 cisptr_lsw */
14397 0, /* 57 cisprt_msw */
14398 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
14399 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
14400 0, /* 60 reserved */
14401 0, /* 61 reserved */
14402 0, /* 62 reserved */
14403 0 /* 63 reserved */
14406 STATIC ADVEEP_38C1600_CONFIG
14407 ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14408 0, /* 00 cfg_lsw */
14409 0, /* 01 cfg_msw */
14410 0, /* 02 disc_enable */
14411 0, /* 03 wdtr_able */
14412 0, /* 04 sdtr_speed1 */
14413 0, /* 05 start_motor */
14414 0, /* 06 tagqng_able */
14415 0, /* 07 bios_scan */
14416 0, /* 08 scam_tolerant */
14417 1, /* 09 adapter_scsi_id */
14418 1, /* bios_boot_delay */
14419 1, /* 10 scsi_reset_delay */
14420 1, /* bios_id_lun */
14421 1, /* 11 termination_se */
14422 1, /* termination_lvd */
14423 0, /* 12 bios_ctrl */
14424 0, /* 13 sdtr_speed2 */
14425 0, /* 14 sdtr_speed3 */
14426 1, /* 15 max_host_qng */
14427 1, /* max_dvc_qng */
14428 0, /* 16 dvc_cntl */
14429 0, /* 17 sdtr_speed4 */
14430 0, /* 18 serial_number_word1 */
14431 0, /* 19 serial_number_word2 */
14432 0, /* 20 serial_number_word3 */
14433 0, /* 21 check_sum */
14434 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14435 0, /* 30 dvc_err_code */
14436 0, /* 31 adv_err_code */
14437 0, /* 32 adv_err_addr */
14438 0, /* 33 saved_dvc_err_code */
14439 0, /* 34 saved_adv_err_code */
14440 0, /* 35 saved_adv_err_addr */
14441 0, /* 36 reserved */
14442 0, /* 37 reserved */
14443 0, /* 38 reserved */
14444 0, /* 39 reserved */
14445 0, /* 40 reserved */
14446 0, /* 41 reserved */
14447 0, /* 42 reserved */
14448 0, /* 43 reserved */
14449 0, /* 44 reserved */
14450 0, /* 45 reserved */
14451 0, /* 46 reserved */
14452 0, /* 47 reserved */
14453 0, /* 48 reserved */
14454 0, /* 49 reserved */
14455 0, /* 50 reserved */
14456 0, /* 51 reserved */
14457 0, /* 52 reserved */
14458 0, /* 53 reserved */
14459 0, /* 54 reserved */
14460 0, /* 55 reserved */
14461 0, /* 56 cisptr_lsw */
14462 0, /* 57 cisprt_msw */
14463 0, /* 58 subsysvid */
14464 0, /* 59 subsysid */
14465 0, /* 60 reserved */
14466 0, /* 61 reserved */
14467 0, /* 62 reserved */
14468 0 /* 63 reserved */
14472 * Initialize the ADV_DVC_VAR structure.
14474 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14476 * For a non-fatal error return a warning code. If there are no warnings
14477 * then 0 is returned.
14480 AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14483 AdvPortAddr iop_base;
14488 asc_dvc->err_code = 0;
14489 iop_base = asc_dvc->iop_base;
14492 * PCI Command Register
14494 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14495 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14498 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14499 AscPCIConfigCommandRegister))
14500 & AscPCICmdRegBits_BusMastering)
14501 != AscPCICmdRegBits_BusMastering)
14503 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14505 DvcAdvWritePCIConfigByte(asc_dvc,
14506 AscPCIConfigCommandRegister, pci_cmd_reg);
14508 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister))
14509 & AscPCICmdRegBits_BusMastering)
14510 != AscPCICmdRegBits_BusMastering)
14512 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14517 * PCI Latency Timer
14519 * If the "latency timer" register is 0x20 or above, then we don't need
14520 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14521 * comes up less than 0x20).
14523 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14524 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer, 0x20);
14525 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20)
14527 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14532 * Save the state of the PCI Configuration Command Register
14533 * "Parity Error Response Control" Bit. If the bit is clear (0),
14534 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14535 * DMA parity errors.
14537 asc_dvc->cfg->control_flag = 0;
14538 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14539 & AscPCICmdRegBits_ParErrRespCtrl)) == 0)
14541 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14544 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14545 ADV_LIB_VERSION_MINOR;
14546 asc_dvc->cfg->chip_version =
14547 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14549 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14550 (ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14551 (ushort) ADV_CHIP_ID_BYTE);
14553 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14554 (ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14555 (ushort) ADV_CHIP_ID_WORD);
14558 * Reset the chip to start and allow register writes.
14560 if (AdvFindSignature(iop_base) == 0)
14562 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14567 * The caller must set 'chip_type' to a valid setting.
14569 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14570 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14571 asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
14573 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14580 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14581 ADV_CTRL_REG_CMD_RESET);
14582 DvcSleepMilliSecond(100);
14583 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14584 ADV_CTRL_REG_CMD_WR_IO_REG);
14586 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
14588 if ((status = AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR)
14592 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
14594 if ((status = AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR)
14600 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR)
14605 warn_code |= status;
14612 * Initialize the ASC-3550.
14614 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14616 * For a non-fatal error return a warning code. If there are no warnings
14617 * then 0 is returned.
14619 * Needed after initialization for error recovery.
14622 AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14624 AdvPortAddr iop_base;
14632 int adv_asc3550_expanded_size;
14634 ADV_DCNT contig_len;
14635 ADV_SDCNT buf_size;
14636 ADV_PADDR carr_paddr;
14640 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
14641 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14642 uchar max_cmd[ADV_MAX_TID + 1];
14644 /* If there is already an error, don't continue. */
14645 if (asc_dvc->err_code != 0)
14651 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14653 if (asc_dvc->chip_type != ADV_CHIP_ASC3550)
14655 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14660 iop_base = asc_dvc->iop_base;
14663 * Save the RISC memory BIOS region before writing the microcode.
14664 * The BIOS may already be loaded and using its RISC LRAM region
14665 * so its region must be saved and restored.
14667 * Note: This code makes the assumption, which is currently true,
14668 * that a chip reset does not clear RISC LRAM.
14670 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14672 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14676 * Save current per TID negotiated values.
14678 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
14680 ushort bios_version, major, minor;
14682 bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
14683 major = (bios_version >> 12) & 0xF;
14684 minor = (bios_version >> 8) & 0xF;
14685 if (major < 3 || (major == 3 && minor == 1))
14687 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14688 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14691 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14694 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14695 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14696 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14698 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14703 * Load the Microcode
14705 * Write the microcode image to RISC memory starting at address 0.
14707 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14708 /* Assume the following compressed format of the microcode buffer:
14710 * 254 word (508 byte) table indexed by byte code followed
14711 * by the following byte codes:
14714 * 00: Emit word 0 in table.
14715 * 01: Emit word 1 in table.
14717 * FD: Emit word 253 in table.
14720 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14721 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14724 for (i = 253 * 2; i < _adv_asc3550_size; i++)
14726 if (_adv_asc3550_buf[i] == 0xff)
14728 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
14730 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14731 _adv_asc3550_buf[i + 3] << 8) |
14732 _adv_asc3550_buf[i + 2]));
14736 } else if (_adv_asc3550_buf[i] == 0xfe)
14738 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14739 _adv_asc3550_buf[i + 2] << 8) |
14740 _adv_asc3550_buf[i + 1]));
14745 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14746 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
14747 _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14753 * Set 'word' for later use to clear the rest of memory and save
14754 * the expanded mcode size.
14757 adv_asc3550_expanded_size = word;
14760 * Clear the rest of ASC-3550 Internal RAM (8KB).
14762 for (; word < ADV_3550_MEMSIZE; word += 2)
14764 AdvWriteWordAutoIncLram(iop_base, 0);
14768 * Verify the microcode checksum.
14771 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14773 for (word = 0; word < adv_asc3550_expanded_size; word += 2)
14775 sum += AdvReadWordAutoIncLram(iop_base);
14778 if (sum != _adv_asc3550_chksum)
14780 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14785 * Restore the RISC memory BIOS region.
14787 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14789 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14793 * Calculate and write the microcode code checksum to the microcode
14794 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14796 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14797 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14799 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14800 for (word = begin_addr; word < end_addr; word += 2)
14802 code_sum += AdvReadWordAutoIncLram(iop_base);
14804 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14807 * Read and save microcode version and date.
14809 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
14810 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
14813 * Set the chip type to indicate the ASC3550.
14815 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14818 * If the PCI Configuration Command Register "Parity Error Response
14819 * Control" Bit was clear (0), then set the microcode variable
14820 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14821 * to ignore DMA parity errors.
14823 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
14825 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14826 word |= CONTROL_FLAG_IGNORE_PERR;
14827 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14831 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14832 * threshold of 128 bytes. This register is only accessible to the host.
14834 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14835 START_CTL_EMFU | READ_CMD_MRM);
14838 * Microcode operating variables for WDTR, SDTR, and command tag
14839 * queuing will be set in AdvInquiryHandling() based on what a
14840 * device reports it is capable of in Inquiry byte 7.
14842 * If SCSI Bus Resets have been disabled, then directly set
14843 * SDTR and WDTR from the EEPROM configuration. This will allow
14844 * the BIOS and warm boot to work without a SCSI bus hang on
14845 * the Inquiry caused by host and target mismatched DTR values.
14846 * Without the SCSI Bus Reset, before an Inquiry a device can't
14847 * be assumed to be in Asynchronous, Narrow mode.
14849 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
14851 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
14852 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
14856 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14857 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14858 * bitmask. These values determine the maximum SDTR speed negotiated
14861 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14862 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14863 * without determining here whether the device supports SDTR.
14865 * 4-bit speed SDTR speed name
14866 * =========== ===============
14867 * 0000b (0x0) SDTR disabled
14868 * 0001b (0x1) 5 Mhz
14869 * 0010b (0x2) 10 Mhz
14870 * 0011b (0x3) 20 Mhz (Ultra)
14871 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14872 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14873 * 0110b (0x6) Undefined
14875 * 1111b (0xF) Undefined
14878 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14880 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able)
14882 /* Set Ultra speed for TID 'tid'. */
14883 word |= (0x3 << (4 * (tid % 4)));
14886 /* Set Fast speed for TID 'tid'. */
14887 word |= (0x2 << (4 * (tid % 4)));
14889 if (tid == 3) /* Check if done with sdtr_speed1. */
14891 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14893 } else if (tid == 7) /* Check if done with sdtr_speed2. */
14895 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14897 } else if (tid == 11) /* Check if done with sdtr_speed3. */
14899 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14901 } else if (tid == 15) /* Check if done with sdtr_speed4. */
14903 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14909 * Set microcode operating variable for the disconnect per TID bitmask.
14911 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
14914 * Set SCSI_CFG0 Microcode Default Value.
14916 * The microcode will set the SCSI_CFG0 register using this value
14917 * after it is started below.
14919 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14920 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14921 asc_dvc->chip_scsi_id);
14924 * Determine SCSI_CFG1 Microcode Default Value.
14926 * The microcode will set the SCSI_CFG1 register using this value
14927 * after it is started below.
14930 /* Read current SCSI_CFG1 Register value. */
14931 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14934 * If all three connectors are in use, return an error.
14936 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14937 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0)
14939 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14944 * If the internal narrow cable is reversed all of the SCSI_CTRL
14945 * register signals will be set. Check for and return an error if
14946 * this condition is found.
14948 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
14950 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14955 * If this is a differential board and a single-ended device
14956 * is attached to one of the connectors, return an error.
14958 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0)
14960 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14965 * If automatic termination control is enabled, then set the
14966 * termination value based on a table listed in a_condor.h.
14968 * If manual termination was specified with an EEPROM setting
14969 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
14970 * is ready to be 'ored' into SCSI_CFG1.
14972 if (asc_dvc->cfg->termination == 0)
14975 * The software always controls termination by setting TERM_CTL_SEL.
14976 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
14978 asc_dvc->cfg->termination |= TERM_CTL_SEL;
14980 switch(scsi_cfg1 & CABLE_DETECT)
14982 /* TERM_CTL_H: on, TERM_CTL_L: on */
14983 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF:
14984 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
14987 /* TERM_CTL_H: on, TERM_CTL_L: off */
14988 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC:
14989 asc_dvc->cfg->termination |= TERM_CTL_H;
14992 /* TERM_CTL_H: off, TERM_CTL_L: off */
14993 case 0x2: case 0x6:
14999 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
15001 scsi_cfg1 &= ~TERM_CTL;
15004 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
15005 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
15006 * referenced, because the hardware internally inverts
15007 * the Termination High and Low bits if TERM_POL is set.
15009 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
15012 * Set SCSI_CFG1 Microcode Default Value
15014 * Set filter value and possibly modified termination control
15015 * bits in the Microcode SCSI_CFG1 Register Value.
15017 * The microcode will set the SCSI_CFG1 register using this value
15018 * after it is started below.
15020 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
15021 FLTR_DISABLE | scsi_cfg1);
15024 * Set MEM_CFG Microcode Default Value
15026 * The microcode will set the MEM_CFG register using this value
15027 * after it is started below.
15029 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15032 * ASC-3550 has 8KB internal memory.
15034 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15035 BIOS_EN | RAM_SZ_8KB);
15038 * Set SEL_MASK Microcode Default Value
15040 * The microcode will set the SEL_MASK register using this value
15041 * after it is started below.
15043 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15044 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15047 * Build carrier freelist.
15049 * Driver must have already allocated memory and set 'carrier_buf'.
15051 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15053 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15054 asc_dvc->carr_freelist = NULL;
15055 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15057 buf_size = ADV_CARRIER_BUFSIZE;
15060 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15065 * Get physical address of the carrier 'carrp'.
15067 contig_len = sizeof(ADV_CARR_T);
15068 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15069 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15071 buf_size -= sizeof(ADV_CARR_T);
15074 * If the current carrier is not physically contiguous, then
15075 * maybe there was a page crossing. Try the next carrier aligned
15078 if (contig_len < sizeof(ADV_CARR_T))
15084 carrp->carr_pa = carr_paddr;
15085 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15088 * Insert the carrier at the beginning of the freelist.
15090 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15091 asc_dvc->carr_freelist = carrp;
15095 while (buf_size > 0);
15098 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15101 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15103 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15106 asc_dvc->carr_freelist = (ADV_CARR_T *)
15107 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15110 * The first command issued will be placed in the stopper carrier.
15112 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15115 * Set RISC ICQ physical address start value.
15117 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15120 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15122 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15124 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15127 asc_dvc->carr_freelist = (ADV_CARR_T *)
15128 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15131 * The first command completed by the RISC will be placed in
15134 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15135 * completed the RISC will set the ASC_RQ_STOPPER bit.
15137 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15140 * Set RISC IRQ physical address start value.
15142 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15143 asc_dvc->carr_pending_cnt = 0;
15145 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15146 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15148 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15149 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15151 /* finally, finally, gentlemen, start your engine */
15152 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15155 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15156 * Resets should be performed. The RISC has to be running
15157 * to issue a SCSI Bus Reset.
15159 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15162 * If the BIOS Signature is present in memory, restore the
15163 * BIOS Handshake Configuration Table and do not perform
15164 * a SCSI Bus Reset.
15166 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15169 * Restore per TID negotiated values.
15171 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15172 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15173 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15174 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15176 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15181 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15183 warn_code = ASC_WARN_BUSRESET_ERROR;
15192 * Initialize the ASC-38C0800.
15194 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
15196 * For a non-fatal error return a warning code. If there are no warnings
15197 * then 0 is returned.
15199 * Needed after initialization for error recovery.
15202 AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
15204 AdvPortAddr iop_base;
15212 int adv_asc38C0800_expanded_size;
15214 ADV_DCNT contig_len;
15215 ADV_SDCNT buf_size;
15216 ADV_PADDR carr_paddr;
15221 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15222 ushort wdtr_able, sdtr_able, tagqng_able;
15223 uchar max_cmd[ADV_MAX_TID + 1];
15225 /* If there is already an error, don't continue. */
15226 if (asc_dvc->err_code != 0)
15232 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
15234 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
15236 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15241 iop_base = asc_dvc->iop_base;
15244 * Save the RISC memory BIOS region before writing the microcode.
15245 * The BIOS may already be loaded and using its RISC LRAM region
15246 * so its region must be saved and restored.
15248 * Note: This code makes the assumption, which is currently true,
15249 * that a chip reset does not clear RISC LRAM.
15251 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15253 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15257 * Save current per TID negotiated values.
15259 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15260 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15261 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15262 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15264 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15269 * RAM BIST (RAM Built-In Self Test)
15271 * Address : I/O base + offset 0x38h register (byte).
15272 * Function: Bit 7-6(RW) : RAM mode
15273 * Normal Mode : 0x00
15274 * Pre-test Mode : 0x40
15275 * RAM Test Mode : 0x80
15277 * Bit 4(RO) : Done bit
15278 * Bit 3-0(RO) : Status
15279 * Host Error : 0x08
15280 * Int_RAM Error : 0x04
15281 * RISC Error : 0x02
15282 * SCSI Error : 0x01
15285 * Note: RAM BIST code should be put right here, before loading the
15286 * microcode and after saving the RISC memory BIOS region.
15292 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15293 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15294 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15295 * to NORMAL_MODE, return an error too.
15297 for (i = 0; i < 2; i++)
15299 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15300 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15301 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15302 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15304 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15308 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15309 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15310 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15313 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15319 * LRAM Test - It takes about 1.5 ms to run through the test.
15321 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15322 * If Done bit not set or Status not 0, save register byte, set the
15323 * err_code, and return an error.
15325 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15326 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15328 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15329 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15331 /* Get here if Done bit not set or Status not 0. */
15332 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15333 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15337 /* We need to reset back to normal mode after LRAM test passes. */
15338 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15341 * Load the Microcode
15343 * Write the microcode image to RISC memory starting at address 0.
15346 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15348 /* Assume the following compressed format of the microcode buffer:
15350 * 254 word (508 byte) table indexed by byte code followed
15351 * by the following byte codes:
15354 * 00: Emit word 0 in table.
15355 * 01: Emit word 1 in table.
15357 * FD: Emit word 253 in table.
15360 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15361 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15364 for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
15366 if (_adv_asc38C0800_buf[i] == 0xff)
15368 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
15370 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15371 _adv_asc38C0800_buf[i + 3] << 8) |
15372 _adv_asc38C0800_buf[i + 2]));
15376 } else if (_adv_asc38C0800_buf[i] == 0xfe)
15378 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15379 _adv_asc38C0800_buf[i + 2] << 8) |
15380 _adv_asc38C0800_buf[i + 1]));
15385 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15386 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
15387 _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15393 * Set 'word' for later use to clear the rest of memory and save
15394 * the expanded mcode size.
15397 adv_asc38C0800_expanded_size = word;
15400 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15402 for (; word < ADV_38C0800_MEMSIZE; word += 2)
15404 AdvWriteWordAutoIncLram(iop_base, 0);
15408 * Verify the microcode checksum.
15411 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15413 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
15415 sum += AdvReadWordAutoIncLram(iop_base);
15417 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15420 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15421 (ulong) sum, (ulong) _adv_asc38C0800_chksum);
15423 if (sum != _adv_asc38C0800_chksum)
15425 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15430 * Restore the RISC memory BIOS region.
15432 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15434 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15438 * Calculate and write the microcode code checksum to the microcode
15439 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15441 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15442 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15444 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15445 for (word = begin_addr; word < end_addr; word += 2)
15447 code_sum += AdvReadWordAutoIncLram(iop_base);
15449 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15452 * Read microcode version and date.
15454 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
15455 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
15458 * Set the chip type to indicate the ASC38C0800.
15460 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15463 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15464 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15465 * cable detection and then we are able to read C_DET[3:0].
15467 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15468 * Microcode Default Value' section below.
15470 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15471 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
15474 * If the PCI Configuration Command Register "Parity Error Response
15475 * Control" Bit was clear (0), then set the microcode variable
15476 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15477 * to ignore DMA parity errors.
15479 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
15481 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15482 word |= CONTROL_FLAG_IGNORE_PERR;
15483 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15487 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15488 * bits for the default FIFO threshold.
15490 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15492 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15494 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15495 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15498 * Microcode operating variables for WDTR, SDTR, and command tag
15499 * queuing will be set in AdvInquiryHandling() based on what a
15500 * device reports it is capable of in Inquiry byte 7.
15502 * If SCSI Bus Resets have been disabled, then directly set
15503 * SDTR and WDTR from the EEPROM configuration. This will allow
15504 * the BIOS and warm boot to work without a SCSI bus hang on
15505 * the Inquiry caused by host and target mismatched DTR values.
15506 * Without the SCSI Bus Reset, before an Inquiry a device can't
15507 * be assumed to be in Asynchronous, Narrow mode.
15509 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
15511 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
15512 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
15516 * Set microcode operating variables for DISC and SDTR_SPEED1,
15517 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15518 * configuration values.
15520 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15521 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15522 * without determining here whether the device supports SDTR.
15524 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
15525 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15526 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15527 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15528 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15531 * Set SCSI_CFG0 Microcode Default Value.
15533 * The microcode will set the SCSI_CFG0 register using this value
15534 * after it is started below.
15536 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15537 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15538 asc_dvc->chip_scsi_id);
15541 * Determine SCSI_CFG1 Microcode Default Value.
15543 * The microcode will set the SCSI_CFG1 register using this value
15544 * after it is started below.
15547 /* Read current SCSI_CFG1 Register value. */
15548 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15551 * If the internal narrow cable is reversed all of the SCSI_CTRL
15552 * register signals will be set. Check for and return an error if
15553 * this condition is found.
15555 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
15557 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15562 * All kind of combinations of devices attached to one of four connectors
15563 * are acceptable except HVD device attached. For example, LVD device can
15564 * be attached to SE connector while SE device attached to LVD connector.
15565 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15567 * If an HVD device is attached to one of LVD connectors, return an error.
15568 * However, there is no way to detect HVD device attached to SE connectors.
15570 if (scsi_cfg1 & HVD)
15572 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15577 * If either SE or LVD automatic termination control is enabled, then
15578 * set the termination value based on a table listed in a_condor.h.
15580 * If manual termination was specified with an EEPROM setting then
15581 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15582 * be 'ored' into SCSI_CFG1.
15584 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
15586 /* SE automatic termination control is enabled. */
15587 switch(scsi_cfg1 & C_DET_SE)
15589 /* TERM_SE_HI: on, TERM_SE_LO: on */
15590 case 0x1: case 0x2: case 0x3:
15591 asc_dvc->cfg->termination |= TERM_SE;
15594 /* TERM_SE_HI: on, TERM_SE_LO: off */
15596 asc_dvc->cfg->termination |= TERM_SE_HI;
15601 if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
15603 /* LVD automatic termination control is enabled. */
15604 switch(scsi_cfg1 & C_DET_LVD)
15606 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15607 case 0x4: case 0x8: case 0xC:
15608 asc_dvc->cfg->termination |= TERM_LVD;
15611 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15618 * Clear any set TERM_SE and TERM_LVD bits.
15620 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15623 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15625 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15628 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15629 * and set possibly modified termination control bits in the Microcode
15630 * SCSI_CFG1 Register Value.
15632 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15635 * Set SCSI_CFG1 Microcode Default Value
15637 * Set possibly modified termination control and reset DIS_TERM_DRV
15638 * bits in the Microcode SCSI_CFG1 Register Value.
15640 * The microcode will set the SCSI_CFG1 register using this value
15641 * after it is started below.
15643 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15646 * Set MEM_CFG Microcode Default Value
15648 * The microcode will set the MEM_CFG register using this value
15649 * after it is started below.
15651 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15654 * ASC-38C0800 has 16KB internal memory.
15656 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15657 BIOS_EN | RAM_SZ_16KB);
15660 * Set SEL_MASK Microcode Default Value
15662 * The microcode will set the SEL_MASK register using this value
15663 * after it is started below.
15665 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15666 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15669 * Build the carrier freelist.
15671 * Driver must have already allocated memory and set 'carrier_buf'.
15673 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15675 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15676 asc_dvc->carr_freelist = NULL;
15677 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15679 buf_size = ADV_CARRIER_BUFSIZE;
15682 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15687 * Get physical address for the carrier 'carrp'.
15689 contig_len = sizeof(ADV_CARR_T);
15690 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15691 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15693 buf_size -= sizeof(ADV_CARR_T);
15696 * If the current carrier is not physically contiguous, then
15697 * maybe there was a page crossing. Try the next carrier aligned
15700 if (contig_len < sizeof(ADV_CARR_T))
15706 carrp->carr_pa = carr_paddr;
15707 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15710 * Insert the carrier at the beginning of the freelist.
15712 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15713 asc_dvc->carr_freelist = carrp;
15717 while (buf_size > 0);
15720 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15723 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15725 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15728 asc_dvc->carr_freelist = (ADV_CARR_T *)
15729 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15732 * The first command issued will be placed in the stopper carrier.
15734 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15737 * Set RISC ICQ physical address start value.
15738 * carr_pa is LE, must be native before write
15740 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15743 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15745 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15747 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15750 asc_dvc->carr_freelist = (ADV_CARR_T *)
15751 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15754 * The first command completed by the RISC will be placed in
15757 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15758 * completed the RISC will set the ASC_RQ_STOPPER bit.
15760 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15763 * Set RISC IRQ physical address start value.
15765 * carr_pa is LE, must be native before write *
15767 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15768 asc_dvc->carr_pending_cnt = 0;
15770 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15771 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15773 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15774 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15776 /* finally, finally, gentlemen, start your engine */
15777 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15780 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15781 * Resets should be performed. The RISC has to be running
15782 * to issue a SCSI Bus Reset.
15784 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15787 * If the BIOS Signature is present in memory, restore the
15788 * BIOS Handshake Configuration Table and do not perform
15789 * a SCSI Bus Reset.
15791 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15794 * Restore per TID negotiated values.
15796 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15797 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15798 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15799 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15801 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15806 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15808 warn_code = ASC_WARN_BUSRESET_ERROR;
15817 * Initialize the ASC-38C1600.
15819 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15821 * For a non-fatal error return a warning code. If there are no warnings
15822 * then 0 is returned.
15824 * Needed after initialization for error recovery.
15827 AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15829 AdvPortAddr iop_base;
15837 int adv_asc38C1600_expanded_size;
15839 ADV_DCNT contig_len;
15840 ADV_SDCNT buf_size;
15841 ADV_PADDR carr_paddr;
15846 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15847 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15848 uchar max_cmd[ASC_MAX_TID + 1];
15850 /* If there is already an error, don't continue. */
15851 if (asc_dvc->err_code != 0)
15857 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15859 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
15861 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15866 iop_base = asc_dvc->iop_base;
15869 * Save the RISC memory BIOS region before writing the microcode.
15870 * The BIOS may already be loaded and using its RISC LRAM region
15871 * so its region must be saved and restored.
15873 * Note: This code makes the assumption, which is currently true,
15874 * that a chip reset does not clear RISC LRAM.
15876 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15878 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15882 * Save current per TID negotiated values.
15884 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15885 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15886 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15887 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15888 for (tid = 0; tid <= ASC_MAX_TID; tid++)
15890 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15895 * RAM BIST (Built-In Self Test)
15897 * Address : I/O base + offset 0x38h register (byte).
15898 * Function: Bit 7-6(RW) : RAM mode
15899 * Normal Mode : 0x00
15900 * Pre-test Mode : 0x40
15901 * RAM Test Mode : 0x80
15903 * Bit 4(RO) : Done bit
15904 * Bit 3-0(RO) : Status
15905 * Host Error : 0x08
15906 * Int_RAM Error : 0x04
15907 * RISC Error : 0x02
15908 * SCSI Error : 0x01
15911 * Note: RAM BIST code should be put right here, before loading the
15912 * microcode and after saving the RISC memory BIOS region.
15918 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15919 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15920 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15921 * to NORMAL_MODE, return an error too.
15923 for (i = 0; i < 2; i++)
15925 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15926 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15927 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15928 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15930 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15934 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15935 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15936 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15939 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15945 * LRAM Test - It takes about 1.5 ms to run through the test.
15947 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15948 * If Done bit not set or Status not 0, save register byte, set the
15949 * err_code, and return an error.
15951 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15952 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15954 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15955 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15957 /* Get here if Done bit not set or Status not 0. */
15958 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15959 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15963 /* We need to reset back to normal mode after LRAM test passes. */
15964 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15967 * Load the Microcode
15969 * Write the microcode image to RISC memory starting at address 0.
15972 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15975 * Assume the following compressed format of the microcode buffer:
15977 * 254 word (508 byte) table indexed by byte code followed
15978 * by the following byte codes:
15981 * 00: Emit word 0 in table.
15982 * 01: Emit word 1 in table.
15984 * FD: Emit word 253 in table.
15987 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15988 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15991 for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
15993 if (_adv_asc38C1600_buf[i] == 0xff)
15995 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
15997 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15998 _adv_asc38C1600_buf[i + 3] << 8) |
15999 _adv_asc38C1600_buf[i + 2]));
16003 } else if (_adv_asc38C1600_buf[i] == 0xfe)
16005 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16006 _adv_asc38C1600_buf[i + 2] << 8) |
16007 _adv_asc38C1600_buf[i + 1]));
16012 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16013 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
16014 _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
16020 * Set 'word' for later use to clear the rest of memory and save
16021 * the expanded mcode size.
16024 adv_asc38C1600_expanded_size = word;
16027 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
16029 for (; word < ADV_38C1600_MEMSIZE; word += 2)
16031 AdvWriteWordAutoIncLram(iop_base, 0);
16035 * Verify the microcode checksum.
16038 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16040 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
16042 sum += AdvReadWordAutoIncLram(iop_base);
16045 if (sum != _adv_asc38C1600_chksum)
16047 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
16052 * Restore the RISC memory BIOS region.
16054 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
16056 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
16060 * Calculate and write the microcode code checksum to the microcode
16061 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
16063 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
16064 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
16066 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
16067 for (word = begin_addr; word < end_addr; word += 2)
16069 code_sum += AdvReadWordAutoIncLram(iop_base);
16071 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
16074 * Read microcode version and date.
16076 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
16077 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
16080 * Set the chip type to indicate the ASC38C1600.
16082 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
16085 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
16086 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
16087 * cable detection and then we are able to read C_DET[3:0].
16089 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
16090 * Microcode Default Value' section below.
16092 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16093 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
16096 * If the PCI Configuration Command Register "Parity Error Response
16097 * Control" Bit was clear (0), then set the microcode variable
16098 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
16099 * to ignore DMA parity errors.
16101 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
16103 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16104 word |= CONTROL_FLAG_IGNORE_PERR;
16105 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16109 * If the BIOS control flag AIPP (Asynchronous Information
16110 * Phase Protection) disable bit is not set, then set the firmware
16111 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
16112 * AIPP checking and encoding.
16114 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
16116 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16117 word |= CONTROL_FLAG_ENABLE_AIPP;
16118 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16122 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
16123 * and START_CTL_TH [3:2].
16125 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
16126 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
16129 * Microcode operating variables for WDTR, SDTR, and command tag
16130 * queuing will be set in AdvInquiryHandling() based on what a
16131 * device reports it is capable of in Inquiry byte 7.
16133 * If SCSI Bus Resets have been disabled, then directly set
16134 * SDTR and WDTR from the EEPROM configuration. This will allow
16135 * the BIOS and warm boot to work without a SCSI bus hang on
16136 * the Inquiry caused by host and target mismatched DTR values.
16137 * Without the SCSI Bus Reset, before an Inquiry a device can't
16138 * be assumed to be in Asynchronous, Narrow mode.
16140 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
16142 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
16143 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
16147 * Set microcode operating variables for DISC and SDTR_SPEED1,
16148 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
16149 * configuration values.
16151 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
16152 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
16153 * without determining here whether the device supports SDTR.
16155 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
16156 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
16157 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
16158 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
16159 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
16162 * Set SCSI_CFG0 Microcode Default Value.
16164 * The microcode will set the SCSI_CFG0 register using this value
16165 * after it is started below.
16167 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
16168 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
16169 asc_dvc->chip_scsi_id);
16172 * Calculate SCSI_CFG1 Microcode Default Value.
16174 * The microcode will set the SCSI_CFG1 register using this value
16175 * after it is started below.
16177 * Each ASC-38C1600 function has only two cable detect bits.
16178 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
16180 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16183 * If the cable is reversed all of the SCSI_CTRL register signals
16184 * will be set. Check for and return an error if this condition is
16187 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
16189 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
16194 * Each ASC-38C1600 function has two connectors. Only an HVD device
16195 * can not be connected to either connector. An LVD device or SE device
16196 * may be connected to either connecor. If an SE device is connected,
16197 * then at most Ultra speed (20 Mhz) can be used on both connectors.
16199 * If an HVD device is attached, return an error.
16201 if (scsi_cfg1 & HVD)
16203 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
16208 * Each function in the ASC-38C1600 uses only the SE cable detect and
16209 * termination because there are two connectors for each function. Each
16210 * function may use either LVD or SE mode. Corresponding the SE automatic
16211 * termination control EEPROM bits are used for each function. Each
16212 * function has its own EEPROM. If SE automatic control is enabled for
16213 * the function, then set the termination value based on a table listed
16216 * If manual termination is specified in the EEPROM for the function,
16217 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
16218 * ready to be 'ored' into SCSI_CFG1.
16220 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
16222 /* SE automatic termination control is enabled. */
16223 switch(scsi_cfg1 & C_DET_SE)
16225 /* TERM_SE_HI: on, TERM_SE_LO: on */
16226 case 0x1: case 0x2: case 0x3:
16227 asc_dvc->cfg->termination |= TERM_SE;
16231 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
16233 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
16237 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
16238 asc_dvc->cfg->termination |= TERM_SE_HI;
16245 * Clear any set TERM_SE bits.
16247 scsi_cfg1 &= ~TERM_SE;
16250 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
16252 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
16255 * Clear Big Endian and Terminator Polarity bits and set possibly
16256 * modified termination control bits in the Microcode SCSI_CFG1
16259 * Big Endian bit is not used even on big endian machines.
16261 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
16264 * Set SCSI_CFG1 Microcode Default Value
16266 * Set possibly modified termination control bits in the Microcode
16267 * SCSI_CFG1 Register Value.
16269 * The microcode will set the SCSI_CFG1 register using this value
16270 * after it is started below.
16272 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
16275 * Set MEM_CFG Microcode Default Value
16277 * The microcode will set the MEM_CFG register using this value
16278 * after it is started below.
16280 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
16283 * ASC-38C1600 has 32KB internal memory.
16285 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
16286 * out a special 16K Adv Library and Microcode version. After the issue
16287 * resolved, we should turn back to the 32K support. Both a_condor.h and
16288 * mcode.sas files also need to be updated.
16290 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
16291 * BIOS_EN | RAM_SZ_32KB);
16293 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
16296 * Set SEL_MASK Microcode Default Value
16298 * The microcode will set the SEL_MASK register using this value
16299 * after it is started below.
16301 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
16302 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
16305 * Build the carrier freelist.
16307 * Driver must have already allocated memory and set 'carrier_buf'.
16310 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
16312 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
16313 asc_dvc->carr_freelist = NULL;
16314 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
16316 buf_size = ADV_CARRIER_BUFSIZE;
16319 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
16324 * Get physical address for the carrier 'carrp'.
16326 contig_len = sizeof(ADV_CARR_T);
16327 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
16328 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
16330 buf_size -= sizeof(ADV_CARR_T);
16333 * If the current carrier is not physically contiguous, then
16334 * maybe there was a page crossing. Try the next carrier aligned
16337 if (contig_len < sizeof(ADV_CARR_T))
16343 carrp->carr_pa = carr_paddr;
16344 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16347 * Insert the carrier at the beginning of the freelist.
16349 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16350 asc_dvc->carr_freelist = carrp;
16354 while (buf_size > 0);
16357 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16359 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
16361 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16364 asc_dvc->carr_freelist = (ADV_CARR_T *)
16365 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16368 * The first command issued will be placed in the stopper carrier.
16370 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16373 * Set RISC ICQ physical address start value. Initialize the
16374 * COMMA register to the same value otherwise the RISC will
16375 * prematurely detect a command is available.
16377 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16378 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16379 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16382 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16384 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
16386 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16389 asc_dvc->carr_freelist = (ADV_CARR_T *)
16390 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16393 * The first command completed by the RISC will be placed in
16396 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16397 * completed the RISC will set the ASC_RQ_STOPPER bit.
16399 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16402 * Set RISC IRQ physical address start value.
16404 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16405 asc_dvc->carr_pending_cnt = 0;
16407 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16408 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
16409 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16410 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16412 /* finally, finally, gentlemen, start your engine */
16413 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16416 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16417 * Resets should be performed. The RISC has to be running
16418 * to issue a SCSI Bus Reset.
16420 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
16423 * If the BIOS Signature is present in memory, restore the
16424 * per TID microcode operating variables.
16426 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
16429 * Restore per TID negotiated values.
16431 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16432 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16433 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16434 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
16435 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16437 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
16442 if (AdvResetSB(asc_dvc) != ADV_TRUE)
16444 warn_code = ASC_WARN_BUSRESET_ERROR;
16453 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16454 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16455 * all of this is done.
16457 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16459 * For a non-fatal error return a warning code. If there are no warnings
16460 * then 0 is returned.
16462 * Note: Chip is stopped on entry.
16465 AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16467 AdvPortAddr iop_base;
16469 ADVEEP_3550_CONFIG eep_config;
16472 iop_base = asc_dvc->iop_base;
16477 * Read the board's EEPROM configuration.
16479 * Set default values if a bad checksum is found.
16481 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16483 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16486 * Set EEPROM default values.
16488 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
16490 *((uchar *) &eep_config + i) =
16491 *((uchar *) &Default_3550_EEPROM_Config + i);
16495 * Assume the 6 byte board serial number that was read
16496 * from EEPROM is correct even if the EEPROM checksum
16499 eep_config.serial_number_word3 =
16500 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16502 eep_config.serial_number_word2 =
16503 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16505 eep_config.serial_number_word1 =
16506 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16508 AdvSet3550EEPConfig(iop_base, &eep_config);
16511 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16512 * EEPROM configuration that was read.
16514 * This is the mapping of EEPROM fields to Adv Library fields.
16516 asc_dvc->wdtr_able = eep_config.wdtr_able;
16517 asc_dvc->sdtr_able = eep_config.sdtr_able;
16518 asc_dvc->ultra_able = eep_config.ultra_able;
16519 asc_dvc->tagqng_able = eep_config.tagqng_able;
16520 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16521 asc_dvc->max_host_qng = eep_config.max_host_qng;
16522 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16523 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16524 asc_dvc->start_motor = eep_config.start_motor;
16525 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16526 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16527 asc_dvc->no_scam = eep_config.scam_tolerant;
16528 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16529 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16530 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16533 * Set the host maximum queuing (max. 253, min. 16) and the per device
16534 * maximum queuing (max. 63, min. 4).
16536 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16538 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16539 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16541 /* If the value is zero, assume it is uninitialized. */
16542 if (eep_config.max_host_qng == 0)
16544 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16547 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16551 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16553 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16554 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16556 /* If the value is zero, assume it is uninitialized. */
16557 if (eep_config.max_dvc_qng == 0)
16559 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16562 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16567 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16568 * set 'max_dvc_qng' to 'max_host_qng'.
16570 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16572 eep_config.max_dvc_qng = eep_config.max_host_qng;
16576 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16577 * values based on possibly adjusted EEPROM values.
16579 asc_dvc->max_host_qng = eep_config.max_host_qng;
16580 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16584 * If the EEPROM 'termination' field is set to automatic (0), then set
16585 * the ADV_DVC_CFG 'termination' field to automatic also.
16587 * If the termination is specified with a non-zero 'termination'
16588 * value check that a legal value is set and set the ADV_DVC_CFG
16589 * 'termination' field appropriately.
16591 if (eep_config.termination == 0)
16593 asc_dvc->cfg->termination = 0; /* auto termination */
16596 /* Enable manual control with low off / high off. */
16597 if (eep_config.termination == 1)
16599 asc_dvc->cfg->termination = TERM_CTL_SEL;
16601 /* Enable manual control with low off / high on. */
16602 } else if (eep_config.termination == 2)
16604 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16606 /* Enable manual control with low on / high on. */
16607 } else if (eep_config.termination == 3)
16609 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16613 * The EEPROM 'termination' field contains a bad value. Use
16614 * automatic termination instead.
16616 asc_dvc->cfg->termination = 0;
16617 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16625 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16626 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16627 * all of this is done.
16629 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16631 * For a non-fatal error return a warning code. If there are no warnings
16632 * then 0 is returned.
16634 * Note: Chip is stopped on entry.
16637 AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16639 AdvPortAddr iop_base;
16641 ADVEEP_38C0800_CONFIG eep_config;
16643 uchar tid, termination;
16644 ushort sdtr_speed = 0;
16646 iop_base = asc_dvc->iop_base;
16651 * Read the board's EEPROM configuration.
16653 * Set default values if a bad checksum is found.
16655 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16657 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16660 * Set EEPROM default values.
16662 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
16664 *((uchar *) &eep_config + i) =
16665 *((uchar *) &Default_38C0800_EEPROM_Config + i);
16669 * Assume the 6 byte board serial number that was read
16670 * from EEPROM is correct even if the EEPROM checksum
16673 eep_config.serial_number_word3 =
16674 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16676 eep_config.serial_number_word2 =
16677 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16679 eep_config.serial_number_word1 =
16680 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16682 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16685 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16686 * EEPROM configuration that was read.
16688 * This is the mapping of EEPROM fields to Adv Library fields.
16690 asc_dvc->wdtr_able = eep_config.wdtr_able;
16691 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16692 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16693 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16694 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16695 asc_dvc->tagqng_able = eep_config.tagqng_able;
16696 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16697 asc_dvc->max_host_qng = eep_config.max_host_qng;
16698 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16699 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16700 asc_dvc->start_motor = eep_config.start_motor;
16701 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16702 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16703 asc_dvc->no_scam = eep_config.scam_tolerant;
16704 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16705 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16706 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16709 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16710 * are set, then set an 'sdtr_able' bit for it.
16712 asc_dvc->sdtr_able = 0;
16713 for (tid = 0; tid <= ADV_MAX_TID; tid++)
16717 sdtr_speed = asc_dvc->sdtr_speed1;
16718 } else if (tid == 4)
16720 sdtr_speed = asc_dvc->sdtr_speed2;
16721 } else if (tid == 8)
16723 sdtr_speed = asc_dvc->sdtr_speed3;
16724 } else if (tid == 12)
16726 sdtr_speed = asc_dvc->sdtr_speed4;
16728 if (sdtr_speed & ADV_MAX_TID)
16730 asc_dvc->sdtr_able |= (1 << tid);
16736 * Set the host maximum queuing (max. 253, min. 16) and the per device
16737 * maximum queuing (max. 63, min. 4).
16739 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16741 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16742 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16744 /* If the value is zero, assume it is uninitialized. */
16745 if (eep_config.max_host_qng == 0)
16747 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16750 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16754 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16756 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16757 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16759 /* If the value is zero, assume it is uninitialized. */
16760 if (eep_config.max_dvc_qng == 0)
16762 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16765 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16770 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16771 * set 'max_dvc_qng' to 'max_host_qng'.
16773 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16775 eep_config.max_dvc_qng = eep_config.max_host_qng;
16779 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16780 * values based on possibly adjusted EEPROM values.
16782 asc_dvc->max_host_qng = eep_config.max_host_qng;
16783 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16786 * If the EEPROM 'termination' field is set to automatic (0), then set
16787 * the ADV_DVC_CFG 'termination' field to automatic also.
16789 * If the termination is specified with a non-zero 'termination'
16790 * value check that a legal value is set and set the ADV_DVC_CFG
16791 * 'termination' field appropriately.
16793 if (eep_config.termination_se == 0)
16795 termination = 0; /* auto termination for SE */
16798 /* Enable manual control with low off / high off. */
16799 if (eep_config.termination_se == 1)
16803 /* Enable manual control with low off / high on. */
16804 } else if (eep_config.termination_se == 2)
16806 termination = TERM_SE_HI;
16808 /* Enable manual control with low on / high on. */
16809 } else if (eep_config.termination_se == 3)
16811 termination = TERM_SE;
16815 * The EEPROM 'termination_se' field contains a bad value.
16816 * Use automatic termination instead.
16819 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16823 if (eep_config.termination_lvd == 0)
16825 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16828 /* Enable manual control with low off / high off. */
16829 if (eep_config.termination_lvd == 1)
16831 asc_dvc->cfg->termination = termination;
16833 /* Enable manual control with low off / high on. */
16834 } else if (eep_config.termination_lvd == 2)
16836 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16838 /* Enable manual control with low on / high on. */
16839 } else if (eep_config.termination_lvd == 3)
16841 asc_dvc->cfg->termination =
16842 termination | TERM_LVD;
16846 * The EEPROM 'termination_lvd' field contains a bad value.
16847 * Use automatic termination instead.
16849 asc_dvc->cfg->termination = termination;
16850 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16858 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16859 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16860 * all of this is done.
16862 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16864 * For a non-fatal error return a warning code. If there are no warnings
16865 * then 0 is returned.
16867 * Note: Chip is stopped on entry.
16870 AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16872 AdvPortAddr iop_base;
16874 ADVEEP_38C1600_CONFIG eep_config;
16876 uchar tid, termination;
16877 ushort sdtr_speed = 0;
16879 iop_base = asc_dvc->iop_base;
16884 * Read the board's EEPROM configuration.
16886 * Set default values if a bad checksum is found.
16888 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16890 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16893 * Set EEPROM default values.
16895 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
16897 if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
16900 * Set Function 1 EEPROM Word 0 MSB
16902 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16905 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16906 * old Mac system booting problem. The Expansion ROM must
16907 * be disabled in Function 1 for these systems.
16910 *((uchar *) &eep_config + i) =
16911 ((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
16912 (~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
16916 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16917 * the Function 1 interrupt line is wired to INTA.
16919 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16920 * 1 - Function 1 interrupt line wired to INT A.
16921 * 0 - Function 1 interrupt line wired to INT B.
16923 * Note: Adapter boards always have Function 0 wired to INTA.
16924 * Put all 5 GPIO bits in input mode and then read
16925 * their input values.
16927 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
16928 if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
16930 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16931 *((uchar *) &eep_config + i) |=
16932 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16937 *((uchar *) &eep_config + i) =
16938 *((uchar *) &Default_38C1600_EEPROM_Config + i);
16943 * Assume the 6 byte board serial number that was read
16944 * from EEPROM is correct even if the EEPROM checksum
16947 eep_config.serial_number_word3 =
16948 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16950 eep_config.serial_number_word2 =
16951 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16953 eep_config.serial_number_word1 =
16954 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16956 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16960 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16961 * EEPROM configuration that was read.
16963 * This is the mapping of EEPROM fields to Adv Library fields.
16965 asc_dvc->wdtr_able = eep_config.wdtr_able;
16966 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16967 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16968 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16969 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16970 asc_dvc->ppr_able = 0;
16971 asc_dvc->tagqng_able = eep_config.tagqng_able;
16972 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16973 asc_dvc->max_host_qng = eep_config.max_host_qng;
16974 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16975 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
16976 asc_dvc->start_motor = eep_config.start_motor;
16977 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16978 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16979 asc_dvc->no_scam = eep_config.scam_tolerant;
16982 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16983 * are set, then set an 'sdtr_able' bit for it.
16985 asc_dvc->sdtr_able = 0;
16986 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16990 sdtr_speed = asc_dvc->sdtr_speed1;
16991 } else if (tid == 4)
16993 sdtr_speed = asc_dvc->sdtr_speed2;
16994 } else if (tid == 8)
16996 sdtr_speed = asc_dvc->sdtr_speed3;
16997 } else if (tid == 12)
16999 sdtr_speed = asc_dvc->sdtr_speed4;
17001 if (sdtr_speed & ASC_MAX_TID)
17003 asc_dvc->sdtr_able |= (1 << tid);
17009 * Set the host maximum queuing (max. 253, min. 16) and the per device
17010 * maximum queuing (max. 63, min. 4).
17012 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
17014 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17015 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
17017 /* If the value is zero, assume it is uninitialized. */
17018 if (eep_config.max_host_qng == 0)
17020 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17023 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
17027 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
17029 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17030 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
17032 /* If the value is zero, assume it is uninitialized. */
17033 if (eep_config.max_dvc_qng == 0)
17035 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17038 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
17043 * If 'max_dvc_qng' is greater than 'max_host_qng', then
17044 * set 'max_dvc_qng' to 'max_host_qng'.
17046 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
17048 eep_config.max_dvc_qng = eep_config.max_host_qng;
17052 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
17053 * values based on possibly adjusted EEPROM values.
17055 asc_dvc->max_host_qng = eep_config.max_host_qng;
17056 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17059 * If the EEPROM 'termination' field is set to automatic (0), then set
17060 * the ASC_DVC_CFG 'termination' field to automatic also.
17062 * If the termination is specified with a non-zero 'termination'
17063 * value check that a legal value is set and set the ASC_DVC_CFG
17064 * 'termination' field appropriately.
17066 if (eep_config.termination_se == 0)
17068 termination = 0; /* auto termination for SE */
17071 /* Enable manual control with low off / high off. */
17072 if (eep_config.termination_se == 1)
17076 /* Enable manual control with low off / high on. */
17077 } else if (eep_config.termination_se == 2)
17079 termination = TERM_SE_HI;
17081 /* Enable manual control with low on / high on. */
17082 } else if (eep_config.termination_se == 3)
17084 termination = TERM_SE;
17088 * The EEPROM 'termination_se' field contains a bad value.
17089 * Use automatic termination instead.
17092 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17096 if (eep_config.termination_lvd == 0)
17098 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
17101 /* Enable manual control with low off / high off. */
17102 if (eep_config.termination_lvd == 1)
17104 asc_dvc->cfg->termination = termination;
17106 /* Enable manual control with low off / high on. */
17107 } else if (eep_config.termination_lvd == 2)
17109 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
17111 /* Enable manual control with low on / high on. */
17112 } else if (eep_config.termination_lvd == 3)
17114 asc_dvc->cfg->termination =
17115 termination | TERM_LVD;
17119 * The EEPROM 'termination_lvd' field contains a bad value.
17120 * Use automatic termination instead.
17122 asc_dvc->cfg->termination = termination;
17123 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17131 * Read EEPROM configuration into the specified buffer.
17133 * Return a checksum based on the EEPROM configuration read.
17135 STATIC ushort __init
17136 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17138 ushort wval, chksum;
17141 ushort *charfields;
17143 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17144 wbuf = (ushort *) cfg_buf;
17147 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17148 eep_addr < ADV_EEP_DVC_CFG_END;
17149 eep_addr++, wbuf++)
17151 wval = AdvReadEEPWord(iop_base, eep_addr);
17152 chksum += wval; /* Checksum is calculated from word values. */
17153 if (*charfields++) {
17154 *wbuf = le16_to_cpu(wval);
17159 /* Read checksum word. */
17160 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17161 wbuf++; charfields++;
17163 /* Read rest of EEPROM not covered by the checksum. */
17164 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17165 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17166 eep_addr++, wbuf++)
17168 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17169 if (*charfields++) {
17170 *wbuf = le16_to_cpu(*wbuf);
17177 * Read EEPROM configuration into the specified buffer.
17179 * Return a checksum based on the EEPROM configuration read.
17181 STATIC ushort __init
17182 AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
17183 ADVEEP_38C0800_CONFIG *cfg_buf)
17185 ushort wval, chksum;
17188 ushort *charfields;
17190 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17191 wbuf = (ushort *) cfg_buf;
17194 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17195 eep_addr < ADV_EEP_DVC_CFG_END;
17196 eep_addr++, wbuf++)
17198 wval = AdvReadEEPWord(iop_base, eep_addr);
17199 chksum += wval; /* Checksum is calculated from word values. */
17200 if (*charfields++) {
17201 *wbuf = le16_to_cpu(wval);
17206 /* Read checksum word. */
17207 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17208 wbuf++; charfields++;
17210 /* Read rest of EEPROM not covered by the checksum. */
17211 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17212 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17213 eep_addr++, wbuf++)
17215 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17216 if (*charfields++) {
17217 *wbuf = le16_to_cpu(*wbuf);
17224 * Read EEPROM configuration into the specified buffer.
17226 * Return a checksum based on the EEPROM configuration read.
17228 STATIC ushort __init
17229 AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
17230 ADVEEP_38C1600_CONFIG *cfg_buf)
17232 ushort wval, chksum;
17235 ushort *charfields;
17237 charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
17238 wbuf = (ushort *) cfg_buf;
17241 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17242 eep_addr < ADV_EEP_DVC_CFG_END;
17243 eep_addr++, wbuf++)
17245 wval = AdvReadEEPWord(iop_base, eep_addr);
17246 chksum += wval; /* Checksum is calculated from word values. */
17247 if (*charfields++) {
17248 *wbuf = le16_to_cpu(wval);
17253 /* Read checksum word. */
17254 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17255 wbuf++; charfields++;
17257 /* Read rest of EEPROM not covered by the checksum. */
17258 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17259 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17260 eep_addr++, wbuf++)
17262 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17263 if (*charfields++) {
17264 *wbuf = le16_to_cpu(*wbuf);
17271 * Read the EEPROM from specified location
17273 STATIC ushort __init
17274 AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
17276 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17277 ASC_EEP_CMD_READ | eep_word_addr);
17278 AdvWaitEEPCmd(iop_base);
17279 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
17283 * Wait for EEPROM command to complete
17286 AdvWaitEEPCmd(AdvPortAddr iop_base)
17290 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
17292 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
17296 DvcSleepMilliSecond(1);
17298 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
17306 * Write the EEPROM from 'cfg_buf'.
17309 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17312 ushort addr, chksum;
17313 ushort *charfields;
17315 wbuf = (ushort *) cfg_buf;
17316 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17319 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17320 AdvWaitEEPCmd(iop_base);
17323 * Write EEPROM from word 0 to word 20.
17325 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17326 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17330 if (*charfields++) {
17331 word = cpu_to_le16(*wbuf);
17335 chksum += *wbuf; /* Checksum is calculated from word values. */
17336 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17337 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17338 AdvWaitEEPCmd(iop_base);
17339 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17343 * Write EEPROM checksum at word 21.
17345 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17346 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17347 AdvWaitEEPCmd(iop_base);
17348 wbuf++; charfields++;
17351 * Write EEPROM OEM name at words 22 to 29.
17353 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17354 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17358 if (*charfields++) {
17359 word = cpu_to_le16(*wbuf);
17363 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17364 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17365 AdvWaitEEPCmd(iop_base);
17367 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17368 AdvWaitEEPCmd(iop_base);
17373 * Write the EEPROM from 'cfg_buf'.
17376 AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
17377 ADVEEP_38C0800_CONFIG *cfg_buf)
17380 ushort *charfields;
17381 ushort addr, chksum;
17383 wbuf = (ushort *) cfg_buf;
17384 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17387 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17388 AdvWaitEEPCmd(iop_base);
17391 * Write EEPROM from word 0 to word 20.
17393 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17394 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17398 if (*charfields++) {
17399 word = cpu_to_le16(*wbuf);
17403 chksum += *wbuf; /* Checksum is calculated from word values. */
17404 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17405 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17406 AdvWaitEEPCmd(iop_base);
17407 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17411 * Write EEPROM checksum at word 21.
17413 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17414 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17415 AdvWaitEEPCmd(iop_base);
17416 wbuf++; charfields++;
17419 * Write EEPROM OEM name at words 22 to 29.
17421 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17422 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17426 if (*charfields++) {
17427 word = cpu_to_le16(*wbuf);
17431 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17432 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17433 AdvWaitEEPCmd(iop_base);
17435 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17436 AdvWaitEEPCmd(iop_base);
17441 * Write the EEPROM from 'cfg_buf'.
17444 AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
17445 ADVEEP_38C1600_CONFIG *cfg_buf)
17448 ushort *charfields;
17449 ushort addr, chksum;
17451 wbuf = (ushort *) cfg_buf;
17452 charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
17455 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17456 AdvWaitEEPCmd(iop_base);
17459 * Write EEPROM from word 0 to word 20.
17461 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17462 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17466 if (*charfields++) {
17467 word = cpu_to_le16(*wbuf);
17471 chksum += *wbuf; /* Checksum is calculated from word values. */
17472 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17473 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17474 AdvWaitEEPCmd(iop_base);
17475 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17479 * Write EEPROM checksum at word 21.
17481 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17482 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17483 AdvWaitEEPCmd(iop_base);
17484 wbuf++; charfields++;
17487 * Write EEPROM OEM name at words 22 to 29.
17489 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17490 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17494 if (*charfields++) {
17495 word = cpu_to_le16(*wbuf);
17499 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17500 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17501 AdvWaitEEPCmd(iop_base);
17503 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17504 AdvWaitEEPCmd(iop_base);
17510 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17512 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17513 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17514 * RISC to notify it a new command is ready to be executed.
17516 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17517 * set to SCSI_MAX_RETRY.
17519 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17520 * for DMA addresses or math operations are byte swapped to little-endian
17524 * ADV_SUCCESS(1) - The request was successfully queued.
17525 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17526 * request completes.
17527 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17531 AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
17532 ADV_SCSI_REQ_Q *scsiq)
17534 ulong last_int_level;
17535 AdvPortAddr iop_base;
17537 ADV_PADDR req_paddr;
17538 ADV_CARR_T *new_carrp;
17540 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17543 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17545 if (scsiq->target_id > ADV_MAX_TID)
17547 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17548 scsiq->done_status = QD_WITH_ERROR;
17552 iop_base = asc_dvc->iop_base;
17554 last_int_level = DvcEnterCritical();
17557 * Allocate a carrier ensuring at least one carrier always
17558 * remains on the freelist and initialize fields.
17560 if ((new_carrp = asc_dvc->carr_freelist) == NULL)
17562 DvcLeaveCritical(last_int_level);
17565 asc_dvc->carr_freelist = (ADV_CARR_T *)
17566 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17567 asc_dvc->carr_pending_cnt++;
17570 * Set the carrier to be a stopper by setting 'next_vpa'
17571 * to the stopper value. The current stopper will be changed
17572 * below to point to the new stopper.
17574 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17577 * Clear the ADV_SCSI_REQ_Q done flag.
17579 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17581 req_size = sizeof(ADV_SCSI_REQ_Q);
17582 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
17583 (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
17585 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17586 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17588 /* Wait for assertion before making little-endian */
17589 req_paddr = cpu_to_le32(req_paddr);
17591 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17592 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17593 scsiq->scsiq_rptr = req_paddr;
17595 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17597 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17598 * order during initialization.
17600 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17603 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17604 * the microcode. The newly allocated stopper will become the new
17607 asc_dvc->icq_sp->areq_vpa = req_paddr;
17610 * Set the 'next_vpa' pointer for the old stopper to be the
17611 * physical address of the new stopper. The RISC can only
17612 * follow physical addresses.
17614 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17617 * Set the host adapter stopper pointer to point to the new carrier.
17619 asc_dvc->icq_sp = new_carrp;
17621 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17622 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17625 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17627 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17628 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17631 * Clear the tickle value. In the ASC-3550 the RISC flag
17632 * command 'clr_tickle_a' does not work unless the host
17633 * value is cleared.
17635 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17637 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17640 * Notify the RISC a carrier is ready by writing the physical
17641 * address of the new carrier stopper to the COMMA register.
17643 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17644 le32_to_cpu(new_carrp->carr_pa));
17647 DvcLeaveCritical(last_int_level);
17649 return ADV_SUCCESS;
17653 * Reset SCSI Bus and purge all outstanding requests.
17656 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17657 * ADV_FALSE(0) - Microcode command failed.
17658 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17659 * may be hung which requires driver recovery.
17662 AdvResetSB(ADV_DVC_VAR *asc_dvc)
17667 * Send the SCSI Bus Reset idle start idle command which asserts
17668 * the SCSI Bus Reset signal.
17670 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
17671 if (status != ADV_TRUE)
17677 * Delay for the specified SCSI Bus Reset hold time.
17679 * The hold time delay is done on the host because the RISC has no
17680 * microsecond accurate timer.
17682 DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
17685 * Send the SCSI Bus Reset end idle command which de-asserts
17686 * the SCSI Bus Reset signal and purges any pending requests.
17688 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
17689 if (status != ADV_TRUE)
17694 DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
17700 * Reset chip and SCSI Bus.
17703 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17704 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17707 AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17710 ushort wdtr_able, sdtr_able, tagqng_able;
17711 ushort ppr_able = 0;
17712 uchar tid, max_cmd[ADV_MAX_TID + 1];
17713 AdvPortAddr iop_base;
17716 iop_base = asc_dvc->iop_base;
17719 * Save current per TID negotiated values.
17721 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17722 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17723 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17725 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17727 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17728 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17730 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17735 * Force the AdvInitAsc3550/38C0800Driver() function to
17736 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17737 * The initialization functions assumes a SCSI Bus Reset is not
17738 * needed if the BIOS signature word is present.
17740 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17741 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17744 * Stop chip and reset it.
17746 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17747 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17748 DvcSleepMilliSecond(100);
17749 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
17752 * Reset Adv Library error code, if any, and try
17753 * re-initializing the chip.
17755 asc_dvc->err_code = 0;
17756 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17758 status = AdvInitAsc38C1600Driver(asc_dvc);
17760 else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17762 status = AdvInitAsc38C0800Driver(asc_dvc);
17765 status = AdvInitAsc3550Driver(asc_dvc);
17768 /* Translate initialization return value to status value. */
17774 status = ADV_FALSE;
17778 * Restore the BIOS signature word.
17780 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17783 * Restore per TID negotiated values.
17785 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17786 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17787 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17789 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17791 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17792 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17794 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17802 * Adv Library Interrupt Service Routine
17804 * This function is called by a driver's interrupt service routine.
17805 * The function disables and re-enables interrupts.
17807 * When a microcode idle command is completed, the ADV_DVC_VAR
17808 * 'idle_cmd_done' field is set to ADV_TRUE.
17810 * Note: AdvISR() can be called when interrupts are disabled or even
17811 * when there is no hardware interrupt condition present. It will
17812 * always check for completed idle commands and microcode requests.
17813 * This is an important feature that shouldn't be changed because it
17814 * allows commands to be completed from polling mode loops.
17817 * ADV_TRUE(1) - interrupt was pending
17818 * ADV_FALSE(0) - no interrupt was pending
17821 AdvISR(ADV_DVC_VAR *asc_dvc)
17823 AdvPortAddr iop_base;
17826 ADV_CARR_T *free_carrp;
17827 ADV_VADDR irq_next_vpa;
17829 ADV_SCSI_REQ_Q *scsiq;
17831 flags = DvcEnterCritical();
17833 iop_base = asc_dvc->iop_base;
17835 /* Reading the register clears the interrupt. */
17836 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17838 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17839 ADV_INTR_STATUS_INTRC)) == 0)
17841 DvcLeaveCritical(flags);
17846 * Notify the driver of an asynchronous microcode condition by
17847 * calling the ADV_DVC_VAR.async_callback function. The function
17848 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17850 if (int_stat & ADV_INTR_STATUS_INTRB)
17854 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17856 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17857 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17859 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17860 asc_dvc->carr_pending_cnt != 0)
17862 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17863 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17865 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17870 if (asc_dvc->async_callback != 0)
17872 (*asc_dvc->async_callback)(asc_dvc, intrb_code);
17877 * Check if the IRQ stopper carrier contains a completed request.
17879 while (((irq_next_vpa =
17880 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
17883 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17884 * The RISC will have set 'areq_vpa' to a virtual address.
17886 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17887 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17888 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17889 * in AdvExeScsiQueue().
17891 scsiq = (ADV_SCSI_REQ_Q *)
17892 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17895 * Request finished with good status and the queue was not
17896 * DMAed to host memory by the firmware. Set all status fields
17897 * to indicate good status.
17899 if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
17901 scsiq->done_status = QD_NO_ERROR;
17902 scsiq->host_status = scsiq->scsi_status = 0;
17903 scsiq->data_cnt = 0L;
17907 * Advance the stopper pointer to the next carrier
17908 * ignoring the lower four bits. Free the previous
17911 free_carrp = asc_dvc->irq_sp;
17912 asc_dvc->irq_sp = (ADV_CARR_T *)
17913 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17915 free_carrp->next_vpa =
17916 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17917 asc_dvc->carr_freelist = free_carrp;
17918 asc_dvc->carr_pending_cnt--;
17920 ASC_ASSERT(scsiq != NULL);
17921 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17924 * Clear request microcode control flag.
17929 * If the command that completed was a SCSI INQUIRY and
17930 * LUN 0 was sent the command, then process the INQUIRY
17931 * command information for the device.
17933 * Note: If data returned were either VPD or CmdDt data,
17934 * don't process the INQUIRY command information for
17935 * the device, otherwise may erroneously set *_able bits.
17937 if (scsiq->done_status == QD_NO_ERROR &&
17938 scsiq->cdb[0] == INQUIRY &&
17939 scsiq->target_lun == 0 &&
17940 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17941 == ADV_INQ_RTN_STD_INQUIRY_DATA)
17943 AdvInquiryHandling(asc_dvc, scsiq);
17947 * Notify the driver of the completed request by passing
17948 * the ADV_SCSI_REQ_Q pointer to its callback function.
17950 scsiq->a_flag |= ADV_SCSIQ_DONE;
17951 (*asc_dvc->isr_callback)(asc_dvc, scsiq);
17953 * Note: After the driver callback function is called, 'scsiq'
17954 * can no longer be referenced.
17956 * Fall through and continue processing other completed
17961 * Disable interrupts again in case the driver inadvertently
17962 * enabled interrupts in its callback function.
17964 * The DvcEnterCritical() return value is ignored, because
17965 * the 'flags' saved when AdvISR() was first entered will be
17966 * used to restore the interrupt flag on exit.
17968 (void) DvcEnterCritical();
17970 DvcLeaveCritical(flags);
17975 * Send an idle command to the chip and wait for completion.
17977 * Command completion is polled for once per microsecond.
17979 * The function can be called from anywhere including an interrupt handler.
17980 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
17981 * functions to prevent reentrancy.
17984 * ADV_TRUE - command completed successfully
17985 * ADV_FALSE - command failed
17986 * ADV_ERROR - command timed out
17989 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
17991 ADV_DCNT idle_cmd_parameter)
17993 ulong last_int_level;
17996 AdvPortAddr iop_base;
17998 last_int_level = DvcEnterCritical();
18000 iop_base = asc_dvc->iop_base;
18003 * Clear the idle command status which is set by the microcode
18004 * to a non-zero value to indicate when the command is completed.
18005 * The non-zero result is one of the IDLE_CMD_STATUS_* values
18006 * defined in a_advlib.h.
18008 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
18011 * Write the idle command value after the idle command parameter
18012 * has been written to avoid a race condition. If the order is not
18013 * followed, the microcode may process the idle command before the
18014 * parameters have been written to LRAM.
18016 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
18017 cpu_to_le32(idle_cmd_parameter));
18018 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
18021 * Tickle the RISC to tell it to process the idle command.
18023 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
18024 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
18027 * Clear the tickle value. In the ASC-3550 the RISC flag
18028 * command 'clr_tickle_b' does not work unless the host
18029 * value is cleared.
18031 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
18034 /* Wait for up to 100 millisecond for the idle command to timeout. */
18035 for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
18037 /* Poll once each microsecond for command completion. */
18038 for (j = 0; j < SCSI_US_PER_MSEC; j++)
18040 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
18043 DvcLeaveCritical(last_int_level);
18046 DvcDelayMicroSecond(asc_dvc, (ushort) 1);
18050 ASC_ASSERT(0); /* The idle command should never timeout. */
18051 DvcLeaveCritical(last_int_level);
18056 * Inquiry Information Byte 7 Handling
18058 * Handle SCSI Inquiry Command information for a device by setting
18059 * microcode operating variables that affect WDTR, SDTR, and Tag
18063 AdvInquiryHandling(
18064 ADV_DVC_VAR *asc_dvc,
18065 ADV_SCSI_REQ_Q *scsiq)
18067 AdvPortAddr iop_base;
18069 ADV_SCSI_INQUIRY *inq;
18074 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
18077 * If less than 8 bytes of INQUIRY information were requested or less
18078 * than 8 bytes were transferred, then return. cdb[4] is the request
18079 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
18080 * microcode to the transfer residual count.
18083 if (scsiq->cdb[4] < 8 ||
18084 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
18089 iop_base = asc_dvc->iop_base;
18090 tid = scsiq->target_id;
18092 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
18095 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
18097 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
18103 * INQUIRY Byte 7 Handling
18105 * Use a device's INQUIRY byte 7 to determine whether it
18106 * supports WDTR, SDTR, and Tag Queuing. If the feature
18107 * is enabled in the EEPROM and the device supports the
18108 * feature, then enable it in the microcode.
18111 tidmask = ADV_TID_TO_TIDMASK(tid);
18116 * If the EEPROM enabled WDTR for the device and the device
18117 * supports wide bus (16 bit) transfers, then turn on the
18118 * device's 'wdtr_able' bit and write the new value to the
18121 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
18123 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18124 if ((cfg_word & tidmask) == 0)
18126 cfg_word |= tidmask;
18127 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18130 * Clear the microcode "SDTR negotiation" and "WDTR
18131 * negotiation" done indicators for the target to cause
18132 * it to negotiate with the new setting set above.
18133 * WDTR when accepted causes the target to enter
18134 * asynchronous mode, so SDTR must be negotiated.
18136 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18137 cfg_word &= ~tidmask;
18138 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18139 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18140 cfg_word &= ~tidmask;
18141 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18146 * Synchronous Transfers
18148 * If the EEPROM enabled SDTR for the device and the device
18149 * supports synchronous transfers, then turn on the device's
18150 * 'sdtr_able' bit. Write the new value to the microcode.
18152 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
18154 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18155 if ((cfg_word & tidmask) == 0)
18157 cfg_word |= tidmask;
18158 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18161 * Clear the microcode "SDTR negotiation" done indicator
18162 * for the target to cause it to negotiate with the new
18163 * setting set above.
18165 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18166 cfg_word &= ~tidmask;
18167 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18171 * If the Inquiry data included enough space for the SPI-3
18172 * Clocking field, then check if DT mode is supported.
18174 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
18175 (scsiq->cdb[4] >= 57 ||
18176 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
18179 * PPR (Parallel Protocol Request) Capable
18181 * If the device supports DT mode, then it must be PPR capable.
18182 * The PPR message will be used in place of the SDTR and WDTR
18183 * messages to negotiate synchronous speed and offset, transfer
18184 * width, and protocol options.
18186 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
18188 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18189 asc_dvc->ppr_able |= tidmask;
18190 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18195 * If the EEPROM enabled Tag Queuing for the device and the
18196 * device supports Tag Queueing, then turn on the device's
18197 * 'tagqng_enable' bit in the microcode and set the microcode
18198 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
18201 * Tag Queuing is disabled for the BIOS which runs in polled
18202 * mode and would see no benefit from Tag Queuing. Also by
18203 * disabling Tag Queuing in the BIOS devices with Tag Queuing
18204 * bugs will at least work with the BIOS.
18206 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
18208 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18209 cfg_word |= tidmask;
18210 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18212 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
18213 asc_dvc->max_dvc_qng);
18217 MODULE_LICENSE("Dual BSD/GPL");
18219 /* PCI Devices supported by this driver */
18220 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
18221 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
18222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18223 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
18224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18225 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
18226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18227 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
18228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18229 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
18230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18231 { PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
18232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18235 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);