2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "1.2"
57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_USE_CLUSTERING = 0,
60 AHCI_CMD_SLOT_SZ = 32 * 32,
62 AHCI_CMD_TBL_HDR = 0x80,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
65 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
67 AHCI_IRQ_ON_SG = (1 << 31),
68 AHCI_CMD_ATAPI = (1 << 5),
69 AHCI_CMD_WRITE = (1 << 6),
70 AHCI_CMD_PREFETCH = (1 << 7),
71 AHCI_CMD_RESET = (1 << 8),
72 AHCI_CMD_CLR_BUSY = (1 << 10),
74 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78 /* global controller registers */
79 HOST_CAP = 0x00, /* host capabilities */
80 HOST_CTL = 0x04, /* global host control */
81 HOST_IRQ_STAT = 0x08, /* interrupt status */
82 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
83 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
86 HOST_RESET = (1 << 0), /* reset controller; self-clear */
87 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
88 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
91 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
92 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
93 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
94 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
96 /* registers for each SATA port */
97 PORT_LST_ADDR = 0x00, /* command list DMA addr */
98 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
99 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
100 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
101 PORT_IRQ_STAT = 0x10, /* interrupt status */
102 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
103 PORT_CMD = 0x18, /* port command */
104 PORT_TFDATA = 0x20, /* taskfile data */
105 PORT_SIG = 0x24, /* device TF signature */
106 PORT_CMD_ISSUE = 0x38, /* command issue */
107 PORT_SCR = 0x28, /* SATA phy register block */
108 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
109 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
110 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
111 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
113 /* PORT_IRQ_{STAT,MASK} bits */
114 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
115 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
116 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
117 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
118 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
119 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
120 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
121 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
123 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
124 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
125 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
126 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
127 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
128 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
129 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
130 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
131 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
133 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
135 PORT_IRQ_HBUS_DATA_ERR |
137 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
138 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
139 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
140 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
141 PORT_IRQ_D2H_REG_FIS,
144 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
145 PORT_CMD_CPD = (1 << 20), /* Cold presence detection */
146 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
147 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
148 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
149 PORT_CMD_CLO = (1 << 3), /* Command list override */
150 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
151 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
152 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
154 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
155 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
156 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
157 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
159 /* hpriv->flags bits */
160 AHCI_FLAG_MSI = (1 << 0),
163 struct ahci_cmd_hdr {
178 struct ahci_host_priv {
180 u32 cap; /* cache of HOST_CAP register */
181 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
182 u32 dev_map; /* connected devices */
185 struct ahci_port_priv {
186 struct ahci_cmd_hdr *cmd_slot;
187 dma_addr_t cmd_slot_dma;
189 dma_addr_t cmd_tbl_dma;
190 struct ahci_sg *cmd_tbl_sg;
192 dma_addr_t rx_fis_dma;
195 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
196 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
197 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
198 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
199 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
200 static int ahci_start_engine(void __iomem *port_mmio);
201 static int ahci_stop_engine(void __iomem *port_mmio);
202 static int ahci_stop_fis_rx(void __iomem *port_mmio);
203 static void ahci_start_fis_rx(void __iomem *port_mmio,
204 struct ahci_port_priv *pp,
205 struct ahci_host_priv *hpriv);
206 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
207 static void ahci_irq_clear(struct ata_port *ap);
208 static void ahci_eng_timeout(struct ata_port *ap);
209 static int ahci_port_start(struct ata_port *ap);
210 static void ahci_port_stop(struct ata_port *ap);
211 static int ahci_port_suspend(struct ata_port *ap, pm_message_t state);
212 static int ahci_port_resume(struct ata_port *ap);
213 static int ahci_port_standby(void __iomem *port_mmio, u32 cap);
214 static int ahci_port_spinup(void __iomem *port_mmio, u32 cap);
215 static void ahci_port_disable(struct ata_port *ap);
216 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
217 static void ahci_qc_prep(struct ata_queued_cmd *qc);
218 static u8 ahci_check_status(struct ata_port *ap);
219 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
220 static int ahci_scsi_device_suspend(struct scsi_device *sdev, pm_message_t state);
221 static int ahci_scsi_device_resume(struct scsi_device *sdev);
222 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t state);
223 static int ahci_pci_device_resume(struct pci_dev *pdev);
224 static void ahci_remove_one (struct pci_dev *pdev);
226 static struct scsi_host_template ahci_sht = {
227 .module = THIS_MODULE,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
231 .can_queue = ATA_DEF_QUEUE,
232 .this_id = ATA_SHT_THIS_ID,
233 .sg_tablesize = AHCI_MAX_SG,
234 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
235 .emulated = ATA_SHT_EMULATED,
236 .use_clustering = AHCI_USE_CLUSTERING,
237 .proc_name = DRV_NAME,
238 .dma_boundary = AHCI_DMA_BOUNDARY,
239 .slave_configure = ata_scsi_slave_config,
240 .bios_param = ata_std_bios_param,
241 .resume = ahci_scsi_device_resume,
242 .suspend = ahci_scsi_device_suspend,
245 static const struct ata_port_operations ahci_ops = {
246 .port_disable = ahci_port_disable,
248 .check_status = ahci_check_status,
249 .check_altstatus = ahci_check_status,
250 .dev_select = ata_noop_dev_select,
252 .tf_read = ahci_tf_read,
254 .probe_reset = ahci_probe_reset,
256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
259 .eng_timeout = ahci_eng_timeout,
261 .irq_handler = ahci_interrupt,
262 .irq_clear = ahci_irq_clear,
264 .scr_read = ahci_scr_read,
265 .scr_write = ahci_scr_write,
267 .port_start = ahci_port_start,
268 .port_stop = ahci_port_stop,
271 static const struct ata_port_info ahci_port_info[] = {
275 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
276 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
277 .pio_mask = 0x1f, /* pio0-4 */
278 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
279 .port_ops = &ahci_ops,
283 static const struct pci_device_id ahci_pci_tbl[] = {
284 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
285 board_ahci }, /* ICH6 */
286 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH6M */
288 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH7 */
290 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH7M */
292 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH7R */
294 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* ULi M5288 */
296 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* ESB2 */
298 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
299 board_ahci }, /* ESB2 */
300 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
301 board_ahci }, /* ESB2 */
302 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
303 board_ahci }, /* ICH7-M DH */
304 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
305 board_ahci }, /* ICH8 */
306 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
307 board_ahci }, /* ICH8 */
308 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
309 board_ahci }, /* ICH8 */
310 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
311 board_ahci }, /* ICH8M */
312 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
313 board_ahci }, /* ICH8M */
314 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
315 board_ahci }, /* JMicron JMB360 */
316 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
317 board_ahci }, /* JMicron JMB363 */
318 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
319 board_ahci }, /* ATI SB600 non-raid */
320 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
321 board_ahci }, /* ATI SB600 raid */
322 { } /* terminate list */
326 static struct pci_driver ahci_pci_driver = {
328 .id_table = ahci_pci_tbl,
329 .probe = ahci_init_one,
330 .remove = ahci_remove_one,
331 .suspend = ahci_pci_device_suspend,
332 .resume = ahci_pci_device_resume,
336 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
338 return base + 0x100 + (port * 0x80);
341 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
343 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
346 static int ahci_port_start(struct ata_port *ap)
348 struct device *dev = ap->host_set->dev;
349 struct ahci_host_priv *hpriv = ap->host_set->private_data;
350 struct ahci_port_priv *pp;
351 void __iomem *mmio = ap->host_set->mmio_base;
352 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
357 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
360 memset(pp, 0, sizeof(*pp));
362 rc = ata_pad_alloc(ap, dev);
368 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
370 ata_pad_free(ap, dev);
374 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
377 * First item in chunk of DMA memory: 32-slot command table,
378 * 32 bytes each in size
381 pp->cmd_slot_dma = mem_dma;
383 mem += AHCI_CMD_SLOT_SZ;
384 mem_dma += AHCI_CMD_SLOT_SZ;
387 * Second item: Received-FIS area
390 pp->rx_fis_dma = mem_dma;
392 mem += AHCI_RX_FIS_SZ;
393 mem_dma += AHCI_RX_FIS_SZ;
396 * Third item: data area for storing a single command
397 * and its scatter-gather table
400 pp->cmd_tbl_dma = mem_dma;
402 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
404 ap->private_data = pp;
407 * Driver is setup; initialize the HBA
409 ahci_start_fis_rx(port_mmio, pp, hpriv);
410 rc = ahci_port_spinup(port_mmio, hpriv->cap);
412 printk(KERN_WARNING "ata%d: could not spinup device (%d)\n",
416 * Do not enable DMA here; according to the spec
417 * (section 10.1.1) we should first enable FIS reception,
418 * then check if the port is enabled before we try to
420 * And as the port check is done during probe
421 * we really shouldn't be doing it here.
427 static void ahci_port_stop(struct ata_port *ap)
429 struct device *dev = ap->host_set->dev;
430 struct ahci_port_priv *pp = ap->private_data;
432 ahci_port_suspend(ap, PMSG_SUSPEND);
434 ap->private_data = NULL;
435 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
436 pp->cmd_slot, pp->cmd_slot_dma);
437 ata_pad_free(ap, dev);
441 static int ahci_port_suspend(struct ata_port *ap, pm_message_t state)
443 void __iomem *mmio = ap->host_set->mmio_base;
444 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
445 struct ahci_host_priv *hpriv = ap->host_set->private_data;
451 rc = ahci_stop_engine(port_mmio);
453 printk(KERN_WARNING "ata%u: DMA engine busy\n", ap->id);
458 * Disable FIS reception
460 rc = ahci_stop_fis_rx(port_mmio);
462 printk(KERN_WARNING "ata%d: FIS RX still running (rc %d)\n",
466 * Put device into slumber mode
468 if (!rc && state.event != PM_EVENT_FREEZE)
469 ahci_port_standby(port_mmio, hpriv->cap);
474 static int ahci_port_resume(struct ata_port *ap)
476 void __iomem *mmio = ap->host_set->mmio_base;
477 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
478 struct ahci_host_priv *hpriv = ap->host_set->private_data;
479 struct ahci_port_priv *pp = ap->private_data;
484 * Enable FIS reception
486 ahci_start_fis_rx(port_mmio, pp, hpriv);
488 rc = ahci_port_spinup(port_mmio, hpriv->cap);
490 printk(KERN_WARNING "ata%d: could not spinup device (%d)\n",
496 tmp = readl(port_mmio + PORT_SCR_ERR);
497 writel(tmp, port_mmio + PORT_SCR_ERR);
499 * Clear interrupt status
501 tmp = readl(mmio + HOST_CTL);
502 if (!(tmp & HOST_IRQ_EN)) {
505 /* ack any pending irq events for this port */
506 irq_stat = readl(port_mmio + PORT_IRQ_STAT);
508 writel(irq_stat, port_mmio + PORT_IRQ_STAT);
510 /* set irq mask (enables interrupts) */
511 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
513 if ((hpriv->dev_map >> (ap->port_no + 1)) == 0) {
515 * Enable interrupts if this was the last port
517 printk(KERN_WARNING "ata%d: enabling interrupts\n",
520 irq_stat = readl(mmio + HOST_IRQ_STAT);
522 writel(irq_stat, mmio + HOST_IRQ_STAT);
525 writel(tmp, mmio + HOST_CTL);
526 (void) readl(mmio + HOST_CTL);
533 rc = ahci_start_engine(port_mmio);
535 printk(KERN_WARNING "ata%d: cannot start DMA engine (rc %d)\n",
541 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
546 case SCR_STATUS: sc_reg = 0; break;
547 case SCR_CONTROL: sc_reg = 1; break;
548 case SCR_ERROR: sc_reg = 2; break;
549 case SCR_ACTIVE: sc_reg = 3; break;
554 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
558 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
564 case SCR_STATUS: sc_reg = 0; break;
565 case SCR_CONTROL: sc_reg = 1; break;
566 case SCR_ERROR: sc_reg = 2; break;
567 case SCR_ACTIVE: sc_reg = 3; break;
572 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
575 static int ahci_stop_engine(void __iomem *port_mmio)
580 tmp = readl(port_mmio + PORT_CMD);
581 /* Check if the HBA is idle */
582 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
585 /* Setting HBA to idle */
586 tmp &= ~PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
590 * wait for engine to become idle
594 tmp = readl(port_mmio + PORT_CMD);
595 if ((tmp & PORT_CMD_LIST_ON) == 0)
603 static int ahci_start_engine(void __iomem *port_mmio)
611 tmp = readl(port_mmio + PORT_CMD);
614 * AHCI rev 1.1 section 10.3.1:
615 * Software shall not set PxCMD.ST to '1' until it verifies
616 * that PxCMD.CR is '0' and has set PxCMD.FRE to '1'
618 if ((tmp & PORT_CMD_FIS_RX) == 0)
622 * wait for engine to become idle.
625 tmp = readl(port_mmio + PORT_CMD);
626 if ((tmp & PORT_CMD_LIST_ON) == 0)
633 * We need to do a port reset / HBA reset here
641 tmp |= PORT_CMD_START;
642 writel(tmp, port_mmio + PORT_CMD);
643 readl(port_mmio + PORT_CMD); /* flush */
648 static int ahci_stop_fis_rx(void __iomem *port_mmio)
656 tmp = readl(port_mmio + PORT_CMD);
658 /* Check if FIS RX is already disabled */
659 if ((tmp & PORT_CMD_FIS_RX) == 0)
663 * AHCI Rev 1.1 section 10.3.2
664 * Software shall not clear PxCMD.FRE while
665 * PxCMD.ST or PxCMD.CR is set to '1'
667 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_START)) {
672 * Disable FIS reception
674 * AHCI Rev 1.1 Section 10.1.2:
675 * If PxCMD.FRE is set to '1', software should clear it
676 * to '0' and wait at least 500 milliseconds for PxCMD.FR
677 * to return '0' when read. If PxCMD.FR does not clear
678 * '0' correctly, then software may attempt a port reset
679 * of a full HBA reset to recover.
681 tmp &= ~(PORT_CMD_FIS_RX);
682 writel(tmp, port_mmio + PORT_CMD);
687 tmp = readl(port_mmio + PORT_CMD);
688 if ((tmp & PORT_CMD_FIS_ON) == 0)
696 static void ahci_start_fis_rx(void __iomem *port_mmio,
697 struct ahci_port_priv *pp,
698 struct ahci_host_priv *hpriv)
705 if (hpriv->cap & HOST_CAP_64)
706 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
707 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
708 readl(port_mmio + PORT_LST_ADDR); /* flush */
710 if (hpriv->cap & HOST_CAP_64)
711 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
712 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
713 readl(port_mmio + PORT_FIS_ADDR); /* flush */
716 * Enable FIS reception
718 tmp = readl(port_mmio + PORT_CMD);
719 tmp |= PORT_CMD_FIS_RX;
720 writel(tmp, port_mmio + PORT_CMD);
721 readl(port_mmio + PORT_CMD); /* flush */
724 static int ahci_port_standby(void __iomem *port_mmio, u32 cap)
726 u32 tmp, scontrol, sstatus;
728 tmp = readl(port_mmio + PORT_CMD);
730 * AHCI Rev1.1 Section 5.3.2.3:
731 * Software is only allowed to program the PxCMD.FRE,
732 * PxCMD.POD, PxSCTL.DET, and PxCMD.SUD register bits
733 * when PxCMD.ST is set to '0'
735 if (tmp & PORT_CMD_START)
738 if (cap & HOST_CAP_SSC) {
740 * Enable transitions to slumber mode
742 scontrol = readl(port_mmio + PORT_SCR_CTL);
743 if ((scontrol & 0x0f00) > 0x100) {
745 writel(scontrol, port_mmio + PORT_SCR_CTL);
748 * Put device into slumber mode
750 tmp |= PORT_CMD_ICC_SLUMBER;
751 writel(tmp, port_mmio + PORT_CMD);
752 tmp = readl(port_mmio + PORT_CMD);
755 * Actually, we should wait for the device to
756 * enter slumber mode by checking
757 * sstatus & 0xf00 == 6
759 sstatus = readl(port_mmio + PORT_SCR_STAT);
763 * Put device into listen mode
765 scontrol = readl(port_mmio + PORT_SCR_CTL);
767 writel(scontrol, port_mmio + PORT_SCR_CTL);
769 tmp = readl(port_mmio + PORT_CMD);
770 if (cap & HOST_CAP_SSS) {
772 * Spin down the device for staggered spin-up support
774 tmp &= ~PORT_CMD_SPIN_UP;
775 writel(tmp, port_mmio + PORT_CMD);
776 readl(port_mmio + PORT_CMD); /* flush */
782 static int ahci_port_spinup(void __iomem *port_mmio, u32 cap)
786 tmp = readl(port_mmio + PORT_CMD);
788 * AHCI Rev1.1 Section 5.3.2.3:
789 * Software is only allowed to program the PxCMD.FRE,
790 * PxCMD.POD, PxSCTL.DET, and PxCMD.SUD register bits
791 * when PxCMD.ST is set to '0'
793 if (tmp & PORT_CMD_START)
797 * Power on device if supported
799 if (tmp & PORT_CMD_CPD) {
800 tmp |= PORT_CMD_POWER_ON;
801 writel(tmp, port_mmio + PORT_CMD);
802 tmp = readl(port_mmio + PORT_CMD);
808 if (cap & HOST_CAP_SSS) {
809 tmp |= PORT_CMD_SPIN_UP;
810 writel(tmp, port_mmio + PORT_CMD);
811 tmp = readl(port_mmio + PORT_CMD);
814 if ((tmp & PORT_CMD_ICC_MASK) != PORT_CMD_ICC_ACTIVE) {
815 tmp |= PORT_CMD_ICC_ACTIVE;
816 writel(tmp, port_mmio + PORT_CMD);
817 tmp = readl(port_mmio + PORT_CMD);
823 static void ahci_port_disable(struct ata_port *ap)
825 struct ahci_host_priv *hpriv = ap->host_set->private_data;
827 ata_port_disable(ap);
829 hpriv->dev_map &= ~(1 << ap->port_no);
832 static unsigned int ahci_dev_classify(struct ata_port *ap)
834 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
835 struct ata_taskfile tf;
838 tmp = readl(port_mmio + PORT_SIG);
839 tf.lbah = (tmp >> 24) & 0xff;
840 tf.lbam = (tmp >> 16) & 0xff;
841 tf.lbal = (tmp >> 8) & 0xff;
842 tf.nsect = (tmp) & 0xff;
844 return ata_dev_classify(&tf);
847 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
849 pp->cmd_slot[0].opts = cpu_to_le32(opts);
850 pp->cmd_slot[0].status = 0;
851 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
852 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
855 static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
856 unsigned long interval_msec,
857 unsigned long timeout_msec)
859 unsigned long timeout;
862 timeout = jiffies + (timeout_msec * HZ) / 1000;
865 if ((tmp & mask) == val)
867 msleep(interval_msec);
868 } while (time_before(jiffies, timeout));
873 static int ahci_softreset(struct ata_port *ap, int verbose, unsigned int *class)
875 struct ahci_host_priv *hpriv = ap->host_set->private_data;
876 struct ahci_port_priv *pp = ap->private_data;
877 void __iomem *mmio = ap->host_set->mmio_base;
878 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
879 const u32 cmd_fis_len = 5; /* five dwords */
880 const char *reason = NULL;
881 struct ata_taskfile tf;
887 /* prepare for SRST (AHCI-1.1 10.4.1) */
888 rc = ahci_stop_engine(port_mmio);
890 reason = "failed to stop engine";
894 /* check BUSY/DRQ, perform Command List Override if necessary */
895 ahci_tf_read(ap, &tf);
896 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
899 if (!(hpriv->cap & HOST_CAP_CLO)) {
901 reason = "port busy but no CLO";
905 tmp = readl(port_mmio + PORT_CMD);
907 writel(tmp, port_mmio + PORT_CMD);
908 readl(port_mmio + PORT_CMD); /* flush */
910 if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
913 reason = "CLO failed";
919 ahci_start_engine(port_mmio);
921 ata_tf_init(ap, &tf, 0);
924 /* issue the first D2H Register FIS */
925 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
928 ata_tf_to_fis(&tf, fis, 0);
929 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
931 writel(1, port_mmio + PORT_CMD_ISSUE);
932 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
934 if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
936 reason = "1st FIS failed";
940 /* spec says at least 5us, but be generous and sleep for 1ms */
943 /* issue the second D2H Register FIS */
944 ahci_fill_cmd_slot(pp, cmd_fis_len);
947 ata_tf_to_fis(&tf, fis, 0);
948 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
950 writel(1, port_mmio + PORT_CMD_ISSUE);
951 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
953 /* spec mandates ">= 2ms" before checking status.
954 * We wait 150ms, because that was the magic delay used for
955 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
956 * between when the ATA command register is written, and then
957 * status is checked. Because waiting for "a while" before
958 * checking status is fine, post SRST, we perform this magic
959 * delay here as well.
963 *class = ATA_DEV_NONE;
964 if (sata_dev_present(ap)) {
965 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
967 reason = "device not ready";
970 *class = ahci_dev_classify(ap);
973 DPRINTK("EXIT, class=%u\n", *class);
977 ahci_start_engine(port_mmio);
980 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
983 DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc, reason);
987 static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
990 void __iomem *mmio = ap->host_set->mmio_base;
991 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
996 ahci_stop_engine(port_mmio);
997 rc = sata_std_hardreset(ap, verbose, class);
998 ahci_start_engine(port_mmio);
1001 *class = ahci_dev_classify(ap);
1002 if (*class == ATA_DEV_UNKNOWN)
1003 *class = ATA_DEV_NONE;
1005 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1009 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1011 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1012 struct ahci_host_priv *hpriv = ap->host_set->private_data;
1015 ata_std_postreset(ap, class);
1017 /* Make sure port's ATAPI bit is set appropriately */
1018 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1019 if (*class == ATA_DEV_ATAPI)
1020 new_tmp |= PORT_CMD_ATAPI;
1022 new_tmp &= ~PORT_CMD_ATAPI;
1023 if (new_tmp != tmp) {
1024 writel(new_tmp, port_mmio + PORT_CMD);
1025 readl(port_mmio + PORT_CMD); /* flush */
1028 if (*class != ATA_DEV_NONE)
1029 hpriv->dev_map |= (1 << ap->port_no);
1032 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
1034 return ata_drive_probe_reset(ap, ata_std_probeinit,
1035 ahci_softreset, ahci_hardreset,
1036 ahci_postreset, classes);
1039 static u8 ahci_check_status(struct ata_port *ap)
1041 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1043 return readl(mmio + PORT_TFDATA) & 0xFF;
1046 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1048 struct ahci_port_priv *pp = ap->private_data;
1049 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1051 ata_tf_from_fis(d2h_fis, tf);
1054 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
1056 struct ahci_port_priv *pp = qc->ap->private_data;
1057 struct scatterlist *sg;
1058 struct ahci_sg *ahci_sg;
1059 unsigned int n_sg = 0;
1064 * Next, the S/G list.
1066 ahci_sg = pp->cmd_tbl_sg;
1067 ata_for_each_sg(sg, qc) {
1068 dma_addr_t addr = sg_dma_address(sg);
1069 u32 sg_len = sg_dma_len(sg);
1071 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1072 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1073 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1082 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1084 struct ata_port *ap = qc->ap;
1085 struct ahci_port_priv *pp = ap->private_data;
1086 int is_atapi = is_atapi_taskfile(&qc->tf);
1088 const u32 cmd_fis_len = 5; /* five dwords */
1089 unsigned int n_elem;
1092 * Fill in command table information. First, the header,
1093 * a SATA Register - Host to Device command FIS.
1095 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
1097 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1098 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
1103 if (qc->flags & ATA_QCFLAG_DMAMAP)
1104 n_elem = ahci_fill_sg(qc);
1107 * Fill in command slot information.
1109 opts = cmd_fis_len | n_elem << 16;
1110 if (qc->tf.flags & ATA_TFLAG_WRITE)
1111 opts |= AHCI_CMD_WRITE;
1113 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1115 ahci_fill_cmd_slot(pp, opts);
1118 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
1120 void __iomem *mmio = ap->host_set->mmio_base;
1121 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1124 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
1125 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
1126 printk(KERN_WARNING "ata%u: port reset, "
1127 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
1130 readl(mmio + HOST_IRQ_STAT),
1131 readl(port_mmio + PORT_IRQ_STAT),
1132 readl(port_mmio + PORT_CMD),
1133 readl(port_mmio + PORT_TFDATA),
1134 readl(port_mmio + PORT_SCR_STAT),
1135 readl(port_mmio + PORT_SCR_ERR));
1138 ahci_stop_engine(port_mmio);
1140 /* clear SATA phy error, if any */
1141 tmp = readl(port_mmio + PORT_SCR_ERR);
1142 writel(tmp, port_mmio + PORT_SCR_ERR);
1144 /* if DRQ/BSY is set, device needs to be reset.
1145 * if so, issue COMRESET
1147 tmp = readl(port_mmio + PORT_TFDATA);
1148 if (tmp & (ATA_BUSY | ATA_DRQ)) {
1149 writel(0x301, port_mmio + PORT_SCR_CTL);
1150 readl(port_mmio + PORT_SCR_CTL); /* flush */
1152 writel(0x300, port_mmio + PORT_SCR_CTL);
1153 readl(port_mmio + PORT_SCR_CTL); /* flush */
1157 ahci_start_engine(port_mmio);
1160 static void ahci_eng_timeout(struct ata_port *ap)
1162 struct ata_host_set *host_set = ap->host_set;
1163 void __iomem *mmio = host_set->mmio_base;
1164 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1165 struct ata_queued_cmd *qc;
1166 unsigned long flags;
1168 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
1170 spin_lock_irqsave(&host_set->lock, flags);
1172 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
1173 qc = ata_qc_from_tag(ap, ap->active_tag);
1174 qc->err_mask |= AC_ERR_TIMEOUT;
1176 spin_unlock_irqrestore(&host_set->lock, flags);
1178 ata_eh_qc_complete(qc);
1181 int ahci_scsi_device_suspend(struct scsi_device *sdev, pm_message_t state)
1183 struct ata_port *ap = (struct ata_port *) &sdev->host->hostdata[0];
1184 struct ata_device *dev = &ap->device[sdev->id];
1187 rc = ata_device_suspend(ap, dev, state);
1190 rc = ahci_port_suspend(ap, state);
1195 int ahci_scsi_device_resume(struct scsi_device *sdev)
1197 struct ata_port *ap = (struct ata_port *) &sdev->host->hostdata[0];
1198 struct ata_device *dev = &ap->device[sdev->id];
1200 ahci_port_resume(ap);
1202 return ata_device_resume(ap, dev);
1205 int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
1207 struct device *dev = pci_dev_to_dev(pdev);
1208 struct ata_host_set *host_set = dev_get_drvdata(dev);
1209 void __iomem *mmio = host_set->mmio_base;
1213 * AHCI spec rev1.1 section 8.3.3:
1214 * Software must disable interrupts prior to
1215 * requesting a transition of the HBA to
1218 tmp = readl(mmio + HOST_CTL);
1219 tmp &= ~HOST_IRQ_EN;
1220 writel(tmp, mmio + HOST_CTL);
1221 tmp = readl(mmio + HOST_CTL); /* flush */
1223 return ata_pci_device_suspend(pdev, state);
1226 int ahci_pci_device_resume(struct pci_dev *pdev)
1228 struct device *dev = pci_dev_to_dev(pdev);
1229 struct ata_host_set *host_set = dev_get_drvdata(dev);
1230 void __iomem *mmio = host_set->mmio_base;
1234 * Enabling AHCI mode
1236 tmp = readl(mmio + HOST_CTL);
1237 if (!(tmp & HOST_AHCI_EN)) {
1238 tmp |= HOST_AHCI_EN;
1239 writel(tmp, mmio + HOST_CTL);
1240 tmp = readl(mmio + HOST_CTL);
1243 return ata_pci_device_resume(pdev);
1246 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1248 void __iomem *mmio = ap->host_set->mmio_base;
1249 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1250 u32 status, serr, ci;
1252 serr = readl(port_mmio + PORT_SCR_ERR);
1253 writel(serr, port_mmio + PORT_SCR_ERR);
1255 status = readl(port_mmio + PORT_IRQ_STAT);
1256 writel(status, port_mmio + PORT_IRQ_STAT);
1258 ci = readl(port_mmio + PORT_CMD_ISSUE);
1259 if (likely((ci & 0x1) == 0)) {
1261 WARN_ON(qc->err_mask);
1262 ata_qc_complete(qc);
1267 if (status & PORT_IRQ_FATAL) {
1268 unsigned int err_mask;
1269 if (status & PORT_IRQ_TF_ERR)
1270 err_mask = AC_ERR_DEV;
1271 else if (status & PORT_IRQ_IF_ERR)
1272 err_mask = AC_ERR_ATA_BUS;
1274 err_mask = AC_ERR_HOST_BUS;
1276 /* command processing has stopped due to error; restart */
1277 ahci_restart_port(ap, status);
1280 qc->err_mask |= err_mask;
1281 ata_qc_complete(qc);
1288 static void ahci_irq_clear(struct ata_port *ap)
1293 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1295 struct ata_host_set *host_set = dev_instance;
1296 struct ahci_host_priv *hpriv;
1297 unsigned int i, handled = 0;
1299 u32 irq_stat, irq_ack = 0;
1303 hpriv = host_set->private_data;
1304 mmio = host_set->mmio_base;
1306 /* sigh. 0xffffffff is a valid return from h/w */
1307 irq_stat = readl(mmio + HOST_IRQ_STAT);
1308 irq_stat &= hpriv->port_map;
1312 spin_lock(&host_set->lock);
1314 for (i = 0; i < host_set->n_ports; i++) {
1315 struct ata_port *ap;
1317 if (!(irq_stat & (1 << i)))
1320 ap = host_set->ports[i];
1322 struct ata_queued_cmd *qc;
1323 qc = ata_qc_from_tag(ap, ap->active_tag);
1324 if (!ahci_host_intr(ap, qc))
1325 if (ata_ratelimit())
1326 dev_printk(KERN_WARNING, host_set->dev,
1327 "unhandled interrupt on port %u\n",
1330 VPRINTK("port %u\n", i);
1332 VPRINTK("port %u (no irq)\n", i);
1333 if (ata_ratelimit())
1334 dev_printk(KERN_WARNING, host_set->dev,
1335 "interrupt on disabled port %u\n", i);
1338 irq_ack |= (1 << i);
1342 writel(irq_ack, mmio + HOST_IRQ_STAT);
1346 spin_unlock(&host_set->lock);
1350 return IRQ_RETVAL(handled);
1353 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1355 struct ata_port *ap = qc->ap;
1356 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1358 writel(1, port_mmio + PORT_CMD_ISSUE);
1359 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1364 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1365 unsigned int port_idx)
1367 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1368 base = ahci_port_base_ul(base, port_idx);
1369 VPRINTK("base now==0x%lx\n", base);
1371 port->cmd_addr = base;
1372 port->scr_addr = base + PORT_SCR;
1377 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1379 struct ahci_host_priv *hpriv = probe_ent->private_data;
1380 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1381 void __iomem *mmio = probe_ent->mmio_base;
1383 unsigned int i, j, using_dac;
1385 void __iomem *port_mmio;
1387 cap_save = readl(mmio + HOST_CAP);
1388 cap_save &= ( (1<<28) | (1<<17) );
1389 cap_save |= (1 << 27);
1391 /* global controller reset */
1392 tmp = readl(mmio + HOST_CTL);
1393 if ((tmp & HOST_RESET) == 0) {
1394 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1395 readl(mmio + HOST_CTL); /* flush */
1398 /* reset must complete within 1 second, or
1399 * the hardware should be considered fried.
1403 tmp = readl(mmio + HOST_CTL);
1404 if (tmp & HOST_RESET) {
1405 dev_printk(KERN_ERR, &pdev->dev,
1406 "controller reset failed (0x%x)\n", tmp);
1410 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1411 (void) readl(mmio + HOST_CTL); /* flush */
1412 writel(cap_save, mmio + HOST_CAP);
1413 writel(0xf, mmio + HOST_PORTS_IMPL);
1414 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1416 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1419 pci_read_config_word(pdev, 0x92, &tmp16);
1421 pci_write_config_word(pdev, 0x92, tmp16);
1424 hpriv->cap = readl(mmio + HOST_CAP);
1425 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1427 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1429 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1430 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1432 using_dac = hpriv->cap & HOST_CAP_64;
1434 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1435 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1437 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1439 dev_printk(KERN_ERR, &pdev->dev,
1440 "64-bit DMA enable failed\n");
1445 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1447 dev_printk(KERN_ERR, &pdev->dev,
1448 "32-bit DMA enable failed\n");
1451 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1453 dev_printk(KERN_ERR, &pdev->dev,
1454 "32-bit consistent DMA enable failed\n");
1459 for (i = 0; i < probe_ent->n_ports; i++) {
1460 #if 0 /* BIOSen initialize this incorrectly */
1461 if (!(hpriv->port_map & (1 << i)))
1465 port_mmio = ahci_port_base(mmio, i);
1466 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1468 ahci_setup_port(&probe_ent->port[i],
1469 (unsigned long) mmio, i);
1471 /* make sure port is not active */
1472 rc = ahci_stop_engine(port_mmio);
1474 printk(KERN_WARNING "ata%u: DMA engine busy (rc %d)\n",
1477 rc = ahci_stop_fis_rx(port_mmio);
1479 printk(KERN_WARNING "ata%u: FIS RX not stopped (rc %d)\n",
1483 * Actually, this is wrong again.
1484 * AHCI spec says that we first should
1485 * enable FIS reception before sending
1486 * SPIN_UP to the device ...
1489 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1492 * Wait for the communications link to establish
1498 tmp = readl(port_mmio + PORT_SCR_STAT);
1499 if ((tmp & 0xf) == 0x3)
1504 tmp = readl(port_mmio + PORT_SCR_ERR);
1505 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1506 writel(tmp, port_mmio + PORT_SCR_ERR);
1508 /* ack any pending irq events for this port */
1509 tmp = readl(port_mmio + PORT_IRQ_STAT);
1510 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1512 writel(tmp, port_mmio + PORT_IRQ_STAT);
1514 writel(1 << i, mmio + HOST_IRQ_STAT);
1516 /* set irq mask (enables interrupts) */
1517 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1520 tmp = readl(mmio + HOST_CTL);
1521 VPRINTK("HOST_CTL 0x%x\n", tmp);
1522 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1523 tmp = readl(mmio + HOST_CTL);
1524 VPRINTK("HOST_CTL 0x%x\n", tmp);
1526 pci_set_master(pdev);
1531 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1533 struct ahci_host_priv *hpriv = probe_ent->private_data;
1534 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1535 void __iomem *mmio = probe_ent->mmio_base;
1536 u32 vers, cap, impl, speed;
1537 const char *speed_s;
1541 vers = readl(mmio + HOST_VERSION);
1543 impl = hpriv->port_map;
1545 speed = (cap >> 20) & 0xf;
1548 else if (speed == 2)
1553 pci_read_config_word(pdev, 0x0a, &cc);
1556 else if (cc == 0x0106)
1558 else if (cc == 0x0104)
1563 dev_printk(KERN_INFO, &pdev->dev,
1564 "AHCI %02x%02x.%02x%02x "
1565 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1568 (vers >> 24) & 0xff,
1569 (vers >> 16) & 0xff,
1573 ((cap >> 8) & 0x1f) + 1,
1579 dev_printk(KERN_INFO, &pdev->dev,
1585 cap & (1 << 31) ? "64bit " : "",
1586 cap & (1 << 30) ? "ncq " : "",
1587 cap & (1 << 28) ? "ilck " : "",
1588 cap & (1 << 27) ? "stag " : "",
1589 cap & (1 << 26) ? "pm " : "",
1590 cap & (1 << 25) ? "led " : "",
1592 cap & (1 << 24) ? "clo " : "",
1593 cap & (1 << 19) ? "nz " : "",
1594 cap & (1 << 18) ? "only " : "",
1595 cap & (1 << 17) ? "pmp " : "",
1596 cap & (1 << 15) ? "pio " : "",
1597 cap & (1 << 14) ? "slum " : "",
1598 cap & (1 << 13) ? "part " : ""
1602 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1604 static int printed_version;
1605 struct ata_probe_ent *probe_ent = NULL;
1606 struct ahci_host_priv *hpriv;
1608 void __iomem *mmio_base;
1609 unsigned int board_idx = (unsigned int) ent->driver_data;
1610 int have_msi, pci_dev_busy = 0;
1615 if (!printed_version++)
1616 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1618 rc = pci_enable_device(pdev);
1622 rc = pci_request_regions(pdev, DRV_NAME);
1628 if (pci_enable_msi(pdev) == 0)
1635 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1636 if (probe_ent == NULL) {
1641 memset(probe_ent, 0, sizeof(*probe_ent));
1642 probe_ent->dev = pci_dev_to_dev(pdev);
1643 INIT_LIST_HEAD(&probe_ent->node);
1645 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1646 if (mmio_base == NULL) {
1648 goto err_out_free_ent;
1650 base = (unsigned long) mmio_base;
1652 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1655 goto err_out_iounmap;
1657 memset(hpriv, 0, sizeof(*hpriv));
1659 probe_ent->sht = ahci_port_info[board_idx].sht;
1660 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1661 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1662 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1663 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1665 probe_ent->irq = pdev->irq;
1666 probe_ent->irq_flags = SA_SHIRQ;
1667 probe_ent->mmio_base = mmio_base;
1668 probe_ent->private_data = hpriv;
1671 hpriv->flags |= AHCI_FLAG_MSI;
1673 /* JMicron-specific fixup: make sure we're in AHCI mode */
1674 if (pdev->vendor == 0x197b)
1675 pci_write_config_byte(pdev, 0x41, 0xa1);
1677 /* initialize adapter */
1678 rc = ahci_host_init(probe_ent);
1682 ahci_print_info(probe_ent);
1684 /* FIXME: check ata_device_add return value */
1685 ata_device_add(probe_ent);
1693 pci_iounmap(pdev, mmio_base);
1698 pci_disable_msi(pdev);
1701 pci_release_regions(pdev);
1704 pci_disable_device(pdev);
1708 static void ahci_remove_one (struct pci_dev *pdev)
1710 struct device *dev = pci_dev_to_dev(pdev);
1711 struct ata_host_set *host_set = dev_get_drvdata(dev);
1712 struct ahci_host_priv *hpriv = host_set->private_data;
1713 struct ata_port *ap;
1717 for (i = 0; i < host_set->n_ports; i++) {
1718 ap = host_set->ports[i];
1720 scsi_remove_host(ap->host);
1723 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1724 free_irq(host_set->irq, host_set);
1726 for (i = 0; i < host_set->n_ports; i++) {
1727 ap = host_set->ports[i];
1729 ata_scsi_release(ap->host);
1730 scsi_host_put(ap->host);
1734 pci_iounmap(pdev, host_set->mmio_base);
1738 pci_disable_msi(pdev);
1741 pci_release_regions(pdev);
1742 pci_disable_device(pdev);
1743 dev_set_drvdata(dev, NULL);
1746 static int __init ahci_init(void)
1748 return pci_module_init(&ahci_pci_driver);
1751 static void __exit ahci_exit(void)
1753 pci_unregister_driver(&ahci_pci_driver);
1757 MODULE_AUTHOR("Jeff Garzik");
1758 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1759 MODULE_LICENSE("GPL");
1760 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1761 MODULE_VERSION(DRV_VERSION);
1763 module_init(ahci_init);
1764 module_exit(ahci_exit);