2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
48 #include "aic7xxx_osm.h"
49 #include "aic7xxx_inline.h"
50 #include "aic7xxx_93cx6.h"
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aic7xxx_93cx6.h>
57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
60 static __inline uint64_t
61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
67 | ((uint64_t)vendor << 32)
68 | ((uint64_t)device << 48);
73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
77 #define ID_9005_SISL_ID 0x0005900500000000ull
78 #define ID_AIC7850 0x5078900400000000ull
79 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
80 #define ID_AIC7855 0x5578900400000000ull
81 #define ID_AIC7859 0x3860900400000000ull
82 #define ID_AHA_2930CU 0x3860900438699004ull
83 #define ID_AIC7860 0x6078900400000000ull
84 #define ID_AIC7860C 0x6078900478609004ull
85 #define ID_AHA_1480A 0x6075900400000000ull
86 #define ID_AHA_2940AU_0 0x6178900400000000ull
87 #define ID_AHA_2940AU_1 0x6178900478619004ull
88 #define ID_AHA_2940AU_CN 0x2178900478219004ull
89 #define ID_AHA_2930C_VAR 0x6038900438689004ull
91 #define ID_AIC7870 0x7078900400000000ull
92 #define ID_AHA_2940 0x7178900400000000ull
93 #define ID_AHA_3940 0x7278900400000000ull
94 #define ID_AHA_398X 0x7378900400000000ull
95 #define ID_AHA_2944 0x7478900400000000ull
96 #define ID_AHA_3944 0x7578900400000000ull
97 #define ID_AHA_4944 0x7678900400000000ull
99 #define ID_AIC7880 0x8078900400000000ull
100 #define ID_AIC7880_B 0x8078900478809004ull
101 #define ID_AHA_2940U 0x8178900400000000ull
102 #define ID_AHA_3940U 0x8278900400000000ull
103 #define ID_AHA_2944U 0x8478900400000000ull
104 #define ID_AHA_3944U 0x8578900400000000ull
105 #define ID_AHA_398XU 0x8378900400000000ull
106 #define ID_AHA_4944U 0x8678900400000000ull
107 #define ID_AHA_2940UB 0x8178900478819004ull
108 #define ID_AHA_2930U 0x8878900478889004ull
109 #define ID_AHA_2940U_PRO 0x8778900478879004ull
110 #define ID_AHA_2940U_CN 0x0078900478009004ull
112 #define ID_AIC7895 0x7895900478959004ull
113 #define ID_AIC7895_ARO 0x7890900478939004ull
114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
116 #define ID_AHA_3940AU 0x7895900478929004ull
117 #define ID_AHA_3944AU 0x7895900478949004ull
119 #define ID_AIC7890 0x001F9005000F9005ull
120 #define ID_AIC7890_ARO 0x00139005000F9005ull
121 #define ID_AAA_131U2 0x0013900500039005ull
122 #define ID_AHA_2930U2 0x0011900501819005ull
123 #define ID_AHA_2940U2B 0x00109005A1009005ull
124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
125 #define ID_AHA_2940U2 0x00109005A1809005ull
126 #define ID_AHA_2950U2B 0x00109005E1009005ull
128 #define ID_AIC7892 0x008F9005FFFF9005ull
129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
130 #define ID_AHA_29160 0x00809005E2A09005ull
131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
132 #define ID_AHA_29160N 0x0080900562A09005ull
133 #define ID_AHA_29160C 0x0080900562209005ull
134 #define ID_AHA_29160B 0x00809005E2209005ull
135 #define ID_AHA_19160B 0x0081900562A19005ull
137 #define ID_AIC7896 0x005F9005FFFF9005ull
138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
144 #define ID_AIC7899 0x00CF9005FFFF9005ull
145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
146 #define ID_AHA_3960D 0x00C09005F6209005ull
147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
149 #define ID_AIC7810 0x1078900400000000ull
150 #define ID_AIC7815 0x7815900400000000ull
152 #define DEVID_9005_TYPE(id) ((id) & 0xF)
153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
159 #define DEVID_9005_MAXRATE_U160 0x0
160 #define DEVID_9005_MAXRATE_ULTRA2 0x1
161 #define DEVID_9005_MAXRATE_ULTRA 0x2
162 #define DEVID_9005_MAXRATE_FAST 0x3
164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
169 #define SUBID_9005_TYPE(id) ((id) & 0xF)
170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
175 #define SUBID_9005_TYPE_KNOWN(id) \
176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
182 #define SUBID_9005_MAXRATE_ULTRA2 0x0
183 #define SUBID_9005_MAXRATE_ULTRA 0x1
184 #define SUBID_9005_MAXRATE_U160 0x2
185 #define SUBID_9005_MAXRATE_RESERVED 0x3
187 #define SUBID_9005_SEEPTYPE(id) \
188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
189 ? ((id) & 0xC0) >> 6 \
190 : ((id) & 0x300) >> 8)
191 #define SUBID_9005_SEEPTYPE_NONE 0x0
192 #define SUBID_9005_SEEPTYPE_1K 0x1
193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
195 #define SUBID_9005_AUTOTERM(id) \
196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
197 ? (((id) & 0x400) >> 10) == 0 \
198 : (((id) & 0x40) >> 6) == 0)
200 #define SUBID_9005_NUMCHAN(id) \
201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
202 ? ((id) & 0x300) >> 8 \
203 : ((id) & 0xC00) >> 10)
205 #define SUBID_9005_LEGACYCONN(id) \
206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
208 : ((id) & 0x80) >> 7)
210 #define SUBID_9005_MFUNCENB(id) \
211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
212 ? ((id) & 0x800) >> 11 \
213 : ((id) & 0x1000) >> 12)
215 * Informational only. Should use chip register to be
216 * certain, but may be use in identification strings.
218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
222 static ahc_device_setup_t ahc_aic785X_setup;
223 static ahc_device_setup_t ahc_aic7860_setup;
224 static ahc_device_setup_t ahc_apa1480_setup;
225 static ahc_device_setup_t ahc_aic7870_setup;
226 static ahc_device_setup_t ahc_aha394X_setup;
227 static ahc_device_setup_t ahc_aha494X_setup;
228 static ahc_device_setup_t ahc_aha398X_setup;
229 static ahc_device_setup_t ahc_aic7880_setup;
230 static ahc_device_setup_t ahc_aha2940Pro_setup;
231 static ahc_device_setup_t ahc_aha394XU_setup;
232 static ahc_device_setup_t ahc_aha398XU_setup;
233 static ahc_device_setup_t ahc_aic7890_setup;
234 static ahc_device_setup_t ahc_aic7892_setup;
235 static ahc_device_setup_t ahc_aic7895_setup;
236 static ahc_device_setup_t ahc_aic7896_setup;
237 static ahc_device_setup_t ahc_aic7899_setup;
238 static ahc_device_setup_t ahc_aha29160C_setup;
239 static ahc_device_setup_t ahc_raid_setup;
240 static ahc_device_setup_t ahc_aha394XX_setup;
241 static ahc_device_setup_t ahc_aha494XX_setup;
242 static ahc_device_setup_t ahc_aha398XX_setup;
244 struct ahc_pci_identity ahc_pci_ident_table [] =
246 /* aic7850 based controllers */
248 ID_AHA_2902_04_10_15_20C_30C,
250 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
253 /* aic7860 based controllers */
257 "Adaptec 2930CU SCSI adapter",
261 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
263 "Adaptec 1480A Ultra SCSI adapter",
267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
269 "Adaptec 2940A Ultra SCSI adapter",
273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
275 "Adaptec 2940A/CN Ultra SCSI adapter",
279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
281 "Adaptec 2930C Ultra SCSI adapter (VAR)",
284 /* aic7870 based controllers */
288 "Adaptec 2940 SCSI adapter",
294 "Adaptec 3940 SCSI adapter",
300 "Adaptec 398X SCSI RAID adapter",
306 "Adaptec 2944 SCSI adapter",
312 "Adaptec 3944 SCSI adapter",
318 "Adaptec 4944 SCSI adapter",
321 /* aic7880 based controllers */
323 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
325 "Adaptec 2940 Ultra SCSI adapter",
329 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
331 "Adaptec 3940 Ultra SCSI adapter",
335 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
337 "Adaptec 2944 Ultra SCSI adapter",
341 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
343 "Adaptec 3944 Ultra SCSI adapter",
347 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
349 "Adaptec 398X Ultra SCSI RAID adapter",
354 * XXX Don't know the slot numbers
355 * so we can't identify channels
357 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
359 "Adaptec 4944 Ultra SCSI adapter",
363 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
365 "Adaptec 2930 Ultra SCSI adapter",
369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
371 "Adaptec 2940 Pro Ultra SCSI adapter",
375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
377 "Adaptec 2940/CN Ultra SCSI adapter",
380 /* Ignore all SISL (AAC on MB) based controllers. */
387 /* aic7890 based controllers */
391 "Adaptec 2930 Ultra2 SCSI adapter",
397 "Adaptec 2940B Ultra2 SCSI adapter",
403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
409 "Adaptec 2940 Ultra2 SCSI adapter",
415 "Adaptec 2950 Ultra2 SCSI adapter",
421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
427 "Adaptec AAA-131 Ultra2 RAID adapter",
430 /* aic7892 based controllers */
434 "Adaptec 29160 Ultra160 SCSI adapter",
440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
446 "Adaptec 29160N Ultra160 SCSI adapter",
452 "Adaptec 29160C Ultra160 SCSI adapter",
458 "Adaptec 29160B Ultra160 SCSI adapter",
464 "Adaptec 19160B Ultra160 SCSI adapter",
470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
473 /* aic7895 based controllers */
477 "Adaptec 2940/DUAL Ultra SCSI adapter",
483 "Adaptec 3940A Ultra SCSI adapter",
489 "Adaptec 3944A Ultra SCSI adapter",
495 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
498 /* aic7896/97 based controllers */
502 "Adaptec 3950B Ultra2 SCSI adapter",
508 "Adaptec 3950B Ultra2 SCSI adapter",
514 "Adaptec 3950D Ultra2 SCSI adapter",
520 "Adaptec 3950D Ultra2 SCSI adapter",
526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
529 /* aic7899 based controllers */
533 "Adaptec 3960D Ultra160 SCSI adapter",
539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
548 /* Generic chip probes for devices we don't know 'exactly' */
550 ID_AIC7850 & ID_DEV_VENDOR_MASK,
552 "Adaptec aic7850 SCSI adapter",
556 ID_AIC7855 & ID_DEV_VENDOR_MASK,
558 "Adaptec aic7855 SCSI adapter",
562 ID_AIC7859 & ID_DEV_VENDOR_MASK,
564 "Adaptec aic7859 SCSI adapter",
568 ID_AIC7860 & ID_DEV_VENDOR_MASK,
570 "Adaptec aic7860 Ultra SCSI adapter",
574 ID_AIC7870 & ID_DEV_VENDOR_MASK,
576 "Adaptec aic7870 SCSI adapter",
580 ID_AIC7880 & ID_DEV_VENDOR_MASK,
582 "Adaptec aic7880 Ultra SCSI adapter",
586 ID_AIC7890 & ID_9005_GENERIC_MASK,
587 ID_9005_GENERIC_MASK,
588 "Adaptec aic7890/91 Ultra2 SCSI adapter",
592 ID_AIC7892 & ID_9005_GENERIC_MASK,
593 ID_9005_GENERIC_MASK,
594 "Adaptec aic7892 Ultra160 SCSI adapter",
598 ID_AIC7895 & ID_DEV_VENDOR_MASK,
600 "Adaptec aic7895 Ultra SCSI adapter",
604 ID_AIC7896 & ID_9005_GENERIC_MASK,
605 ID_9005_GENERIC_MASK,
606 "Adaptec aic7896/97 Ultra2 SCSI adapter",
610 ID_AIC7899 & ID_9005_GENERIC_MASK,
611 ID_9005_GENERIC_MASK,
612 "Adaptec aic7899 Ultra160 SCSI adapter",
616 ID_AIC7810 & ID_DEV_VENDOR_MASK,
618 "Adaptec aic7810 RAID memory controller",
622 ID_AIC7815 & ID_DEV_VENDOR_MASK,
624 "Adaptec aic7815 RAID memory controller",
629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
631 #define AHC_394X_SLOT_CHANNEL_A 4
632 #define AHC_394X_SLOT_CHANNEL_B 5
634 #define AHC_398X_SLOT_CHANNEL_A 4
635 #define AHC_398X_SLOT_CHANNEL_B 8
636 #define AHC_398X_SLOT_CHANNEL_C 12
638 #define AHC_494X_SLOT_CHANNEL_A 4
639 #define AHC_494X_SLOT_CHANNEL_B 5
640 #define AHC_494X_SLOT_CHANNEL_C 6
641 #define AHC_494X_SLOT_CHANNEL_D 7
643 #define DEVCONFIG 0x40
644 #define PCIERRGENDIS 0x80000000ul
645 #define SCBSIZE32 0x00010000ul /* aic789X only */
646 #define REXTVALID 0x00001000ul /* ultra cards only */
647 #define MPORTMODE 0x00000400ul /* aic7870+ only */
648 #define RAMPSM 0x00000200ul /* aic7870+ only */
649 #define VOLSENSE 0x00000100ul
650 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
651 #define SCBRAMSEL 0x00000080ul
652 #define MRDCEN 0x00000040ul
653 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
654 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
655 #define BERREN 0x00000008ul
656 #define DACEN 0x00000004ul
657 #define STPWLEVEL 0x00000002ul
658 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
660 #define CSIZE_LATTIME 0x0c
661 #define CACHESIZE 0x0000003ful /* only 5 bits */
662 #define LATTIME 0x0000ff00ul
664 /* PCI STATUS definitions */
672 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
673 uint16_t subvendor, uint16_t subdevice);
674 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
675 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
676 int pcheck, int fast, int large);
677 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
678 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
679 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
680 struct seeprom_config *sc);
681 static void configure_termination(struct ahc_softc *ahc,
682 struct seeprom_descriptor *sd,
683 u_int adapter_control,
686 static void ahc_new_term_detect(struct ahc_softc *ahc,
691 int *eeprom_present);
692 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
693 int *internal68_present,
694 int *externalcable_present,
695 int *eeprom_present);
696 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
697 int *externalcable_present,
698 int *eeprom_present);
699 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
700 static uint8_t read_brdctl(struct ahc_softc *ahc);
701 static void ahc_pci_intr(struct ahc_softc *ahc);
702 static int ahc_pci_chip_init(struct ahc_softc *ahc);
703 static int ahc_pci_suspend(struct ahc_softc *ahc);
704 static int ahc_pci_resume(struct ahc_softc *ahc);
707 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
708 uint16_t subdevice, uint16_t subvendor)
712 /* Default to invalid. */
715 && subvendor == 0x9005
716 && subdevice != device
717 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
719 switch (SUBID_9005_TYPE(subdevice)) {
720 case SUBID_9005_TYPE_MB:
722 case SUBID_9005_TYPE_CARD:
723 case SUBID_9005_TYPE_LCCARD:
725 * Currently only trust Adaptec cards to
726 * get the sub device info correct.
728 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
731 case SUBID_9005_TYPE_RAID:
740 struct ahc_pci_identity *
741 ahc_find_pci_device(ahc_dev_softc_t pci)
748 struct ahc_pci_identity *entry;
751 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
752 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
753 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
754 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
755 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
758 * If the second function is not hooked up, ignore it.
759 * Unfortunately, not all MB vendors implement the
760 * subdevice ID as per the Adaptec spec, so do our best
761 * to sanity check it prior to accepting the subdevice
764 if (ahc_get_pci_function(pci) > 0
765 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
766 && SUBID_9005_MFUNCENB(subdevice) == 0)
769 for (i = 0; i < ahc_num_pci_devs; i++) {
770 entry = &ahc_pci_ident_table[i];
771 if (entry->full_id == (full_id & entry->id_mask)) {
772 /* Honor exclusion entries. */
773 if (entry->name == NULL)
782 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
795 error = entry->setup(ahc);
798 ahc->chip |= AHC_PCI;
799 ahc->description = entry->name;
801 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
803 error = ahc_pci_map_registers(ahc);
808 * Before we continue probing the card, ensure that
809 * its interrupts are *disabled*. We don't want
810 * a misstep to hang the machine in an interrupt
813 ahc_intr_enable(ahc, FALSE);
815 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
818 * If we need to support high memory, enable dual
819 * address cycles. This bit must be set to enable
820 * high address bit generation even if we are on a
821 * 64bit bus (PCI64BIT set in devconfig).
823 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
826 printf("%s: Enabling 39Bit Addressing\n",
831 /* Ensure that pci error generation, a test feature, is disabled. */
832 devconfig |= PCIERRGENDIS;
834 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
836 /* Ensure busmastering is enabled */
837 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
838 command |= PCIM_CMD_BUSMASTEREN;
840 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
842 /* On all PCI adapters, we allow SCB paging */
843 ahc->flags |= AHC_PAGESCBS;
845 error = ahc_softc_init(ahc);
850 * Disable PCI parity error checking. Users typically
851 * do this to work around broken PCI chipsets that get
852 * the parity timing wrong and thus generate lots of spurious
853 * errors. The chip only allows us to disable *all* parity
854 * error reporting when doing this, so CIO bus, scb ram, and
855 * scratch ram parity errors will be ignored too.
857 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
858 ahc->seqctl |= FAILDIS;
860 ahc->bus_intr = ahc_pci_intr;
861 ahc->bus_chip_init = ahc_pci_chip_init;
862 ahc->bus_suspend = ahc_pci_suspend;
863 ahc->bus_resume = ahc_pci_resume;
865 /* Remeber how the card was setup in case there is no SEEPROM */
866 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
868 if ((ahc->features & AHC_ULTRA2) != 0)
869 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
871 our_id = ahc_inb(ahc, SCSIID) & OID;
872 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
873 scsiseq = ahc_inb(ahc, SCSISEQ);
880 error = ahc_reset(ahc, /*reinit*/FALSE);
884 if ((ahc->features & AHC_DT) != 0) {
887 /* Perform ALT-Mode Setup */
888 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
889 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
890 ahc_outb(ahc, OPTIONMODE,
891 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
892 ahc_outb(ahc, SFUNCT, sfunct);
894 /* Normal mode setup */
895 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
899 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
900 dscommand0 |= MPARCKEN|CACHETHEN;
901 if ((ahc->features & AHC_ULTRA2) != 0) {
904 * DPARCKEN doesn't work correctly on
905 * some MBs so don't use it.
907 dscommand0 &= ~DPARCKEN;
911 * Handle chips that must have cache line
912 * streaming (dis/en)abled.
914 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
915 dscommand0 |= CACHETHEN;
917 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
918 dscommand0 &= ~CACHETHEN;
920 ahc_outb(ahc, DSCOMMAND0, dscommand0);
923 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
924 /*bytes*/1) & CACHESIZE;
925 ahc->pci_cachesize *= 4;
927 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
928 && ahc->pci_cachesize == 4) {
930 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
932 ahc->pci_cachesize = 0;
936 * We cannot perform ULTRA speeds without the presense
937 * of the external precision resistor.
939 if ((ahc->features & AHC_ULTRA) != 0) {
942 devconfig = ahc_pci_read_config(ahc->dev_softc,
943 DEVCONFIG, /*bytes*/4);
944 if ((devconfig & REXTVALID) == 0)
945 ahc->features &= ~AHC_ULTRA;
948 /* See if we have a SEEPROM and perform auto-term */
949 check_extport(ahc, &sxfrctl1);
952 * Take the LED out of diagnostic mode
954 sblkctl = ahc_inb(ahc, SBLKCTL);
955 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
957 if ((ahc->features & AHC_ULTRA2) != 0) {
958 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
960 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
963 if (ahc->flags & AHC_USEDEFAULTS) {
965 * PCI Adapter default setup
966 * Should only be used if the adapter does not have
969 /* See if someone else set us up already */
970 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
972 printf("%s: Using left over BIOS settings\n",
974 ahc->flags &= ~AHC_USEDEFAULTS;
975 ahc->flags |= AHC_BIOS_ENABLED;
978 * Assume only one connector and always turn
984 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
986 ahc->our_id = our_id;
990 * Take a look to see if we have external SRAM.
991 * We currently do not attempt to use SRAM that is
992 * shared among multiple controllers.
994 ahc_probe_ext_scbram(ahc);
997 * Record our termination setting for the
998 * generic initialization routine.
1000 if ((sxfrctl1 & STPWEN) != 0)
1001 ahc->flags |= AHC_TERM_ENB_A;
1004 * Save chip register configuration data for chip resets
1005 * that occur during runtime and resume events.
1007 ahc->bus_softc.pci_softc.devconfig =
1008 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1009 ahc->bus_softc.pci_softc.command =
1010 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1011 ahc->bus_softc.pci_softc.csize_lattime =
1012 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1013 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1014 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1015 if ((ahc->features & AHC_DT) != 0) {
1018 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1019 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1020 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1021 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1022 ahc_outb(ahc, SFUNCT, sfunct);
1023 ahc->bus_softc.pci_softc.crccontrol1 =
1024 ahc_inb(ahc, CRCCONTROL1);
1026 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1027 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1029 if ((ahc->features & AHC_ULTRA2) != 0)
1030 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1032 /* Core initialization */
1033 error = ahc_init(ahc);
1038 * Allow interrupts now that we are completely setup.
1040 error = ahc_pci_map_int(ahc);
1046 * Link this softc in with all other ahc instances.
1048 ahc_softc_insert(ahc);
1049 ahc_list_unlock(&l);
1054 * Test for the presense of external sram in an
1055 * "unshared" configuration.
1058 ahc_ext_scbram_present(struct ahc_softc *ahc)
1065 chip = ahc->chip & AHC_CHIPID_MASK;
1066 devconfig = ahc_pci_read_config(ahc->dev_softc,
1067 DEVCONFIG, /*bytes*/4);
1068 single_user = (devconfig & MPORTMODE) != 0;
1070 if ((ahc->features & AHC_ULTRA2) != 0)
1071 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1072 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1074 * External SCBRAM arbitration is flakey
1075 * on these chips. Unfortunately this means
1076 * we don't use the extra SCB ram space on the
1080 else if (chip >= AHC_AIC7870)
1081 ramps = (devconfig & RAMPSM) != 0;
1085 if (ramps && single_user)
1091 * Enable external scbram.
1094 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1095 int fast, int large)
1099 if (ahc->features & AHC_MULTI_FUNC) {
1101 * Set the SCB Base addr (highest address bit)
1102 * depending on which channel we are.
1104 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1107 ahc->flags &= ~AHC_LSCBS_ENABLED;
1109 ahc->flags |= AHC_LSCBS_ENABLED;
1110 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1111 if ((ahc->features & AHC_ULTRA2) != 0) {
1114 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1116 dscommand0 &= ~INTSCBRAMSEL;
1118 dscommand0 |= INTSCBRAMSEL;
1120 dscommand0 &= ~USCBSIZE32;
1122 dscommand0 |= USCBSIZE32;
1123 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1126 devconfig &= ~EXTSCBTIME;
1128 devconfig |= EXTSCBTIME;
1130 devconfig &= ~SCBRAMSEL;
1132 devconfig |= SCBRAMSEL;
1134 devconfig &= ~SCBSIZE32;
1136 devconfig |= SCBSIZE32;
1139 devconfig |= EXTSCBPEN;
1141 devconfig &= ~EXTSCBPEN;
1143 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1147 * Take a look to see if we have external SRAM.
1148 * We currently do not attempt to use SRAM that is
1149 * shared among multiple controllers.
1152 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1167 if (ahc_ext_scbram_present(ahc) == 0)
1171 * Probe for the best parameters to use.
1173 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1174 num_scbs = ahc_probe_scbs(ahc);
1175 if (num_scbs == 0) {
1176 /* The SRAM wasn't really present. */
1182 * Clear any outstanding parity error
1183 * and ensure that parity error reporting
1186 ahc_outb(ahc, SEQCTL, 0);
1187 ahc_outb(ahc, CLRINT, CLRPARERR);
1188 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1190 /* Now see if we can do parity */
1191 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1192 num_scbs = ahc_probe_scbs(ahc);
1193 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1194 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1197 /* Clear any resulting parity error */
1198 ahc_outb(ahc, CLRINT, CLRPARERR);
1199 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1201 /* Now see if we can do fast timing */
1202 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1203 test_num_scbs = ahc_probe_scbs(ahc);
1204 if (test_num_scbs == num_scbs
1205 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1206 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1210 * See if we can use large SCBs and still maintain
1211 * the same overall count of SCBs.
1213 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1214 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1215 test_num_scbs = ahc_probe_scbs(ahc);
1216 if (test_num_scbs >= num_scbs) {
1218 num_scbs = test_num_scbs;
1219 if (num_scbs >= 64) {
1221 * We have enough space to move the
1222 * "busy targets table" into SCB space
1223 * and make it qualify all the way to the
1226 ahc->flags |= AHC_SCB_BTT;
1232 * Disable parity error reporting until we
1233 * can load instruction ram.
1235 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1236 /* Clear any latched parity error */
1237 ahc_outb(ahc, CLRINT, CLRPARERR);
1238 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1239 if (bootverbose && enable) {
1240 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1241 ahc_name(ahc), fast ? "fast" : "slow",
1242 pcheck ? ", parity checking enabled" : "",
1245 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1249 * Perform some simple tests that should catch situations where
1250 * our registers are invalidly mapped.
1253 ahc_pci_test_register_access(struct ahc_softc *ahc)
1263 * Enable PCI error interrupt status, but suppress NMIs
1264 * generated by SERR raised due to target aborts.
1266 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1267 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1268 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1271 * First a simple test to see if any
1272 * registers can be read. Reading
1273 * HCNTRL has no side effects and has
1274 * at least one bit that is guaranteed to
1275 * be zero so it is a good register to
1276 * use for this test.
1278 hcntrl = ahc_inb(ahc, HCNTRL);
1283 * Next create a situation where write combining
1284 * or read prefetching could be initiated by the
1285 * CPU or host bridge. Our device does not support
1286 * either, so look for data corruption and/or flagged
1287 * PCI errors. First pause without causing another
1291 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1292 while (ahc_is_paused(ahc) == 0)
1295 /* Clear any PCI errors that occurred before our driver attached. */
1296 status1 = ahc_pci_read_config(ahc->dev_softc,
1297 PCIR_STATUS + 1, /*bytes*/1);
1298 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1299 status1, /*bytes*/1);
1300 ahc_outb(ahc, CLRINT, CLRPARERR);
1302 ahc_outb(ahc, SEQCTL, PERRORDIS);
1303 ahc_outb(ahc, SCBPTR, 0);
1304 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1305 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1308 status1 = ahc_pci_read_config(ahc->dev_softc,
1309 PCIR_STATUS + 1, /*bytes*/1);
1310 if ((status1 & STA) != 0)
1316 /* Silently clear any latched errors. */
1317 status1 = ahc_pci_read_config(ahc->dev_softc,
1318 PCIR_STATUS + 1, /*bytes*/1);
1319 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1320 status1, /*bytes*/1);
1321 ahc_outb(ahc, CLRINT, CLRPARERR);
1322 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1323 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1328 * Check the external port logic for a serial eeprom
1329 * and termination/cable detection contrls.
1332 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1334 struct seeprom_descriptor sd;
1335 struct seeprom_config *sc;
1340 sd.sd_control_offset = SEECTL;
1341 sd.sd_status_offset = SEECTL;
1342 sd.sd_dataout_offset = SEECTL;
1343 sc = ahc->seep_config;
1346 * For some multi-channel devices, the c46 is simply too
1347 * small to work. For the other controller types, we can
1348 * get our information from either SEEPROM type. Set the
1349 * type to start our probe with accordingly.
1351 if (ahc->flags & AHC_LARGE_SEEPROM)
1352 sd.sd_chip = C56_66;
1363 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1367 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1372 start_addr = 32 * (ahc->channel - 'A');
1374 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1379 have_seeprom = ahc_verify_cksum(sc);
1381 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1383 if (have_seeprom == 0)
1384 printf ("checksum error\n");
1390 sd.sd_chip = C56_66;
1392 ahc_release_seeprom(&sd);
1395 if (!have_seeprom) {
1397 * Pull scratch ram settings and treat them as
1398 * if they are the contents of an seeprom if
1399 * the 'ADPT' signature is found in SCB2.
1400 * We manually compose the data as 16bit values
1401 * to avoid endian issues.
1403 ahc_outb(ahc, SCBPTR, 2);
1404 if (ahc_inb(ahc, SCB_BASE) == 'A'
1405 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1406 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1407 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1411 sc_data = (uint16_t *)sc;
1412 for (i = 0; i < 32; i++, sc_data++) {
1416 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1417 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1419 have_seeprom = ahc_verify_cksum(sc);
1421 ahc->flags |= AHC_SCB_CONFIG_USED;
1424 * Clear any SCB parity errors in case this data and
1425 * its associated parity was not initialized by the BIOS
1427 ahc_outb(ahc, CLRINT, CLRPARERR);
1428 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1431 if (!have_seeprom) {
1433 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1434 ahc->flags |= AHC_USEDEFAULTS;
1435 free(ahc->seep_config, M_DEVBUF);
1436 ahc->seep_config = NULL;
1439 ahc_parse_pci_eeprom(ahc, sc);
1443 * Cards that have the external logic necessary to talk to
1444 * a SEEPROM, are almost certain to have the remaining logic
1445 * necessary for auto-termination control. This assumption
1446 * hasn't failed yet...
1448 have_autoterm = have_seeprom;
1451 * Some low-cost chips have SEEPROM and auto-term control built
1452 * in, instead of using a GAL. They can tell us directly
1453 * if the termination logic is enabled.
1455 if ((ahc->features & AHC_SPIOCAP) != 0) {
1456 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1457 have_autoterm = FALSE;
1460 if (have_autoterm) {
1461 ahc->flags |= AHC_HAS_TERM_LOGIC;
1462 ahc_acquire_seeprom(ahc, &sd);
1463 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1464 ahc_release_seeprom(&sd);
1465 } else if (have_seeprom) {
1466 *sxfrctl1 &= ~STPWEN;
1467 if ((sc->adapter_control & CFSTERM) != 0)
1468 *sxfrctl1 |= STPWEN;
1470 printf("%s: Low byte termination %sabled\n",
1472 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1477 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1480 * Put the data we've collected down into SRAM
1481 * where ahc_init will find it.
1484 int max_targ = sc->max_targets & CFMAXTARG;
1486 uint16_t discenable;
1491 if ((sc->adapter_control & CFULTRAEN) != 0) {
1493 * Determine if this adapter has a "newstyle"
1496 for (i = 0; i < max_targ; i++) {
1497 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1498 ahc->flags |= AHC_NEWEEPROM_FMT;
1504 for (i = 0; i < max_targ; i++) {
1506 uint16_t target_mask;
1508 target_mask = 0x01 << i;
1509 if (sc->device_flags[i] & CFDISC)
1510 discenable |= target_mask;
1511 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1512 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1513 ultraenb |= target_mask;
1514 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1515 ultraenb |= target_mask;
1517 if ((sc->device_flags[i] & CFXFER) == 0x04
1518 && (ultraenb & target_mask) != 0) {
1519 /* Treat 10MHz as a non-ultra speed */
1520 sc->device_flags[i] &= ~CFXFER;
1521 ultraenb &= ~target_mask;
1523 if ((ahc->features & AHC_ULTRA2) != 0) {
1526 if (sc->device_flags[i] & CFSYNCH)
1527 offset = MAX_OFFSET_ULTRA2;
1530 ahc_outb(ahc, TARG_OFFSET + i, offset);
1533 * The ultra enable bits contain the
1534 * high bit of the ultra2 sync rate
1537 scsirate = (sc->device_flags[i] & CFXFER)
1538 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1539 if (sc->device_flags[i] & CFWIDEB)
1540 scsirate |= WIDEXFER;
1542 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1543 if (sc->device_flags[i] & CFSYNCH)
1545 if (sc->device_flags[i] & CFWIDEB)
1546 scsirate |= WIDEXFER;
1548 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1550 ahc->our_id = sc->brtime_id & CFSCSIID;
1552 scsi_conf = (ahc->our_id & 0x7);
1553 if (sc->adapter_control & CFSPARITY)
1554 scsi_conf |= ENSPCHK;
1555 if (sc->adapter_control & CFRESETB)
1556 scsi_conf |= RESET_SCSI;
1558 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1560 if (sc->bios_control & CFEXTEND)
1561 ahc->flags |= AHC_EXTENDED_TRANS_A;
1563 if (sc->bios_control & CFBIOSEN)
1564 ahc->flags |= AHC_BIOS_ENABLED;
1565 if (ahc->features & AHC_ULTRA
1566 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1567 /* Should we enable Ultra mode? */
1568 if (!(sc->adapter_control & CFULTRAEN))
1569 /* Treat us as a non-ultra card */
1573 if (sc->signature == CFSIGNATURE
1574 || sc->signature == CFSIGNATURE2) {
1577 /* Honor the STPWLEVEL settings */
1578 devconfig = ahc_pci_read_config(ahc->dev_softc,
1579 DEVCONFIG, /*bytes*/4);
1580 devconfig &= ~STPWLEVEL;
1581 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1582 devconfig |= STPWLEVEL;
1583 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1584 devconfig, /*bytes*/4);
1586 /* Set SCSICONF info */
1587 ahc_outb(ahc, SCSICONF, scsi_conf);
1588 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1589 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1590 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1591 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1595 configure_termination(struct ahc_softc *ahc,
1596 struct seeprom_descriptor *sd,
1597 u_int adapter_control,
1605 * Update the settings in sxfrctl1 to match the
1606 * termination settings
1611 * SEECS must be on for the GALS to latch
1612 * the data properly. Be sure to leave MS
1613 * on or we will release the seeprom.
1615 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1616 if ((adapter_control & CFAUTOTERM) != 0
1617 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1618 int internal50_present;
1619 int internal68_present;
1620 int externalcable_present;
1632 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1633 ahc_new_term_detect(ahc, &enableSEC_low,
1638 if ((adapter_control & CFSEAUTOTERM) == 0) {
1640 printf("%s: Manual SE Termination\n",
1642 enableSEC_low = (adapter_control & CFSELOWTERM);
1644 (adapter_control & CFSEHIGHTERM);
1646 if ((adapter_control & CFAUTOTERM) == 0) {
1648 printf("%s: Manual LVD Termination\n",
1650 enablePRI_low = (adapter_control & CFSTERM);
1651 enablePRI_high = (adapter_control & CFWSTERM);
1653 /* Make the table calculations below happy */
1654 internal50_present = 0;
1655 internal68_present = 1;
1656 externalcable_present = 1;
1657 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1658 aic785X_cable_detect(ahc, &internal50_present,
1659 &externalcable_present,
1661 /* Can never support a wide connector. */
1662 internal68_present = 0;
1664 aic787X_cable_detect(ahc, &internal50_present,
1665 &internal68_present,
1666 &externalcable_present,
1670 if ((ahc->features & AHC_WIDE) == 0)
1671 internal68_present = 0;
1674 && (ahc->features & AHC_ULTRA2) == 0) {
1675 printf("%s: internal 50 cable %s present",
1677 internal50_present ? "is":"not");
1679 if ((ahc->features & AHC_WIDE) != 0)
1680 printf(", internal 68 cable %s present",
1681 internal68_present ? "is":"not");
1682 printf("\n%s: external cable %s present\n",
1684 externalcable_present ? "is":"not");
1687 printf("%s: BIOS eeprom %s present\n",
1688 ahc_name(ahc), eeprom_present ? "is" : "not");
1690 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1692 * The 50 pin connector is a separate bus,
1693 * so force it to always be terminated.
1694 * In the future, perform current sensing
1695 * to determine if we are in the middle of
1696 * a properly terminated bus.
1698 internal50_present = 0;
1702 * Now set the termination based on what
1704 * Flash Enable = BRDDAT7
1705 * Secondary High Term Enable = BRDDAT6
1706 * Secondary Low Term Enable = BRDDAT5 (7890)
1707 * Primary High Term Enable = BRDDAT4 (7890)
1709 if ((ahc->features & AHC_ULTRA2) == 0
1710 && (internal50_present != 0)
1711 && (internal68_present != 0)
1712 && (externalcable_present != 0)) {
1713 printf("%s: Illegal cable configuration!!. "
1714 "Only two connectors on the "
1715 "adapter may be used at a "
1716 "time!\n", ahc_name(ahc));
1719 * Pretend there are no cables in the hope
1720 * that having all of the termination on
1721 * gives us a more stable bus.
1723 internal50_present = 0;
1724 internal68_present = 0;
1725 externalcable_present = 0;
1728 if ((ahc->features & AHC_WIDE) != 0
1729 && ((externalcable_present == 0)
1730 || (internal68_present == 0)
1731 || (enableSEC_high != 0))) {
1734 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1735 printf("%s: 68 pin termination "
1736 "Enabled\n", ahc_name(ahc));
1738 printf("%s: %sHigh byte termination "
1739 "Enabled\n", ahc_name(ahc),
1740 enableSEC_high ? "Secondary "
1745 sum = internal50_present + internal68_present
1746 + externalcable_present;
1747 if (sum < 2 || (enableSEC_low != 0)) {
1748 if ((ahc->features & AHC_ULTRA2) != 0)
1751 *sxfrctl1 |= STPWEN;
1753 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1754 printf("%s: 50 pin termination "
1755 "Enabled\n", ahc_name(ahc));
1757 printf("%s: %sLow byte termination "
1758 "Enabled\n", ahc_name(ahc),
1759 enableSEC_low ? "Secondary "
1764 if (enablePRI_low != 0) {
1765 *sxfrctl1 |= STPWEN;
1767 printf("%s: Primary Low Byte termination "
1768 "Enabled\n", ahc_name(ahc));
1772 * Setup STPWEN before setting up the rest of
1773 * the termination per the tech note on the U160 cards.
1775 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1777 if (enablePRI_high != 0) {
1780 printf("%s: Primary High Byte "
1781 "termination Enabled\n",
1785 write_brdctl(ahc, brddat);
1788 if ((adapter_control & CFSTERM) != 0) {
1789 *sxfrctl1 |= STPWEN;
1792 printf("%s: %sLow byte termination Enabled\n",
1794 (ahc->features & AHC_ULTRA2) ? "Primary "
1798 if ((adapter_control & CFWSTERM) != 0
1799 && (ahc->features & AHC_WIDE) != 0) {
1802 printf("%s: %sHigh byte termination Enabled\n",
1804 (ahc->features & AHC_ULTRA2)
1805 ? "Secondary " : "");
1809 * Setup STPWEN before setting up the rest of
1810 * the termination per the tech note on the U160 cards.
1812 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1814 if ((ahc->features & AHC_WIDE) != 0)
1815 write_brdctl(ahc, brddat);
1817 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1821 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1822 int *enableSEC_high, int *enablePRI_low,
1823 int *enablePRI_high, int *eeprom_present)
1829 * BRDDAT6 = Enable Secondary High Byte termination
1830 * BRDDAT5 = Enable Secondary Low Byte termination
1831 * BRDDAT4 = Enable Primary high byte termination
1832 * BRDDAT3 = Enable Primary low byte termination
1834 brdctl = read_brdctl(ahc);
1835 *eeprom_present = brdctl & BRDDAT7;
1836 *enableSEC_high = (brdctl & BRDDAT6);
1837 *enableSEC_low = (brdctl & BRDDAT5);
1838 *enablePRI_high = (brdctl & BRDDAT4);
1839 *enablePRI_low = (brdctl & BRDDAT3);
1843 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1844 int *internal68_present, int *externalcable_present,
1845 int *eeprom_present)
1850 * First read the status of our cables.
1851 * Set the rom bank to 0 since the
1852 * bank setting serves as a multiplexor
1853 * for the cable detection logic.
1854 * BRDDAT5 controls the bank switch.
1856 write_brdctl(ahc, 0);
1859 * Now read the state of the internal
1860 * connectors. BRDDAT6 is INT50 and
1863 brdctl = read_brdctl(ahc);
1864 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1865 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1868 * Set the rom bank to 1 and determine
1869 * the other signals.
1871 write_brdctl(ahc, BRDDAT5);
1874 * Now read the state of the external
1875 * connectors. BRDDAT6 is EXT68 and
1876 * BRDDAT7 is EPROMPS.
1878 brdctl = read_brdctl(ahc);
1879 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1880 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1884 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1885 int *externalcable_present, int *eeprom_present)
1890 spiocap = ahc_inb(ahc, SPIOCAP);
1891 spiocap &= ~SOFTCMDEN;
1892 spiocap |= EXT_BRDCTL;
1893 ahc_outb(ahc, SPIOCAP, spiocap);
1894 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1895 ahc_flush_device_writes(ahc);
1897 ahc_outb(ahc, BRDCTL, 0);
1898 ahc_flush_device_writes(ahc);
1900 brdctl = ahc_inb(ahc, BRDCTL);
1901 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1902 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1903 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1907 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1911 if ((ahc->features & AHC_SPIOCAP) != 0
1912 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1916 * Request access of the memory port. When access is
1917 * granted, SEERDY will go high. We use a 1 second
1918 * timeout which should be near 1 second more than
1919 * is needed. Reason: after the chip reset, there
1920 * should be no contention.
1922 SEEPROM_OUTB(sd, sd->sd_MS);
1923 wait = 1000; /* 1 second timeout in msec */
1924 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1925 ahc_delay(1000); /* delay 1 msec */
1927 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1928 SEEPROM_OUTB(sd, 0);
1935 ahc_release_seeprom(struct seeprom_descriptor *sd)
1937 /* Release access to the memory port and the serial EEPROM. */
1938 SEEPROM_OUTB(sd, 0);
1942 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1946 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1948 if (ahc->channel == 'B')
1950 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1953 brdctl = BRDSTB|BRDCS;
1955 ahc_outb(ahc, BRDCTL, brdctl);
1956 ahc_flush_device_writes(ahc);
1958 ahc_outb(ahc, BRDCTL, brdctl);
1959 ahc_flush_device_writes(ahc);
1960 if ((ahc->features & AHC_ULTRA2) != 0)
1961 brdctl |= BRDSTB_ULTRA2;
1964 ahc_outb(ahc, BRDCTL, brdctl);
1965 ahc_flush_device_writes(ahc);
1966 if ((ahc->features & AHC_ULTRA2) != 0)
1970 ahc_outb(ahc, BRDCTL, brdctl);
1974 read_brdctl(struct ahc_softc *ahc)
1979 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1981 if (ahc->channel == 'B')
1983 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1984 brdctl = BRDRW_ULTRA2;
1986 brdctl = BRDRW|BRDCS;
1988 ahc_outb(ahc, BRDCTL, brdctl);
1989 ahc_flush_device_writes(ahc);
1990 value = ahc_inb(ahc, BRDCTL);
1991 ahc_outb(ahc, BRDCTL, 0);
1996 ahc_pci_intr(struct ahc_softc *ahc)
2001 error = ahc_inb(ahc, ERROR);
2002 if ((error & PCIERRSTAT) == 0)
2005 status1 = ahc_pci_read_config(ahc->dev_softc,
2006 PCIR_STATUS + 1, /*bytes*/1);
2008 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2010 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2012 if (status1 & DPE) {
2013 ahc->pci_target_perr_count++;
2014 printf("%s: Data Parity Error Detected during address "
2015 "or write data phase\n", ahc_name(ahc));
2017 if (status1 & SSE) {
2018 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2020 if (status1 & RMA) {
2021 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2023 if (status1 & RTA) {
2024 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2026 if (status1 & STA) {
2027 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2029 if (status1 & DPR) {
2030 printf("%s: Data Parity Error has been reported via PERR#\n",
2034 /* Clear latched errors. */
2035 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2036 status1, /*bytes*/1);
2038 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2039 printf("%s: Latched PCIERR interrupt with "
2040 "no status bits set\n", ahc_name(ahc));
2042 ahc_outb(ahc, CLRINT, CLRPARERR);
2045 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
2047 "%s: WARNING WARNING WARNING WARNING\n"
2048 "%s: Too many PCI parity errors observed as a target.\n"
2049 "%s: Some device on this bus is generating bad parity.\n"
2050 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
2051 "%s: PCI parity error checking has been disabled.\n"
2052 "%s: WARNING WARNING WARNING WARNING\n",
2053 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2054 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
2055 ahc->seqctl |= FAILDIS;
2056 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2062 ahc_pci_chip_init(struct ahc_softc *ahc)
2064 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2065 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2066 if ((ahc->features & AHC_DT) != 0) {
2069 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2070 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2071 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2072 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2073 ahc_outb(ahc, SFUNCT, sfunct);
2074 ahc_outb(ahc, CRCCONTROL1,
2075 ahc->bus_softc.pci_softc.crccontrol1);
2077 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2078 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2080 if ((ahc->features & AHC_ULTRA2) != 0)
2081 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2083 return (ahc_chip_init(ahc));
2087 ahc_pci_suspend(struct ahc_softc *ahc)
2089 return (ahc_suspend(ahc));
2093 ahc_pci_resume(struct ahc_softc *ahc)
2096 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
2099 * We assume that the OS has restored our register
2100 * mappings, etc. Just update the config space registers
2101 * that the OS doesn't know about and rely on our chip
2102 * reset handler to handle the rest.
2104 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2105 ahc->bus_softc.pci_softc.devconfig);
2106 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2107 ahc->bus_softc.pci_softc.command);
2108 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2109 ahc->bus_softc.pci_softc.csize_lattime);
2110 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2111 struct seeprom_descriptor sd;
2115 sd.sd_control_offset = SEECTL;
2116 sd.sd_status_offset = SEECTL;
2117 sd.sd_dataout_offset = SEECTL;
2119 ahc_acquire_seeprom(ahc, &sd);
2120 configure_termination(ahc, &sd,
2121 ahc->seep_config->adapter_control,
2123 ahc_release_seeprom(&sd);
2125 return (ahc_resume(ahc));
2129 ahc_aic785X_setup(struct ahc_softc *ahc)
2131 ahc_dev_softc_t pci;
2134 pci = ahc->dev_softc;
2136 ahc->chip = AHC_AIC7850;
2137 ahc->features = AHC_AIC7850_FE;
2138 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2139 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2141 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2142 ahc->instruction_ram_size = 512;
2147 ahc_aic7860_setup(struct ahc_softc *ahc)
2149 ahc_dev_softc_t pci;
2152 pci = ahc->dev_softc;
2154 ahc->chip = AHC_AIC7860;
2155 ahc->features = AHC_AIC7860_FE;
2156 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2157 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2159 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2160 ahc->instruction_ram_size = 512;
2165 ahc_apa1480_setup(struct ahc_softc *ahc)
2169 error = ahc_aic7860_setup(ahc);
2172 ahc->features |= AHC_REMOVABLE;
2177 ahc_aic7870_setup(struct ahc_softc *ahc)
2181 ahc->chip = AHC_AIC7870;
2182 ahc->features = AHC_AIC7870_FE;
2183 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2184 ahc->instruction_ram_size = 512;
2189 ahc_aha394X_setup(struct ahc_softc *ahc)
2193 error = ahc_aic7870_setup(ahc);
2195 error = ahc_aha394XX_setup(ahc);
2200 ahc_aha398X_setup(struct ahc_softc *ahc)
2204 error = ahc_aic7870_setup(ahc);
2206 error = ahc_aha398XX_setup(ahc);
2211 ahc_aha494X_setup(struct ahc_softc *ahc)
2215 error = ahc_aic7870_setup(ahc);
2217 error = ahc_aha494XX_setup(ahc);
2222 ahc_aic7880_setup(struct ahc_softc *ahc)
2224 ahc_dev_softc_t pci;
2227 pci = ahc->dev_softc;
2229 ahc->chip = AHC_AIC7880;
2230 ahc->features = AHC_AIC7880_FE;
2231 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2232 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2234 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2236 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2238 ahc->instruction_ram_size = 512;
2243 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2246 ahc->flags |= AHC_INT50_SPEEDFLEX;
2247 return (ahc_aic7880_setup(ahc));
2251 ahc_aha394XU_setup(struct ahc_softc *ahc)
2255 error = ahc_aic7880_setup(ahc);
2257 error = ahc_aha394XX_setup(ahc);
2262 ahc_aha398XU_setup(struct ahc_softc *ahc)
2266 error = ahc_aic7880_setup(ahc);
2268 error = ahc_aha398XX_setup(ahc);
2273 ahc_aic7890_setup(struct ahc_softc *ahc)
2275 ahc_dev_softc_t pci;
2278 pci = ahc->dev_softc;
2280 ahc->chip = AHC_AIC7890;
2281 ahc->features = AHC_AIC7890_FE;
2282 ahc->flags |= AHC_NEWEEPROM_FMT;
2283 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2285 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2286 ahc->instruction_ram_size = 768;
2291 ahc_aic7892_setup(struct ahc_softc *ahc)
2295 ahc->chip = AHC_AIC7892;
2296 ahc->features = AHC_AIC7892_FE;
2297 ahc->flags |= AHC_NEWEEPROM_FMT;
2298 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2299 ahc->instruction_ram_size = 1024;
2304 ahc_aic7895_setup(struct ahc_softc *ahc)
2306 ahc_dev_softc_t pci;
2309 pci = ahc->dev_softc;
2310 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2312 * The 'C' revision of the aic7895 has a few additional features.
2314 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2316 ahc->chip = AHC_AIC7895C;
2317 ahc->features = AHC_AIC7895C_FE;
2321 ahc->chip = AHC_AIC7895;
2322 ahc->features = AHC_AIC7895_FE;
2325 * The BIOS disables the use of MWI transactions
2326 * since it does not have the MWI bug work around
2327 * we have. Disabling MWI reduces performance, so
2330 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2331 command |= PCIM_CMD_MWRICEN;
2332 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2333 ahc->bugs |= AHC_PCI_MWI_BUG;
2336 * XXX Does CACHETHEN really not work??? What about PCI retry?
2337 * on C level chips. Need to test, but for now, play it safe.
2339 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2340 | AHC_CACHETHEN_BUG;
2346 * Cachesize must also be zero due to stray DAC
2347 * problem when sitting behind some bridges.
2349 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2350 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2351 devconfig |= MRDCEN;
2352 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2354 ahc->flags |= AHC_NEWEEPROM_FMT;
2355 ahc->instruction_ram_size = 512;
2360 ahc_aic7896_setup(struct ahc_softc *ahc)
2362 ahc_dev_softc_t pci;
2364 pci = ahc->dev_softc;
2365 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2366 ahc->chip = AHC_AIC7896;
2367 ahc->features = AHC_AIC7896_FE;
2368 ahc->flags |= AHC_NEWEEPROM_FMT;
2369 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2370 ahc->instruction_ram_size = 768;
2375 ahc_aic7899_setup(struct ahc_softc *ahc)
2377 ahc_dev_softc_t pci;
2379 pci = ahc->dev_softc;
2380 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2381 ahc->chip = AHC_AIC7899;
2382 ahc->features = AHC_AIC7899_FE;
2383 ahc->flags |= AHC_NEWEEPROM_FMT;
2384 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2385 ahc->instruction_ram_size = 1024;
2390 ahc_aha29160C_setup(struct ahc_softc *ahc)
2394 error = ahc_aic7899_setup(ahc);
2397 ahc->features |= AHC_REMOVABLE;
2402 ahc_raid_setup(struct ahc_softc *ahc)
2404 printf("RAID functionality unsupported\n");
2409 ahc_aha394XX_setup(struct ahc_softc *ahc)
2411 ahc_dev_softc_t pci;
2413 pci = ahc->dev_softc;
2414 switch (ahc_get_pci_slot(pci)) {
2415 case AHC_394X_SLOT_CHANNEL_A:
2418 case AHC_394X_SLOT_CHANNEL_B:
2422 printf("adapter at unexpected slot %d\n"
2423 "unable to map to a channel\n",
2424 ahc_get_pci_slot(pci));
2431 ahc_aha398XX_setup(struct ahc_softc *ahc)
2433 ahc_dev_softc_t pci;
2435 pci = ahc->dev_softc;
2436 switch (ahc_get_pci_slot(pci)) {
2437 case AHC_398X_SLOT_CHANNEL_A:
2440 case AHC_398X_SLOT_CHANNEL_B:
2443 case AHC_398X_SLOT_CHANNEL_C:
2447 printf("adapter at unexpected slot %d\n"
2448 "unable to map to a channel\n",
2449 ahc_get_pci_slot(pci));
2453 ahc->flags |= AHC_LARGE_SEEPROM;
2458 ahc_aha494XX_setup(struct ahc_softc *ahc)
2460 ahc_dev_softc_t pci;
2462 pci = ahc->dev_softc;
2463 switch (ahc_get_pci_slot(pci)) {
2464 case AHC_494X_SLOT_CHANNEL_A:
2467 case AHC_494X_SLOT_CHANNEL_B:
2470 case AHC_494X_SLOT_CHANNEL_C:
2473 case AHC_494X_SLOT_CHANNEL_D:
2477 printf("adapter at unexpected slot %d\n"
2478 "unable to map to a channel\n",
2479 ahc_get_pci_slot(pci));
2482 ahc->flags |= AHC_LARGE_SEEPROM;