3 ata_piix.c - Intel PATA/SATA controllers
6 Copyright 2003-2004 Red Hat Inc
7 Copyright 2003-2004 Jeff Garzik
10 Copyright header from piix.c:
12 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
13 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
14 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
16 May be copied or modified under the terms of the GNU General Public License
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
28 #include <linux/libata.h>
30 #define DRV_NAME "ata_piix"
31 #define DRV_VERSION "1.02"
34 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
35 ICH5_PMR = 0x90, /* port mapping register */
36 ICH5_PCS = 0x92, /* port control and status */
38 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
39 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
41 /* combined mode. if set, PATA is channel 0.
42 * if clear, PATA is channel 1.
44 PIIX_COMB_PATA_P0 = (1 << 1),
45 PIIX_COMB = (1 << 2), /* combined mode enabled? */
47 PIIX_PORT_PRESENT = (1 << 0),
48 PIIX_PORT_ENABLED = (1 << 4),
50 PIIX_80C_PRI = (1 << 5) | (1 << 4),
51 PIIX_80C_SEC = (1 << 7) | (1 << 6),
58 static int piix_init_one (struct pci_dev *pdev,
59 const struct pci_device_id *ent);
61 static void piix_pata_phy_reset(struct ata_port *ap);
62 static void piix_sata_phy_reset(struct ata_port *ap);
63 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
65 static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
68 static unsigned int in_module_init = 1;
70 static struct pci_device_id piix_pci_tbl[] = {
71 #ifdef ATA_ENABLE_PATA
72 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
73 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
74 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
77 /* NOTE: The following PCI ids must be kept in sync with the
78 * list in drivers/pci/quirks.c.
81 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
82 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
83 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
84 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
86 /* ICH6 operates in two modes, "looks-like-ICH5" mode,
87 * and enhanced mode, with queueing and other fancy stuff.
88 * This is distinguished by PCI class code.
90 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID,
91 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
92 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID,
93 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
95 { } /* terminate list */
98 static struct pci_driver piix_pci_driver = {
100 .id_table = piix_pci_tbl,
101 .probe = piix_init_one,
102 .remove = ata_pci_remove_one,
105 static Scsi_Host_Template piix_sht = {
106 .module = THIS_MODULE,
108 .queuecommand = ata_scsi_queuecmd,
109 .eh_strategy_handler = ata_scsi_error,
110 .can_queue = ATA_DEF_QUEUE,
111 .this_id = ATA_SHT_THIS_ID,
112 .sg_tablesize = LIBATA_MAX_PRD,
113 .max_sectors = ATA_MAX_SECTORS,
114 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
115 .emulated = ATA_SHT_EMULATED,
116 .use_clustering = ATA_SHT_USE_CLUSTERING,
117 .proc_name = DRV_NAME,
118 .dma_boundary = ATA_DMA_BOUNDARY,
119 .slave_configure = ata_scsi_slave_config,
120 .bios_param = ata_std_bios_param,
123 static struct ata_port_operations piix_pata_ops = {
124 .port_disable = ata_port_disable,
125 .set_piomode = piix_set_piomode,
126 .set_udmamode = piix_set_udmamode,
128 .tf_load = ata_tf_load_pio,
129 .tf_read = ata_tf_read_pio,
130 .check_status = ata_check_status_pio,
131 .exec_command = ata_exec_command_pio,
133 .phy_reset = piix_pata_phy_reset,
135 .bmdma_start = ata_bmdma_start_pio,
136 .fill_sg = ata_fill_sg,
137 .eng_timeout = ata_eng_timeout,
139 .irq_handler = ata_interrupt,
141 .port_start = ata_port_start,
142 .port_stop = ata_port_stop,
145 static struct ata_port_operations piix_sata_ops = {
146 .port_disable = ata_port_disable,
147 .set_piomode = piix_set_piomode,
148 .set_udmamode = piix_set_udmamode,
150 .tf_load = ata_tf_load_pio,
151 .tf_read = ata_tf_read_pio,
152 .check_status = ata_check_status_pio,
153 .exec_command = ata_exec_command_pio,
155 .phy_reset = piix_sata_phy_reset,
157 .bmdma_start = ata_bmdma_start_pio,
158 .fill_sg = ata_fill_sg,
159 .eng_timeout = ata_eng_timeout,
161 .irq_handler = ata_interrupt,
163 .port_start = ata_port_start,
164 .port_stop = ata_port_stop,
167 static struct ata_port_info piix_port_info[] = {
171 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
173 .pio_mask = 0x03, /* pio3-4 */
174 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
175 .port_ops = &piix_pata_ops,
181 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
182 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
183 .pio_mask = 0x03, /* pio3-4 */
184 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
185 .port_ops = &piix_sata_ops,
191 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
192 .pio_mask = 0x03, /* pio3-4 */
193 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
194 .port_ops = &piix_pata_ops,
198 static struct pci_bits piix_enable_bits[] = {
199 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
200 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
203 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
204 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
205 MODULE_LICENSE("GPL");
206 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
209 * piix_pata_cbl_detect - Probe host controller cable detect info
210 * @ap: Port for which cable detect info is desired
212 * Read 80c cable indicator from SATA PCI device's PCI config
213 * register. This register is normally set by firmware (BIOS).
216 * None (inherited from caller).
218 static void piix_pata_cbl_detect(struct ata_port *ap)
220 struct pci_dev *pdev = ap->host_set->pdev;
223 /* no 80c support in host controller? */
224 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
227 /* check BIOS cable detect results */
228 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
229 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
230 if ((tmp & mask) == 0)
233 ap->cbl = ATA_CBL_PATA80;
237 ap->cbl = ATA_CBL_PATA40;
238 ap->udma_mask &= ATA_UDMA_MASK_40C;
242 * piix_pata_phy_reset - Probe specified port on PATA host controller
248 * None (inherited from caller).
251 static void piix_pata_phy_reset(struct ata_port *ap)
253 if (!pci_test_config_bits(ap->host_set->pdev,
254 &piix_enable_bits[ap->port_no])) {
255 ata_port_disable(ap);
256 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
260 piix_pata_cbl_detect(ap);
268 * piix_sata_probe - Probe PCI device for present SATA devices
269 * @pdev: PCI device to probe
271 * Reads SATA PCI device's PCI config register Port Configuration
272 * and Status (PCS) to determine port and device availability.
275 * None (inherited from caller).
278 * Non-zero if device detected, zero otherwise.
280 static int piix_sata_probe (struct ata_port *ap)
282 struct pci_dev *pdev = ap->host_set->pdev;
283 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
284 int orig_mask, mask, i;
287 mask = (PIIX_PORT_PRESENT << ap->port_no) |
288 (PIIX_PORT_ENABLED << ap->port_no);
290 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
291 orig_mask = (int) pcs & 0xff;
293 /* TODO: this is vaguely wrong for ICH6 combined mode,
294 * where only two of the four SATA ports are mapped
295 * onto a single ATA channel. It is also vaguely inaccurate
296 * for ICH5, which has only two ports. However, this is ok,
297 * as further device presence detection code will handle
298 * any false positives produced here.
301 for (i = 0; i < 4; i++) {
302 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
304 if ((orig_mask & mask) == mask)
305 if (combined || (i == ap->port_no))
313 * piix_sata_phy_reset - Probe specified port on SATA host controller
319 * None (inherited from caller).
322 static void piix_sata_phy_reset(struct ata_port *ap)
324 if (!pci_test_config_bits(ap->host_set->pdev,
325 &piix_enable_bits[ap->port_no])) {
326 ata_port_disable(ap);
327 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
331 if (!piix_sata_probe(ap)) {
332 ata_port_disable(ap);
333 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
337 ap->cbl = ATA_CBL_SATA;
345 * piix_set_piomode - Initialize host controller PATA PIO timings
346 * @ap: Port whose timings we are configuring
348 * @pio: PIO mode, 0 - 4
350 * Set PIO mode for device, in host controller PCI config space.
353 * None (inherited from caller).
356 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
359 struct pci_dev *dev = ap->host_set->pdev;
360 unsigned int is_slave = (adev->flags & ATA_DFLAG_MASTER) ? 0 : 1;
361 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
362 unsigned int slave_port = 0x44;
366 static const /* ISP RTC */
367 u8 timings[][2] = { { 0, 0 },
373 pci_read_config_word(dev, master_port, &master_data);
375 master_data |= 0x4000;
376 /* enable PPE, IE and TIME */
377 master_data |= 0x0070;
378 pci_read_config_byte(dev, slave_port, &slave_data);
379 slave_data &= (ap->port_no ? 0x0f : 0xf0);
381 (timings[pio][0] << 2) |
382 (timings[pio][1] << (ap->port_no ? 4 : 0));
384 master_data &= 0xccf8;
385 /* enable PPE, IE and TIME */
386 master_data |= 0x0007;
388 (timings[pio][0] << 12) |
389 (timings[pio][1] << 8);
391 pci_write_config_word(dev, master_port, master_data);
393 pci_write_config_byte(dev, slave_port, slave_data);
397 * piix_set_udmamode - Initialize host controller PATA PIO timings
398 * @ap: Port whose timings we are configuring
400 * @udma: udma mode, 0 - 6
402 * Set UDMA mode for device, in host controller PCI config space.
405 * None (inherited from caller).
408 static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
411 struct pci_dev *dev = ap->host_set->pdev;
412 u8 maslave = ap->port_no ? 0x42 : 0x40;
414 unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
415 int a_speed = 3 << (drive_dn * 4);
416 int u_flag = 1 << drive_dn;
417 int v_flag = 0x01 << drive_dn;
418 int w_flag = 0x10 << drive_dn;
421 u16 reg4042, reg44, reg48, reg4a, reg54;
424 pci_read_config_word(dev, maslave, ®4042);
425 DPRINTK("reg4042 = 0x%04x\n", reg4042);
426 sitre = (reg4042 & 0x4000) ? 1 : 0;
427 pci_read_config_word(dev, 0x44, ®44);
428 pci_read_config_word(dev, 0x48, ®48);
429 pci_read_config_word(dev, 0x4a, ®4a);
430 pci_read_config_word(dev, 0x54, ®54);
431 pci_read_config_byte(dev, 0x55, ®55);
435 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
439 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
440 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
446 if (!(reg48 & u_flag))
447 pci_write_config_word(dev, 0x48, reg48|u_flag);
448 if (speed == XFER_UDMA_5) {
449 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
451 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
453 if (!(reg4a & u_speed)) {
454 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
455 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
457 if (speed > XFER_UDMA_2) {
458 if (!(reg54 & v_flag)) {
459 pci_write_config_word(dev, 0x54, reg54|v_flag);
462 pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
466 /* move to PCI layer, integrate w/ MSI stuff */
467 static void pci_enable_intx(struct pci_dev *pdev)
471 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
472 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
473 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
474 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
479 * piix_init_one - Register PIIX ATA PCI device with kernel services
480 * @pdev: PCI device to register
481 * @ent: Entry in piix_pci_tbl matching with @pdev
483 * Called from kernel PCI layer. We probe for combined mode (sigh),
484 * and then hand over control to libata, for it to do the rest.
487 * Inherited from PCI layer (may sleep).
490 * Zero on success, or -ERRNO value.
493 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
495 static int printed_version;
496 struct ata_port_info *port_info[2];
497 unsigned int combined = 0, n_ports = 1;
498 unsigned int pata_chan = 0, sata_chan = 0;
500 if (!printed_version++)
501 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
503 /* no hotplugging support (FIXME) */
507 port_info[0] = &piix_port_info[ent->driver_data];
510 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
512 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
514 if (tmp & PIIX_COMB) {
516 if (tmp & PIIX_COMB_PATA_P0)
523 /* On ICH5, some BIOSen disable the interrupt using the
524 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
525 * On ICH6, this bit has the same effect, but only when
526 * MSI is disabled (and it is disabled, as we don't use
527 * message-signalled interrupts currently).
529 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
530 pci_enable_intx(pdev);
533 port_info[sata_chan] = &piix_port_info[ent->driver_data];
534 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
535 port_info[pata_chan] = &piix_port_info[ich5_pata];
538 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
541 return ata_pci_init_one(pdev, port_info, n_ports);
553 static int __init piix_init(void)
557 DPRINTK("pci_module_init\n");
558 rc = pci_module_init(&piix_pci_driver);
575 static void __exit piix_exit(void)
577 pci_unregister_driver(&piix_pci_driver);
580 module_init(piix_init);
581 module_exit(piix_exit);