3 ata_piix.c - Intel PATA/SATA controllers
5 Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 Please ALWAYS copy linux-ide@vger.kernel.org
10 Copyright 2003-2004 Red Hat Inc
11 Copyright 2003-2004 Jeff Garzik
14 Copyright header from piix.c:
16 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
17 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
18 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 May be copied or modified under the terms of the GNU General Public License
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
34 #define DRV_NAME "ata_piix"
35 #define DRV_VERSION "1.02"
38 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
39 ICH5_PMR = 0x90, /* port mapping register */
40 ICH5_PCS = 0x92, /* port control and status */
42 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
43 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
45 /* combined mode. if set, PATA is channel 0.
46 * if clear, PATA is channel 1.
48 PIIX_COMB_PATA_P0 = (1 << 1),
49 PIIX_COMB = (1 << 2), /* combined mode enabled? */
51 PIIX_PORT_PRESENT = (1 << 0),
52 PIIX_PORT_ENABLED = (1 << 4),
54 PIIX_80C_PRI = (1 << 5) | (1 << 4),
55 PIIX_80C_SEC = (1 << 7) | (1 << 6),
62 static int piix_init_one (struct pci_dev *pdev,
63 const struct pci_device_id *ent);
65 static void piix_pata_phy_reset(struct ata_port *ap);
66 static void piix_sata_phy_reset(struct ata_port *ap);
67 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
69 static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
72 static unsigned int in_module_init = 1;
74 static struct pci_device_id piix_pci_tbl[] = {
75 #ifdef ATA_ENABLE_PATA
76 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
77 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
78 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
81 /* NOTE: The following PCI ids must be kept in sync with the
82 * list in drivers/pci/quirks.c.
85 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
86 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
87 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
88 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
90 /* ICH6 operates in two modes, "looks-like-ICH5" mode,
91 * and enhanced mode, with queueing and other fancy stuff.
92 * This is distinguished by PCI class code.
94 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID,
95 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
96 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID,
97 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
99 { } /* terminate list */
102 static struct pci_driver piix_pci_driver = {
104 .id_table = piix_pci_tbl,
105 .probe = piix_init_one,
106 .remove = ata_pci_remove_one,
109 static Scsi_Host_Template piix_sht = {
110 .module = THIS_MODULE,
112 .queuecommand = ata_scsi_queuecmd,
113 .eh_strategy_handler = ata_scsi_error,
114 .can_queue = ATA_DEF_QUEUE,
115 .this_id = ATA_SHT_THIS_ID,
116 .sg_tablesize = LIBATA_MAX_PRD,
117 .max_sectors = ATA_MAX_SECTORS,
118 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
119 .emulated = ATA_SHT_EMULATED,
120 .use_clustering = ATA_SHT_USE_CLUSTERING,
121 .proc_name = DRV_NAME,
122 .dma_boundary = ATA_DMA_BOUNDARY,
123 .slave_configure = ata_scsi_slave_config,
124 .bios_param = ata_std_bios_param,
127 static struct ata_port_operations piix_pata_ops = {
128 .port_disable = ata_port_disable,
129 .set_piomode = piix_set_piomode,
130 .set_udmamode = piix_set_udmamode,
132 .tf_load = ata_tf_load_pio,
133 .tf_read = ata_tf_read_pio,
134 .check_status = ata_check_status_pio,
135 .exec_command = ata_exec_command_pio,
137 .phy_reset = piix_pata_phy_reset,
139 .bmdma_setup = ata_bmdma_setup_pio,
140 .bmdma_start = ata_bmdma_start_pio,
141 .fill_sg = ata_fill_sg,
142 .eng_timeout = ata_eng_timeout,
144 .irq_handler = ata_interrupt,
146 .port_start = ata_port_start,
147 .port_stop = ata_port_stop,
150 static struct ata_port_operations piix_sata_ops = {
151 .port_disable = ata_port_disable,
152 .set_piomode = piix_set_piomode,
153 .set_udmamode = piix_set_udmamode,
155 .tf_load = ata_tf_load_pio,
156 .tf_read = ata_tf_read_pio,
157 .check_status = ata_check_status_pio,
158 .exec_command = ata_exec_command_pio,
160 .phy_reset = piix_sata_phy_reset,
162 .bmdma_setup = ata_bmdma_setup_pio,
163 .bmdma_start = ata_bmdma_start_pio,
164 .fill_sg = ata_fill_sg,
165 .eng_timeout = ata_eng_timeout,
167 .irq_handler = ata_interrupt,
169 .port_start = ata_port_start,
170 .port_stop = ata_port_stop,
173 static struct ata_port_info piix_port_info[] = {
177 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
179 .pio_mask = 0x03, /* pio3-4 */
180 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
181 .port_ops = &piix_pata_ops,
187 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
188 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
189 .pio_mask = 0x03, /* pio3-4 */
190 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
191 .port_ops = &piix_sata_ops,
197 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
198 .pio_mask = 0x03, /* pio3-4 */
199 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
200 .port_ops = &piix_pata_ops,
204 static struct pci_bits piix_enable_bits[] = {
205 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
206 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
209 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
210 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
211 MODULE_LICENSE("GPL");
212 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
215 * piix_pata_cbl_detect - Probe host controller cable detect info
216 * @ap: Port for which cable detect info is desired
218 * Read 80c cable indicator from SATA PCI device's PCI config
219 * register. This register is normally set by firmware (BIOS).
222 * None (inherited from caller).
224 static void piix_pata_cbl_detect(struct ata_port *ap)
226 struct pci_dev *pdev = ap->host_set->pdev;
229 /* no 80c support in host controller? */
230 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
233 /* check BIOS cable detect results */
234 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
235 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
236 if ((tmp & mask) == 0)
239 ap->cbl = ATA_CBL_PATA80;
243 ap->cbl = ATA_CBL_PATA40;
244 ap->udma_mask &= ATA_UDMA_MASK_40C;
248 * piix_pata_phy_reset - Probe specified port on PATA host controller
254 * None (inherited from caller).
257 static void piix_pata_phy_reset(struct ata_port *ap)
259 if (!pci_test_config_bits(ap->host_set->pdev,
260 &piix_enable_bits[ap->port_no])) {
261 ata_port_disable(ap);
262 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
266 piix_pata_cbl_detect(ap);
274 * piix_sata_probe - Probe PCI device for present SATA devices
275 * @ap: Port associated with the PCI device we wish to probe
277 * Reads SATA PCI device's PCI config register Port Configuration
278 * and Status (PCS) to determine port and device availability.
281 * None (inherited from caller).
284 * Non-zero if device detected, zero otherwise.
286 static int piix_sata_probe (struct ata_port *ap)
288 struct pci_dev *pdev = ap->host_set->pdev;
289 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
290 int orig_mask, mask, i;
293 mask = (PIIX_PORT_PRESENT << ap->port_no) |
294 (PIIX_PORT_ENABLED << ap->port_no);
296 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
297 orig_mask = (int) pcs & 0xff;
299 /* TODO: this is vaguely wrong for ICH6 combined mode,
300 * where only two of the four SATA ports are mapped
301 * onto a single ATA channel. It is also vaguely inaccurate
302 * for ICH5, which has only two ports. However, this is ok,
303 * as further device presence detection code will handle
304 * any false positives produced here.
307 for (i = 0; i < 4; i++) {
308 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
310 if ((orig_mask & mask) == mask)
311 if (combined || (i == ap->port_no))
319 * piix_sata_phy_reset - Probe specified port on SATA host controller
325 * None (inherited from caller).
328 static void piix_sata_phy_reset(struct ata_port *ap)
330 if (!pci_test_config_bits(ap->host_set->pdev,
331 &piix_enable_bits[ap->port_no])) {
332 ata_port_disable(ap);
333 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
337 if (!piix_sata_probe(ap)) {
338 ata_port_disable(ap);
339 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
343 ap->cbl = ATA_CBL_SATA;
351 * piix_set_piomode - Initialize host controller PATA PIO timings
352 * @ap: Port whose timings we are configuring
354 * @pio: PIO mode, 0 - 4
356 * Set PIO mode for device, in host controller PCI config space.
359 * None (inherited from caller).
362 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
365 struct pci_dev *dev = ap->host_set->pdev;
366 unsigned int is_slave = (adev->flags & ATA_DFLAG_MASTER) ? 0 : 1;
367 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
368 unsigned int slave_port = 0x44;
372 static const /* ISP RTC */
373 u8 timings[][2] = { { 0, 0 },
379 pci_read_config_word(dev, master_port, &master_data);
381 master_data |= 0x4000;
382 /* enable PPE, IE and TIME */
383 master_data |= 0x0070;
384 pci_read_config_byte(dev, slave_port, &slave_data);
385 slave_data &= (ap->port_no ? 0x0f : 0xf0);
387 (timings[pio][0] << 2) |
388 (timings[pio][1] << (ap->port_no ? 4 : 0));
390 master_data &= 0xccf8;
391 /* enable PPE, IE and TIME */
392 master_data |= 0x0007;
394 (timings[pio][0] << 12) |
395 (timings[pio][1] << 8);
397 pci_write_config_word(dev, master_port, master_data);
399 pci_write_config_byte(dev, slave_port, slave_data);
403 * piix_set_udmamode - Initialize host controller PATA PIO timings
404 * @ap: Port whose timings we are configuring
406 * @udma: udma mode, 0 - 6
408 * Set UDMA mode for device, in host controller PCI config space.
411 * None (inherited from caller).
414 static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
417 struct pci_dev *dev = ap->host_set->pdev;
418 u8 maslave = ap->port_no ? 0x42 : 0x40;
420 unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
421 int a_speed = 3 << (drive_dn * 4);
422 int u_flag = 1 << drive_dn;
423 int v_flag = 0x01 << drive_dn;
424 int w_flag = 0x10 << drive_dn;
428 u8 reg48, reg54, reg55;
430 pci_read_config_word(dev, maslave, ®4042);
431 DPRINTK("reg4042 = 0x%04x\n", reg4042);
432 sitre = (reg4042 & 0x4000) ? 1 : 0;
433 pci_read_config_byte(dev, 0x48, ®48);
434 pci_read_config_word(dev, 0x4a, ®4a);
435 pci_read_config_byte(dev, 0x54, ®54);
436 pci_read_config_byte(dev, 0x55, ®55);
440 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
444 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
445 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
451 if (!(reg48 & u_flag))
452 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
453 if (speed == XFER_UDMA_5) {
454 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
456 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
458 if ((reg4a & a_speed) != u_speed)
459 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
460 if (speed > XFER_UDMA_2) {
461 if (!(reg54 & v_flag))
462 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
464 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
467 /* move to PCI layer, integrate w/ MSI stuff */
468 static void pci_enable_intx(struct pci_dev *pdev)
472 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
473 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
474 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
475 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
480 * piix_init_one - Register PIIX ATA PCI device with kernel services
481 * @pdev: PCI device to register
482 * @ent: Entry in piix_pci_tbl matching with @pdev
484 * Called from kernel PCI layer. We probe for combined mode (sigh),
485 * and then hand over control to libata, for it to do the rest.
488 * Inherited from PCI layer (may sleep).
491 * Zero on success, or -ERRNO value.
494 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
496 static int printed_version;
497 struct ata_port_info *port_info[2];
498 unsigned int combined = 0, n_ports = 1;
499 unsigned int pata_chan = 0, sata_chan = 0;
501 if (!printed_version++)
502 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
504 /* no hotplugging support (FIXME) */
508 port_info[0] = &piix_port_info[ent->driver_data];
511 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
513 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
515 if (tmp & PIIX_COMB) {
517 if (tmp & PIIX_COMB_PATA_P0)
524 /* On ICH5, some BIOSen disable the interrupt using the
525 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
526 * On ICH6, this bit has the same effect, but only when
527 * MSI is disabled (and it is disabled, as we don't use
528 * message-signalled interrupts currently).
530 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
531 pci_enable_intx(pdev);
534 port_info[sata_chan] = &piix_port_info[ent->driver_data];
535 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
536 port_info[pata_chan] = &piix_port_info[ich5_pata];
539 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
542 return ata_pci_init_one(pdev, port_info, n_ports);
554 static int __init piix_init(void)
558 DPRINTK("pci_module_init\n");
559 rc = pci_module_init(&piix_pci_driver);
576 static void __exit piix_exit(void)
578 pci_unregister_driver(&piix_pci_driver);
581 module_init(piix_init);
582 module_exit(piix_exit);