1 /* fastlane.c: Driver for Phase5's Fastlane SCSI Controller.
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
5 * This driver is based on the CyberStorm driver, hence the occasional
6 * reference to CyberStorm.
8 * Betatesting & crucial adjustments by
9 * Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
15 * o According to the doc from laire, it is required to reset the DMA when
16 * the transfer is done. ATM we reset DMA just before every new
17 * dma_init_(read|write).
19 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
20 * to the caches and the Sparc MMU mapping.
21 * 2) Make as few routines required outside the generic driver. A lot of the
22 * routines in this file used to be inline!
25 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/delay.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/slab.h>
33 #include <linux/blkdev.h>
34 #include <linux/proc_fs.h>
35 #include <linux/stat.h>
36 #include <linux/interrupt.h>
42 #include <linux/zorro.h>
45 #include <asm/amigaints.h>
46 #include <asm/amigahw.h>
48 #include <asm/pgtable.h>
50 /* Such day has just come... */
52 /* Let this defined unless you really need to enable DMA IRQ one day */
56 /* The controller registers can be found in the Z2 config area at these
59 #define FASTLANE_ESP_ADDR 0x1000001
60 #define FASTLANE_DMA_ADDR 0x1000041
63 /* The Fastlane DMA interface */
64 struct fastlane_dma_registers {
65 volatile unsigned char cond_reg; /* DMA status (ro) [0x0000] */
66 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
67 unsigned char dmapad1[0x3f];
68 volatile unsigned char clear_strobe; /* DMA clear (wo) [0x0040] */
73 #define FASTLANE_DMA_MINT 0x80
74 #define FASTLANE_DMA_IACT 0x40
75 #define FASTLANE_DMA_CREQ 0x20
77 /* DMA control bits */
78 #define FASTLANE_DMA_FCODE 0xa0
79 #define FASTLANE_DMA_MASK 0xf3
80 #define FASTLANE_DMA_LED 0x10 /* HD led control 1 = on */
81 #define FASTLANE_DMA_WRITE 0x08 /* 1 = write */
82 #define FASTLANE_DMA_ENABLE 0x04 /* Enable DMA */
83 #define FASTLANE_DMA_EDI 0x02 /* Enable DMA IRQ ? */
84 #define FASTLANE_DMA_ESI 0x01 /* Enable SCSI IRQ */
86 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
87 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
88 static inline void dma_clear(struct NCR_ESP *esp);
89 static void dma_dump_state(struct NCR_ESP *esp);
90 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
91 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddr, int length);
92 static void dma_ints_off(struct NCR_ESP *esp);
93 static void dma_ints_on(struct NCR_ESP *esp);
94 static int dma_irq_p(struct NCR_ESP *esp);
95 static void dma_irq_exit(struct NCR_ESP *esp);
96 static void dma_led_off(struct NCR_ESP *esp);
97 static void dma_led_on(struct NCR_ESP *esp);
98 static int dma_ports_p(struct NCR_ESP *esp);
99 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
101 static unsigned char ctrl_data = 0; /* Keep backup of the stuff written
102 * to ctrl_reg. Always write a copy
103 * to this register when writing to
104 * the hardware register!
107 static volatile unsigned char cmd_buffer[16];
108 /* This is where all commands are put
109 * before they are transferred to the ESP chip
113 /***************************************************************** Detection */
114 int __init fastlane_esp_detect(Scsi_Host_Template *tpnt)
117 struct zorro_dev *z = NULL;
118 unsigned long address;
120 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, z))) {
121 unsigned long board = z->resource.start;
122 if (request_mem_region(board+FASTLANE_ESP_ADDR,
123 sizeof(struct ESP_regs), "NCR53C9x")) {
124 /* Check if this is really a fastlane controller. The problem
125 * is that also the cyberstorm and blizzard controllers use
126 * this ID value. Fortunately only Fastlane maps in Z3 space
128 if (board < 0x1000000) {
131 esp = esp_allocate(tpnt, (void *)board+FASTLANE_ESP_ADDR);
133 /* Do command transfer with programmed I/O */
134 esp->do_pio_cmds = 1;
136 /* Required functions */
137 esp->dma_bytes_sent = &dma_bytes_sent;
138 esp->dma_can_transfer = &dma_can_transfer;
139 esp->dma_dump_state = &dma_dump_state;
140 esp->dma_init_read = &dma_init_read;
141 esp->dma_init_write = &dma_init_write;
142 esp->dma_ints_off = &dma_ints_off;
143 esp->dma_ints_on = &dma_ints_on;
144 esp->dma_irq_p = &dma_irq_p;
145 esp->dma_ports_p = &dma_ports_p;
146 esp->dma_setup = &dma_setup;
148 /* Optional functions */
149 esp->dma_barrier = 0;
151 esp->dma_invalidate = 0;
152 esp->dma_irq_entry = 0;
153 esp->dma_irq_exit = &dma_irq_exit;
154 esp->dma_led_on = &dma_led_on;
155 esp->dma_led_off = &dma_led_off;
159 /* Initialize the portBits (enable IRQs) */
160 ctrl_data = (FASTLANE_DMA_FCODE |
167 /* SCSI chip clock */
168 esp->cfreq = 40000000;
171 /* Map the physical address space into virtual kernel space */
172 address = (unsigned long)
173 z_ioremap(board, z->resource.end-board+1);
176 printk("Could not remap Fastlane controller memory!");
181 /* The DMA registers on the Fastlane are mapped
182 * relative to the device (i.e. in the same Zorro
185 esp->dregs = (void *)(address + FASTLANE_DMA_ADDR);
187 /* ESP register base */
188 esp->eregs = (struct ESP_regs *)(address + FASTLANE_ESP_ADDR);
191 esp->edev = (void *) address;
193 /* Set the command buffer */
194 esp->esp_command = cmd_buffer;
195 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
197 esp->irq = IRQ_AMIGA_PORTS;
198 esp->slot = board+FASTLANE_ESP_ADDR;
199 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
200 "Fastlane SCSI", esp->ehost)) {
201 printk(KERN_WARNING "Fastlane: Could not get IRQ%d, aborting.\n", IRQ_AMIGA_PORTS);
208 /* We don't have a differential SCSI-bus. */
214 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
215 esps_running = esps_in_use;
222 z_iounmap((void *)address);
224 scsi_unregister (esp->ehost);
226 release_mem_region(z->resource.start+FASTLANE_ESP_ADDR,
227 sizeof(struct ESP_regs));
232 /************************************************************* DMA Functions */
233 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
235 /* Since the Fastlane DMA is fully dedicated to the ESP chip,
236 * the number of bytes sent (to the ESP chip) equals the number
237 * of bytes in the FIFO - there is no buffering in the DMA controller.
238 * XXXX Do I read this right? It is from host to ESP, right?
243 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
245 unsigned long sz = sp->SCp.this_residual;
251 static void dma_dump_state(struct NCR_ESP *esp)
253 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
254 esp->esp_id, ((struct fastlane_dma_registers *)
255 (esp->dregs))->cond_reg));
256 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
257 custom.intreqr, custom.intenar));
260 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
262 struct fastlane_dma_registers *dregs =
263 (struct fastlane_dma_registers *) (esp->dregs);
266 cache_clear(addr, length);
270 t = (unsigned long *)((addr & 0x00ffffff) + esp->edev);
272 dregs->clear_strobe = 0;
275 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK) | FASTLANE_DMA_ENABLE;
276 dregs->ctrl_reg = ctrl_data;
279 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
281 struct fastlane_dma_registers *dregs =
282 (struct fastlane_dma_registers *) (esp->dregs);
285 cache_push(addr, length);
289 t = (unsigned long *)((addr & 0x00ffffff) + (esp->edev));
291 dregs->clear_strobe = 0;
294 ctrl_data = ((ctrl_data & FASTLANE_DMA_MASK) |
295 FASTLANE_DMA_ENABLE |
297 dregs->ctrl_reg = ctrl_data;
300 static inline void dma_clear(struct NCR_ESP *esp)
302 struct fastlane_dma_registers *dregs =
303 (struct fastlane_dma_registers *) (esp->dregs);
306 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK);
307 dregs->ctrl_reg = ctrl_data;
309 t = (unsigned long *)(esp->edev);
311 dregs->clear_strobe = 0;
316 static void dma_ints_off(struct NCR_ESP *esp)
318 disable_irq(esp->irq);
321 static void dma_ints_on(struct NCR_ESP *esp)
323 enable_irq(esp->irq);
326 static void dma_irq_exit(struct NCR_ESP *esp)
328 struct fastlane_dma_registers *dregs =
329 (struct fastlane_dma_registers *) (esp->dregs);
331 dregs->ctrl_reg = ctrl_data & ~(FASTLANE_DMA_EDI|FASTLANE_DMA_ESI);
335 dregs->ctrl_reg = ctrl_data;
338 static int dma_irq_p(struct NCR_ESP *esp)
340 struct fastlane_dma_registers *dregs =
341 (struct fastlane_dma_registers *) (esp->dregs);
342 unsigned char dma_status;
344 dma_status = dregs->cond_reg;
346 if(dma_status & FASTLANE_DMA_IACT)
347 return 0; /* not our IRQ */
349 /* Return non-zero if ESP requested IRQ */
352 (dma_status & FASTLANE_DMA_CREQ) &&
354 (!(dma_status & FASTLANE_DMA_MINT)) &&
355 (esp_read(((struct ESP_regs *) (esp->eregs))->esp_status) & ESP_STAT_INTR));
358 static void dma_led_off(struct NCR_ESP *esp)
360 ctrl_data &= ~FASTLANE_DMA_LED;
361 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
364 static void dma_led_on(struct NCR_ESP *esp)
366 ctrl_data |= FASTLANE_DMA_LED;
367 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
370 static int dma_ports_p(struct NCR_ESP *esp)
372 return ((custom.intenar) & IF_PORTS);
375 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
377 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
378 * so when (write) is true, it actually means READ!
381 dma_init_read(esp, addr, count);
383 dma_init_write(esp, addr, count);
389 int fastlane_esp_release(struct Scsi_Host *instance)
392 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
393 esp_deallocate((struct NCR_ESP *)instance->hostdata);
395 release_mem_region(address, sizeof(struct ESP_regs));
396 free_irq(IRQ_AMIGA_PORTS, esp_intr);
402 static Scsi_Host_Template driver_template = {
403 .proc_name = "esp-fastlane",
404 .proc_info = esp_proc_info,
405 .name = "Fastlane SCSI",
406 .detect = fastlane_esp_detect,
407 .slave_alloc = esp_slave_alloc,
408 .slave_destroy = esp_slave_destroy,
409 .release = fastlane_esp_release,
410 .queuecommand = esp_queue,
411 .eh_abort_handler = esp_abort,
412 .eh_bus_reset_handler = esp_reset,
415 .sg_tablesize = SG_ALL,
417 .use_clustering = ENABLE_CLUSTERING
420 #include "scsi_module.c"
422 MODULE_LICENSE("GPL");