1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Enterprise Fibre Channel Host Bus Adapters. *
4 * Refer to the README file included with this package for *
5 * driver version and adapter support. *
6 * Copyright (C) 2004 Emulex Corporation. *
9 * This program is free software; you can redistribute it and/or *
10 * modify it under the terms of the GNU General Public License *
11 * as published by the Free Software Foundation; either version 2 *
12 * of the License, or (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details, a copy of which *
18 * can be found in the file COPYING included with this package. *
19 *******************************************************************/
22 * $Id: lpfc_hw.h 1.29 2004/11/18 17:28:05EST sf_support Exp $
28 #define FDMI_DID ((uint32_t)0xfffffa)
29 #define NameServer_DID ((uint32_t)0xfffffc)
30 #define SCR_DID ((uint32_t)0xfffffd)
31 #define Fabric_DID ((uint32_t)0xfffffe)
32 #define Bcast_DID ((uint32_t)0xffffff)
33 #define Mask_DID ((uint32_t)0xffffff)
34 #define CT_DID_MASK ((uint32_t)0xffff00)
35 #define Fabric_DID_MASK ((uint32_t)0xfff000)
36 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0)
38 #define PT2PT_LocalID ((uint32_t)1)
39 #define PT2PT_RemoteID ((uint32_t)2)
41 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
42 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
43 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
44 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
46 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
49 #define FCELSSIZE 1024 /* maximum ELS transfer size */
51 #define LPFC_FCP_RING 0 /* ring 2 for FCP initiator commands */
52 #define LPFC_IP_RING 1 /* ring 1 for IP commands */
53 #define LPFC_ELS_RING 2 /* ring 0 for ELS commands */
54 #define LPFC_FCP_NEXT_RING 3
56 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
57 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
58 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */
59 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */
60 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
61 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
62 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
63 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
64 #define SLI2_IOCB_CMD_R3_ENTRIES 0
65 #define SLI2_IOCB_RSP_R3_ENTRIES 0
66 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
67 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
69 /* Common Transport structures and definitions */
72 /* Structure is in Big Endian format */
80 union CtCommandResponse {
81 /* Structure is in Big Endian format */
89 struct lpfc_sli_ct_request {
90 /* Structure is in Big Endian format */
91 union CtRevisionId RevisionId;
96 union CtCommandResponse CommandResponse;
100 uint8_t VendorUnique;
105 uint8_t PortType; /* for GID_PT requests */
108 uint8_t Fc4Type; /* for GID_FT requests */
111 uint32_t PortId; /* For RFT_ID requests */
113 #ifdef __BIG_ENDIAN_BITFIELD
116 uint32_t fcpReg:1; /* Type 8 */
118 uint32_t ipReg:1; /* Type 5 */
120 #else /* __LITTLE_ENDIAN_BITFIELD */
122 uint32_t fcpReg:1; /* Type 8 */
125 uint32_t ipReg:1; /* Type 5 */
132 uint32_t PortId; /* For RNN_ID requests */
135 struct rsnn { /* For RSNN_ID requests */
138 uint8_t symbname[255];
143 #define SLI_CT_REVISION 1
144 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260)
145 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228)
146 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252)
147 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request))
153 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
154 #define SLI_CT_TIME_SERVICE 0xFB
155 #define SLI_CT_DIRECTORY_SERVICE 0xFC
156 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
159 * Directory Service Subtypes
162 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
168 #define SLI_CT_RESPONSE_FS_RJT 0x8001
169 #define SLI_CT_RESPONSE_FS_ACC 0x8002
175 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
176 #define SLI_CT_INVALID_COMMAND 0x01
177 #define SLI_CT_INVALID_VERSION 0x02
178 #define SLI_CT_LOGICAL_ERROR 0x03
179 #define SLI_CT_INVALID_IU_SIZE 0x04
180 #define SLI_CT_LOGICAL_BUSY 0x05
181 #define SLI_CT_PROTOCOL_ERROR 0x07
182 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
183 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
184 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
185 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
186 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
187 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
188 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
189 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
190 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
191 #define SLI_CT_VENDOR_UNIQUE 0xff
194 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
197 #define SLI_CT_NO_PORT_ID 0x01
198 #define SLI_CT_NO_PORT_NAME 0x02
199 #define SLI_CT_NO_NODE_NAME 0x03
200 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
201 #define SLI_CT_NO_IP_ADDRESS 0x05
202 #define SLI_CT_NO_IPA 0x06
203 #define SLI_CT_NO_FC4_TYPES 0x07
204 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
205 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
206 #define SLI_CT_NO_PORT_TYPE 0x0A
207 #define SLI_CT_ACCESS_DENIED 0x10
208 #define SLI_CT_INVALID_PORT_ID 0x11
209 #define SLI_CT_DATABASE_EMPTY 0x12
212 * Name Server Command Codes
215 #define SLI_CTNS_GA_NXT 0x0100
216 #define SLI_CTNS_GPN_ID 0x0112
217 #define SLI_CTNS_GNN_ID 0x0113
218 #define SLI_CTNS_GCS_ID 0x0114
219 #define SLI_CTNS_GFT_ID 0x0117
220 #define SLI_CTNS_GSPN_ID 0x0118
221 #define SLI_CTNS_GPT_ID 0x011A
222 #define SLI_CTNS_GID_PN 0x0121
223 #define SLI_CTNS_GID_NN 0x0131
224 #define SLI_CTNS_GIP_NN 0x0135
225 #define SLI_CTNS_GIPA_NN 0x0136
226 #define SLI_CTNS_GSNN_NN 0x0139
227 #define SLI_CTNS_GNN_IP 0x0153
228 #define SLI_CTNS_GIPA_IP 0x0156
229 #define SLI_CTNS_GID_FT 0x0171
230 #define SLI_CTNS_GID_PT 0x01A1
231 #define SLI_CTNS_RPN_ID 0x0212
232 #define SLI_CTNS_RNN_ID 0x0213
233 #define SLI_CTNS_RCS_ID 0x0214
234 #define SLI_CTNS_RFT_ID 0x0217
235 #define SLI_CTNS_RSPN_ID 0x0218
236 #define SLI_CTNS_RPT_ID 0x021A
237 #define SLI_CTNS_RIP_NN 0x0235
238 #define SLI_CTNS_RIPA_NN 0x0236
239 #define SLI_CTNS_RSNN_NN 0x0239
240 #define SLI_CTNS_DA_ID 0x0300
246 #define SLI_CTPT_N_PORT 0x01
247 #define SLI_CTPT_NL_PORT 0x02
248 #define SLI_CTPT_FNL_PORT 0x03
249 #define SLI_CTPT_IP 0x04
250 #define SLI_CTPT_FCP 0x08
251 #define SLI_CTPT_NX_PORT 0x7F
252 #define SLI_CTPT_F_PORT 0x81
253 #define SLI_CTPT_FL_PORT 0x82
254 #define SLI_CTPT_E_PORT 0x84
256 #define SLI_CT_LAST_ENTRY 0x80000000
258 /* Fibre Channel Service Parameter definitions */
260 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
261 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
262 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
263 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
265 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
266 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
267 #define FC_PH3 0x20 /* FC-PH-3 version */
269 #define FF_FRAME_SIZE 2048
272 #ifdef __BIG_ENDIAN_BITFIELD
273 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
274 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */
275 #else /* __LITTLE_ENDIAN_BITFIELD */
276 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */
277 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
280 #define NAME_IEEE 0x1 /* IEEE name - nameType */
281 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
282 #define NAME_FC_TYPE 0x3 /* FC native name type */
283 #define NAME_IP_TYPE 0x4 /* IP address */
284 #define NAME_CCITT_TYPE 0xC
285 #define NAME_CCITT_GR_TYPE 0xE
286 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE extended Lsb */
287 uint8_t IEEE[6]; /* FC IEEE address */
291 uint8_t fcphHigh; /* FC Word 0, byte 0 */
294 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
296 #ifdef __BIG_ENDIAN_BITFIELD
297 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
298 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
299 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
300 uint16_t fPort:1; /* FC Word 1, bit 28 */
301 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
302 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
303 uint16_t multicast:1; /* FC Word 1, bit 25 */
304 uint16_t broadcast:1; /* FC Word 1, bit 24 */
306 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
307 uint16_t simplex:1; /* FC Word 1, bit 22 */
308 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
309 uint16_t dhd:1; /* FC Word 1, bit 18 */
310 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
311 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
312 #else /* __LITTLE_ENDIAN_BITFIELD */
313 uint16_t broadcast:1; /* FC Word 1, bit 24 */
314 uint16_t multicast:1; /* FC Word 1, bit 25 */
315 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
316 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
317 uint16_t fPort:1; /* FC Word 1, bit 28 */
318 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
319 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
320 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
322 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
323 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
324 uint16_t dhd:1; /* FC Word 1, bit 18 */
325 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
326 uint16_t simplex:1; /* FC Word 1, bit 22 */
327 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
330 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
331 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
334 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
336 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
337 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
339 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
341 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
344 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
348 #ifdef __BIG_ENDIAN_BITFIELD
349 uint8_t classValid:1; /* FC Word 0, bit 31 */
350 uint8_t intermix:1; /* FC Word 0, bit 30 */
351 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
352 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
353 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
354 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
355 #else /* __LITTLE_ENDIAN_BITFIELD */
356 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
357 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
358 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
359 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
360 uint8_t intermix:1; /* FC Word 0, bit 30 */
361 uint8_t classValid:1; /* FC Word 0, bit 31 */
365 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
367 #ifdef __BIG_ENDIAN_BITFIELD
368 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
369 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
370 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
371 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
372 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
373 #else /* __LITTLE_ENDIAN_BITFIELD */
374 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
375 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
376 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
377 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
378 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
381 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
383 #ifdef __BIG_ENDIAN_BITFIELD
384 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
385 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
386 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
387 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
388 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
389 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
390 #else /* __LITTLE_ENDIAN_BITFIELD */
391 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
392 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
393 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
394 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
395 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
396 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
399 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
400 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
401 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
403 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
404 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
405 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
406 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
408 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
409 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
410 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
411 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
414 struct serv_parm { /* Structure is in Big Endian format */
416 struct lpfc_name portName;
417 struct lpfc_name nodeName;
418 struct class_parms cls1;
419 struct class_parms cls2;
420 struct class_parms cls3;
421 struct class_parms cls4;
422 uint8_t vendorVersion[16];
426 * Extended Link Service LS_COMMAND codes (Payload Word 0)
428 #ifdef __BIG_ENDIAN_BITFIELD
429 #define ELS_CMD_MASK 0xffff0000
430 #define ELS_RSP_MASK 0xff000000
431 #define ELS_CMD_LS_RJT 0x01000000
432 #define ELS_CMD_ACC 0x02000000
433 #define ELS_CMD_PLOGI 0x03000000
434 #define ELS_CMD_FLOGI 0x04000000
435 #define ELS_CMD_LOGO 0x05000000
436 #define ELS_CMD_ABTX 0x06000000
437 #define ELS_CMD_RCS 0x07000000
438 #define ELS_CMD_RES 0x08000000
439 #define ELS_CMD_RSS 0x09000000
440 #define ELS_CMD_RSI 0x0A000000
441 #define ELS_CMD_ESTS 0x0B000000
442 #define ELS_CMD_ESTC 0x0C000000
443 #define ELS_CMD_ADVC 0x0D000000
444 #define ELS_CMD_RTV 0x0E000000
445 #define ELS_CMD_RLS 0x0F000000
446 #define ELS_CMD_ECHO 0x10000000
447 #define ELS_CMD_TEST 0x11000000
448 #define ELS_CMD_RRQ 0x12000000
449 #define ELS_CMD_PRLI 0x20100014
450 #define ELS_CMD_PRLO 0x21100014
451 #define ELS_CMD_PDISC 0x50000000
452 #define ELS_CMD_FDISC 0x51000000
453 #define ELS_CMD_ADISC 0x52000000
454 #define ELS_CMD_FARP 0x54000000
455 #define ELS_CMD_FARPR 0x55000000
456 #define ELS_CMD_FAN 0x60000000
457 #define ELS_CMD_RSCN 0x61040000
458 #define ELS_CMD_SCR 0x62000000
459 #define ELS_CMD_RNID 0x78000000
460 #else /* __LITTLE_ENDIAN_BITFIELD */
461 #define ELS_CMD_MASK 0xffff
462 #define ELS_RSP_MASK 0xff
463 #define ELS_CMD_LS_RJT 0x01
464 #define ELS_CMD_ACC 0x02
465 #define ELS_CMD_PLOGI 0x03
466 #define ELS_CMD_FLOGI 0x04
467 #define ELS_CMD_LOGO 0x05
468 #define ELS_CMD_ABTX 0x06
469 #define ELS_CMD_RCS 0x07
470 #define ELS_CMD_RES 0x08
471 #define ELS_CMD_RSS 0x09
472 #define ELS_CMD_RSI 0x0A
473 #define ELS_CMD_ESTS 0x0B
474 #define ELS_CMD_ESTC 0x0C
475 #define ELS_CMD_ADVC 0x0D
476 #define ELS_CMD_RTV 0x0E
477 #define ELS_CMD_RLS 0x0F
478 #define ELS_CMD_ECHO 0x10
479 #define ELS_CMD_TEST 0x11
480 #define ELS_CMD_RRQ 0x12
481 #define ELS_CMD_PRLI 0x14001020
482 #define ELS_CMD_PRLO 0x14001021
483 #define ELS_CMD_PDISC 0x50
484 #define ELS_CMD_FDISC 0x51
485 #define ELS_CMD_ADISC 0x52
486 #define ELS_CMD_FARP 0x54
487 #define ELS_CMD_FARPR 0x55
488 #define ELS_CMD_FAN 0x60
489 #define ELS_CMD_RSCN 0x0461
490 #define ELS_CMD_SCR 0x62
491 #define ELS_CMD_RNID 0x78
495 * LS_RJT Payload Definition
498 struct ls_rjt { /* Structure is in Big Endian format */
502 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
504 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
505 /* LS_RJT reason codes */
506 #define LSRJT_INVALID_CMD 0x01
507 #define LSRJT_LOGICAL_ERR 0x03
508 #define LSRJT_LOGICAL_BSY 0x05
509 #define LSRJT_PROTOCOL_ERR 0x07
510 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
511 #define LSRJT_CMD_UNSUPPORTED 0x0B
512 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
514 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
515 /* LS_RJT reason explanation */
516 #define LSEXP_NOTHING_MORE 0x00
517 #define LSEXP_SPARM_OPTIONS 0x01
518 #define LSEXP_SPARM_ICTL 0x03
519 #define LSEXP_SPARM_RCTL 0x05
520 #define LSEXP_SPARM_RCV_SIZE 0x07
521 #define LSEXP_SPARM_CONCUR_SEQ 0x09
522 #define LSEXP_SPARM_CREDIT 0x0B
523 #define LSEXP_INVALID_PNAME 0x0D
524 #define LSEXP_INVALID_NNAME 0x0E
525 #define LSEXP_INVALID_CSP 0x0F
526 #define LSEXP_INVALID_ASSOC_HDR 0x11
527 #define LSEXP_ASSOC_HDR_REQ 0x13
528 #define LSEXP_INVALID_O_SID 0x15
529 #define LSEXP_INVALID_OX_RX 0x17
530 #define LSEXP_CMD_IN_PROGRESS 0x19
531 #define LSEXP_INVALID_NPORT_ID 0x1F
532 #define LSEXP_INVALID_SEQ_ID 0x21
533 #define LSEXP_INVALID_XCHG 0x23
534 #define LSEXP_INACTIVE_XCHG 0x25
535 #define LSEXP_RQ_REQUIRED 0x27
536 #define LSEXP_OUT_OF_RESOURCE 0x29
537 #define LSEXP_CANT_GIVE_DATA 0x2A
538 #define LSEXP_REQ_UNSUPPORTED 0x2C
539 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
545 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
548 typedef struct _LOGO { /* Structure is in Big Endian format */
550 uint32_t nPortId32; /* Access nPortId as a word */
552 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
553 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
554 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
555 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
558 struct lpfc_name portName; /* N_port name field */
562 * FCP Login (PRLI Request / ACC) Payload Definition
565 #define PRLX_PAGE_LEN 0x10
566 #define TPRLO_PAGE_LEN 0x14
568 typedef struct _PRLI { /* Structure is in Big Endian format */
569 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
571 #define PRLI_FCP_TYPE 0x08
572 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
574 #ifdef __BIG_ENDIAN_BITFIELD
575 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
576 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
577 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
579 /* ACC = imagePairEstablished */
580 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
581 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
582 #else /* __LITTLE_ENDIAN_BITFIELD */
583 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
584 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
585 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
586 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
587 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
588 /* ACC = imagePairEstablished */
591 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
592 #define PRLI_NO_RESOURCES 0x2
593 #define PRLI_INIT_INCOMPLETE 0x3
594 #define PRLI_NO_SUCH_PA 0x4
595 #define PRLI_PREDEF_CONFIG 0x5
596 #define PRLI_PARTIAL_SUCCESS 0x6
597 #define PRLI_INVALID_PAGE_CNT 0x7
598 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
600 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
602 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
604 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
605 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
607 #ifdef __BIG_ENDIAN_BITFIELD
608 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
609 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
610 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
611 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
612 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
613 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
614 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
615 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
616 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
617 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
618 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
619 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
620 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
621 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
622 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
623 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
624 #else /* __LITTLE_ENDIAN_BITFIELD */
625 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
626 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
627 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
628 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
629 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
630 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
631 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
632 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
633 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
634 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
635 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
636 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
637 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
638 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
639 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
640 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
645 * FCP Logout (PRLO Request / ACC) Payload Definition
648 typedef struct _PRLO { /* Structure is in Big Endian format */
649 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
651 #define PRLO_FCP_TYPE 0x08
652 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
654 #ifdef __BIG_ENDIAN_BITFIELD
655 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
656 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
657 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
658 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
659 #else /* __LITTLE_ENDIAN_BITFIELD */
660 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
661 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
662 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
663 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
666 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
667 #define PRLO_NO_SUCH_IMAGE 0x4
668 #define PRLO_INVALID_PAGE_CNT 0x7
670 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
672 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
674 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
676 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
679 typedef struct _ADISC { /* Structure is in Big Endian format */
681 struct lpfc_name portName;
682 struct lpfc_name nodeName;
686 typedef struct _FARP { /* Structure is in Big Endian format */
689 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
691 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
692 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
693 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
694 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
696 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
700 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
701 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
702 struct lpfc_name OportName;
703 struct lpfc_name OnodeName;
704 struct lpfc_name RportName;
705 struct lpfc_name RnodeName;
710 typedef struct _FAN { /* Structure is in Big Endian format */
712 struct lpfc_name FportName;
713 struct lpfc_name FnodeName;
716 typedef struct _SCR { /* Structure is in Big Endian format */
721 #define SCR_FUNC_FABRIC 0x01
722 #define SCR_FUNC_NPORT 0x02
723 #define SCR_FUNC_FULL 0x03
724 #define SCR_CLEAR 0xff
727 typedef struct _RNID_TOP_DISC {
728 struct lpfc_name portName;
732 #define RNID_HOST 0xa
733 #define RNID_DRIVER 0xd
735 uint32_t attachedNodes;
737 #define RNID_IPV4 0x1
738 #define RNID_IPV6 0x2
743 #define RNID_TD_SUPPORT 0x1
744 #define RNID_LP_VALID 0x2
747 typedef struct _RNID { /* Structure is in Big Endian format */
749 #define RNID_TOPOLOGY_DISC 0xdf
753 struct lpfc_name portName;
754 struct lpfc_name nodeName;
756 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
760 typedef struct _RRQ { /* Structure is in Big Endian format */
764 uint8_t resv[32]; /* optional association hdr */
767 /* This is used for RSCN command */
768 typedef struct _D_ID { /* Structure is in Big Endian format */
772 #ifdef __BIG_ENDIAN_BITFIELD
777 #else /* __LITTLE_ENDIAN_BITFIELD */
788 * Structure to define all ELS Payload types
791 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
792 uint8_t elsCode; /* FC Word 0, bit 24:31 */
797 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
798 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
799 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
800 PRLI prli; /* Payload for PRLI/ACC */
801 PRLO prlo; /* Payload for PRLO/ACC */
802 ADISC adisc; /* Payload for ADISC/ACC */
803 FARP farp; /* Payload for FARP/ACC */
804 FAN fan; /* Payload for FAN */
805 SCR scr; /* Payload for SCR/ACC */
806 RRQ rrq; /* Payload for RRQ */
807 RNID rnid; /* Payload for RNID */
808 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
814 * HBA MAnagement Operations Command Codes
816 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
817 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
818 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
819 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
820 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
821 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
822 #define SLI_MGMT_RPRT 0x210 /* Register Port */
823 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
824 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
825 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
828 * Management Service Subtypes
830 #define SLI_CT_FDMI_Subtypes 0x10
833 * HBA Management Service Reject Code
835 #define REJECT_CODE 0x9 /* Unable to perform command request */
838 * HBA Management Service Reject Reason Code
839 * Please refer to the Reason Codes above
843 * HBA Attribute Types
845 #define NODE_NAME 0x1
846 #define MANUFACTURER 0x2
847 #define SERIAL_NUMBER 0x3
849 #define MODEL_DESCRIPTION 0x5
850 #define HARDWARE_VERSION 0x6
851 #define DRIVER_VERSION 0x7
852 #define OPTION_ROM_VERSION 0x8
853 #define FIRMWARE_VERSION 0x9
854 #define OS_NAME_VERSION 0xa
855 #define MAX_CT_PAYLOAD_LEN 0xb
858 * Port Attrubute Types
860 #define SUPPORTED_FC4_TYPES 0x1
861 #define SUPPORTED_SPEED 0x2
862 #define PORT_SPEED 0x3
863 #define MAX_FRAME_SIZE 0x4
864 #define OS_DEVICE_NAME 0x5
865 #define HOST_NAME 0x6
867 union AttributesDef {
868 /* Structure is in Big Endian format */
870 uint32_t AttrType:16;
878 * HBA Attribute Entry (8 - 260 bytes)
881 union AttributesDef ad;
883 uint32_t VendorSpecific;
884 uint8_t Manufacturer[64];
885 uint8_t SerialNumber[64];
887 uint8_t ModelDescription[256];
888 uint8_t HardwareVersion[256];
889 uint8_t DriverVersion[256];
890 uint8_t OptionROMVersion[256];
891 uint8_t FirmwareVersion[256];
892 struct lpfc_name NodeName;
893 uint8_t SupportFC4Types[32];
894 uint32_t SupportSpeed;
896 uint32_t MaxFrameSize;
897 uint8_t OsDeviceName[256];
898 uint8_t OsNameVersion[256];
899 uint32_t MaxCTPayloadLen;
900 uint8_t HostName[256];
905 * HBA Attribute Block
908 uint32_t EntryCnt; /* Number of HBA attribute entries */
909 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
916 struct lpfc_name PortName;
923 struct lpfc_name PortName;
927 * Registered Port List Format
931 PORT_ENTRY pe; /* Variable-length array */
939 REG_PORT_LIST rpl; /* variable-length array */
940 /* ATTRIBUTE_BLOCK ab; */
944 * Register HBA Attributes (RHAT)
947 struct lpfc_name HBA_PortName;
952 * Register Port Attributes (RPA)
955 struct lpfc_name PortName;
957 } REG_PORT_ATTRIBUTE;
960 * Get Registered HBA List (GRHL) Accept Payload Format
963 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
964 struct lpfc_name HBA_PortName; /* Variable-length array */
968 * Get Registered Port List (GRPL) Accept Payload Format
971 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
972 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
976 * Get Port Attributes (GPAT) Accept Payload Format
985 * Begin HBA configuration parameters.
986 * The PCI configuration register BAR assignments are:
987 * BAR0, offset 0x10 - SLIM base memory address
988 * BAR1, offset 0x14 - SLIM base memory high address
989 * BAR2, offset 0x18 - REGISTER base memory address
990 * BAR3, offset 0x1c - REGISTER base memory high address
991 * BAR4, offset 0x20 - BIU I/O registers
992 * BAR5, offset 0x24 - REGISTER base io high address
995 /* Number of rings currently used and available. */
996 #define MAX_CONFIGURED_RINGS 3
999 /* IOCB / Mailbox is owned by FireFly */
1002 /* IOCB / Mailbox is owned by Host */
1005 /* Number of 4-byte words in an IOCB. */
1006 #define IOCB_WORD_SZ 8
1008 /* defines for type field in fc header */
1009 #define FC_ELS_DATA 0x1
1010 #define FC_LLC_SNAP 0x5
1011 #define FC_FCP_DATA 0x8
1012 #define FC_COMMON_TRANSPORT_ULP 0x20
1014 /* defines for rctl field in fc header */
1015 #define FC_DEV_DATA 0x0
1016 #define FC_UNSOL_CTL 0x2
1017 #define FC_SOL_CTL 0x3
1018 #define FC_UNSOL_DATA 0x4
1019 #define FC_FCP_CMND 0x6
1020 #define FC_ELS_REQ 0x22
1021 #define FC_ELS_RSP 0x23
1023 /* network headers for Dfctl field */
1024 #define FC_NET_HDR 0x20
1026 /* Start FireFly Register definitions */
1027 #define PCI_VENDOR_ID_EMULEX 0x10df
1028 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1029 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1030 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1031 #define PCI_DEVICE_ID_RFLY 0xf095
1032 #define PCI_DEVICE_ID_PFLY 0xf098
1033 #define PCI_DEVICE_ID_TFLY 0xf0a5
1034 #define PCI_DEVICE_ID_CENTAUR 0xf900
1035 #define PCI_DEVICE_ID_PEGASUS 0xf980
1036 #define PCI_DEVICE_ID_THOR 0xfa00
1037 #define PCI_DEVICE_ID_VIPER 0xfb00
1038 #define PCI_DEVICE_ID_HELIOS 0xfd00
1039 #define PCI_DEVICE_ID_BMID 0xf0d5
1040 #define PCI_DEVICE_ID_BSMB 0xf0d1
1041 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1042 #define PCI_DEVICE_ID_ZMID 0xf0e5
1043 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1044 #define PCI_DEVICE_ID_LP101 0xf0a1
1046 #define JEDEC_ID_ADDRESS 0x0080001c
1047 #define FIREFLY_JEDEC_ID 0x1ACC
1048 #define SUPERFLY_JEDEC_ID 0x0020
1049 #define DRAGONFLY_JEDEC_ID 0x0021
1050 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1051 #define CENTAUR_2G_JEDEC_ID 0x0026
1052 #define CENTAUR_1G_JEDEC_ID 0x0028
1053 #define PEGASUS_ORION_JEDEC_ID 0x0036
1054 #define PEGASUS_JEDEC_ID 0x0038
1055 #define THOR_JEDEC_ID 0x0012
1056 #define HELIOS_JEDEC_ID 0x0364
1057 #define ZEPHYR_JEDEC_ID 0x0577
1058 #define VIPER_JEDEC_ID 0x4838
1060 #define JEDEC_ID_MASK 0x0FFFF000
1061 #define JEDEC_ID_SHIFT 12
1062 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1064 typedef struct { /* FireFly BIU registers */
1065 uint32_t hostAtt; /* See definitions for Host Attention
1067 uint32_t chipAtt; /* See definitions for Chip Attention
1069 uint32_t hostStatus; /* See definitions for Host Status register */
1070 uint32_t hostControl; /* See definitions for Host Control register */
1071 uint32_t buiConfig; /* See definitions for BIU configuration
1075 /* IO Register size in bytes */
1076 #define FF_REG_AREA_SIZE 256
1078 /* Host Attention Register */
1080 #define HA_REG_OFFSET 0 /* Word offset from register base address */
1082 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1083 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1084 #define HA_R0ATT 0x00000008 /* Bit 3 */
1085 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1086 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1087 #define HA_R1ATT 0x00000080 /* Bit 7 */
1088 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1089 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1090 #define HA_R2ATT 0x00000800 /* Bit 11 */
1091 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1092 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1093 #define HA_R3ATT 0x00008000 /* Bit 15 */
1094 #define HA_LATT 0x20000000 /* Bit 29 */
1095 #define HA_MBATT 0x40000000 /* Bit 30 */
1096 #define HA_ERATT 0x80000000 /* Bit 31 */
1098 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1099 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1100 #define HA_RXATT 0x00000008 /* Bit 3 */
1101 #define HA_RXMASK 0x0000000f
1103 /* Chip Attention Register */
1105 #define CA_REG_OFFSET 1 /* Word offset from register base address */
1107 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1108 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1109 #define CA_R0ATT 0x00000008 /* Bit 3 */
1110 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1111 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1112 #define CA_R1ATT 0x00000080 /* Bit 7 */
1113 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1114 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1115 #define CA_R2ATT 0x00000800 /* Bit 11 */
1116 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1117 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1118 #define CA_R3ATT 0x00008000 /* Bit 15 */
1119 #define CA_MBATT 0x40000000 /* Bit 30 */
1121 /* Host Status Register */
1123 #define HS_REG_OFFSET 2 /* Word offset from register base address */
1125 #define HS_MBRDY 0x00400000 /* Bit 22 */
1126 #define HS_FFRDY 0x00800000 /* Bit 23 */
1127 #define HS_FFER8 0x01000000 /* Bit 24 */
1128 #define HS_FFER7 0x02000000 /* Bit 25 */
1129 #define HS_FFER6 0x04000000 /* Bit 26 */
1130 #define HS_FFER5 0x08000000 /* Bit 27 */
1131 #define HS_FFER4 0x10000000 /* Bit 28 */
1132 #define HS_FFER3 0x20000000 /* Bit 29 */
1133 #define HS_FFER2 0x40000000 /* Bit 30 */
1134 #define HS_FFER1 0x80000000 /* Bit 31 */
1135 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1137 /* Host Control Register */
1139 #define HC_REG_OFFSET 3 /* Word offset from register base address */
1141 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1142 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1143 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1144 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1145 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1146 #define HC_INITHBI 0x02000000 /* Bit 25 */
1147 #define HC_INITMB 0x04000000 /* Bit 26 */
1148 #define HC_INITFF 0x08000000 /* Bit 27 */
1149 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1150 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1152 /* Mailbox Commands */
1153 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1154 #define MBX_LOAD_SM 0x01
1155 #define MBX_READ_NV 0x02
1156 #define MBX_WRITE_NV 0x03
1157 #define MBX_RUN_BIU_DIAG 0x04
1158 #define MBX_INIT_LINK 0x05
1159 #define MBX_DOWN_LINK 0x06
1160 #define MBX_CONFIG_LINK 0x07
1161 #define MBX_CONFIG_RING 0x09
1162 #define MBX_RESET_RING 0x0A
1163 #define MBX_READ_CONFIG 0x0B
1164 #define MBX_READ_RCONFIG 0x0C
1165 #define MBX_READ_SPARM 0x0D
1166 #define MBX_READ_STATUS 0x0E
1167 #define MBX_READ_RPI 0x0F
1168 #define MBX_READ_XRI 0x10
1169 #define MBX_READ_REV 0x11
1170 #define MBX_READ_LNK_STAT 0x12
1171 #define MBX_REG_LOGIN 0x13
1172 #define MBX_UNREG_LOGIN 0x14
1173 #define MBX_READ_LA 0x15
1174 #define MBX_CLEAR_LA 0x16
1175 #define MBX_DUMP_MEMORY 0x17
1176 #define MBX_DUMP_CONTEXT 0x18
1177 #define MBX_RUN_DIAGS 0x19
1178 #define MBX_RESTART 0x1A
1179 #define MBX_UPDATE_CFG 0x1B
1180 #define MBX_DOWN_LOAD 0x1C
1181 #define MBX_DEL_LD_ENTRY 0x1D
1182 #define MBX_RUN_PROGRAM 0x1E
1183 #define MBX_SET_MASK 0x20
1184 #define MBX_SET_SLIM 0x21
1185 #define MBX_UNREG_D_ID 0x23
1186 #define MBX_CONFIG_FARP 0x25
1188 #define MBX_LOAD_AREA 0x81
1189 #define MBX_RUN_BIU_DIAG64 0x84
1190 #define MBX_CONFIG_PORT 0x88
1191 #define MBX_READ_SPARM64 0x8D
1192 #define MBX_READ_RPI64 0x8F
1193 #define MBX_REG_LOGIN64 0x93
1194 #define MBX_READ_LA64 0x95
1196 #define MBX_FLASH_WR_ULA 0x98
1197 #define MBX_SET_DEBUG 0x99
1198 #define MBX_LOAD_EXP_ROM 0x9C
1200 #define MBX_MAX_CMDS 0x9D
1201 #define MBX_SLI2_CMD_MASK 0x80
1205 #define CMD_RCV_SEQUENCE_CX 0x01
1206 #define CMD_XMIT_SEQUENCE_CR 0x02
1207 #define CMD_XMIT_SEQUENCE_CX 0x03
1208 #define CMD_XMIT_BCAST_CN 0x04
1209 #define CMD_XMIT_BCAST_CX 0x05
1210 #define CMD_QUE_RING_BUF_CN 0x06
1211 #define CMD_QUE_XRI_BUF_CX 0x07
1212 #define CMD_IOCB_CONTINUE_CN 0x08
1213 #define CMD_RET_XRI_BUF_CX 0x09
1214 #define CMD_ELS_REQUEST_CR 0x0A
1215 #define CMD_ELS_REQUEST_CX 0x0B
1216 #define CMD_RCV_ELS_REQ_CX 0x0D
1217 #define CMD_ABORT_XRI_CN 0x0E
1218 #define CMD_ABORT_XRI_CX 0x0F
1219 #define CMD_CLOSE_XRI_CN 0x10
1220 #define CMD_CLOSE_XRI_CX 0x11
1221 #define CMD_CREATE_XRI_CR 0x12
1222 #define CMD_CREATE_XRI_CX 0x13
1223 #define CMD_GET_RPI_CN 0x14
1224 #define CMD_XMIT_ELS_RSP_CX 0x15
1225 #define CMD_GET_RPI_CR 0x16
1226 #define CMD_XRI_ABORTED_CX 0x17
1227 #define CMD_FCP_IWRITE_CR 0x18
1228 #define CMD_FCP_IWRITE_CX 0x19
1229 #define CMD_FCP_IREAD_CR 0x1A
1230 #define CMD_FCP_IREAD_CX 0x1B
1231 #define CMD_FCP_ICMND_CR 0x1C
1232 #define CMD_FCP_ICMND_CX 0x1D
1234 #define CMD_ADAPTER_MSG 0x20
1235 #define CMD_ADAPTER_DUMP 0x22
1237 /* SLI_2 IOCB Command Set */
1239 #define CMD_RCV_SEQUENCE64_CX 0x81
1240 #define CMD_XMIT_SEQUENCE64_CR 0x82
1241 #define CMD_XMIT_SEQUENCE64_CX 0x83
1242 #define CMD_XMIT_BCAST64_CN 0x84
1243 #define CMD_XMIT_BCAST64_CX 0x85
1244 #define CMD_QUE_RING_BUF64_CN 0x86
1245 #define CMD_QUE_XRI_BUF64_CX 0x87
1246 #define CMD_IOCB_CONTINUE64_CN 0x88
1247 #define CMD_RET_XRI_BUF64_CX 0x89
1248 #define CMD_ELS_REQUEST64_CR 0x8A
1249 #define CMD_ELS_REQUEST64_CX 0x8B
1250 #define CMD_ABORT_MXRI64_CN 0x8C
1251 #define CMD_RCV_ELS_REQ64_CX 0x8D
1252 #define CMD_XMIT_ELS_RSP64_CX 0x95
1253 #define CMD_FCP_IWRITE64_CR 0x98
1254 #define CMD_FCP_IWRITE64_CX 0x99
1255 #define CMD_FCP_IREAD64_CR 0x9A
1256 #define CMD_FCP_IREAD64_CX 0x9B
1257 #define CMD_FCP_ICMND64_CR 0x9C
1258 #define CMD_FCP_ICMND64_CX 0x9D
1260 #define CMD_GEN_REQUEST64_CR 0xC2
1261 #define CMD_GEN_REQUEST64_CX 0xC3
1263 #define CMD_MAX_IOCB_CMD 0xE6
1264 #define CMD_IOCB_MASK 0xff
1266 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1268 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1272 #define MBX_SUCCESS 0
1273 #define MBXERR_NUM_RINGS 1
1274 #define MBXERR_NUM_IOCBS 2
1275 #define MBXERR_IOCBS_EXCEEDED 3
1276 #define MBXERR_BAD_RING_NUMBER 4
1277 #define MBXERR_MASK_ENTRIES_RANGE 5
1278 #define MBXERR_MASKS_EXCEEDED 6
1279 #define MBXERR_BAD_PROFILE 7
1280 #define MBXERR_BAD_DEF_CLASS 8
1281 #define MBXERR_BAD_MAX_RESPONDER 9
1282 #define MBXERR_BAD_MAX_ORIGINATOR 10
1283 #define MBXERR_RPI_REGISTERED 11
1284 #define MBXERR_RPI_FULL 12
1285 #define MBXERR_NO_RESOURCES 13
1286 #define MBXERR_BAD_RCV_LENGTH 14
1287 #define MBXERR_DMA_ERROR 15
1288 #define MBXERR_ERROR 16
1289 #define MBX_NOT_FINISHED 255
1291 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1292 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1295 * Begin Structure Definitions for Mailbox Commands
1299 #ifdef __BIG_ENDIAN_BITFIELD
1304 #else /* __LITTLE_ENDIAN_BITFIELD */
1313 uint32_t bdeAddress;
1314 #ifdef __BIG_ENDIAN_BITFIELD
1315 uint32_t bdeReserved:4;
1316 uint32_t bdeAddrHigh:4;
1317 uint32_t bdeSize:24;
1318 #else /* __LITTLE_ENDIAN_BITFIELD */
1319 uint32_t bdeSize:24;
1320 uint32_t bdeAddrHigh:4;
1321 uint32_t bdeReserved:4;
1325 struct ulp_bde64 { /* SLI-2 */
1329 #ifdef __BIG_ENDIAN_BITFIELD
1330 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1332 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1333 #else /* __LITTLE_ENDIAN_BITFIELD */
1334 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1335 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1339 #define BUFF_USE_RSVD 0x01 /* bdeFlags */
1340 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1341 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1342 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1344 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1346 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1347 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1348 #define BUFF_TYPE_INVALID 0x80 /* "" "" */
1354 #define BDE64_SIZE_WORD 0
1355 #define BPL64_SIZE_WORD 0x40
1357 typedef struct ULP_BDL { /* SLI-2 */
1358 #ifdef __BIG_ENDIAN_BITFIELD
1359 uint32_t bdeFlags:8; /* BDL Flags */
1360 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1361 #else /* __LITTLE_ENDIAN_BITFIELD */
1362 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1363 uint32_t bdeFlags:8; /* BDL Flags */
1366 uint32_t addrLow; /* Address 0:31 */
1367 uint32_t addrHigh; /* Address 32:63 */
1368 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1371 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1374 #ifdef __BIG_ENDIAN_BITFIELD
1376 uint32_t acknowledgment:1;
1378 uint32_t erase_or_prog:1;
1379 uint32_t update_flash:1;
1380 uint32_t update_ram:1;
1382 uint32_t load_cmplt:1;
1383 #else /* __LITTLE_ENDIAN_BITFIELD */
1384 uint32_t load_cmplt:1;
1386 uint32_t update_ram:1;
1387 uint32_t update_flash:1;
1388 uint32_t erase_or_prog:1;
1390 uint32_t acknowledgment:1;
1394 uint32_t dl_to_adr_low;
1395 uint32_t dl_to_adr_high;
1398 uint32_t dl_from_mbx_offset;
1399 struct ulp_bde dl_from_bde;
1400 struct ulp_bde64 dl_from_bde64;
1405 /* Structure for MB Command READ_NVPARM (02) */
1408 uint32_t rsvd1[3]; /* Read as all one's */
1409 uint32_t rsvd2; /* Read as all zero's */
1410 uint32_t portname[2]; /* N_PORT name */
1411 uint32_t nodename[2]; /* NODE name */
1413 #ifdef __BIG_ENDIAN_BITFIELD
1414 uint32_t pref_DID:24;
1415 uint32_t hardAL_PA:8;
1416 #else /* __LITTLE_ENDIAN_BITFIELD */
1417 uint32_t hardAL_PA:8;
1418 uint32_t pref_DID:24;
1421 uint32_t rsvd3[21]; /* Read as all one's */
1424 /* Structure for MB Command WRITE_NVPARMS (03) */
1427 uint32_t rsvd1[3]; /* Must be all one's */
1428 uint32_t rsvd2; /* Must be all zero's */
1429 uint32_t portname[2]; /* N_PORT name */
1430 uint32_t nodename[2]; /* NODE name */
1432 #ifdef __BIG_ENDIAN_BITFIELD
1433 uint32_t pref_DID:24;
1434 uint32_t hardAL_PA:8;
1435 #else /* __LITTLE_ENDIAN_BITFIELD */
1436 uint32_t hardAL_PA:8;
1437 uint32_t pref_DID:24;
1440 uint32_t rsvd3[21]; /* Must be all one's */
1443 /* Structure for MB Command RUN_BIU_DIAG (04) */
1444 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1450 struct ulp_bde xmit_bde;
1451 struct ulp_bde rcv_bde;
1454 struct ulp_bde64 xmit_bde64;
1455 struct ulp_bde64 rcv_bde64;
1460 /* Structure for MB Command INIT_LINK (05) */
1463 #ifdef __BIG_ENDIAN_BITFIELD
1465 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1466 #else /* __LITTLE_ENDIAN_BITFIELD */
1467 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1471 #ifdef __BIG_ENDIAN_BITFIELD
1472 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1474 uint16_t link_flags;
1475 #else /* __LITTLE_ENDIAN_BITFIELD */
1476 uint16_t link_flags;
1478 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1481 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1482 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1483 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1484 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1485 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1486 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1488 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1489 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1491 uint32_t link_speed;
1492 #define LINK_SPEED_AUTO 0 /* Auto selection */
1493 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1494 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1495 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1496 #define LINK_SPEED_8G 8 /* 4 Gigabaud */
1497 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1501 /* Structure for MB Command DOWN_LINK (06) */
1507 /* Structure for MB Command CONFIG_LINK (07) */
1510 #ifdef __BIG_ENDIAN_BITFIELD
1513 uint32_t cr_delay:6;
1514 uint32_t cr_count:8;
1517 #else /* __LITTLE_ENDIAN_BITFIELD */
1520 uint32_t cr_count:8;
1521 uint32_t cr_delay:6;
1535 #ifdef __BIG_ENDIAN_BITFIELD
1536 uint32_t rrq_enable:1;
1537 uint32_t rrq_immed:1;
1539 uint32_t ack0_enable:1;
1540 #else /* __LITTLE_ENDIAN_BITFIELD */
1541 uint32_t ack0_enable:1;
1543 uint32_t rrq_immed:1;
1544 uint32_t rrq_enable:1;
1548 /* Structure for MB Command PART_SLIM (08)
1549 * will be removed since SLI1 is no longer supported!
1552 #ifdef __BIG_ENDIAN_BITFIELD
1557 #else /* __LITTLE_ENDIAN_BITFIELD */
1566 #ifdef __BIG_ENDIAN_BITFIELD
1567 uint32_t unused1:24;
1569 #else /* __LITTLE_ENDIAN_BITFIELD */
1571 uint32_t unused1:24;
1574 RING_DEF ringdef[4];
1578 /* Structure for MB Command CONFIG_RING (09) */
1581 #ifdef __BIG_ENDIAN_BITFIELD
1584 uint32_t recvNotify:1;
1589 #else /* __LITTLE_ENDIAN_BITFIELD */
1594 uint32_t recvNotify:1;
1599 #ifdef __BIG_ENDIAN_BITFIELD
1600 uint16_t maxRespXchg;
1601 uint16_t maxOrigXchg;
1602 #else /* __LITTLE_ENDIAN_BITFIELD */
1603 uint16_t maxOrigXchg;
1604 uint16_t maxRespXchg;
1610 /* Structure for MB Command RESET_RING (10) */
1616 /* Structure for MB Command READ_CONFIG (11) */
1619 #ifdef __BIG_ENDIAN_BITFIELD
1622 uint32_t cr_delay:6;
1623 uint32_t cr_count:8;
1626 #else /* __LITTLE_ENDIAN_BITFIELD */
1629 uint32_t cr_count:8;
1630 uint32_t cr_delay:6;
1635 #ifdef __BIG_ENDIAN_BITFIELD
1636 uint32_t topology:8;
1638 #else /* __LITTLE_ENDIAN_BITFIELD */
1640 uint32_t topology:8;
1643 /* Defines for topology (defined previously) */
1644 #ifdef __BIG_ENDIAN_BITFIELD
1649 #else /* __LITTLE_ENDIAN_BITFIELD */
1662 #define LMT_RESERVED 0x0 /* Not used */
1663 #define LMT_266_10bit 0x1 /* 265.625 Mbaud 10 bit iface */
1664 #define LMT_532_10bit 0x2 /* 531.25 Mbaud 10 bit iface */
1665 #define LMT_1063_20bit 0x3 /* 1062.5 Mbaud 20 bit iface */
1666 #define LMT_1063_10bit 0x4 /* 1062.5 Mbaud 10 bit iface */
1667 #define LMT_2125_10bit 0x8 /* 2125 Mbaud 10 bit iface */
1668 #define LMT_4250_10bit 0x40 /* 4250 Mbaud 10 bit iface */
1676 uint32_t avail_iocb;
1678 uint32_t default_rpi;
1681 /* Structure for MB Command READ_RCONFIG (12) */
1684 #ifdef __BIG_ENDIAN_BITFIELD
1686 uint32_t recvNotify:1;
1691 #else /* __LITTLE_ENDIAN_BITFIELD */
1696 uint32_t recvNotify:1;
1700 #ifdef __BIG_ENDIAN_BITFIELD
1703 #else /* __LITTLE_ENDIAN_BITFIELD */
1710 #ifdef __BIG_ENDIAN_BITFIELD
1711 uint16_t cmdRingOffset;
1712 uint16_t cmdEntryCnt;
1713 uint16_t rspRingOffset;
1714 uint16_t rspEntryCnt;
1715 uint16_t nextCmdOffset;
1717 uint16_t nextRspOffset;
1719 #else /* __LITTLE_ENDIAN_BITFIELD */
1720 uint16_t cmdEntryCnt;
1721 uint16_t cmdRingOffset;
1722 uint16_t rspEntryCnt;
1723 uint16_t rspRingOffset;
1725 uint16_t nextCmdOffset;
1727 uint16_t nextRspOffset;
1731 /* Structure for MB Command READ_SPARM (13) */
1732 /* Structure for MB Command READ_SPARM64 (0x8D) */
1738 struct ulp_bde sp; /* This BDE points to struct serv_parm
1740 struct ulp_bde64 sp64;
1744 /* Structure for MB Command READ_STATUS (14) */
1747 #ifdef __BIG_ENDIAN_BITFIELD
1749 uint32_t clrCounters:1;
1750 uint16_t activeXriCnt;
1751 uint16_t activeRpiCnt;
1752 #else /* __LITTLE_ENDIAN_BITFIELD */
1753 uint32_t clrCounters:1;
1755 uint16_t activeRpiCnt;
1756 uint16_t activeXriCnt;
1759 uint32_t xmitByteCnt;
1760 uint32_t rcvByteCnt;
1761 uint32_t xmitFrameCnt;
1762 uint32_t rcvFrameCnt;
1763 uint32_t xmitSeqCnt;
1765 uint32_t totalOrigExchanges;
1766 uint32_t totalRespExchanges;
1767 uint32_t rcvPbsyCnt;
1768 uint32_t rcvFbsyCnt;
1771 /* Structure for MB Command READ_RPI (15) */
1772 /* Structure for MB Command READ_RPI64 (0x8F) */
1775 #ifdef __BIG_ENDIAN_BITFIELD
1780 #else /* __LITTLE_ENDIAN_BITFIELD */
1789 struct ulp_bde64 sp64;
1794 /* Structure for MB Command READ_XRI (16) */
1797 #ifdef __BIG_ENDIAN_BITFIELD
1814 uint32_t exchOrig:1;
1815 #else /* __LITTLE_ENDIAN_BITFIELD */
1830 uint32_t exchOrig:1;
1836 /* Structure for MB Command READ_REV (17) */
1839 #ifdef __BIG_ENDIAN_BITFIELD
1844 #else /* __LITTLE_ENDIAN_BITFIELD */
1856 #ifdef __BIG_ENDIAN_BITFIELD
1861 uint16_t ProgFixLvl:2;
1862 uint16_t ProgDistType:2;
1864 #else /* __LITTLE_ENDIAN_BITFIELD */
1866 uint16_t ProgDistType:2;
1867 uint16_t ProgFixLvl:2;
1877 #ifdef __BIG_ENDIAN_BITFIELD
1878 uint8_t feaLevelHigh;
1879 uint8_t feaLevelLow;
1882 #else /* __LITTLE_ENDIAN_BITFIELD */
1885 uint8_t feaLevelLow;
1886 uint8_t feaLevelHigh;
1889 uint32_t postKernRev;
1891 uint8_t opFwName[16];
1893 uint8_t sli1FwName[16];
1895 uint8_t sli2FwName[16];
1897 uint32_t RandomData[7];
1900 /* Structure for MB Command READ_LINK_STAT (18) */
1904 uint32_t linkFailureCnt;
1905 uint32_t lossSyncCnt;
1907 uint32_t lossSignalCnt;
1908 uint32_t primSeqErrCnt;
1909 uint32_t invalidXmitWord;
1911 uint32_t primSeqTimeout;
1912 uint32_t elasticOverrun;
1913 uint32_t arbTimeout;
1916 /* Structure for MB Command REG_LOGIN (19) */
1917 /* Structure for MB Command REG_LOGIN64 (0x93) */
1920 #ifdef __BIG_ENDIAN_BITFIELD
1925 #else /* __LITTLE_ENDIAN_BITFIELD */
1934 struct ulp_bde64 sp64;
1939 /* Word 30 contents for REG_LOGIN */
1942 #ifdef __BIG_ENDIAN_BITFIELD
1944 uint16_t wd30_class:4;
1946 #else /* __LITTLE_ENDIAN_BITFIELD */
1948 uint16_t wd30_class:4;
1955 /* Structure for MB Command UNREG_LOGIN (20) */
1958 #ifdef __BIG_ENDIAN_BITFIELD
1961 #else /* __LITTLE_ENDIAN_BITFIELD */
1967 /* Structure for MB Command UNREG_D_ID (0x23) */
1973 /* Structure for MB Command READ_LA (21) */
1974 /* Structure for MB Command READ_LA64 (0x95) */
1977 uint32_t eventTag; /* Event tag */
1978 #ifdef __BIG_ENDIAN_BITFIELD
1983 #else /* __LITTLE_ENDIAN_BITFIELD */
1990 #define AT_RESERVED 0x00 /* Reserved - attType */
1991 #define AT_LINK_UP 0x01 /* Link is up */
1992 #define AT_LINK_DOWN 0x02 /* Link is down */
1994 #ifdef __BIG_ENDIAN_BITFIELD
1995 uint8_t granted_AL_PA;
1999 #else /* __LITTLE_ENDIAN_BITFIELD */
2003 uint8_t granted_AL_PA;
2006 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2007 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2010 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2012 /* store the LILP AL_PA position map into */
2013 struct ulp_bde64 lilpBde64;
2016 #ifdef __BIG_ENDIAN_BITFIELD
2020 uint32_t DlnkSpeed:8;
2024 #else /* __LITTLE_ENDIAN_BITFIELD */
2028 uint32_t DlnkSpeed:8;
2034 #ifdef __BIG_ENDIAN_BITFIELD
2038 uint32_t UlnkSpeed:8;
2042 #else /* __LITTLE_ENDIAN_BITFIELD */
2046 uint32_t UlnkSpeed:8;
2052 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2053 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2054 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2055 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2056 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2057 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2061 /* Structure for MB Command CLEAR_LA (22) */
2064 uint32_t eventTag; /* Event tag */
2068 /* Structure for MB Command DUMP */
2071 #ifdef __BIG_ENDIAN_BITFIELD
2077 uint32_t entry_index:16;
2078 uint32_t region_id:16;
2079 #else /* __LITTLE_ENDIAN_BITFIELD */
2085 uint32_t region_id:16;
2086 uint32_t entry_index:16;
2091 uint32_t resp_offset;
2094 #define DMP_MEM_REG 0x1
2095 #define DMP_NV_PARAMS 0x2
2097 #define DMP_REGION_VPD 0xe
2098 #define DMP_VPD_SIZE 0x100
2100 /* Structure for MB Command CONFIG_PORT (0x88) */
2104 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2105 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2106 uint32_t hbainit[5];
2109 /* SLI-2 Port Control Block */
2112 #define SLIMOFF 0x30 /* WORD */
2114 typedef struct _SLI2_RDSC {
2115 uint32_t cmdEntries;
2116 uint32_t cmdAddrLow;
2117 uint32_t cmdAddrHigh;
2119 uint32_t rspEntries;
2120 uint32_t rspAddrLow;
2121 uint32_t rspAddrHigh;
2124 typedef struct _PCB {
2125 #ifdef __BIG_ENDIAN_BITFIELD
2127 #define TYPE_NATIVE_SLI2 0x01;
2129 #define FEATURE_INITIAL_SLI2 0x01;
2132 #else /* __LITTLE_ENDIAN_BITFIELD */
2136 #define FEATURE_INITIAL_SLI2 0x01;
2138 #define TYPE_NATIVE_SLI2 0x01;
2141 uint32_t mailBoxSize;
2143 uint32_t mbAddrHigh;
2145 uint32_t hgpAddrLow;
2146 uint32_t hgpAddrHigh;
2148 uint32_t pgpAddrLow;
2149 uint32_t pgpAddrHigh;
2150 SLI2_RDSC rdsc[MAX_RINGS];
2155 #ifdef __BIG_ENDIAN_BITFIELD
2157 uint32_t discardFarp:1;
2158 uint32_t IPEnable:1;
2159 uint32_t nodeName:1;
2160 uint32_t portName:1;
2161 uint32_t filterEnable:1;
2162 #else /* __LITTLE_ENDIAN_BITFIELD */
2163 uint32_t filterEnable:1;
2164 uint32_t portName:1;
2165 uint32_t nodeName:1;
2166 uint32_t IPEnable:1;
2167 uint32_t discardFarp:1;
2171 uint8_t portname[8]; /* Used to be struct lpfc_name */
2172 uint8_t nodename[8];
2179 /* Union of all Mailbox Command types */
2180 #define MAILBOX_CMD_WSIZE 32
2183 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2184 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2185 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2186 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2187 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2188 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2189 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2190 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2191 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2192 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2193 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2194 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2195 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2196 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2197 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2198 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2199 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2200 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2201 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2202 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2203 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2204 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2205 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2206 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2207 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2208 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */
2209 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2213 * SLI-2 specific structures
2226 typedef struct _SLI2_DESC {
2227 HGP host[MAX_RINGS];
2228 uint32_t unused1[16];
2229 PGP port[MAX_RINGS];
2236 typedef volatile struct {
2237 #ifdef __BIG_ENDIAN_BITFIELD
2240 uint8_t mbxReserved:6;
2242 uint8_t mbxOwner:1; /* Low order bit first word */
2243 #else /* __LITTLE_ENDIAN_BITFIELD */
2244 uint8_t mbxOwner:1; /* Low order bit first word */
2246 uint8_t mbxReserved:6;
2256 * Begin Structure Definitions for IOCB Commands
2260 #ifdef __BIG_ENDIAN_BITFIELD
2264 uint8_t statLocalError;
2265 #else /* __LITTLE_ENDIAN_BITFIELD */
2266 uint8_t statLocalError;
2271 /* statRsn P/F_RJT reason codes */
2272 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2273 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2274 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2275 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2276 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2277 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2278 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2279 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2280 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2281 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2282 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2283 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2284 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2285 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2286 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2287 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2288 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2289 #define RJT_PROT_ERR 0x12 /* Protocol error */
2290 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2291 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2292 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2293 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2294 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2295 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2296 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2297 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2299 #define IOERR_SUCCESS 0x00 /* statLocalError */
2300 #define IOERR_MISSING_CONTINUE 0x01
2301 #define IOERR_SEQUENCE_TIMEOUT 0x02
2302 #define IOERR_INTERNAL_ERROR 0x03
2303 #define IOERR_INVALID_RPI 0x04
2304 #define IOERR_NO_XRI 0x05
2305 #define IOERR_ILLEGAL_COMMAND 0x06
2306 #define IOERR_XCHG_DROPPED 0x07
2307 #define IOERR_ILLEGAL_FIELD 0x08
2308 #define IOERR_BAD_CONTINUE 0x09
2309 #define IOERR_TOO_MANY_BUFFERS 0x0A
2310 #define IOERR_RCV_BUFFER_WAITING 0x0B
2311 #define IOERR_NO_CONNECTION 0x0C
2312 #define IOERR_TX_DMA_FAILED 0x0D
2313 #define IOERR_RX_DMA_FAILED 0x0E
2314 #define IOERR_ILLEGAL_FRAME 0x0F
2315 #define IOERR_EXTRA_DATA 0x10
2316 #define IOERR_NO_RESOURCES 0x11
2317 #define IOERR_RESERVED 0x12
2318 #define IOERR_ILLEGAL_LENGTH 0x13
2319 #define IOERR_UNSUPPORTED_FEATURE 0x14
2320 #define IOERR_ABORT_IN_PROGRESS 0x15
2321 #define IOERR_ABORT_REQUESTED 0x16
2322 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2323 #define IOERR_LOOP_OPEN_FAILURE 0x18
2324 #define IOERR_RING_RESET 0x19
2325 #define IOERR_LINK_DOWN 0x1A
2326 #define IOERR_CORRUPTED_DATA 0x1B
2327 #define IOERR_CORRUPTED_RPI 0x1C
2328 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2329 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2330 #define IOERR_DUP_FRAME 0x1F
2331 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2332 #define IOERR_BAD_HOST_ADDRESS 0x21
2333 #define IOERR_RCV_HDRBUF_WAITING 0x22
2334 #define IOERR_MISSING_HDR_BUFFER 0x23
2335 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2336 #define IOERR_ABORTMULT_REQUESTED 0x25
2337 #define IOERR_BUFFER_SHORTAGE 0x28
2338 #define IOERR_DEFAULT 0x29
2339 #define IOERR_CNT 0x2A
2341 #define IOERR_DRVR_MASK 0x100
2342 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2343 #define IOERR_SLI_BRESET 0x102
2344 #define IOERR_SLI_ABORTED 0x103
2349 #ifdef __BIG_ENDIAN_BITFIELD
2350 uint8_t Rctl; /* R_CTL field */
2351 uint8_t Type; /* TYPE field */
2352 uint8_t Dfctl; /* DF_CTL field */
2353 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2354 #else /* __LITTLE_ENDIAN_BITFIELD */
2355 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2356 uint8_t Dfctl; /* DF_CTL field */
2357 uint8_t Type; /* TYPE field */
2358 uint8_t Rctl; /* R_CTL field */
2361 #define BC 0x02 /* Broadcast Received - Fctl */
2362 #define SI 0x04 /* Sequence Initiative */
2363 #define LA 0x08 /* Ignore Link Attention state */
2364 #define LS 0x80 /* Last Sequence */
2369 /* IOCB Command template for a generic response */
2371 uint32_t reserved[4];
2375 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2377 struct ulp_bde xrsqbde[2];
2378 uint32_t xrsqRo; /* Starting Relative Offset */
2379 WORD5 w5; /* Header control/status word */
2382 /* IOCB Command template for ELS_REQUEST */
2384 struct ulp_bde elsReq;
2385 struct ulp_bde elsRsp;
2387 #ifdef __BIG_ENDIAN_BITFIELD
2388 uint32_t word4Rsvd:7;
2391 uint32_t word5Rsvd:8;
2392 uint32_t remoteID:24;
2393 #else /* __LITTLE_ENDIAN_BITFIELD */
2396 uint32_t word4Rsvd:7;
2397 uint32_t remoteID:24;
2398 uint32_t word5Rsvd:8;
2402 /* IOCB Command template for RCV_ELS_REQ */
2404 struct ulp_bde elsReq[2];
2407 #ifdef __BIG_ENDIAN_BITFIELD
2408 uint32_t word5Rsvd:8;
2409 uint32_t remoteID:24;
2410 #else /* __LITTLE_ENDIAN_BITFIELD */
2411 uint32_t remoteID:24;
2412 uint32_t word5Rsvd:8;
2416 /* IOCB Command template for ABORT / CLOSE_XRI */
2420 #define ABORT_TYPE_ABTX 0x00000000
2421 #define ABORT_TYPE_ABTS 0x00000001
2423 #ifdef __BIG_ENDIAN_BITFIELD
2424 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2425 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2426 #else /* __LITTLE_ENDIAN_BITFIELD */
2427 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2428 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2432 /* IOCB Command template for ABORT_MXRI64 */
2440 /* IOCB Command template for GET_RPI */
2444 #ifdef __BIG_ENDIAN_BITFIELD
2445 uint32_t word5Rsvd:8;
2446 uint32_t remoteID:24;
2447 #else /* __LITTLE_ENDIAN_BITFIELD */
2448 uint32_t remoteID:24;
2449 uint32_t word5Rsvd:8;
2453 /* IOCB Command template for all FCP Initiator commands */
2455 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2456 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2458 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2461 /* IOCB Command template for all FCP Target commands */
2463 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2464 uint32_t fcpt_Offset;
2465 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2468 /* SLI-2 IOCB structure definitions */
2470 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2473 uint32_t xrsqRo; /* Starting Relative Offset */
2474 WORD5 w5; /* Header control/status word */
2477 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2479 struct ulp_bde64 rcvBde;
2481 uint32_t xrsqRo; /* Starting Relative Offset */
2482 WORD5 w5; /* Header control/status word */
2485 /* IOCB Command template for ELS_REQUEST64 */
2488 #ifdef __BIG_ENDIAN_BITFIELD
2489 uint32_t word4Rsvd:7;
2492 uint32_t word5Rsvd:8;
2493 uint32_t remoteID:24;
2494 #else /* __LITTLE_ENDIAN_BITFIELD */
2497 uint32_t word4Rsvd:7;
2498 uint32_t remoteID:24;
2499 uint32_t word5Rsvd:8;
2503 /* IOCB Command template for GEN_REQUEST64 */
2506 uint32_t xrsqRo; /* Starting Relative Offset */
2507 WORD5 w5; /* Header control/status word */
2510 /* IOCB Command template for RCV_ELS_REQ64 */
2512 struct ulp_bde64 elsReq;
2516 #ifdef __BIG_ENDIAN_BITFIELD
2517 uint32_t word5Rsvd:8;
2518 uint32_t remoteID:24;
2519 #else /* __LITTLE_ENDIAN_BITFIELD */
2520 uint32_t remoteID:24;
2521 uint32_t word5Rsvd:8;
2525 /* IOCB Command template for all 64 bit FCP Initiator commands */
2529 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2532 /* IOCB Command template for all 64 bit FCP Target commands */
2535 uint32_t fcpt_Offset;
2536 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2539 typedef volatile struct _IOCB { /* IOCB structure */
2541 GENERIC_RSP grsp; /* Generic response */
2542 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2543 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2544 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2545 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2546 A_MXRI64 amxri; /* abort multiple xri command overlay */
2547 GET_RPI getrpi; /* GET_RPI template */
2548 FCPI_FIELDS fcpi; /* FCP Initiator template */
2549 FCPT_FIELDS fcpt; /* FCP target template */
2551 /* SLI-2 structures */
2553 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2555 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2556 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2557 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2558 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2559 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2560 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2562 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
2566 #ifdef __BIG_ENDIAN_BITFIELD
2567 uint16_t ulpContext; /* High order bits word 6 */
2568 uint16_t ulpIoTag; /* Low order bits word 6 */
2569 #else /* __LITTLE_ENDIAN_BITFIELD */
2570 uint16_t ulpIoTag; /* Low order bits word 6 */
2571 uint16_t ulpContext; /* High order bits word 6 */
2575 #ifdef __BIG_ENDIAN_BITFIELD
2576 uint16_t ulpContext; /* High order bits word 6 */
2577 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2578 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2579 #else /* __LITTLE_ENDIAN_BITFIELD */
2580 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2581 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2582 uint16_t ulpContext; /* High order bits word 6 */
2586 #define ulpContext un1.t1.ulpContext
2587 #define ulpIoTag un1.t1.ulpIoTag
2588 #define ulpIoTag0 un1.t2.ulpIoTag0
2590 #ifdef __BIG_ENDIAN_BITFIELD
2591 uint32_t ulpTimeout:8;
2593 uint32_t ulpFCP2Rcvy:1;
2596 uint32_t ulpClass:3;
2597 uint32_t ulpCommand:8;
2598 uint32_t ulpStatus:4;
2599 uint32_t ulpBdeCount:2;
2601 uint32_t ulpOwner:1; /* Low order bit word 7 */
2602 #else /* __LITTLE_ENDIAN_BITFIELD */
2603 uint32_t ulpOwner:1; /* Low order bit word 7 */
2605 uint32_t ulpBdeCount:2;
2606 uint32_t ulpStatus:4;
2607 uint32_t ulpCommand:8;
2608 uint32_t ulpClass:3;
2611 uint32_t ulpFCP2Rcvy:1;
2613 uint32_t ulpTimeout:8;
2616 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
2617 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2618 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
2619 #define CLASS1 0 /* Class 1 */
2620 #define CLASS2 1 /* Class 2 */
2621 #define CLASS3 2 /* Class 3 */
2622 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
2624 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
2625 #define IOSTAT_FCP_RSP_ERROR 0x1
2626 #define IOSTAT_REMOTE_STOP 0x2
2627 #define IOSTAT_LOCAL_REJECT 0x3
2628 #define IOSTAT_NPORT_RJT 0x4
2629 #define IOSTAT_FABRIC_RJT 0x5
2630 #define IOSTAT_NPORT_BSY 0x6
2631 #define IOSTAT_FABRIC_BSY 0x7
2632 #define IOSTAT_INTERMED_RSP 0x8
2633 #define IOSTAT_LS_RJT 0x9
2634 #define IOSTAT_BA_RJT 0xA
2635 #define IOSTAT_RSVD1 0xB
2636 #define IOSTAT_RSVD2 0xC
2637 #define IOSTAT_RSVD3 0xD
2638 #define IOSTAT_RSVD4 0xE
2639 #define IOSTAT_RSVD5 0xF
2640 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2641 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2642 #define IOSTAT_CNT 0x11
2647 #define SLI1_SLIM_SIZE (4 * 1024)
2649 /* Up to 498 IOCBs will fit into 16k
2650 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2652 #define SLI2_SLIM_SIZE (16 * 1024)
2654 /* Maximum IOCBs that will fit in SLI2 slim */
2655 #define MAX_SLI2_IOCB 498
2657 struct lpfc_sli2_slim {
2660 IOCB_t IOCBs[MAX_SLI2_IOCB];
2663 /*******************************************************************
2664 This macro check PCI device to allow special handling for LC HBAs.
2667 device : struct pci_dev 's device field
2671 *******************************************************************/
2673 lpfc_is_LC_HBA(unsigned short device)
2675 if ((device == PCI_DEVICE_ID_TFLY) ||
2676 (device == PCI_DEVICE_ID_PFLY) ||
2677 (device == PCI_DEVICE_ID_LP101) ||
2678 (device == PCI_DEVICE_ID_BMID) ||
2679 (device == PCI_DEVICE_ID_BSMB) ||
2680 (device == PCI_DEVICE_ID_ZMID) ||
2681 (device == PCI_DEVICE_ID_ZSMB) ||
2682 (device == PCI_DEVICE_ID_RFLY))
2688 #endif /* _H_LPFC_HW */