1 /******************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
5 * Copyright (C) 2000 Qlogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
24 * Data bit definitions.
42 #define BIT_16 0x10000
43 #define BIT_17 0x20000
44 #define BIT_18 0x40000
45 #define BIT_19 0x80000
46 #define BIT_20 0x100000
47 #define BIT_21 0x200000
48 #define BIT_22 0x400000
49 #define BIT_23 0x800000
50 #define BIT_24 0x1000000
51 #define BIT_25 0x2000000
52 #define BIT_26 0x4000000
53 #define BIT_27 0x8000000
54 #define BIT_28 0x10000000
55 #define BIT_29 0x20000000
56 #define BIT_30 0x40000000
57 #define BIT_31 0x80000000
60 #define RD_REG_WORD(addr) readw(addr)
61 #define WRT_REG_WORD(addr, data) writew(data, addr)
62 #else /* MEMORY_MAPPED_IO */
63 #define RD_REG_WORD(addr) inw((unsigned long)addr)
64 #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr)
65 #endif /* MEMORY_MAPPED_IO */
68 * Host adapter default definitions.
70 #define MAX_BUSES 2 /* 2 */
73 #define MAX_TARGETS 16 /* 16 */
74 #define MAX_T_BITS 4 /* 4 */
76 #define MAX_LUNS 8 /* 32 */
77 #define MAX_L_BITS 3 /* 5 */
80 * Watchdog time quantum
82 #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */
84 /* Command retry count (0-65535) */
85 #define COMMAND_RETRY_COUNT 255
87 /* Maximum outstanding commands in ISP queues */
88 #define MAX_OUTSTANDING_COMMANDS 512
89 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS + 2)
91 /* ISP request and response entry counts (37-65535) */
92 #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */
93 #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */
95 /* Number of segments 1 - 65535 */
96 #define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */
99 * SCSI Request Block structure (sp) that is placed
100 * on cmd->SCp location of every I/O
103 struct list_head list; /* (8/16) LU queue */
104 struct scsi_cmnd *cmd; /* (4/8) SCSI command block */
105 /* NOTE: the sp->cmd will be NULL when this completion is
106 * called, so you should know the scsi_cmnd when using this */
107 struct completion *wait;
108 dma_addr_t saved_dma_handle; /* for unmap of single transfers */
109 uint8_t flags; /* (1) Status flags. */
110 uint8_t dir; /* direction of transfer */
114 * SRB flag definitions
116 #define SRB_TIMEOUT (1 << 0) /* Command timed out */
117 #define SRB_SENT (1 << 1) /* Command sent to ISP */
118 #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */
119 #define SRB_ABORTED (1 << 3) /* Command aborted command already */
122 * ISP I/O Register Set structure definitions.
125 uint16_t id_l; /* ID low */
126 uint16_t id_h; /* ID high */
127 uint16_t cfg_0; /* Configuration 0 */
128 uint16_t cfg_1; /* Configuration 1 */
129 uint16_t ictrl; /* Interface control */
130 #define ISP_RESET BIT_0 /* ISP soft reset */
131 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
132 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
133 #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
134 #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
135 uint16_t istatus; /* Interface status */
136 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
137 #define RISC_INT BIT_2 /* RISC interrupt */
138 #define PCI_INT BIT_1 /* PCI interrupt */
139 uint16_t semaphore; /* Semaphore */
140 uint16_t nvram; /* NVRAM register. */
141 #define NV_DESELECT 0
142 #define NV_CLOCK BIT_0
143 #define NV_SELECT BIT_1
144 #define NV_DATA_OUT BIT_2
145 #define NV_DATA_IN BIT_3
146 uint16_t flash_data; /* Flash BIOS data */
147 uint16_t flash_address; /* Flash BIOS address */
149 uint16_t unused_1[0x2e]; /* 0x14-0x6f Gap */
151 uint16_t mailbox0; /* Mailbox 0 */
152 uint16_t mailbox1; /* Mailbox 1 */
153 uint16_t mailbox2; /* Mailbox 2 */
154 uint16_t mailbox3; /* Mailbox 3 */
155 uint16_t mailbox4; /* Mailbox 4 */
156 uint16_t mailbox5; /* Mailbox 5 */
157 uint16_t mailbox6; /* Mailbox 6 */
158 uint16_t mailbox7; /* Mailbox 7 */
160 uint16_t unused_2[0x20];/* 0x80-0xbf Gap */
162 uint16_t host_cmd; /* Host command and control */
163 #define HOST_INT BIT_7 /* host interrupt bit */
164 #define BIOS_ENABLE BIT_0
166 uint16_t unused_6[0x5]; /* 0xc2-0xcb Gap */
169 uint16_t gpio_enable;
171 uint16_t unused_7[0x11]; /* d0-f0 */
172 uint16_t scsiControlPins; /* f2 */
175 #define MAILBOX_REGISTER_COUNT 8
178 * ISP product identification definitions in mailboxes after reset.
180 #define PROD_ID_1 0x4953
181 #define PROD_ID_2 0x0000
182 #define PROD_ID_2a 0x5020
183 #define PROD_ID_3 0x2020
184 #define PROD_ID_4 0x1
187 * ISP host command and control register command definitions
189 #define HC_RESET_RISC 0x1000 /* Reset RISC */
190 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
191 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
192 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
193 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
194 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
195 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
198 * ISP mailbox Self-Test status codes
200 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
201 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
202 #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */
203 #define MBS_BUSY 4 /* Busy. */
206 * ISP mailbox command complete status codes
208 #define MBS_CMD_CMP 0x4000 /* Command Complete. */
209 #define MBS_INV_CMD 0x4001 /* Invalid Command. */
210 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
211 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
212 #define MBS_CMD_ERR 0x4005 /* Command Error. */
213 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
216 * ISP mailbox asynchronous event status codes
218 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
219 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
220 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
221 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
222 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
223 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
224 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
225 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
226 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
227 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
230 * ISP mailbox commands
232 #define MBC_NOP 0 /* No Operation */
233 #define MBC_LOAD_RAM 1 /* Load RAM */
234 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */
235 #define MBC_DUMP_RAM 3 /* Dump RAM contents */
236 #define MBC_WRITE_RAM_WORD 4 /* Write ram word */
237 #define MBC_READ_RAM_WORD 5 /* Read ram word */
238 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
239 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */
240 #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */
241 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */
242 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */
243 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */
244 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */
245 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */
246 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */
247 #define MBC_BUS_RESET 0x18 /* SCSI bus reset */
248 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */
249 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */
250 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */
251 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */
252 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */
253 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */
254 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */
255 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */
256 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */
257 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */
258 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */
259 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
260 #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */
261 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */
262 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */
263 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
264 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */
265 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */
266 #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */
269 * ISP Get/Set Target Parameters mailbox command control flags.
271 #define TP_PPR BIT_5 /* PPR */
272 #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
273 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
274 #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */
275 #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */
276 #define TP_SYNC BIT_12 /* Synchronous data transfers. */
277 #define TP_WIDE BIT_13 /* Wide data transfers. */
278 #define TP_PARITY BIT_14 /* Parity checking. */
279 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
282 * NVRAM Command values.
284 #define NV_START_BIT BIT_2
285 #define NV_WRITE_OP (BIT_26 | BIT_24)
286 #define NV_READ_OP (BIT_26 | BIT_25)
287 #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24)
288 #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24)
289 #define NV_DELAY_COUNT 10
292 * QLogic ISP1280/ISP12160 NVRAM structure definition.
299 uint8_t version; /* 4 */
302 uint8_t bios_configuration_mode:2;
303 uint8_t bios_disable:1;
304 uint8_t selectable_scsi_boot_enable:1;
305 uint8_t cd_rom_boot_enable:1;
306 uint8_t disable_loading_risc_code:1;
307 uint8_t enable_64bit_addressing:1;
309 } cntr_flags_1; /* 5 */
312 uint8_t boot_lun_number:5;
313 uint8_t scsi_bus_number:1;
316 } cntr_flags_2l; /* 7 */
319 uint8_t boot_target_number:4;
324 } cntr_flags_2h; /* 8 */
326 uint16_t unused_8; /* 8, 9 */
327 uint16_t unused_10; /* 10, 11 */
328 uint16_t unused_12; /* 12, 13 */
329 uint16_t unused_14; /* 14, 15 */
335 uint8_t burst_enable:1;
336 uint8_t reserved_1:1;
337 uint8_t fifo_threshold:4;
339 } isp_config; /* 16 */
342 * 0 = Disable, 1 = high only, 3 = Auto term
347 uint8_t scsi_bus_1_control:2;
348 uint8_t scsi_bus_0_control:2;
352 uint8_t auto_term_support:1;
354 } termination; /* 17 */
356 uint16_t isp_parameter; /* 18, 19 */
361 uint16_t enable_fast_posting:1;
362 uint16_t report_lvd_bus_transition:1;
365 uint16_t disable_iosbs_with_bus_reset_status:1;
366 uint16_t disable_synchronous_backoff:1;
368 uint16_t synchronous_backoff_reporting:1;
369 uint16_t disable_reselection_fairness:1;
371 uint16_t unused_10:1;
372 uint16_t unused_11:1;
373 uint16_t unused_12:1;
374 uint16_t unused_13:1;
375 uint16_t unused_14:1;
376 uint16_t unused_15:1;
378 } firmware_feature; /* 20, 21 */
380 uint16_t unused_22; /* 22, 23 */
384 uint8_t initiator_id:4;
385 uint8_t scsi_reset_disable:1;
386 uint8_t scsi_bus_size:1;
387 uint8_t scsi_bus_type:1;
391 uint8_t bus_reset_delay; /* 25 */
392 uint8_t retry_count; /* 26 */
393 uint8_t retry_delay; /* 27 */
396 uint8_t async_data_setup_time:4;
397 uint8_t req_ack_active_negation:1;
398 uint8_t data_line_active_negation:1;
403 uint8_t unused_29; /* 29 */
405 uint16_t selection_timeout; /* 30, 31 */
406 uint16_t max_queue_depth; /* 32, 33 */
408 uint16_t unused_34; /* 34, 35 */
409 uint16_t unused_36; /* 36, 37 */
410 uint16_t unused_38; /* 38, 39 */
416 uint8_t renegotiate_on_error:1;
417 uint8_t stop_queue_on_check:1;
418 uint8_t auto_request_sense:1;
419 uint8_t tag_queuing:1;
420 uint8_t enable_sync:1;
421 uint8_t enable_wide:1;
422 uint8_t parity_checking:1;
423 uint8_t disconnect_allowed:1;
425 } parameter; /* 40 */
427 uint8_t execution_throttle; /* 41 */
428 uint8_t sync_period; /* 42 */
433 uint8_t sync_offset:4;
434 uint8_t device_enable:1;
435 uint8_t lun_disable:1;
440 uint8_t sync_offset:5;
441 uint8_t device_enable:1;
446 union { /* PPR flags for the 1x160 controllers */
449 uint8_t ppr_options:4;
450 uint8_t ppr_bus_width:2;
452 uint8_t enable_ppr:1;
455 uint8_t unused_45; /* 45 */
456 } target[MAX_TARGETS];
459 uint16_t unused_248; /* 248, 249 */
461 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
465 uint8_t system_id_pointer;
468 uint8_t chksum; /* 255 */
472 * ISP queue - command entry structure definition.
474 #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */
476 uint8_t entry_type; /* Entry type. */
477 #define COMMAND_TYPE 1 /* Command entry */
478 uint8_t entry_count; /* Entry count. */
479 uint8_t sys_define; /* System defined. */
480 uint8_t entry_status; /* Entry Status. */
481 uint32_t handle; /* System handle. */
482 uint8_t lun; /* SCSI LUN */
483 uint8_t target; /* SCSI ID */
484 uint16_t cdb_len; /* SCSI command length. */
485 uint16_t control_flags; /* Control flags. */
487 uint16_t timeout; /* Command timeout. */
488 uint16_t dseg_count; /* Data segment count. */
489 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
490 uint32_t dseg_0_address; /* Data segment 0 address. */
491 uint32_t dseg_0_length; /* Data segment 0 length. */
492 uint32_t dseg_1_address; /* Data segment 1 address. */
493 uint32_t dseg_1_length; /* Data segment 1 length. */
494 uint32_t dseg_2_address; /* Data segment 2 address. */
495 uint32_t dseg_2_length; /* Data segment 2 length. */
496 uint32_t dseg_3_address; /* Data segment 3 address. */
497 uint32_t dseg_3_length; /* Data segment 3 length. */
501 * ISP queue - continuation entry structure definition.
504 uint8_t entry_type; /* Entry type. */
505 #define CONTINUE_TYPE 2 /* Continuation entry. */
506 uint8_t entry_count; /* Entry count. */
507 uint8_t sys_define; /* System defined. */
508 uint8_t entry_status; /* Entry Status. */
509 uint32_t reserved; /* Reserved */
510 uint32_t dseg_0_address; /* Data segment 0 address. */
511 uint32_t dseg_0_length; /* Data segment 0 length. */
512 uint32_t dseg_1_address; /* Data segment 1 address. */
513 uint32_t dseg_1_length; /* Data segment 1 length. */
514 uint32_t dseg_2_address; /* Data segment 2 address. */
515 uint32_t dseg_2_length; /* Data segment 2 length. */
516 uint32_t dseg_3_address; /* Data segment 3 address. */
517 uint32_t dseg_3_length; /* Data segment 3 length. */
518 uint32_t dseg_4_address; /* Data segment 4 address. */
519 uint32_t dseg_4_length; /* Data segment 4 length. */
520 uint32_t dseg_5_address; /* Data segment 5 address. */
521 uint32_t dseg_5_length; /* Data segment 5 length. */
522 uint32_t dseg_6_address; /* Data segment 6 address. */
523 uint32_t dseg_6_length; /* Data segment 6 length. */
527 * ISP queue - status entry structure definition.
530 uint8_t entry_type; /* Entry type. */
531 #define STATUS_TYPE 3 /* Status entry. */
532 uint8_t entry_count; /* Entry count. */
533 uint8_t sys_define; /* System defined. */
534 uint8_t entry_status; /* Entry Status. */
535 #define RF_CONT BIT_0 /* Continuation. */
536 #define RF_FULL BIT_1 /* Full */
537 #define RF_BAD_HEADER BIT_2 /* Bad header. */
538 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
539 uint32_t handle; /* System handle. */
540 uint16_t scsi_status; /* SCSI status. */
541 uint16_t comp_status; /* Completion status. */
542 uint16_t state_flags; /* State flags. */
543 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
544 #define SF_GOT_SENSE BIT_13 /* Got Sense */
545 #define SF_GOT_STATUS BIT_12 /* Got Status */
546 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
547 #define SF_SENT_CDB BIT_10 /* Send CDB */
548 #define SF_GOT_TARGET BIT_9 /* */
549 #define SF_GOT_BUS BIT_8 /* */
550 uint16_t status_flags; /* Status flags. */
551 uint16_t time; /* Time. */
552 uint16_t req_sense_length; /* Request sense data length. */
553 uint32_t residual_length; /* Residual transfer length. */
554 uint16_t reserved[4];
555 uint8_t req_sense_data[32]; /* Request sense data. */
559 * ISP queue - marker entry structure definition.
562 uint8_t entry_type; /* Entry type. */
563 #define MARKER_TYPE 4 /* Marker entry. */
564 uint8_t entry_count; /* Entry count. */
565 uint8_t sys_define; /* System defined. */
566 uint8_t entry_status; /* Entry Status. */
568 uint8_t lun; /* SCSI LUN */
569 uint8_t target; /* SCSI ID */
570 uint8_t modifier; /* Modifier (7-0). */
571 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
572 #define MK_SYNC_ID 1 /* Synchronize ID */
573 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
574 uint8_t reserved_1[53];
578 * ISP queue - extended command entry structure definition.
580 * Unused by the driver!
583 uint8_t entry_type; /* Entry type. */
584 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */
585 uint8_t entry_count; /* Entry count. */
586 uint8_t sys_define; /* System defined. */
587 uint8_t entry_status; /* Entry Status. */
588 uint32_t handle; /* System handle. */
589 uint8_t lun; /* SCSI LUN */
590 uint8_t target; /* SCSI ID */
591 uint16_t cdb_len; /* SCSI command length. */
592 uint16_t control_flags; /* Control flags. */
594 uint16_t timeout; /* Command timeout. */
595 uint16_t dseg_count; /* Data segment count. */
596 uint8_t scsi_cdb[88]; /* SCSI command words. */
600 * ISP queue - 64-Bit addressing, command entry structure definition.
603 uint8_t entry_type; /* Entry type. */
604 #define COMMAND_A64_TYPE 9 /* Command A64 entry */
605 uint8_t entry_count; /* Entry count. */
606 uint8_t sys_define; /* System defined. */
607 uint8_t entry_status; /* Entry Status. */
608 uint32_t handle; /* System handle. */
609 uint8_t lun; /* SCSI LUN */
610 uint8_t target; /* SCSI ID */
611 uint16_t cdb_len; /* SCSI command length. */
612 uint16_t control_flags; /* Control flags. */
614 uint16_t timeout; /* Command timeout. */
615 uint16_t dseg_count; /* Data segment count. */
616 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
617 uint32_t reserved_1[2]; /* unused */
618 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
619 uint32_t dseg_0_length; /* Data segment 0 length. */
620 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
621 uint32_t dseg_1_length; /* Data segment 1 length. */
622 } cmd_a64_entry_t, request_t;
625 * ISP queue - 64-Bit addressing, continuation entry structure definition.
627 struct cont_a64_entry {
628 uint8_t entry_type; /* Entry type. */
629 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
630 uint8_t entry_count; /* Entry count. */
631 uint8_t sys_define; /* System defined. */
632 uint8_t entry_status; /* Entry Status. */
633 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
634 uint32_t dseg_0_length; /* Data segment 0 length. */
635 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
636 uint32_t dseg_1_length; /* Data segment 1 length. */
637 uint32_t dseg_2_address[2]; /* Data segment 2 address. */
638 uint32_t dseg_2_length; /* Data segment 2 length. */
639 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
640 uint32_t dseg_3_length; /* Data segment 3 length. */
641 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
642 uint32_t dseg_4_length; /* Data segment 4 length. */
646 * ISP queue - enable LUN entry structure definition.
649 uint8_t entry_type; /* Entry type. */
650 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
651 uint8_t entry_count; /* Entry count. */
653 uint8_t entry_status; /* Entry Status not used. */
655 uint16_t lun; /* Bit 15 is bus number. */
657 uint32_t option_flags;
660 uint8_t command_count; /* Number of ATIOs allocated. */
661 uint8_t immed_notify_count; /* Number of Immediate Notify */
662 /* entries allocated. */
663 uint8_t group_6_length; /* SCSI CDB length for group 6 */
664 /* commands (2-26). */
665 uint8_t group_7_length; /* SCSI CDB length for group 7 */
666 /* commands (2-26). */
667 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
668 uint16_t reserved_6[20];
672 * ISP queue - modify LUN entry structure definition.
674 * Unused by the driver!
676 struct modify_lun_entry {
677 uint8_t entry_type; /* Entry type. */
678 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
679 uint8_t entry_count; /* Entry count. */
681 uint8_t entry_status; /* Entry Status. */
683 uint8_t lun; /* SCSI LUN */
687 uint32_t option_flags;
690 uint8_t command_count; /* Number of ATIOs allocated. */
691 uint8_t immed_notify_count; /* Number of Immediate Notify */
692 /* entries allocated. */
694 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
695 uint16_t reserved_7[20];
699 * ISP queue - immediate notify entry structure definition.
701 struct notify_entry {
702 uint8_t entry_type; /* Entry type. */
703 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
704 uint8_t entry_count; /* Entry count. */
706 uint8_t entry_status; /* Entry Status. */
709 uint8_t initiator_id;
712 uint32_t option_flags;
715 uint8_t tag_value; /* Received queue tag message value */
716 uint8_t tag_type; /* Received queue tag message type */
717 /* entries allocated. */
719 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
720 uint16_t reserved_5[8];
721 uint8_t sense_data[18];
725 * ISP queue - notify acknowledge entry structure definition.
728 uint8_t entry_type; /* Entry type. */
729 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
730 uint8_t entry_count; /* Entry count. */
732 uint8_t entry_status; /* Entry Status. */
735 uint8_t initiator_id;
738 uint32_t option_flags;
742 uint16_t reserved_4[22];
746 * ISP queue - Accept Target I/O (ATIO) entry structure definition.
749 uint8_t entry_type; /* Entry type. */
750 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */
751 uint8_t entry_count; /* Entry count. */
753 uint8_t entry_status; /* Entry Status. */
756 uint8_t initiator_id;
759 uint32_t option_flags;
762 uint8_t tag_value; /* Received queue tag message value */
763 uint8_t tag_type; /* Received queue tag message type */
765 uint8_t sense_data[18];
769 * ISP queue - Continue Target I/O (CTIO) entry structure definition.
772 uint8_t entry_type; /* Entry type. */
773 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */
774 uint8_t entry_count; /* Entry count. */
776 uint8_t entry_status; /* Entry Status. */
778 uint8_t lun; /* SCSI LUN */
779 uint8_t initiator_id;
782 uint32_t option_flags;
785 uint8_t tag_value; /* Received queue tag message value */
786 uint8_t tag_type; /* Received queue tag message type */
787 uint32_t transfer_length;
789 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
790 uint16_t dseg_count; /* Data segment count. */
791 uint32_t dseg_0_address; /* Data segment 0 address. */
792 uint32_t dseg_0_length; /* Data segment 0 length. */
793 uint32_t dseg_1_address; /* Data segment 1 address. */
794 uint32_t dseg_1_length; /* Data segment 1 length. */
795 uint32_t dseg_2_address; /* Data segment 2 address. */
796 uint32_t dseg_2_length; /* Data segment 2 length. */
797 uint32_t dseg_3_address; /* Data segment 3 address. */
798 uint32_t dseg_3_length; /* Data segment 3 length. */
802 * ISP queue - CTIO returned entry structure definition.
804 struct ctio_ret_entry {
805 uint8_t entry_type; /* Entry type. */
806 #define CTIO_RET_TYPE 7 /* CTIO return entry */
807 uint8_t entry_count; /* Entry count. */
809 uint8_t entry_status; /* Entry Status. */
811 uint8_t lun; /* SCSI LUN */
812 uint8_t initiator_id;
815 uint32_t option_flags;
818 uint8_t tag_value; /* Received queue tag message value */
819 uint8_t tag_type; /* Received queue tag message type */
820 uint32_t transfer_length;
822 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
823 uint16_t dseg_count; /* Data segment count. */
824 uint32_t dseg_0_address; /* Data segment 0 address. */
825 uint32_t dseg_0_length; /* Data segment 0 length. */
826 uint32_t dseg_1_address; /* Data segment 1 address. */
827 uint16_t dseg_1_length; /* Data segment 1 length. */
828 uint8_t sense_data[18];
832 * ISP queue - CTIO A64 entry structure definition.
834 struct ctio_a64_entry {
835 uint8_t entry_type; /* Entry type. */
836 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
837 uint8_t entry_count; /* Entry count. */
839 uint8_t entry_status; /* Entry Status. */
841 uint8_t lun; /* SCSI LUN */
842 uint8_t initiator_id;
845 uint32_t option_flags;
848 uint8_t tag_value; /* Received queue tag message value */
849 uint8_t tag_type; /* Received queue tag message type */
850 uint32_t transfer_length;
852 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
853 uint16_t dseg_count; /* Data segment count. */
854 uint32_t reserved_4[2];
855 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
856 uint32_t dseg_0_length; /* Data segment 0 length. */
857 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
858 uint32_t dseg_1_length; /* Data segment 1 length. */
862 * ISP queue - CTIO returned entry structure definition.
864 struct ctio_a64_ret_entry {
865 uint8_t entry_type; /* Entry type. */
866 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
867 uint8_t entry_count; /* Entry count. */
869 uint8_t entry_status; /* Entry Status. */
871 uint8_t lun; /* SCSI LUN */
872 uint8_t initiator_id;
875 uint32_t option_flags;
878 uint8_t tag_value; /* Received queue tag message value */
879 uint8_t tag_type; /* Received queue tag message type */
880 uint32_t transfer_length;
882 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
883 uint16_t dseg_count; /* Data segment count. */
884 uint16_t reserved_4[7];
885 uint8_t sense_data[18];
889 * ISP request and response queue entry sizes
891 #define RESPONSE_ENTRY_SIZE (sizeof(struct response))
892 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
895 * ISP status entry - completion status definitions.
897 #define CS_COMPLETE 0x0 /* No errors */
898 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
899 #define CS_DMA 0x2 /* A DMA direction error. */
900 #define CS_TRANSPORT 0x3 /* Transport error. */
901 #define CS_RESET 0x4 /* SCSI bus reset occurred */
902 #define CS_ABORTED 0x5 /* System aborted command. */
903 #define CS_TIMEOUT 0x6 /* Timeout error. */
904 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
905 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
906 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
907 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
908 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
909 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
910 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
911 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
912 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
913 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
914 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
915 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
916 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
917 #define CS_FREE 0x14 /* Unexpected bus free. */
918 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
919 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
920 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
921 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
922 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
923 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
924 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
925 #define CS_ARS_FAILED 0x1e /* ARS failed */
926 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
927 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
928 #define CS_UNKNOWN 0x81 /* Driver defined */
929 #define CS_RETRY 0x82 /* Driver defined */
932 * ISP status entry - SCSI status byte bit definitions.
934 #define SS_CHECK_CONDITION BIT_1
935 #define SS_CONDITION_MET BIT_2
936 #define SS_BUSY_CONDITION BIT_3
937 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
940 * ISP target entries - Option flags bit definitions.
942 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
943 #define OF_DATA_IN BIT_6 /* Data in to initiator */
944 /* (data from target to initiator) */
945 #define OF_DATA_OUT BIT_7 /* Data out from initiator */
946 /* (data from initiator to target) */
947 #define OF_NO_DATA (BIT_7 | BIT_6)
948 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
949 #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */
950 #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */
951 #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */
952 #define OF_SSTS BIT_31 /* Send SCSI status */
956 * BUS parameters/settings structure - UNUSED
959 uint8_t id; /* Host adapter SCSI id */
960 uint8_t bus_reset_delay; /* SCSI bus reset delay. */
961 uint8_t failed_reset_count; /* number of time reset failed */
963 uint16_t device_enables; /* Device enable bits. */
964 uint16_t lun_disables; /* LUN disable bits. */
965 uint16_t qtag_enables; /* Tag queue enables. */
966 uint16_t hiwat; /* High water mark per device. */
967 uint8_t reset_marker:1;
968 uint8_t disable_scsi_reset:1;
969 uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */
973 struct qla_driver_setup {
985 * Linux Host Adapter structure
987 struct scsi_qla_host {
988 /* Linux adapter configuration data */
989 struct Scsi_Host *host; /* pointer to host data */
990 struct scsi_qla_host *next;
991 struct device_reg *iobase; /* Base Memory-mapped I/O address */
993 unsigned char *mmpbase; /* memory mapped address */
994 unsigned long host_no;
995 struct pci_dev *pdev;
1000 unsigned long actthreads;
1001 unsigned long isr_count; /* Interrupt count */
1002 unsigned long spurious_int;
1004 /* Outstandings ISP commands. */
1005 struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
1007 /* BUS configuration data */
1008 struct bus_param bus_settings[MAX_BUSES];
1010 /* Received ISP mailbox data. */
1011 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1013 dma_addr_t request_dma; /* Physical Address */
1014 request_t *request_ring; /* Base virtual address */
1015 request_t *request_ring_ptr; /* Current address. */
1016 uint16_t req_ring_index; /* Current index. */
1017 uint16_t req_q_cnt; /* Number of available entries. */
1019 dma_addr_t response_dma; /* Physical address. */
1020 struct response *response_ring; /* Base virtual address */
1021 struct response *response_ring_ptr; /* Current address. */
1022 uint16_t rsp_ring_index; /* Current index. */
1024 struct list_head done_q; /* Done queue */
1026 struct completion *mailbox_wait;
1029 uint32_t online:1; /* 0 */
1030 uint32_t reset_marker:1; /* 1 */
1031 uint32_t disable_host_adapter:1; /* 2 */
1032 uint32_t reset_active:1; /* 3 */
1033 uint32_t abort_isp_active:1; /* 4 */
1034 uint32_t disable_risc_code_load:1; /* 5 */
1035 uint32_t enable_64bit_addressing:1; /* 6 */
1036 uint32_t in_reset:1; /* 7 */
1037 uint32_t ints_enabled:1;
1038 uint32_t ignore_nvram:1;
1040 uint32_t use_pci_vchannel:1;
1048 #endif /* _QLA1280_H */