1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/mempool.h>
32 #include <linux/spinlock.h>
33 #include <linux/completion.h>
34 #include <asm/semaphore.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_host.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_cmnd.h>
41 /* XXX(hch): move to pci_ids.h */
42 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
43 #define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
47 #define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
51 #define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
55 #define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
59 #define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
62 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
63 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
65 #define IS_QLA2100(ha) 0
68 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
69 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
71 #define IS_QLA2200(ha) 0
74 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
75 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
76 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
78 #define IS_QLA2300(ha) 0
79 #define IS_QLA2312(ha) 0
82 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
83 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
85 #define IS_QLA2322(ha) 0
88 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
89 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
91 #define IS_QLA6312(ha) 0
94 #if defined(CONFIG_SCSI_QLA6322) || defined(CONFIG_SCSI_QLA6322_MODULE)
95 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
97 #define IS_QLA6322(ha) 0
100 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
101 IS_QLA6312(ha) || IS_QLA6322(ha))
104 * Only non-ISP2[12]00 have extended addressing support in the firmware.
106 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
109 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
110 * but that's fine as we don't look at the last 24 ones for
113 #define MAILBOX_REGISTER_COUNT_2100 8
114 #define MAILBOX_REGISTER_COUNT 32
116 #define QLA2200A_RISC_ROM_VER 4
120 #include "qla_settings.h"
123 * Data bit definitions
137 #define BIT_12 0x1000
138 #define BIT_13 0x2000
139 #define BIT_14 0x4000
140 #define BIT_15 0x8000
141 #define BIT_16 0x10000
142 #define BIT_17 0x20000
143 #define BIT_18 0x40000
144 #define BIT_19 0x80000
145 #define BIT_20 0x100000
146 #define BIT_21 0x200000
147 #define BIT_22 0x400000
148 #define BIT_23 0x800000
149 #define BIT_24 0x1000000
150 #define BIT_25 0x2000000
151 #define BIT_26 0x4000000
152 #define BIT_27 0x8000000
153 #define BIT_28 0x10000000
154 #define BIT_29 0x20000000
155 #define BIT_30 0x40000000
156 #define BIT_31 0x80000000
158 #define LSB(x) ((uint8_t)(x))
159 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
161 #define LSW(x) ((uint16_t)(x))
162 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
164 #define LSD(x) ((uint32_t)((uint64_t)(x)))
165 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
172 #define RD_REG_BYTE(addr) readb(addr)
173 #define RD_REG_WORD(addr) readw(addr)
174 #define RD_REG_DWORD(addr) readl(addr)
175 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
176 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
177 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
178 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
179 #define WRT_REG_WORD(addr, data) writew(data,addr)
180 #define WRT_REG_DWORD(addr, data) writel(data,addr)
183 * Fibre Channel device definitions.
185 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
186 #define MAX_FIBRE_DEVICES 512
187 #define MAX_FIBRE_LUNS 256
188 #define MAX_RSCN_COUNT 32
189 #define MAX_HOST_COUNT 16
192 * Host adapter default definitions.
194 #define MAX_BUSES 1 /* We only have one bus today */
195 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
196 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
197 #define MAX_TARGETS MAX_FIBRE_DEVICES
199 #define MAX_LUNS MAX_FIBRE_LUNS
200 #define MAX_CMDS_PER_LUN 255
203 * Fibre Channel device definitions.
205 #define SNS_LAST_LOOP_ID_2100 0xfe
206 #define SNS_LAST_LOOP_ID_2300 0x7ff
208 #define LAST_LOCAL_LOOP_ID 0x7d
209 #define SNS_FL_PORT 0x7e
210 #define FABRIC_CONTROLLER 0x7f
211 #define SIMPLE_NAME_SERVER 0x80
212 #define SNS_FIRST_LOOP_ID 0x81
213 #define MANAGEMENT_SERVER 0xfe
214 #define BROADCAST 0xff
216 #define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
217 x < SNS_FIRST_LOOP_ID) || \
218 x == MANAGEMENT_SERVER || \
222 * Timeout timer counts in seconds
224 #define PORT_RETRY_TIME 2
225 #define LOOP_DOWN_TIMEOUT 60
226 #define LOOP_DOWN_TIME 255 /* 240 */
227 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
229 /* Maximum outstanding commands in ISP queues (1-65535) */
230 #define MAX_OUTSTANDING_COMMANDS 1024
232 /* ISP request and response entry counts (37-65535) */
233 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
234 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
235 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
236 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
242 struct list_head list;
244 struct scsi_qla_host *ha; /* HA the SP is queued on */
246 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
248 struct timer_list timer; /* Command timer */
249 atomic_t ref_count; /* Reference count for this structure */
255 /* Target/LUN queue pointers. */
256 struct os_tgt *tgt_queue; /* ptr to visible ha's target */
257 struct os_lun *lun_queue; /* ptr to visible ha's lun */
258 struct fc_lun *fclun; /* FC LUN context pointer. */
261 unsigned long e_start; /* Start of extend timeout */
262 unsigned long r_start; /* Start of request */
263 unsigned long u_start; /* When sent to RISC */
264 unsigned long f_start; /* When placed in FO queue*/
266 /* Single transfer DMA context */
267 dma_addr_t dma_handle;
269 uint32_t request_sense_length;
270 uint8_t *request_sense_ptr;
277 /* Raw completion info for use by failover ? */
278 uint8_t fo_retry_cnt; /* Retry count this request */
279 uint8_t err_id; /* error id */
280 #define SRB_ERR_PORT 1 /* Request failed -- "port down" */
281 #define SRB_ERR_LOOP 2 /* Request failed -- "loop down" */
282 #define SRB_ERR_DEVICE 3 /* Request failed -- "device error" */
283 #define SRB_ERR_OTHER 4
285 /* SRB magic number */
287 #define SRB_MAGIC 0x10CB
291 * SRB flag definitions
293 #define SRB_TIMEOUT BIT_0 /* Command timed out */
294 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
295 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
296 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
298 #define SRB_ABORTED BIT_4 /* Command aborted command already */
299 #define SRB_RETRY BIT_5 /* Command needs retrying */
300 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
301 #define SRB_FAILOVER BIT_7 /* Command in failover state */
303 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
304 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
305 #define SRB_IOCTL BIT_10 /* IOCTL command. */
306 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
309 * SRB state definitions
311 #define SRB_FREE_STATE 0 /* returned back */
312 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
313 #define SRB_ACTIVE_STATE 2 /* in Active Array */
314 #define SRB_DONE_STATE 3 /* queued in Done Queue */
315 #define SRB_RETRY_STATE 4 /* in Retry Queue */
316 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
317 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
318 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
319 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
320 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
324 * ISP I/O Register Set structure definitions.
326 typedef volatile struct {
327 volatile uint16_t flash_address; /* Flash BIOS address */
328 volatile uint16_t flash_data; /* Flash BIOS data */
329 uint16_t unused_1[1]; /* Gap */
330 volatile uint16_t ctrl_status; /* Control/Status */
331 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
332 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
333 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
335 volatile uint16_t ictrl; /* Interrupt control */
336 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
337 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
339 volatile uint16_t istatus; /* Interrupt status */
340 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
342 volatile uint16_t semaphore; /* Semaphore */
343 volatile uint16_t nvram; /* NVRAM register. */
344 #define NVR_DESELECT 0
345 #define NVR_BUSY BIT_15
346 #define NVR_DATA_IN BIT_3
347 #define NVR_DATA_OUT BIT_2
348 #define NVR_SELECT BIT_1
349 #define NVR_CLOCK BIT_0
353 volatile uint16_t mailbox0;
354 volatile uint16_t mailbox1;
355 volatile uint16_t mailbox2;
356 volatile uint16_t mailbox3;
357 volatile uint16_t mailbox4;
358 volatile uint16_t mailbox5;
359 volatile uint16_t mailbox6;
360 volatile uint16_t mailbox7;
361 uint16_t unused_2[59]; /* Gap */
362 } __attribute__((packed)) isp2100;
365 volatile uint16_t req_q_in; /* In-Pointer */
366 volatile uint16_t req_q_out; /* Out-Pointer */
368 volatile uint16_t rsp_q_in; /* In-Pointer */
369 volatile uint16_t rsp_q_out; /* Out-Pointer */
371 /* RISC to Host Status */
372 volatile uint32_t host_status;
373 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
374 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
376 /* Host to Host Semaphore */
377 volatile uint16_t host_semaphore;
378 uint16_t unused_3[17]; /* Gap */
379 volatile uint16_t mailbox0;
380 volatile uint16_t mailbox1;
381 volatile uint16_t mailbox2;
382 volatile uint16_t mailbox3;
383 volatile uint16_t mailbox4;
384 volatile uint16_t mailbox5;
385 volatile uint16_t mailbox6;
386 volatile uint16_t mailbox7;
387 volatile uint16_t mailbox8;
388 volatile uint16_t mailbox9;
389 volatile uint16_t mailbox10;
390 volatile uint16_t mailbox11;
391 volatile uint16_t mailbox12;
392 volatile uint16_t mailbox13;
393 volatile uint16_t mailbox14;
394 volatile uint16_t mailbox15;
395 volatile uint16_t mailbox16;
396 volatile uint16_t mailbox17;
397 volatile uint16_t mailbox18;
398 volatile uint16_t mailbox19;
399 volatile uint16_t mailbox20;
400 volatile uint16_t mailbox21;
401 volatile uint16_t mailbox22;
402 volatile uint16_t mailbox23;
403 volatile uint16_t mailbox24;
404 volatile uint16_t mailbox25;
405 volatile uint16_t mailbox26;
406 volatile uint16_t mailbox27;
407 volatile uint16_t mailbox28;
408 volatile uint16_t mailbox29;
409 volatile uint16_t mailbox30;
410 volatile uint16_t mailbox31;
411 volatile uint16_t fb_cmd;
412 uint16_t unused_4[10]; /* Gap */
413 } __attribute__((packed)) isp2300;
416 volatile uint16_t fpm_diag_config;
417 uint16_t unused_5[0x6]; /* Gap */
418 volatile uint16_t pcr; /* Processor Control Register. */
419 uint16_t unused_6[0x5]; /* Gap */
420 volatile uint16_t mctr; /* Memory Configuration and Timing. */
421 uint16_t unused_7[0x3]; /* Gap */
422 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
423 uint16_t unused_8[0x3]; /* Gap */
424 volatile uint16_t hccr; /* Host command & control register. */
425 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
426 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
428 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
429 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
430 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
431 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
432 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
433 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
434 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
435 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
437 uint16_t unused_9[5]; /* Gap */
438 volatile uint16_t gpiod; /* GPIO Data register. */
439 volatile uint16_t gpioe; /* GPIO Enable register. */
440 #define GPIO_LED_MASK 0x00C0
441 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
442 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
443 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
444 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
448 uint16_t unused_10[8]; /* Gap */
449 volatile uint16_t mailbox8;
450 volatile uint16_t mailbox9;
451 volatile uint16_t mailbox10;
452 volatile uint16_t mailbox11;
453 volatile uint16_t mailbox12;
454 volatile uint16_t mailbox13;
455 volatile uint16_t mailbox14;
456 volatile uint16_t mailbox15;
457 volatile uint16_t mailbox16;
458 volatile uint16_t mailbox17;
459 volatile uint16_t mailbox18;
460 volatile uint16_t mailbox19;
461 volatile uint16_t mailbox20;
462 volatile uint16_t mailbox21;
463 volatile uint16_t mailbox22;
464 volatile uint16_t mailbox23; /* Also probe reg. */
465 } __attribute__((packed)) isp2200;
469 #define ISP_REQ_Q_IN(ha, reg) \
470 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
471 &(reg)->u.isp2100.mailbox4 : \
472 &(reg)->u.isp2300.req_q_in)
473 #define ISP_REQ_Q_OUT(ha, reg) \
474 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
475 &(reg)->u.isp2100.mailbox4 : \
476 &(reg)->u.isp2300.req_q_out)
477 #define ISP_RSP_Q_IN(ha, reg) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 &(reg)->u.isp2100.mailbox5 : \
480 &(reg)->u.isp2300.rsp_q_in)
481 #define ISP_RSP_Q_OUT(ha, reg) \
482 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
483 &(reg)->u.isp2100.mailbox5 : \
484 &(reg)->u.isp2300.rsp_q_out)
486 #define MAILBOX_REG(ha, reg, num) \
487 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
489 &(reg)->u.isp2100.mailbox0 + (num) : \
490 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
491 &(reg)->u.isp2300.mailbox0 + (num))
492 #define RD_MAILBOX_REG(ha, reg, num) \
493 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
494 #define WRT_MAILBOX_REG(ha, reg, num, data) \
495 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
497 #define FB_CMD_REG(ha, reg) \
498 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
499 &(reg)->fb_cmd_2100 : \
500 &(reg)->u.isp2300.fb_cmd)
501 #define RD_FB_CMD_REG(ha, reg) \
502 RD_REG_WORD(FB_CMD_REG(ha, reg))
503 #define WRT_FB_CMD_REG(ha, reg, data) \
504 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
507 uint32_t out_mb; /* outbound from driver */
508 uint32_t in_mb; /* Incoming from RISC */
509 uint16_t mb[MAILBOX_REGISTER_COUNT];
514 #define MBX_DMA_IN BIT_0
515 #define MBX_DMA_OUT BIT_1
516 #define IOCTL_CMD BIT_2
519 #define MBX_TOV_SECONDS 30
522 * ISP product identification definitions in mailboxes after reset.
524 #define PROD_ID_1 0x4953
525 #define PROD_ID_2 0x0000
526 #define PROD_ID_2a 0x5020
527 #define PROD_ID_3 0x2020
530 * ISP mailbox Self-Test status codes
532 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
533 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
534 #define MBS_BUSY 4 /* Busy. */
537 * ISP mailbox command complete status codes
539 #define MBS_COMMAND_COMPLETE 0x4000
540 #define MBS_INVALID_COMMAND 0x4001
541 #define MBS_HOST_INTERFACE_ERROR 0x4002
542 #define MBS_TEST_FAILED 0x4003
543 #define MBS_COMMAND_ERROR 0x4005
544 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
545 #define MBS_PORT_ID_USED 0x4007
546 #define MBS_LOOP_ID_USED 0x4008
547 #define MBS_ALL_IDS_IN_USE 0x4009
548 #define MBS_NOT_LOGGED_IN 0x400A
551 * ISP mailbox asynchronous event status codes
553 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
554 #define MBA_RESET 0x8001 /* Reset Detected. */
555 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
556 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
557 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
558 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
559 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
561 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
562 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
563 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
564 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
565 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
566 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
567 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
568 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
569 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
570 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
571 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
572 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
573 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
574 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
575 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
576 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
578 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
579 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
580 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
581 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
582 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
583 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
584 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
585 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
586 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
587 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
588 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
589 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
590 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
593 * Firmware options 1, 2, 3.
595 #define FO1_AE_ON_LIPF8 BIT_0
596 #define FO1_AE_ALL_LIP_RESET BIT_1
597 #define FO1_CTIO_RETRY BIT_3
598 #define FO1_DISABLE_LIP_F7_SW BIT_4
599 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
600 #define FO1_DISABLE_GPIO6_7 BIT_6
601 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
602 #define FO1_SET_EMPHASIS_SWING BIT_8
603 #define FO1_AE_AUTO_BYPASS BIT_9
604 #define FO1_ENABLE_PURE_IOCB BIT_10
605 #define FO1_AE_PLOGI_RJT BIT_11
606 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
607 #define FO1_AE_QUEUE_FULL BIT_13
609 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
610 #define FO2_REV_LOOPBACK BIT_1
612 #define FO3_ENABLE_EMERG_IOCB BIT_0
613 #define FO3_AE_RND_ERROR BIT_1
616 * ISP mailbox commands
618 #define MBC_LOAD_RAM 1 /* Load RAM. */
619 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
620 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
621 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
622 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
623 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
624 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
625 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
626 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
627 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
628 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
629 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
630 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
631 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
632 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
633 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
634 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
635 #define MBC_RESET 0x18 /* Reset. */
636 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
637 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
638 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
639 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
640 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
641 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
642 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
643 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
644 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
645 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
646 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
647 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
648 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
649 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
650 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
651 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
652 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
653 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
654 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
655 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
656 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
657 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
658 /* Initialization Procedure */
659 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
660 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
661 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
662 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
663 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
664 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
665 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
666 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
667 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
668 #define MBC_LIP_RESET 0x6c /* LIP reset. */
669 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
671 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
672 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
673 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
674 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
675 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
676 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
677 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
678 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
679 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
680 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
681 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
683 /* Firmware return data sizes */
684 #define FCAL_MAP_SIZE 128
686 /* Mailbox bit definitions for out_mb and in_mb */
687 #define MBX_31 BIT_31
688 #define MBX_30 BIT_30
689 #define MBX_29 BIT_29
690 #define MBX_28 BIT_28
691 #define MBX_27 BIT_27
692 #define MBX_26 BIT_26
693 #define MBX_25 BIT_25
694 #define MBX_24 BIT_24
695 #define MBX_23 BIT_23
696 #define MBX_22 BIT_22
697 #define MBX_21 BIT_21
698 #define MBX_20 BIT_20
699 #define MBX_19 BIT_19
700 #define MBX_18 BIT_18
701 #define MBX_17 BIT_17
702 #define MBX_16 BIT_16
703 #define MBX_15 BIT_15
704 #define MBX_14 BIT_14
705 #define MBX_13 BIT_13
706 #define MBX_12 BIT_12
707 #define MBX_11 BIT_11
708 #define MBX_10 BIT_10
721 * Firmware state codes from get firmware state mailbox command
723 #define FSTATE_CONFIG_WAIT 0
724 #define FSTATE_WAIT_AL_PA 1
725 #define FSTATE_WAIT_LOGIN 2
726 #define FSTATE_READY 3
727 #define FSTATE_LOSS_OF_SYNC 4
728 #define FSTATE_ERROR 5
729 #define FSTATE_REINIT 6
730 #define FSTATE_NON_PART 7
732 #define FSTATE_CONFIG_CORRECT 0
733 #define FSTATE_P2P_RCV_LIP 1
734 #define FSTATE_P2P_CHOOSE_LOOP 2
735 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
736 #define FSTATE_FATAL_ERROR 4
737 #define FSTATE_LOOP_BACK_CONN 5
740 * Port Database structure definition
741 * Little endian except where noted.
743 #define PORT_DATABASE_SIZE 128 /* bytes */
747 uint8_t master_state;
750 uint8_t hard_address;
753 uint8_t node_name[WWN_SIZE];
754 uint8_t port_name[WWN_SIZE];
755 uint16_t execution_throttle;
756 uint16_t execution_count;
759 uint16_t resource_allocation;
760 uint16_t current_allocation;
763 uint16_t transmit_execution_list_next;
764 uint16_t transmit_execution_list_previous;
765 uint16_t common_features;
766 uint16_t total_concurrent_sequences;
767 uint16_t RO_by_information_category;
770 uint16_t receive_data_size;
771 uint16_t concurrent_sequences;
772 uint16_t open_sequences_per_exchange;
773 uint16_t lun_abort_flags;
774 uint16_t lun_stop_flags;
775 uint16_t stop_queue_head;
776 uint16_t stop_queue_tail;
777 uint16_t port_retry_timer;
778 uint16_t next_sequence_id;
779 uint16_t frame_count;
780 uint16_t PRLI_payload_length;
781 uint8_t prli_svc_param_word_0[2]; /* Big endian */
782 /* Bits 15-0 of word 0 */
783 uint8_t prli_svc_param_word_3[2]; /* Big endian */
784 /* Bits 15-0 of word 3 */
786 uint16_t extended_lun_info_list_pointer;
787 uint16_t extended_lun_stop_list_pointer;
791 * Port database slave/master states
793 #define PD_STATE_DISCOVERY 0
794 #define PD_STATE_WAIT_DISCOVERY_ACK 1
795 #define PD_STATE_PORT_LOGIN 2
796 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
797 #define PD_STATE_PROCESS_LOGIN 4
798 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
799 #define PD_STATE_PORT_LOGGED_IN 6
800 #define PD_STATE_PORT_UNAVAILABLE 7
801 #define PD_STATE_PROCESS_LOGOUT 8
802 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
803 #define PD_STATE_PORT_LOGOUT 10
804 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
808 * ISP Initialization Control Block.
809 * Little endian except where noted.
811 #define ICB_VERSION 1
817 * LSB BIT 0 = Enable Hard Loop Id
818 * LSB BIT 1 = Enable Fairness
819 * LSB BIT 2 = Enable Full-Duplex
820 * LSB BIT 3 = Enable Fast Posting
821 * LSB BIT 4 = Enable Target Mode
822 * LSB BIT 5 = Disable Initiator Mode
823 * LSB BIT 6 = Enable ADISC
824 * LSB BIT 7 = Enable Target Inquiry Data
826 * MSB BIT 0 = Enable PDBC Notify
827 * MSB BIT 1 = Non Participating LIP
828 * MSB BIT 2 = Descending Loop ID Search
829 * MSB BIT 3 = Acquire Loop ID in LIPA
830 * MSB BIT 4 = Stop PortQ on Full Status
831 * MSB BIT 5 = Full Login after LIP
832 * MSB BIT 6 = Node Name Option
833 * MSB BIT 7 = Ext IFWCB enable bit
835 uint8_t firmware_options[2];
837 uint16_t frame_payload_size;
838 uint16_t max_iocb_allocation;
839 uint16_t execution_throttle;
841 uint8_t retry_delay; /* unused */
842 uint8_t port_name[WWN_SIZE]; /* Big endian. */
843 uint16_t hard_address;
844 uint8_t inquiry_data;
845 uint8_t login_timeout;
846 uint8_t node_name[WWN_SIZE]; /* Big endian. */
848 uint16_t request_q_outpointer;
849 uint16_t response_q_inpointer;
850 uint16_t request_q_length;
851 uint16_t response_q_length;
852 uint32_t request_q_address[2];
853 uint32_t response_q_address[2];
855 uint16_t lun_enables;
856 uint8_t command_resource_count;
857 uint8_t immediate_notify_resource_count;
859 uint8_t reserved_2[2];
862 * LSB BIT 0 = Timer Operation mode bit 0
863 * LSB BIT 1 = Timer Operation mode bit 1
864 * LSB BIT 2 = Timer Operation mode bit 2
865 * LSB BIT 3 = Timer Operation mode bit 3
866 * LSB BIT 4 = Init Config Mode bit 0
867 * LSB BIT 5 = Init Config Mode bit 1
868 * LSB BIT 6 = Init Config Mode bit 2
869 * LSB BIT 7 = Enable Non part on LIHA failure
871 * MSB BIT 0 = Enable class 2
872 * MSB BIT 1 = Enable ACK0
875 * MSB BIT 4 = FC Tape Enable
876 * MSB BIT 5 = Enable FC Confirm
877 * MSB BIT 6 = Enable command queuing in target mode
878 * MSB BIT 7 = No Logo On Link Down
880 uint8_t add_firmware_options[2];
882 uint8_t response_accumulation_timer;
883 uint8_t interrupt_delay_timer;
886 * LSB BIT 0 = Enable Read xfr_rdy
887 * LSB BIT 1 = Soft ID only
890 * LSB BIT 4 = FCP RSP Payload [0]
891 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
892 * LSB BIT 6 = Enable Out-of-Order frame handling
893 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
895 * MSB BIT 0 = Sbus enable - 2300
900 * MSB BIT 5 = enable 50 ohm termination
901 * MSB BIT 6 = Data Rate (2300 only)
902 * MSB BIT 7 = Data Rate (2300 only)
904 uint8_t special_options[2];
906 uint8_t reserved_3[26];
910 * Get Link Status mailbox command return buffer.
913 uint32_t link_fail_cnt;
914 uint32_t loss_sync_cnt;
915 uint32_t loss_sig_cnt;
916 uint32_t prim_seq_err_cnt;
917 uint32_t inval_xmit_word_cnt;
918 uint32_t inval_crc_cnt;
922 * NVRAM Command values.
924 #define NV_START_BIT BIT_2
925 #define NV_WRITE_OP (BIT_26+BIT_24)
926 #define NV_READ_OP (BIT_26+BIT_25)
927 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
928 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
929 #define NV_DELAY_COUNT 10
932 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
939 uint8_t nvram_version;
943 * NVRAM RISC parameter block
945 uint8_t parameter_block_version;
949 * LSB BIT 0 = Enable Hard Loop Id
950 * LSB BIT 1 = Enable Fairness
951 * LSB BIT 2 = Enable Full-Duplex
952 * LSB BIT 3 = Enable Fast Posting
953 * LSB BIT 4 = Enable Target Mode
954 * LSB BIT 5 = Disable Initiator Mode
955 * LSB BIT 6 = Enable ADISC
956 * LSB BIT 7 = Enable Target Inquiry Data
958 * MSB BIT 0 = Enable PDBC Notify
959 * MSB BIT 1 = Non Participating LIP
960 * MSB BIT 2 = Descending Loop ID Search
961 * MSB BIT 3 = Acquire Loop ID in LIPA
962 * MSB BIT 4 = Stop PortQ on Full Status
963 * MSB BIT 5 = Full Login after LIP
964 * MSB BIT 6 = Node Name Option
965 * MSB BIT 7 = Ext IFWCB enable bit
967 uint8_t firmware_options[2];
969 uint16_t frame_payload_size;
970 uint16_t max_iocb_allocation;
971 uint16_t execution_throttle;
973 uint8_t retry_delay; /* unused */
974 uint8_t port_name[WWN_SIZE]; /* Big endian. */
975 uint16_t hard_address;
976 uint8_t inquiry_data;
977 uint8_t login_timeout;
978 uint8_t node_name[WWN_SIZE]; /* Big endian. */
981 * LSB BIT 0 = Timer Operation mode bit 0
982 * LSB BIT 1 = Timer Operation mode bit 1
983 * LSB BIT 2 = Timer Operation mode bit 2
984 * LSB BIT 3 = Timer Operation mode bit 3
985 * LSB BIT 4 = Init Config Mode bit 0
986 * LSB BIT 5 = Init Config Mode bit 1
987 * LSB BIT 6 = Init Config Mode bit 2
988 * LSB BIT 7 = Enable Non part on LIHA failure
990 * MSB BIT 0 = Enable class 2
991 * MSB BIT 1 = Enable ACK0
994 * MSB BIT 4 = FC Tape Enable
995 * MSB BIT 5 = Enable FC Confirm
996 * MSB BIT 6 = Enable command queuing in target mode
997 * MSB BIT 7 = No Logo On Link Down
999 uint8_t add_firmware_options[2];
1001 uint8_t response_accumulation_timer;
1002 uint8_t interrupt_delay_timer;
1005 * LSB BIT 0 = Enable Read xfr_rdy
1006 * LSB BIT 1 = Soft ID only
1009 * LSB BIT 4 = FCP RSP Payload [0]
1010 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1011 * LSB BIT 6 = Enable Out-of-Order frame handling
1012 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1014 * MSB BIT 0 = Sbus enable - 2300
1019 * MSB BIT 5 = enable 50 ohm termination
1020 * MSB BIT 6 = Data Rate (2300 only)
1021 * MSB BIT 7 = Data Rate (2300 only)
1023 uint8_t special_options[2];
1025 /* Reserved for expanded RISC parameter block */
1026 uint8_t reserved_2[24];
1029 * LSB BIT 0 = Output Swing 1G bit 0
1030 * LSB BIT 1 = Output Swing 1G bit 1
1031 * LSB BIT 2 = Output Swing 1G bit 2
1032 * LSB BIT 3 = Output Emphasis 1G bit 0
1033 * LSB BIT 4 = Output Emphasis 1G bit 1
1034 * LSB BIT 5 = Output Swing 2G bit 0
1035 * LSB BIT 6 = Output Swing 2G bit 1
1036 * LSB BIT 7 = Output Swing 2G bit 2
1038 * MSB BIT 0 = Output Emphasis 2G bit 0
1039 * MSB BIT 1 = Output Emphasis 2G bit 1
1040 * MSB BIT 2 = Output Enable
1047 uint8_t seriallink_options[2];
1050 * NVRAM host parameter block
1052 * LSB BIT 0 = Enable spinup delay
1053 * LSB BIT 1 = Disable BIOS
1054 * LSB BIT 2 = Enable Memory Map BIOS
1055 * LSB BIT 3 = Enable Selectable Boot
1056 * LSB BIT 4 = Disable RISC code load
1057 * LSB BIT 5 = Set cache line size 1
1058 * LSB BIT 6 = PCI Parity Disable
1059 * LSB BIT 7 = Enable extended logging
1061 * MSB BIT 0 = Enable 64bit addressing
1062 * MSB BIT 1 = Enable lip reset
1063 * MSB BIT 2 = Enable lip full login
1064 * MSB BIT 3 = Enable target reset
1065 * MSB BIT 4 = Enable database storage
1066 * MSB BIT 5 = Enable cache flush read
1067 * MSB BIT 6 = Enable database load
1068 * MSB BIT 7 = Enable alternate WWN
1072 uint8_t boot_node_name[WWN_SIZE];
1073 uint8_t boot_lun_number;
1074 uint8_t reset_delay;
1075 uint8_t port_down_retry_count;
1076 uint8_t boot_id_number;
1077 uint16_t max_luns_per_target;
1078 uint8_t fcode_boot_port_name[WWN_SIZE];
1079 uint8_t alternate_port_name[WWN_SIZE];
1080 uint8_t alternate_node_name[WWN_SIZE];
1083 * BIT 0 = Boot Zoning
1084 * BIT 1 = Alt-Boot Enable
1085 * BIT 2 = Report SCSI Path
1092 uint8_t efi_parameters;
1094 uint8_t link_down_timeout;
1096 uint8_t adapter_id_0[4];
1097 uint8_t adapter_id_1[4];
1098 uint8_t adapter_id_2[4];
1099 uint8_t adapter_id_3[4];
1101 uint8_t alt1_boot_node_name[WWN_SIZE];
1102 uint16_t alt1_boot_lun_number;
1103 uint8_t alt2_boot_node_name[WWN_SIZE];
1104 uint16_t alt2_boot_lun_number;
1105 uint8_t alt3_boot_node_name[WWN_SIZE];
1106 uint16_t alt3_boot_lun_number;
1107 uint8_t alt4_boot_node_name[WWN_SIZE];
1108 uint16_t alt4_boot_lun_number;
1109 uint8_t alt5_boot_node_name[WWN_SIZE];
1110 uint16_t alt5_boot_lun_number;
1111 uint8_t alt6_boot_node_name[WWN_SIZE];
1112 uint16_t alt6_boot_lun_number;
1113 uint8_t alt7_boot_node_name[WWN_SIZE];
1114 uint16_t alt7_boot_lun_number;
1116 uint8_t reserved_3[2];
1118 /* Offset 200-215 : Model Number */
1119 uint8_t model_number[16];
1121 /* OEM related items */
1122 uint8_t oem_specific[16];
1125 * NVRAM Adapter Features offset 232-239
1127 * LSB BIT 0 = External GBIC
1128 * LSB BIT 1 = Risc RAM parity
1129 * LSB BIT 2 = Buffer Plus Module
1130 * LSB BIT 3 = Multi Chip Adapter
1131 * LSB BIT 4 = Internal connector
1145 uint8_t adapter_features[2];
1147 uint8_t reserved_4[16];
1149 /* Subsystem vendor ID for ISP2200 */
1150 uint16_t subsystem_vendor_id_2200;
1152 /* Subsystem device ID for ISP2200 */
1153 uint16_t subsystem_device_id_2200;
1160 * ISP queue - response queue entry definition.
1165 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1176 #define SET_TARGET_ID(ha, to, from) \
1178 if (HAS_EXTENDED_IDS(ha)) \
1179 to.extended = cpu_to_le16(from); \
1181 to.id.standard = (uint8_t)from; \
1185 * ISP queue - command entry structure definition.
1187 #define COMMAND_TYPE 0x11 /* Command entry */
1188 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1190 uint8_t entry_type; /* Entry type. */
1191 uint8_t entry_count; /* Entry count. */
1192 uint8_t sys_define; /* System defined. */
1193 uint8_t entry_status; /* Entry Status. */
1194 uint32_t handle; /* System handle. */
1195 target_id_t target; /* SCSI ID */
1196 uint16_t lun; /* SCSI LUN */
1197 uint16_t control_flags; /* Control flags. */
1198 #define CF_WRITE BIT_6
1199 #define CF_READ BIT_5
1200 #define CF_SIMPLE_TAG BIT_3
1201 #define CF_ORDERED_TAG BIT_2
1202 #define CF_HEAD_TAG BIT_1
1203 uint16_t reserved_1;
1204 uint16_t timeout; /* Command timeout. */
1205 uint16_t dseg_count; /* Data segment count. */
1206 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1207 uint32_t byte_count; /* Total byte count. */
1208 uint32_t dseg_0_address; /* Data segment 0 address. */
1209 uint32_t dseg_0_length; /* Data segment 0 length. */
1210 uint32_t dseg_1_address; /* Data segment 1 address. */
1211 uint32_t dseg_1_length; /* Data segment 1 length. */
1212 uint32_t dseg_2_address; /* Data segment 2 address. */
1213 uint32_t dseg_2_length; /* Data segment 2 length. */
1217 * ISP queue - 64-Bit addressing, command entry structure definition.
1219 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1221 uint8_t entry_type; /* Entry type. */
1222 uint8_t entry_count; /* Entry count. */
1223 uint8_t sys_define; /* System defined. */
1224 uint8_t entry_status; /* Entry Status. */
1225 uint32_t handle; /* System handle. */
1226 target_id_t target; /* SCSI ID */
1227 uint16_t lun; /* SCSI LUN */
1228 uint16_t control_flags; /* Control flags. */
1229 uint16_t reserved_1;
1230 uint16_t timeout; /* Command timeout. */
1231 uint16_t dseg_count; /* Data segment count. */
1232 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1233 uint32_t byte_count; /* Total byte count. */
1234 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1235 uint32_t dseg_0_length; /* Data segment 0 length. */
1236 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1237 uint32_t dseg_1_length; /* Data segment 1 length. */
1238 } cmd_a64_entry_t, request_t;
1241 * ISP queue - continuation entry structure definition.
1243 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1245 uint8_t entry_type; /* Entry type. */
1246 uint8_t entry_count; /* Entry count. */
1247 uint8_t sys_define; /* System defined. */
1248 uint8_t entry_status; /* Entry Status. */
1250 uint32_t dseg_0_address; /* Data segment 0 address. */
1251 uint32_t dseg_0_length; /* Data segment 0 length. */
1252 uint32_t dseg_1_address; /* Data segment 1 address. */
1253 uint32_t dseg_1_length; /* Data segment 1 length. */
1254 uint32_t dseg_2_address; /* Data segment 2 address. */
1255 uint32_t dseg_2_length; /* Data segment 2 length. */
1256 uint32_t dseg_3_address; /* Data segment 3 address. */
1257 uint32_t dseg_3_length; /* Data segment 3 length. */
1258 uint32_t dseg_4_address; /* Data segment 4 address. */
1259 uint32_t dseg_4_length; /* Data segment 4 length. */
1260 uint32_t dseg_5_address; /* Data segment 5 address. */
1261 uint32_t dseg_5_length; /* Data segment 5 length. */
1262 uint32_t dseg_6_address; /* Data segment 6 address. */
1263 uint32_t dseg_6_length; /* Data segment 6 length. */
1267 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1269 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1271 uint8_t entry_type; /* Entry type. */
1272 uint8_t entry_count; /* Entry count. */
1273 uint8_t sys_define; /* System defined. */
1274 uint8_t entry_status; /* Entry Status. */
1275 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1276 uint32_t dseg_0_length; /* Data segment 0 length. */
1277 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1278 uint32_t dseg_1_length; /* Data segment 1 length. */
1279 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1280 uint32_t dseg_2_length; /* Data segment 2 length. */
1281 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1282 uint32_t dseg_3_length; /* Data segment 3 length. */
1283 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1284 uint32_t dseg_4_length; /* Data segment 4 length. */
1288 * ISP queue - status entry structure definition.
1290 #define STATUS_TYPE 0x03 /* Status entry. */
1292 uint8_t entry_type; /* Entry type. */
1293 uint8_t entry_count; /* Entry count. */
1294 uint8_t sys_define; /* System defined. */
1295 uint8_t entry_status; /* Entry Status. */
1296 uint32_t handle; /* System handle. */
1297 uint16_t scsi_status; /* SCSI status. */
1298 uint16_t comp_status; /* Completion status. */
1299 uint16_t state_flags; /* State flags. */
1300 uint16_t status_flags; /* Status flags. */
1301 uint16_t rsp_info_len; /* Response Info Length. */
1302 uint16_t req_sense_length; /* Request sense data length. */
1303 uint32_t residual_length; /* Residual transfer length. */
1304 uint8_t rsp_info[8]; /* FCP response information. */
1305 uint8_t req_sense_data[32]; /* Request sense data. */
1309 * Status entry entry status
1311 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1312 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1313 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1314 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1315 #define RF_BUSY BIT_1 /* Busy */
1318 * Status entry SCSI status bit definitions.
1320 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1321 #define SS_RESIDUAL_UNDER BIT_11
1322 #define SS_RESIDUAL_OVER BIT_10
1323 #define SS_SENSE_LEN_VALID BIT_9
1324 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1326 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1327 #define SS_BUSY_CONDITION BIT_3
1328 #define SS_CONDITION_MET BIT_2
1329 #define SS_CHECK_CONDITION BIT_1
1332 * Status entry completion status
1334 #define CS_COMPLETE 0x0 /* No errors */
1335 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1336 #define CS_DMA 0x2 /* A DMA direction error. */
1337 #define CS_TRANSPORT 0x3 /* Transport error. */
1338 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1339 #define CS_ABORTED 0x5 /* System aborted command. */
1340 #define CS_TIMEOUT 0x6 /* Timeout error. */
1341 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1343 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1344 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1345 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1346 /* (selection timeout) */
1347 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1348 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1349 #define CS_PORT_BUSY 0x2B /* Port Busy */
1350 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1351 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1352 #define CS_UNKNOWN 0x81 /* Driver defined */
1353 #define CS_RETRY 0x82 /* Driver defined */
1354 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1357 * Status entry status flags
1359 #define SF_LOGOUT_SENT BIT_13
1362 * ISP queue - status continuation entry structure definition.
1364 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1366 uint8_t entry_type; /* Entry type. */
1367 uint8_t entry_count; /* Entry count. */
1368 uint8_t sys_define; /* System defined. */
1369 uint8_t entry_status; /* Entry Status. */
1370 uint8_t data[60]; /* data */
1374 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1375 * structure definition.
1377 #define STATUS_TYPE_21 0x21 /* Status entry. */
1379 uint8_t entry_type; /* Entry type. */
1380 uint8_t entry_count; /* Entry count. */
1381 uint8_t handle_count; /* Handle count. */
1382 uint8_t entry_status; /* Entry Status. */
1383 uint32_t handle[15]; /* System handles. */
1387 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1388 * structure definition.
1390 #define STATUS_TYPE_22 0x22 /* Status entry. */
1392 uint8_t entry_type; /* Entry type. */
1393 uint8_t entry_count; /* Entry count. */
1394 uint8_t handle_count; /* Handle count. */
1395 uint8_t entry_status; /* Entry Status. */
1396 uint16_t handle[30]; /* System handles. */
1400 * ISP queue - marker entry structure definition.
1402 #define MARKER_TYPE 0x04 /* Marker entry. */
1404 uint8_t entry_type; /* Entry type. */
1405 uint8_t entry_count; /* Entry count. */
1406 uint8_t handle_count; /* Handle count. */
1407 uint8_t entry_status; /* Entry Status. */
1408 uint32_t sys_define_2; /* System defined. */
1409 target_id_t target; /* SCSI ID */
1410 uint8_t modifier; /* Modifier (7-0). */
1411 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1412 #define MK_SYNC_ID 1 /* Synchronize ID */
1413 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1414 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1415 /* clear port changed, */
1416 /* use sequence number. */
1418 uint16_t sequence_number; /* Sequence number of event */
1419 uint16_t lun; /* SCSI LUN */
1420 uint8_t reserved_2[48];
1424 * ISP queue - Management Server entry structure definition.
1426 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1428 uint8_t entry_type; /* Entry type. */
1429 uint8_t entry_count; /* Entry count. */
1430 uint8_t handle_count; /* Handle count. */
1431 uint8_t entry_status; /* Entry Status. */
1432 uint32_t handle1; /* System handle. */
1433 target_id_t loop_id;
1435 uint16_t control_flags; /* Control flags. */
1438 uint16_t cmd_dsd_count;
1439 uint16_t total_dsd_count;
1445 uint32_t rsp_bytecount;
1446 uint32_t req_bytecount;
1447 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1448 uint32_t dseg_req_length; /* Data segment 0 length. */
1449 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1450 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1455 * ISP queue - Mailbox Command entry structure definition.
1457 #define MBX_IOCB_TYPE 0x39
1460 uint8_t entry_count;
1461 uint8_t sys_define1;
1462 /* Use sys_define1 for source type */
1463 #define SOURCE_SCSI 0x00
1464 #define SOURCE_IP 0x01
1465 #define SOURCE_VI 0x02
1466 #define SOURCE_SCTP 0x03
1467 #define SOURCE_MP 0x04
1468 #define SOURCE_MPIOCTL 0x05
1469 #define SOURCE_ASYNC_IOCB 0x07
1471 uint8_t entry_status;
1474 target_id_t loop_id;
1477 uint16_t state_flags;
1478 uint16_t status_flags;
1480 uint32_t sys_define2[2];
1490 uint32_t reserved_2[2];
1491 uint8_t node_name[WWN_SIZE];
1492 uint8_t port_name[WWN_SIZE];
1496 * ISP request and response queue entry sizes
1498 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1499 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1503 * 24 bit port ID type definition.
1520 #define INVALID_PORT_ID 0xFFFFFF
1523 * Switch info gathering structure.
1527 uint8_t node_name[WWN_SIZE];
1528 uint8_t port_name[WWN_SIZE];
1530 #define SW_TYPE_IP BIT_1
1531 #define SW_TYPE_SCSI BIT_0
1535 * Inquiry command structure.
1537 #define INQ_DATA_SIZE 36
1540 * Inquiry mailbox IOCB packet definition.
1544 cmd_a64_entry_t cmd;
1547 uint8_t inq[INQ_DATA_SIZE];
1551 * Report LUN command structure.
1553 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1563 uint8_t address_method : 2;
1571 rpt_lun_t lst[MAX_LUNS];
1575 * Report Lun mailbox IOCB packet definition.
1579 cmd_a64_entry_t cmd;
1583 } rpt_lun_cmd_rsp_t;
1586 * SCSI Target Queue structure
1588 typedef struct os_tgt {
1589 struct os_lun *olun[MAX_LUNS]; /* LUN context pointer. */
1590 struct fc_port *fcport;
1591 unsigned long flags;
1592 uint8_t port_down_retry_count;
1593 uint32_t down_timer;
1594 struct scsi_qla_host *ha;
1596 /* Persistent binding information */
1598 uint8_t node_name[WWN_SIZE];
1599 uint8_t port_name[WWN_SIZE];
1603 * SCSI Target Queue flags
1605 #define TQF_ONLINE 0 /* Device online to OS. */
1606 #define TQF_SUSPENDED 1
1607 #define TQF_RETRY_CMDS 2
1610 * SCSI LUN Queue structure
1612 typedef struct os_lun {
1613 struct fc_lun *fclun; /* FC LUN context pointer. */
1614 spinlock_t q_lock; /* Lun Lock */
1616 unsigned long q_flag;
1617 #define LUN_MPIO_BUSY 2 /* Lun is changing paths */
1618 #define LUN_EXEC_DELAYED 7 /* Lun execution is delayed */
1620 u_long q_timeout; /* total command timeouts */
1621 atomic_t q_timer; /* suspend timer */
1622 uint32_t q_count; /* current count */
1623 uint32_t q_max; /* maxmum count lun can be suspended */
1624 uint8_t q_state; /* lun State */
1625 #define LUN_STATE_READY 1 /* lun is ready for i/o */
1626 #define LUN_STATE_RUN 2 /* lun has a timer running */
1627 #define LUN_STATE_WAIT 3 /* lun is suspended */
1628 #define LUN_STATE_TIMEOUT 4 /* lun has timed out */
1630 u_long io_cnt; /* total xfer count since boot */
1631 u_long out_cnt; /* total outstanding IO count */
1632 u_long w_cnt; /* total writes */
1633 u_long r_cnt; /* total reads */
1634 u_long avg_time; /* */
1638 /* LUN BitMask structure definition, array of 32bit words,
1639 * 1 bit per lun. When bit == 1, the lun is masked.
1640 * Most significant bit of mask[0] is lun 0, bit 24 is lun 7.
1642 typedef struct lun_bit_mask {
1643 /* Must allocate at least enough bits to accomodate all LUNs */
1644 #if ((MAX_FIBRE_LUNS & 0x7) == 0)
1645 uint8_t mask[MAX_FIBRE_LUNS >> 3];
1647 uint8_t mask[(MAX_FIBRE_LUNS + 8) >> 3];
1652 * Fibre channel port type.
1664 * Fibre channel port structure.
1666 typedef struct fc_port {
1667 struct list_head list;
1668 struct list_head fcluns;
1670 struct scsi_qla_host *ha;
1671 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1673 uint8_t node_name[WWN_SIZE];
1674 uint8_t port_name[WWN_SIZE];
1677 uint16_t old_loop_id;
1679 fc_port_type_t port_type;
1684 os_tgt_t *tgt_queue;
1685 uint16_t os_target_id;
1687 uint16_t iodesc_idx_sent;
1689 int port_login_retry_count;
1691 atomic_t port_down_timer;
1693 uint8_t device_type;
1696 uint8_t mp_byte; /* multi-path byte (not used) */
1697 uint8_t cur_path; /* current path id */
1699 lun_bit_mask_t lun_mask;
1703 * Fibre channel port/lun states.
1705 #define FCS_UNCONFIGURED 1
1706 #define FCS_DEVICE_DEAD 2
1707 #define FCS_DEVICE_LOST 3
1708 #define FCS_ONLINE 4
1709 #define FCS_NOT_SUPPORTED 5
1710 #define FCS_FAILOVER 6
1711 #define FCS_FAILOVER_FAILED 7
1716 #define FCF_FABRIC_DEVICE BIT_0
1717 #define FCF_LOGIN_NEEDED BIT_1
1718 #define FCF_FO_MASKED BIT_2
1719 #define FCF_FAILOVER_NEEDED BIT_3
1720 #define FCF_RESET_NEEDED BIT_4
1721 #define FCF_PERSISTENT_BOUND BIT_5
1722 #define FCF_TAPE_PRESENT BIT_6
1723 #define FCF_FARP_DONE BIT_7
1724 #define FCF_FARP_FAILED BIT_8
1725 #define FCF_FARP_REPLY_NEEDED BIT_9
1726 #define FCF_AUTH_REQ BIT_10
1727 #define FCF_SEND_AUTH_REQ BIT_11
1728 #define FCF_RECEIVE_AUTH_REQ BIT_12
1729 #define FCF_AUTH_SUCCESS BIT_13
1730 #define FCF_RLC_SUPPORT BIT_14
1731 #define FCF_CONFIG BIT_15 /* Needed? */
1732 #define FCF_RESCAN_NEEDED BIT_16
1733 #define FCF_XP_DEVICE BIT_17
1734 #define FCF_MSA_DEVICE BIT_18
1735 #define FCF_EVA_DEVICE BIT_19
1736 #define FCF_MSA_PORT_ACTIVE BIT_20
1737 #define FCF_FAILBACK_DISABLE BIT_21
1738 #define FCF_FAILOVER_DISABLE BIT_22
1740 /* No loop ID flag. */
1741 #define FC_NO_LOOP_ID 0x1000
1744 * Fibre channel LUN structure.
1746 typedef struct fc_lun {
1747 struct list_head list;
1750 fc_port_t *o_fcport;
1753 uint8_t device_type;
1755 uint8_t max_path_retries;
1759 #define FLF_VISIBLE_LUN BIT_0
1760 #define FLF_ACTIVE_LUN BIT_1
1765 * NOTE: All structures are big-endian in form.
1768 #define CT_REJECT_RESPONSE 0x8001
1769 #define CT_ACCEPT_RESPONSE 0x8002
1771 #define NS_N_PORT_TYPE 0x01
1772 #define NS_NL_PORT_TYPE 0x02
1773 #define NS_NX_PORT_TYPE 0x7F
1775 #define GA_NXT_CMD 0x100
1776 #define GA_NXT_REQ_SIZE (16 + 4)
1777 #define GA_NXT_RSP_SIZE (16 + 620)
1779 #define GID_PT_CMD 0x1A1
1780 #define GID_PT_REQ_SIZE (16 + 4)
1781 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1783 #define GPN_ID_CMD 0x112
1784 #define GPN_ID_REQ_SIZE (16 + 4)
1785 #define GPN_ID_RSP_SIZE (16 + 8)
1787 #define GNN_ID_CMD 0x113
1788 #define GNN_ID_REQ_SIZE (16 + 4)
1789 #define GNN_ID_RSP_SIZE (16 + 8)
1791 #define GFT_ID_CMD 0x117
1792 #define GFT_ID_REQ_SIZE (16 + 4)
1793 #define GFT_ID_RSP_SIZE (16 + 32)
1795 #define RFT_ID_CMD 0x217
1796 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1797 #define RFT_ID_RSP_SIZE 16
1799 #define RFF_ID_CMD 0x21F
1800 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1801 #define RFF_ID_RSP_SIZE 16
1803 #define RNN_ID_CMD 0x213
1804 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1805 #define RNN_ID_RSP_SIZE 16
1807 #define RSNN_NN_CMD 0x239
1808 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1809 #define RSNN_NN_RSP_SIZE 16
1811 /* CT command header -- request/response common fields */
1821 /* CT command request */
1823 struct ct_cmd_hdr header;
1825 uint16_t max_rsp_size;
1826 uint8_t fragment_id;
1827 uint8_t reserved[3];
1830 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1846 uint8_t fc4_types[32];
1853 uint8_t fc4_feature;
1860 uint8_t node_name[8];
1864 uint8_t node_name[8];
1866 uint8_t sym_node_name[255];
1871 /* CT command response header */
1873 struct ct_cmd_hdr header;
1876 uint8_t fragment_id;
1877 uint8_t reason_code;
1878 uint8_t explanation_code;
1879 uint8_t vendor_unique;
1882 struct ct_sns_gid_pt_data {
1883 uint8_t control_byte;
1888 struct ct_rsp_hdr header;
1894 uint8_t port_name[8];
1895 uint8_t sym_port_name_len;
1896 uint8_t sym_port_name[255];
1897 uint8_t node_name[8];
1898 uint8_t sym_node_name_len;
1899 uint8_t sym_node_name[255];
1900 uint8_t init_proc_assoc[8];
1901 uint8_t node_ip_addr[16];
1902 uint8_t class_of_service[4];
1903 uint8_t fc4_types[32];
1904 uint8_t ip_address[16];
1905 uint8_t fabric_port_name[8];
1907 uint8_t hard_address[3];
1911 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1915 uint8_t port_name[8];
1919 uint8_t node_name[8];
1923 uint8_t fc4_types[32];
1930 struct ct_sns_req req;
1931 struct ct_sns_rsp rsp;
1936 * SNS command structures -- for 2200 compatability.
1938 #define RFT_ID_SNS_SCMD_LEN 22
1939 #define RFT_ID_SNS_CMD_SIZE 60
1940 #define RFT_ID_SNS_DATA_SIZE 16
1942 #define RNN_ID_SNS_SCMD_LEN 10
1943 #define RNN_ID_SNS_CMD_SIZE 36
1944 #define RNN_ID_SNS_DATA_SIZE 16
1946 #define GA_NXT_SNS_SCMD_LEN 6
1947 #define GA_NXT_SNS_CMD_SIZE 28
1948 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1950 #define GID_PT_SNS_SCMD_LEN 6
1951 #define GID_PT_SNS_CMD_SIZE 28
1952 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1954 #define GPN_ID_SNS_SCMD_LEN 6
1955 #define GPN_ID_SNS_CMD_SIZE 28
1956 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1958 #define GNN_ID_SNS_SCMD_LEN 6
1959 #define GNN_ID_SNS_CMD_SIZE 28
1960 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1962 struct sns_cmd_pkt {
1965 uint16_t buffer_length;
1966 uint16_t reserved_1;
1967 uint32_t buffer_address[2];
1968 uint16_t subcommand_length;
1969 uint16_t reserved_2;
1970 uint16_t subcommand;
1972 uint32_t reserved_3;
1976 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1977 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1978 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1979 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1980 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1981 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1985 /* IO descriptors */
1986 #define MAX_IO_DESCRIPTORS 32
1988 #define ABORT_IOCB_CB 0
1989 #define ADISC_PORT_IOCB_CB 1
1990 #define LOGOUT_PORT_IOCB_CB 2
1991 #define LOGIN_PORT_IOCB_CB 3
1992 #define LAST_IOCB_CB 4
1994 #define IODESC_INVALID_INDEX 0xFFFF
1995 #define IODESC_ADISC_NEEDED 0xFFFE
1996 #define IODESC_LOGIN_NEEDED 0xFFFD
1998 struct io_descriptor {
2003 struct timer_list timer;
2005 struct scsi_qla_host *ha;
2008 fc_port_t *remote_fcport;
2013 struct qla_fw_info {
2014 unsigned short addressing; /* addressing method used to load fw */
2015 #define FW_INFO_ADDR_NORMAL 0
2016 #define FW_INFO_ADDR_EXTENDED 1
2017 #define FW_INFO_ADDR_NOMORE 0xffff
2018 unsigned short *fwcode; /* pointer to FW array */
2019 unsigned short *fwlen; /* number of words in array */
2020 unsigned short *fwstart; /* start address for F/W */
2021 unsigned long *lfwstart; /* start address (long) for F/W */
2024 struct qla_board_info {
2028 struct qla_fw_info *fw_info;
2032 * Linux Host Adapter structure
2034 typedef struct scsi_qla_host {
2035 struct list_head list;
2037 /* Commonly used flags and state information. */
2038 struct Scsi_Host *host;
2039 struct pci_dev *pdev;
2041 unsigned long host_no;
2042 unsigned long instance;
2045 uint32_t init_done :1;
2047 uint32_t mbox_int :1;
2048 uint32_t mbox_busy :1;
2049 uint32_t rscn_queue_overflow :1;
2050 uint32_t reset_active :1;
2052 uint32_t management_server_logged_in :1;
2053 uint32_t process_response_queue :1;
2055 uint32_t disable_risc_code_load :1;
2056 uint32_t enable_64bit_addressing :1;
2057 uint32_t enable_lip_reset :1;
2058 uint32_t enable_lip_full_login :1;
2059 uint32_t enable_target_reset :1;
2062 atomic_t loop_state;
2063 #define LOOP_TIMEOUT 1
2066 #define LOOP_UPDATE 4
2067 #define LOOP_READY 5
2070 unsigned long dpc_flags;
2071 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2072 #define RESET_ACTIVE 1
2073 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2074 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2075 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2076 #define LOOP_RESYNC_ACTIVE 5
2077 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2078 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2079 #define MAILBOX_RETRY 8
2080 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2081 #define FAILOVER_EVENT_NEEDED 10
2082 #define FAILOVER_EVENT 11
2083 #define FAILOVER_NEEDED 12
2084 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2085 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2086 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2087 #define ABORT_QUEUES_NEEDED 16
2088 #define RELOGIN_NEEDED 17
2089 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2090 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2091 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2092 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2093 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2094 #define IOCTL_ERROR_RECOVERY 23
2096 uint32_t device_flags;
2097 #define DFLG_LOCAL_DEVICES BIT_0
2098 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2099 #define DFLG_FABRIC_DEVICES BIT_2
2100 #define SWITCH_FOUND BIT_3
2101 #define DFLG_NO_CABLE BIT_4
2104 #define SRB_MIN_REQ 128
2105 mempool_t *srb_mempool;
2107 /* This spinlock is used to protect "io transactions", you must
2108 * aquire it before doing any IO to the card, eg with RD_REG*() and
2109 * WRT_REG*() for the duration of your entire commandtransaction.
2111 * This spinlock is of lower priority than the io request lock.
2114 spinlock_t hardware_lock ____cacheline_aligned;
2116 device_reg_t *iobase; /* Base I/O address */
2117 unsigned long pio_address;
2118 unsigned long pio_length;
2119 void * mmio_address;
2120 unsigned long mmio_length;
2121 #define MIN_IOBASE_LEN 0x100
2123 /* ISP ring lock, rings, and indexes */
2124 dma_addr_t request_dma; /* Physical address. */
2125 request_t *request_ring; /* Base virtual address */
2126 request_t *request_ring_ptr; /* Current address. */
2127 uint16_t req_ring_index; /* Current index. */
2128 uint16_t req_q_cnt; /* Number of available entries. */
2129 uint16_t request_q_length;
2131 dma_addr_t response_dma; /* Physical address. */
2132 response_t *response_ring; /* Base virtual address */
2133 response_t *response_ring_ptr; /* Current address. */
2134 uint16_t rsp_ring_index; /* Current index. */
2135 uint16_t response_q_length;
2137 uint16_t (*calc_request_entries)(uint16_t);
2138 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2140 /* Outstandings ISP commands. */
2141 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2142 uint32_t current_outstanding_cmd;
2143 srb_t *status_srb; /* Status continuation entry. */
2146 * Need to hold the list_lock with irq's disabled in order to access
2147 * the following list.
2149 * This list_lock is of lower priority than the host_lock.
2151 spinlock_t list_lock ____cacheline_aligned;
2152 /* lock to guard lists which
2154 struct list_head retry_queue; /* watchdog queue */
2155 struct list_head done_queue; /* job on done queue */
2156 struct list_head failover_queue; /* failover list link. */
2157 struct list_head scsi_retry_queue; /* SCSI retry queue */
2158 struct list_head pending_queue; /* SCSI command pending queue */
2160 unsigned long done_q_cnt;
2161 unsigned long pending_in_q;
2162 uint32_t retry_q_cnt;
2163 uint32_t scsi_retry_q_cnt;
2164 uint32_t failover_cnt;
2166 unsigned long last_irq_cpu; /* cpu where we got our last irq */
2174 uint32_t total_isr_cnt; /* Interrupt count */
2175 uint32_t total_isp_aborts; /* controller err cnt */
2176 uint32_t total_lip_cnt; /* LIP cnt */
2177 uint32_t total_dev_errs; /* device error cnt */
2178 uint32_t total_ios; /* IO cnt */
2179 uint64_t total_bytes; /* xfr byte cnt */
2180 uint32_t total_mbx_timeout; /* mailbox timeout cnt */
2181 uint32_t total_loop_resync; /* loop resyn cnt */
2182 uint32_t dropped_frame_error_cnt;
2184 /* ISP configuration data. */
2185 uint16_t loop_id; /* Host adapter loop id */
2188 port_id_t d_id; /* Host adapter port id */
2189 uint16_t max_public_loop_ids;
2190 uint16_t min_external_loopid; /* First external loop Id */
2192 uint16_t link_data_rate; /* F/W operating speed */
2194 uint8_t current_topology;
2195 uint8_t prev_topology;
2196 #define ISP_CFG_NL 1
2198 #define ISP_CFG_FL 4
2201 uint8_t operating_mode; /* F/W operating mode */
2207 uint8_t marker_needed;
2208 uint8_t sns_retry_cnt;
2211 uint8_t interrupts_on;
2213 /* HBA serial number */
2218 /* NVRAM configuration data */
2219 uint16_t nvram_base;
2221 uint16_t loop_reset_delay;
2222 uint16_t minimum_timeout;
2223 uint8_t retry_count;
2224 uint8_t login_timeout;
2226 int port_down_retry_count;
2227 uint8_t loop_down_timeout;
2229 uint16_t max_probe_luns;
2231 uint16_t max_targets;
2232 uint16_t last_loop_id;
2234 uint32_t login_retry_count;
2236 /* Fibre Channel Device List. */
2237 struct list_head fcports;
2238 struct list_head rscn_fcports;
2240 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2241 uint16_t iodesc_signature;
2242 port_database_t *iodesc_pd;
2243 dma_addr_t iodesc_pd_dma;
2245 /* OS target queue pointers. */
2246 os_tgt_t *otgt[MAX_FIBRE_DEVICES];
2249 uint32_t rscn_queue[MAX_RSCN_COUNT];
2250 uint8_t rscn_in_ptr;
2251 uint8_t rscn_out_ptr;
2253 /* SNS command interfaces. */
2254 ms_iocb_entry_t *ms_iocb;
2255 dma_addr_t ms_iocb_dma;
2256 struct ct_sns_pkt *ct_sns;
2257 dma_addr_t ct_sns_dma;
2258 /* SNS command interfaces for 2200. */
2259 struct sns_cmd_pkt *sns_cmd;
2260 dma_addr_t sns_cmd_dma;
2264 struct completion dpc_inited;
2265 struct completion dpc_exited;
2266 struct semaphore *dpc_wait;
2267 uint8_t dpc_active; /* DPC routine is active */
2269 /* Timeout timers. */
2270 uint8_t queue_restart_timer;
2271 uint8_t loop_down_abort_time; /* port down timer */
2272 atomic_t loop_down_timer; /* loop down timer */
2273 uint8_t link_down_timeout; /* link down timeout */
2275 uint32_t timer_active;
2276 struct timer_list timer;
2278 /* Firmware Initialization Control Block data */
2279 dma_addr_t init_cb_dma; /* Physical address. */
2282 /* These are used by mailbox operations. */
2283 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2286 unsigned long mbx_cmd_flags;
2287 #define MBX_INTERRUPT 1
2288 #define MBX_INTR_WAIT 2
2289 #define MBX_UPDATE_FLASH_ACTIVE 3
2291 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2293 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2294 struct semaphore mbx_intr_sem; /* Used for completion notification */
2297 #define MBX_IN_PROGRESS BIT_0
2298 #define MBX_BUSY BIT_1 /* Got the Access */
2299 #define MBX_SLEEPING_ON_SEM BIT_2
2300 #define MBX_POLLING_FOR_COMP BIT_3
2301 #define MBX_COMPLETED BIT_4
2302 #define MBX_TIMEDOUT BIT_5
2303 #define MBX_ACCESS_TIMEDOUT BIT_6
2309 uint32_t failover_type;
2310 uint32_t failback_delay;
2311 unsigned long cfg_flags;
2312 #define CFG_ACTIVE 0 /* CFG during a failover, event update, or ioctl */
2313 #define CFG_FAILOVER 1 /* CFG during path change */
2315 uint32_t binding_type;
2316 #define BIND_BY_PORT_NAME 0
2317 #define BIND_BY_PORT_ID 1
2319 /* Basic firmware related information. */
2320 struct qla_board_info *brd_info;
2321 uint16_t fw_major_version;
2322 uint16_t fw_minor_version;
2323 uint16_t fw_subminor_version;
2324 uint16_t fw_attributes;
2325 uint32_t fw_memory_size;
2326 uint32_t fw_transfer_size;
2328 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2329 uint8_t fw_seriallink_options[2];
2331 /* Firmware dump information. */
2334 int fw_dump_reading;
2335 char *fw_dump_buffer;
2336 int fw_dump_buffer_len;
2338 uint8_t host_str[16];
2341 uint16_t product_id[4];
2343 uint8_t model_number[16+1];
2344 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2347 uint8_t node_name[WWN_SIZE];
2348 uint8_t nvram_version;
2349 uint32_t isp_abort_cnt;
2351 /* Adapter I/O statistics for failover */
2352 uint64_t IosRequested;
2353 uint64_t BytesRequested;
2354 uint64_t IosExecuted;
2355 uint64_t BytesExecuted;
2357 /* Needed for BEACON */
2358 uint16_t beacon_blink_led;
2359 uint16_t beacon_green_on;
2364 * Macros to help code, maintain, etc.
2366 #define LOOP_TRANSITION(ha) \
2367 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2368 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2370 #define LOOP_NOT_READY(ha) \
2371 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2372 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2373 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2374 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2375 atomic_read(&ha->loop_state) == LOOP_DOWN)
2377 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2379 #define TGT_Q(ha, t) (ha->otgt[t])
2380 #define LUN_Q(ha, t, l) (TGT_Q(ha, t)->olun[l])
2381 #define GET_LU_Q(ha, t, l) ((TGT_Q(ha,t) != NULL)? TGT_Q(ha, t)->olun[l] : NULL)
2383 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2385 #define qla_printk(level, ha, format, arg...) \
2386 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2389 * qla2x00 local function return status codes
2391 #define MBS_MASK 0x3fff
2393 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2394 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2395 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2396 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2397 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2398 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2399 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2400 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2401 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2402 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2404 #define QLA_FUNCTION_TIMEOUT 0x100
2405 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2406 #define QLA_FUNCTION_FAILED 0x102
2407 #define QLA_MEMORY_ALLOC_FAILED 0x103
2408 #define QLA_LOCK_TIMEOUT 0x104
2409 #define QLA_ABORTED 0x105
2410 #define QLA_SUSPENDED 0x106
2411 #define QLA_BUSY 0x107
2412 #define QLA_RSCNS_HANDLED 0x108
2415 * Stat info for all adpaters
2417 struct _qla2x00stats {
2418 unsigned long mboxtout; /* mailbox timeouts */
2419 unsigned long mboxerr; /* mailbox errors */
2420 unsigned long ispAbort; /* ISP aborts */
2421 unsigned long debugNo;
2422 unsigned long loop_resync;
2423 unsigned long outarray_full;
2424 unsigned long retry_q_cnt;
2427 #define NVRAM_DELAY() udelay(10)
2429 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2432 * Flash support definitions
2434 #define FLASH_IMAGE_SIZE 131072
2436 #include "qla_gbl.h"
2437 #include "qla_dbg.h"
2438 #include "qla_inline.h"
2439 #include "qla_listops.h"
2444 #define LINESIZE 256
2447 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2448 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2449 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2450 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2451 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2452 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)