1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/dmapool.h>
33 #include <linux/mempool.h>
34 #include <linux/spinlock.h>
35 #include <linux/completion.h>
36 #include <asm/semaphore.h>
38 #include <scsi/scsi.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_device.h>
41 #include <scsi/scsi_cmnd.h>
43 /* XXX(hch): move to pci_ids.h */
44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
45 #define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
49 #define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
53 #define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
56 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
57 #define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
60 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
61 #define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
64 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
65 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
67 #define IS_QLA2100(ha) 0
70 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
71 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
73 #define IS_QLA2200(ha) 0
76 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
77 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
78 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
80 #define IS_QLA2300(ha) 0
81 #define IS_QLA2312(ha) 0
84 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
85 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
87 #define IS_QLA2322(ha) 0
90 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
91 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
93 #define IS_QLA6312(ha) 0
96 #if defined(CONFIG_SCSI_QLA6322) || defined(CONFIG_SCSI_QLA6322_MODULE)
97 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
99 #define IS_QLA6322(ha) 0
102 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
103 IS_QLA6312(ha) || IS_QLA6322(ha))
106 * Only non-ISP2[12]00 have extended addressing support in the firmware.
108 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
111 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
112 * but that's fine as we don't look at the last 24 ones for
115 #define MAILBOX_REGISTER_COUNT_2100 8
116 #define MAILBOX_REGISTER_COUNT 32
118 #define QLA2200A_RISC_ROM_VER 4
122 #include "qla_settings.h"
125 * Data bit definitions
139 #define BIT_12 0x1000
140 #define BIT_13 0x2000
141 #define BIT_14 0x4000
142 #define BIT_15 0x8000
143 #define BIT_16 0x10000
144 #define BIT_17 0x20000
145 #define BIT_18 0x40000
146 #define BIT_19 0x80000
147 #define BIT_20 0x100000
148 #define BIT_21 0x200000
149 #define BIT_22 0x400000
150 #define BIT_23 0x800000
151 #define BIT_24 0x1000000
152 #define BIT_25 0x2000000
153 #define BIT_26 0x4000000
154 #define BIT_27 0x8000000
155 #define BIT_28 0x10000000
156 #define BIT_29 0x20000000
157 #define BIT_30 0x40000000
158 #define BIT_31 0x80000000
160 #define LSB(x) ((uint8_t)(x))
161 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
163 #define LSW(x) ((uint16_t)(x))
164 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
166 #define LSD(x) ((uint32_t)((uint64_t)(x)))
167 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
174 #define RD_REG_BYTE(addr) readb(addr)
175 #define RD_REG_WORD(addr) readw(addr)
176 #define RD_REG_DWORD(addr) readl(addr)
177 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
178 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
179 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
180 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
181 #define WRT_REG_WORD(addr, data) writew(data,addr)
182 #define WRT_REG_DWORD(addr, data) writel(data,addr)
185 * Fibre Channel device definitions.
187 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
188 #define MAX_FIBRE_DEVICES 512
189 #define MAX_FIBRE_LUNS 256
190 #define MAX_RSCN_COUNT 32
191 #define MAX_HOST_COUNT 16
194 * Host adapter default definitions.
196 #define MAX_BUSES 1 /* We only have one bus today */
197 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
198 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
199 #define MAX_TARGETS MAX_FIBRE_DEVICES
201 #define MAX_LUNS MAX_FIBRE_LUNS
202 #define MAX_CMDS_PER_LUN 255
205 * Fibre Channel device definitions.
207 #define SNS_LAST_LOOP_ID_2100 0xfe
208 #define SNS_LAST_LOOP_ID_2300 0x7ff
210 #define LAST_LOCAL_LOOP_ID 0x7d
211 #define SNS_FL_PORT 0x7e
212 #define FABRIC_CONTROLLER 0x7f
213 #define SIMPLE_NAME_SERVER 0x80
214 #define SNS_FIRST_LOOP_ID 0x81
215 #define MANAGEMENT_SERVER 0xfe
216 #define BROADCAST 0xff
218 #define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
219 x < SNS_FIRST_LOOP_ID) || \
220 x == MANAGEMENT_SERVER || \
224 * Timeout timer counts in seconds
226 #define PORT_RETRY_TIME 2
227 #define LOOP_DOWN_TIMEOUT 60
228 #define LOOP_DOWN_TIME 255 /* 240 */
229 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
231 /* Maximum outstanding commands in ISP queues (1-65535) */
232 #define MAX_OUTSTANDING_COMMANDS 1024
234 /* ISP request and response entry counts (37-65535) */
235 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
236 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
237 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
238 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
239 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
245 struct list_head list;
247 struct scsi_qla_host *ha; /* HA the SP is queued on */
249 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
251 struct timer_list timer; /* Command timer */
252 atomic_t ref_count; /* Reference count for this structure */
258 /* Target/LUN queue pointers. */
259 struct os_tgt *tgt_queue; /* ptr to visible ha's target */
260 struct os_lun *lun_queue; /* ptr to visible ha's lun */
261 struct fc_lun *fclun; /* FC LUN context pointer. */
264 unsigned long e_start; /* Start of extend timeout */
265 unsigned long r_start; /* Start of request */
266 unsigned long u_start; /* When sent to RISC */
267 unsigned long f_start; /* When placed in FO queue*/
269 /* Single transfer DMA context */
270 dma_addr_t dma_handle;
272 uint32_t request_sense_length;
273 uint8_t *request_sense_ptr;
280 /* Raw completion info for use by failover ? */
281 uint8_t fo_retry_cnt; /* Retry count this request */
282 uint8_t err_id; /* error id */
283 #define SRB_ERR_PORT 1 /* Request failed -- "port down" */
284 #define SRB_ERR_LOOP 2 /* Request failed -- "loop down" */
285 #define SRB_ERR_DEVICE 3 /* Request failed -- "device error" */
286 #define SRB_ERR_OTHER 4
288 /* SRB magic number */
290 #define SRB_MAGIC 0x10CB
294 * SRB flag definitions
296 #define SRB_TIMEOUT BIT_0 /* Command timed out */
297 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
298 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
299 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
301 #define SRB_ABORTED BIT_4 /* Command aborted command already */
302 #define SRB_RETRY BIT_5 /* Command needs retrying */
303 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
304 #define SRB_FAILOVER BIT_7 /* Command in failover state */
306 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
307 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
308 #define SRB_IOCTL BIT_10 /* IOCTL command. */
309 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
312 * SRB state definitions
314 #define SRB_FREE_STATE 0 /* returned back */
315 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
316 #define SRB_ACTIVE_STATE 2 /* in Active Array */
317 #define SRB_DONE_STATE 3 /* queued in Done Queue */
318 #define SRB_RETRY_STATE 4 /* in Retry Queue */
319 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
320 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
321 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
322 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
323 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
327 * ISP I/O Register Set structure definitions.
329 typedef volatile struct {
330 volatile uint16_t flash_address; /* Flash BIOS address */
331 volatile uint16_t flash_data; /* Flash BIOS data */
332 uint16_t unused_1[1]; /* Gap */
333 volatile uint16_t ctrl_status; /* Control/Status */
334 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
335 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
336 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
338 volatile uint16_t ictrl; /* Interrupt control */
339 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
340 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
342 volatile uint16_t istatus; /* Interrupt status */
343 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
345 volatile uint16_t semaphore; /* Semaphore */
346 volatile uint16_t nvram; /* NVRAM register. */
347 #define NVR_DESELECT 0
348 #define NVR_BUSY BIT_15
349 #define NVR_DATA_IN BIT_3
350 #define NVR_DATA_OUT BIT_2
351 #define NVR_SELECT BIT_1
352 #define NVR_CLOCK BIT_0
356 volatile uint16_t mailbox0;
357 volatile uint16_t mailbox1;
358 volatile uint16_t mailbox2;
359 volatile uint16_t mailbox3;
360 volatile uint16_t mailbox4;
361 volatile uint16_t mailbox5;
362 volatile uint16_t mailbox6;
363 volatile uint16_t mailbox7;
364 uint16_t unused_2[59]; /* Gap */
365 } __attribute__((packed)) isp2100;
368 volatile uint16_t req_q_in; /* In-Pointer */
369 volatile uint16_t req_q_out; /* Out-Pointer */
371 volatile uint16_t rsp_q_in; /* In-Pointer */
372 volatile uint16_t rsp_q_out; /* Out-Pointer */
374 /* RISC to Host Status */
375 volatile uint32_t host_status;
376 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
377 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
379 /* Host to Host Semaphore */
380 volatile uint16_t host_semaphore;
381 uint16_t unused_3[17]; /* Gap */
382 volatile uint16_t mailbox0;
383 volatile uint16_t mailbox1;
384 volatile uint16_t mailbox2;
385 volatile uint16_t mailbox3;
386 volatile uint16_t mailbox4;
387 volatile uint16_t mailbox5;
388 volatile uint16_t mailbox6;
389 volatile uint16_t mailbox7;
390 volatile uint16_t mailbox8;
391 volatile uint16_t mailbox9;
392 volatile uint16_t mailbox10;
393 volatile uint16_t mailbox11;
394 volatile uint16_t mailbox12;
395 volatile uint16_t mailbox13;
396 volatile uint16_t mailbox14;
397 volatile uint16_t mailbox15;
398 volatile uint16_t mailbox16;
399 volatile uint16_t mailbox17;
400 volatile uint16_t mailbox18;
401 volatile uint16_t mailbox19;
402 volatile uint16_t mailbox20;
403 volatile uint16_t mailbox21;
404 volatile uint16_t mailbox22;
405 volatile uint16_t mailbox23;
406 volatile uint16_t mailbox24;
407 volatile uint16_t mailbox25;
408 volatile uint16_t mailbox26;
409 volatile uint16_t mailbox27;
410 volatile uint16_t mailbox28;
411 volatile uint16_t mailbox29;
412 volatile uint16_t mailbox30;
413 volatile uint16_t mailbox31;
414 volatile uint16_t fb_cmd;
415 uint16_t unused_4[10]; /* Gap */
416 } __attribute__((packed)) isp2300;
419 volatile uint16_t fpm_diag_config;
420 uint16_t unused_5[0x6]; /* Gap */
421 volatile uint16_t pcr; /* Processor Control Register. */
422 uint16_t unused_6[0x5]; /* Gap */
423 volatile uint16_t mctr; /* Memory Configuration and Timing. */
424 uint16_t unused_7[0x3]; /* Gap */
425 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
426 uint16_t unused_8[0x3]; /* Gap */
427 volatile uint16_t hccr; /* Host command & control register. */
428 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
429 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
431 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
432 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
433 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
434 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
435 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
436 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
437 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
438 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
440 uint16_t unused_9[5]; /* Gap */
441 volatile uint16_t gpiod; /* GPIO Data register. */
442 volatile uint16_t gpioe; /* GPIO Enable register. */
443 #define GPIO_LED_MASK 0x00C0
444 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
445 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
446 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
447 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
451 uint16_t unused_10[8]; /* Gap */
452 volatile uint16_t mailbox8;
453 volatile uint16_t mailbox9;
454 volatile uint16_t mailbox10;
455 volatile uint16_t mailbox11;
456 volatile uint16_t mailbox12;
457 volatile uint16_t mailbox13;
458 volatile uint16_t mailbox14;
459 volatile uint16_t mailbox15;
460 volatile uint16_t mailbox16;
461 volatile uint16_t mailbox17;
462 volatile uint16_t mailbox18;
463 volatile uint16_t mailbox19;
464 volatile uint16_t mailbox20;
465 volatile uint16_t mailbox21;
466 volatile uint16_t mailbox22;
467 volatile uint16_t mailbox23; /* Also probe reg. */
468 } __attribute__((packed)) isp2200;
472 #define ISP_REQ_Q_IN(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox4 : \
475 &(reg)->u.isp2300.req_q_in)
476 #define ISP_REQ_Q_OUT(ha, reg) \
477 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
478 &(reg)->u.isp2100.mailbox4 : \
479 &(reg)->u.isp2300.req_q_out)
480 #define ISP_RSP_Q_IN(ha, reg) \
481 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
482 &(reg)->u.isp2100.mailbox5 : \
483 &(reg)->u.isp2300.rsp_q_in)
484 #define ISP_RSP_Q_OUT(ha, reg) \
485 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
486 &(reg)->u.isp2100.mailbox5 : \
487 &(reg)->u.isp2300.rsp_q_out)
489 #define MAILBOX_REG(ha, reg, num) \
490 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
492 &(reg)->u.isp2100.mailbox0 + (num) : \
493 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
494 &(reg)->u.isp2300.mailbox0 + (num))
495 #define RD_MAILBOX_REG(ha, reg, num) \
496 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
497 #define WRT_MAILBOX_REG(ha, reg, num, data) \
498 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
500 #define FB_CMD_REG(ha, reg) \
501 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
502 &(reg)->fb_cmd_2100 : \
503 &(reg)->u.isp2300.fb_cmd)
504 #define RD_FB_CMD_REG(ha, reg) \
505 RD_REG_WORD(FB_CMD_REG(ha, reg))
506 #define WRT_FB_CMD_REG(ha, reg, data) \
507 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
510 uint32_t out_mb; /* outbound from driver */
511 uint32_t in_mb; /* Incoming from RISC */
512 uint16_t mb[MAILBOX_REGISTER_COUNT];
517 #define MBX_DMA_IN BIT_0
518 #define MBX_DMA_OUT BIT_1
519 #define IOCTL_CMD BIT_2
522 #define MBX_TOV_SECONDS 30
525 * ISP product identification definitions in mailboxes after reset.
527 #define PROD_ID_1 0x4953
528 #define PROD_ID_2 0x0000
529 #define PROD_ID_2a 0x5020
530 #define PROD_ID_3 0x2020
533 * ISP mailbox Self-Test status codes
535 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
536 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
537 #define MBS_BUSY 4 /* Busy. */
540 * ISP mailbox command complete status codes
542 #define MBS_COMMAND_COMPLETE 0x4000
543 #define MBS_INVALID_COMMAND 0x4001
544 #define MBS_HOST_INTERFACE_ERROR 0x4002
545 #define MBS_TEST_FAILED 0x4003
546 #define MBS_COMMAND_ERROR 0x4005
547 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
548 #define MBS_PORT_ID_USED 0x4007
549 #define MBS_LOOP_ID_USED 0x4008
550 #define MBS_ALL_IDS_IN_USE 0x4009
551 #define MBS_NOT_LOGGED_IN 0x400A
554 * ISP mailbox asynchronous event status codes
556 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
557 #define MBA_RESET 0x8001 /* Reset Detected. */
558 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
559 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
560 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
561 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
562 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
564 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
565 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
566 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
567 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
568 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
569 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
570 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
571 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
572 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
573 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
574 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
575 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
576 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
577 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
578 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
579 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
581 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
582 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
583 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
584 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
585 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
586 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
587 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
588 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
589 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
590 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
591 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
592 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
593 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
596 * Firmware options 1, 2, 3.
598 #define FO1_AE_ON_LIPF8 BIT_0
599 #define FO1_AE_ALL_LIP_RESET BIT_1
600 #define FO1_CTIO_RETRY BIT_3
601 #define FO1_DISABLE_LIP_F7_SW BIT_4
602 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
603 #define FO1_DISABLE_GPIO6_7 BIT_6
604 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
605 #define FO1_SET_EMPHASIS_SWING BIT_8
606 #define FO1_AE_AUTO_BYPASS BIT_9
607 #define FO1_ENABLE_PURE_IOCB BIT_10
608 #define FO1_AE_PLOGI_RJT BIT_11
609 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
610 #define FO1_AE_QUEUE_FULL BIT_13
612 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
613 #define FO2_REV_LOOPBACK BIT_1
615 #define FO3_ENABLE_EMERG_IOCB BIT_0
616 #define FO3_AE_RND_ERROR BIT_1
619 * ISP mailbox commands
621 #define MBC_LOAD_RAM 1 /* Load RAM. */
622 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
623 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
624 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
625 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
626 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
627 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
628 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
629 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
630 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
631 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
632 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
633 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
634 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
635 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
636 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
637 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
638 #define MBC_RESET 0x18 /* Reset. */
639 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
640 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
641 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
642 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
643 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
644 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
645 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
646 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
647 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
648 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
649 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
650 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
651 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
652 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
653 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
654 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
655 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
656 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
657 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
658 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
659 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
660 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
661 /* Initialization Procedure */
662 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
663 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
664 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
665 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
666 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
667 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
668 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
669 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
670 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
671 #define MBC_LIP_RESET 0x6c /* LIP reset. */
672 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
674 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
675 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
676 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
677 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
678 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
679 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
680 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
681 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
682 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
683 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
684 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
686 /* Firmware return data sizes */
687 #define FCAL_MAP_SIZE 128
689 /* Mailbox bit definitions for out_mb and in_mb */
690 #define MBX_31 BIT_31
691 #define MBX_30 BIT_30
692 #define MBX_29 BIT_29
693 #define MBX_28 BIT_28
694 #define MBX_27 BIT_27
695 #define MBX_26 BIT_26
696 #define MBX_25 BIT_25
697 #define MBX_24 BIT_24
698 #define MBX_23 BIT_23
699 #define MBX_22 BIT_22
700 #define MBX_21 BIT_21
701 #define MBX_20 BIT_20
702 #define MBX_19 BIT_19
703 #define MBX_18 BIT_18
704 #define MBX_17 BIT_17
705 #define MBX_16 BIT_16
706 #define MBX_15 BIT_15
707 #define MBX_14 BIT_14
708 #define MBX_13 BIT_13
709 #define MBX_12 BIT_12
710 #define MBX_11 BIT_11
711 #define MBX_10 BIT_10
724 * Firmware state codes from get firmware state mailbox command
726 #define FSTATE_CONFIG_WAIT 0
727 #define FSTATE_WAIT_AL_PA 1
728 #define FSTATE_WAIT_LOGIN 2
729 #define FSTATE_READY 3
730 #define FSTATE_LOSS_OF_SYNC 4
731 #define FSTATE_ERROR 5
732 #define FSTATE_REINIT 6
733 #define FSTATE_NON_PART 7
735 #define FSTATE_CONFIG_CORRECT 0
736 #define FSTATE_P2P_RCV_LIP 1
737 #define FSTATE_P2P_CHOOSE_LOOP 2
738 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
739 #define FSTATE_FATAL_ERROR 4
740 #define FSTATE_LOOP_BACK_CONN 5
743 * Port Database structure definition
744 * Little endian except where noted.
746 #define PORT_DATABASE_SIZE 128 /* bytes */
750 uint8_t master_state;
753 uint8_t hard_address;
756 uint8_t node_name[WWN_SIZE];
757 uint8_t port_name[WWN_SIZE];
758 uint16_t execution_throttle;
759 uint16_t execution_count;
762 uint16_t resource_allocation;
763 uint16_t current_allocation;
766 uint16_t transmit_execution_list_next;
767 uint16_t transmit_execution_list_previous;
768 uint16_t common_features;
769 uint16_t total_concurrent_sequences;
770 uint16_t RO_by_information_category;
773 uint16_t receive_data_size;
774 uint16_t concurrent_sequences;
775 uint16_t open_sequences_per_exchange;
776 uint16_t lun_abort_flags;
777 uint16_t lun_stop_flags;
778 uint16_t stop_queue_head;
779 uint16_t stop_queue_tail;
780 uint16_t port_retry_timer;
781 uint16_t next_sequence_id;
782 uint16_t frame_count;
783 uint16_t PRLI_payload_length;
784 uint8_t prli_svc_param_word_0[2]; /* Big endian */
785 /* Bits 15-0 of word 0 */
786 uint8_t prli_svc_param_word_3[2]; /* Big endian */
787 /* Bits 15-0 of word 3 */
789 uint16_t extended_lun_info_list_pointer;
790 uint16_t extended_lun_stop_list_pointer;
794 * Port database slave/master states
796 #define PD_STATE_DISCOVERY 0
797 #define PD_STATE_WAIT_DISCOVERY_ACK 1
798 #define PD_STATE_PORT_LOGIN 2
799 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
800 #define PD_STATE_PROCESS_LOGIN 4
801 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
802 #define PD_STATE_PORT_LOGGED_IN 6
803 #define PD_STATE_PORT_UNAVAILABLE 7
804 #define PD_STATE_PROCESS_LOGOUT 8
805 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
806 #define PD_STATE_PORT_LOGOUT 10
807 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
811 * ISP Initialization Control Block.
812 * Little endian except where noted.
814 #define ICB_VERSION 1
820 * LSB BIT 0 = Enable Hard Loop Id
821 * LSB BIT 1 = Enable Fairness
822 * LSB BIT 2 = Enable Full-Duplex
823 * LSB BIT 3 = Enable Fast Posting
824 * LSB BIT 4 = Enable Target Mode
825 * LSB BIT 5 = Disable Initiator Mode
826 * LSB BIT 6 = Enable ADISC
827 * LSB BIT 7 = Enable Target Inquiry Data
829 * MSB BIT 0 = Enable PDBC Notify
830 * MSB BIT 1 = Non Participating LIP
831 * MSB BIT 2 = Descending Loop ID Search
832 * MSB BIT 3 = Acquire Loop ID in LIPA
833 * MSB BIT 4 = Stop PortQ on Full Status
834 * MSB BIT 5 = Full Login after LIP
835 * MSB BIT 6 = Node Name Option
836 * MSB BIT 7 = Ext IFWCB enable bit
838 uint8_t firmware_options[2];
840 uint16_t frame_payload_size;
841 uint16_t max_iocb_allocation;
842 uint16_t execution_throttle;
844 uint8_t retry_delay; /* unused */
845 uint8_t port_name[WWN_SIZE]; /* Big endian. */
846 uint16_t hard_address;
847 uint8_t inquiry_data;
848 uint8_t login_timeout;
849 uint8_t node_name[WWN_SIZE]; /* Big endian. */
851 uint16_t request_q_outpointer;
852 uint16_t response_q_inpointer;
853 uint16_t request_q_length;
854 uint16_t response_q_length;
855 uint32_t request_q_address[2];
856 uint32_t response_q_address[2];
858 uint16_t lun_enables;
859 uint8_t command_resource_count;
860 uint8_t immediate_notify_resource_count;
862 uint8_t reserved_2[2];
865 * LSB BIT 0 = Timer Operation mode bit 0
866 * LSB BIT 1 = Timer Operation mode bit 1
867 * LSB BIT 2 = Timer Operation mode bit 2
868 * LSB BIT 3 = Timer Operation mode bit 3
869 * LSB BIT 4 = Init Config Mode bit 0
870 * LSB BIT 5 = Init Config Mode bit 1
871 * LSB BIT 6 = Init Config Mode bit 2
872 * LSB BIT 7 = Enable Non part on LIHA failure
874 * MSB BIT 0 = Enable class 2
875 * MSB BIT 1 = Enable ACK0
878 * MSB BIT 4 = FC Tape Enable
879 * MSB BIT 5 = Enable FC Confirm
880 * MSB BIT 6 = Enable command queuing in target mode
881 * MSB BIT 7 = No Logo On Link Down
883 uint8_t add_firmware_options[2];
885 uint8_t response_accumulation_timer;
886 uint8_t interrupt_delay_timer;
889 * LSB BIT 0 = Enable Read xfr_rdy
890 * LSB BIT 1 = Soft ID only
893 * LSB BIT 4 = FCP RSP Payload [0]
894 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
895 * LSB BIT 6 = Enable Out-of-Order frame handling
896 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
898 * MSB BIT 0 = Sbus enable - 2300
903 * MSB BIT 5 = enable 50 ohm termination
904 * MSB BIT 6 = Data Rate (2300 only)
905 * MSB BIT 7 = Data Rate (2300 only)
907 uint8_t special_options[2];
909 uint8_t reserved_3[26];
913 * Get Link Status mailbox command return buffer.
916 uint32_t link_fail_cnt;
917 uint32_t loss_sync_cnt;
918 uint32_t loss_sig_cnt;
919 uint32_t prim_seq_err_cnt;
920 uint32_t inval_xmit_word_cnt;
921 uint32_t inval_crc_cnt;
925 * NVRAM Command values.
927 #define NV_START_BIT BIT_2
928 #define NV_WRITE_OP (BIT_26+BIT_24)
929 #define NV_READ_OP (BIT_26+BIT_25)
930 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
931 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
932 #define NV_DELAY_COUNT 10
935 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
942 uint8_t nvram_version;
946 * NVRAM RISC parameter block
948 uint8_t parameter_block_version;
952 * LSB BIT 0 = Enable Hard Loop Id
953 * LSB BIT 1 = Enable Fairness
954 * LSB BIT 2 = Enable Full-Duplex
955 * LSB BIT 3 = Enable Fast Posting
956 * LSB BIT 4 = Enable Target Mode
957 * LSB BIT 5 = Disable Initiator Mode
958 * LSB BIT 6 = Enable ADISC
959 * LSB BIT 7 = Enable Target Inquiry Data
961 * MSB BIT 0 = Enable PDBC Notify
962 * MSB BIT 1 = Non Participating LIP
963 * MSB BIT 2 = Descending Loop ID Search
964 * MSB BIT 3 = Acquire Loop ID in LIPA
965 * MSB BIT 4 = Stop PortQ on Full Status
966 * MSB BIT 5 = Full Login after LIP
967 * MSB BIT 6 = Node Name Option
968 * MSB BIT 7 = Ext IFWCB enable bit
970 uint8_t firmware_options[2];
972 uint16_t frame_payload_size;
973 uint16_t max_iocb_allocation;
974 uint16_t execution_throttle;
976 uint8_t retry_delay; /* unused */
977 uint8_t port_name[WWN_SIZE]; /* Big endian. */
978 uint16_t hard_address;
979 uint8_t inquiry_data;
980 uint8_t login_timeout;
981 uint8_t node_name[WWN_SIZE]; /* Big endian. */
984 * LSB BIT 0 = Timer Operation mode bit 0
985 * LSB BIT 1 = Timer Operation mode bit 1
986 * LSB BIT 2 = Timer Operation mode bit 2
987 * LSB BIT 3 = Timer Operation mode bit 3
988 * LSB BIT 4 = Init Config Mode bit 0
989 * LSB BIT 5 = Init Config Mode bit 1
990 * LSB BIT 6 = Init Config Mode bit 2
991 * LSB BIT 7 = Enable Non part on LIHA failure
993 * MSB BIT 0 = Enable class 2
994 * MSB BIT 1 = Enable ACK0
997 * MSB BIT 4 = FC Tape Enable
998 * MSB BIT 5 = Enable FC Confirm
999 * MSB BIT 6 = Enable command queuing in target mode
1000 * MSB BIT 7 = No Logo On Link Down
1002 uint8_t add_firmware_options[2];
1004 uint8_t response_accumulation_timer;
1005 uint8_t interrupt_delay_timer;
1008 * LSB BIT 0 = Enable Read xfr_rdy
1009 * LSB BIT 1 = Soft ID only
1012 * LSB BIT 4 = FCP RSP Payload [0]
1013 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1014 * LSB BIT 6 = Enable Out-of-Order frame handling
1015 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1017 * MSB BIT 0 = Sbus enable - 2300
1022 * MSB BIT 5 = enable 50 ohm termination
1023 * MSB BIT 6 = Data Rate (2300 only)
1024 * MSB BIT 7 = Data Rate (2300 only)
1026 uint8_t special_options[2];
1028 /* Reserved for expanded RISC parameter block */
1029 uint8_t reserved_2[24];
1032 * LSB BIT 0 = Output Swing 1G bit 0
1033 * LSB BIT 1 = Output Swing 1G bit 1
1034 * LSB BIT 2 = Output Swing 1G bit 2
1035 * LSB BIT 3 = Output Emphasis 1G bit 0
1036 * LSB BIT 4 = Output Emphasis 1G bit 1
1037 * LSB BIT 5 = Output Swing 2G bit 0
1038 * LSB BIT 6 = Output Swing 2G bit 1
1039 * LSB BIT 7 = Output Swing 2G bit 2
1041 * MSB BIT 0 = Output Emphasis 2G bit 0
1042 * MSB BIT 1 = Output Emphasis 2G bit 1
1043 * MSB BIT 2 = Output Enable
1050 uint8_t seriallink_options[2];
1053 * NVRAM host parameter block
1055 * LSB BIT 0 = Enable spinup delay
1056 * LSB BIT 1 = Disable BIOS
1057 * LSB BIT 2 = Enable Memory Map BIOS
1058 * LSB BIT 3 = Enable Selectable Boot
1059 * LSB BIT 4 = Disable RISC code load
1060 * LSB BIT 5 = Set cache line size 1
1061 * LSB BIT 6 = PCI Parity Disable
1062 * LSB BIT 7 = Enable extended logging
1064 * MSB BIT 0 = Enable 64bit addressing
1065 * MSB BIT 1 = Enable lip reset
1066 * MSB BIT 2 = Enable lip full login
1067 * MSB BIT 3 = Enable target reset
1068 * MSB BIT 4 = Enable database storage
1069 * MSB BIT 5 = Enable cache flush read
1070 * MSB BIT 6 = Enable database load
1071 * MSB BIT 7 = Enable alternate WWN
1075 uint8_t boot_node_name[WWN_SIZE];
1076 uint8_t boot_lun_number;
1077 uint8_t reset_delay;
1078 uint8_t port_down_retry_count;
1079 uint8_t boot_id_number;
1080 uint16_t max_luns_per_target;
1081 uint8_t fcode_boot_port_name[WWN_SIZE];
1082 uint8_t alternate_port_name[WWN_SIZE];
1083 uint8_t alternate_node_name[WWN_SIZE];
1086 * BIT 0 = Boot Zoning
1087 * BIT 1 = Alt-Boot Enable
1088 * BIT 2 = Report SCSI Path
1095 uint8_t efi_parameters;
1097 uint8_t link_down_timeout;
1099 uint8_t adapter_id_0[4];
1100 uint8_t adapter_id_1[4];
1101 uint8_t adapter_id_2[4];
1102 uint8_t adapter_id_3[4];
1104 uint8_t alt1_boot_node_name[WWN_SIZE];
1105 uint16_t alt1_boot_lun_number;
1106 uint8_t alt2_boot_node_name[WWN_SIZE];
1107 uint16_t alt2_boot_lun_number;
1108 uint8_t alt3_boot_node_name[WWN_SIZE];
1109 uint16_t alt3_boot_lun_number;
1110 uint8_t alt4_boot_node_name[WWN_SIZE];
1111 uint16_t alt4_boot_lun_number;
1112 uint8_t alt5_boot_node_name[WWN_SIZE];
1113 uint16_t alt5_boot_lun_number;
1114 uint8_t alt6_boot_node_name[WWN_SIZE];
1115 uint16_t alt6_boot_lun_number;
1116 uint8_t alt7_boot_node_name[WWN_SIZE];
1117 uint16_t alt7_boot_lun_number;
1119 uint8_t reserved_3[2];
1121 /* Offset 200-215 : Model Number */
1122 uint8_t model_number[16];
1124 /* OEM related items */
1125 uint8_t oem_specific[16];
1128 * NVRAM Adapter Features offset 232-239
1130 * LSB BIT 0 = External GBIC
1131 * LSB BIT 1 = Risc RAM parity
1132 * LSB BIT 2 = Buffer Plus Module
1133 * LSB BIT 3 = Multi Chip Adapter
1134 * LSB BIT 4 = Internal connector
1148 uint8_t adapter_features[2];
1150 uint8_t reserved_4[16];
1152 /* Subsystem vendor ID for ISP2200 */
1153 uint16_t subsystem_vendor_id_2200;
1155 /* Subsystem device ID for ISP2200 */
1156 uint16_t subsystem_device_id_2200;
1163 * ISP queue - response queue entry definition.
1168 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1179 #define SET_TARGET_ID(ha, to, from) \
1181 if (HAS_EXTENDED_IDS(ha)) \
1182 to.extended = cpu_to_le16(from); \
1184 to.id.standard = (uint8_t)from; \
1188 * ISP queue - command entry structure definition.
1190 #define COMMAND_TYPE 0x11 /* Command entry */
1191 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1193 uint8_t entry_type; /* Entry type. */
1194 uint8_t entry_count; /* Entry count. */
1195 uint8_t sys_define; /* System defined. */
1196 uint8_t entry_status; /* Entry Status. */
1197 uint32_t handle; /* System handle. */
1198 target_id_t target; /* SCSI ID */
1199 uint16_t lun; /* SCSI LUN */
1200 uint16_t control_flags; /* Control flags. */
1201 #define CF_WRITE BIT_6
1202 #define CF_READ BIT_5
1203 #define CF_SIMPLE_TAG BIT_3
1204 #define CF_ORDERED_TAG BIT_2
1205 #define CF_HEAD_TAG BIT_1
1206 uint16_t reserved_1;
1207 uint16_t timeout; /* Command timeout. */
1208 uint16_t dseg_count; /* Data segment count. */
1209 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1210 uint32_t byte_count; /* Total byte count. */
1211 uint32_t dseg_0_address; /* Data segment 0 address. */
1212 uint32_t dseg_0_length; /* Data segment 0 length. */
1213 uint32_t dseg_1_address; /* Data segment 1 address. */
1214 uint32_t dseg_1_length; /* Data segment 1 length. */
1215 uint32_t dseg_2_address; /* Data segment 2 address. */
1216 uint32_t dseg_2_length; /* Data segment 2 length. */
1220 * ISP queue - 64-Bit addressing, command entry structure definition.
1222 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1224 uint8_t entry_type; /* Entry type. */
1225 uint8_t entry_count; /* Entry count. */
1226 uint8_t sys_define; /* System defined. */
1227 uint8_t entry_status; /* Entry Status. */
1228 uint32_t handle; /* System handle. */
1229 target_id_t target; /* SCSI ID */
1230 uint16_t lun; /* SCSI LUN */
1231 uint16_t control_flags; /* Control flags. */
1232 uint16_t reserved_1;
1233 uint16_t timeout; /* Command timeout. */
1234 uint16_t dseg_count; /* Data segment count. */
1235 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1236 uint32_t byte_count; /* Total byte count. */
1237 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1238 uint32_t dseg_0_length; /* Data segment 0 length. */
1239 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1240 uint32_t dseg_1_length; /* Data segment 1 length. */
1241 } cmd_a64_entry_t, request_t;
1244 * ISP queue - continuation entry structure definition.
1246 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1248 uint8_t entry_type; /* Entry type. */
1249 uint8_t entry_count; /* Entry count. */
1250 uint8_t sys_define; /* System defined. */
1251 uint8_t entry_status; /* Entry Status. */
1253 uint32_t dseg_0_address; /* Data segment 0 address. */
1254 uint32_t dseg_0_length; /* Data segment 0 length. */
1255 uint32_t dseg_1_address; /* Data segment 1 address. */
1256 uint32_t dseg_1_length; /* Data segment 1 length. */
1257 uint32_t dseg_2_address; /* Data segment 2 address. */
1258 uint32_t dseg_2_length; /* Data segment 2 length. */
1259 uint32_t dseg_3_address; /* Data segment 3 address. */
1260 uint32_t dseg_3_length; /* Data segment 3 length. */
1261 uint32_t dseg_4_address; /* Data segment 4 address. */
1262 uint32_t dseg_4_length; /* Data segment 4 length. */
1263 uint32_t dseg_5_address; /* Data segment 5 address. */
1264 uint32_t dseg_5_length; /* Data segment 5 length. */
1265 uint32_t dseg_6_address; /* Data segment 6 address. */
1266 uint32_t dseg_6_length; /* Data segment 6 length. */
1270 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1272 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1274 uint8_t entry_type; /* Entry type. */
1275 uint8_t entry_count; /* Entry count. */
1276 uint8_t sys_define; /* System defined. */
1277 uint8_t entry_status; /* Entry Status. */
1278 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1279 uint32_t dseg_0_length; /* Data segment 0 length. */
1280 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1281 uint32_t dseg_1_length; /* Data segment 1 length. */
1282 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1283 uint32_t dseg_2_length; /* Data segment 2 length. */
1284 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1285 uint32_t dseg_3_length; /* Data segment 3 length. */
1286 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1287 uint32_t dseg_4_length; /* Data segment 4 length. */
1291 * ISP queue - status entry structure definition.
1293 #define STATUS_TYPE 0x03 /* Status entry. */
1295 uint8_t entry_type; /* Entry type. */
1296 uint8_t entry_count; /* Entry count. */
1297 uint8_t sys_define; /* System defined. */
1298 uint8_t entry_status; /* Entry Status. */
1299 uint32_t handle; /* System handle. */
1300 uint16_t scsi_status; /* SCSI status. */
1301 uint16_t comp_status; /* Completion status. */
1302 uint16_t state_flags; /* State flags. */
1303 uint16_t status_flags; /* Status flags. */
1304 uint16_t rsp_info_len; /* Response Info Length. */
1305 uint16_t req_sense_length; /* Request sense data length. */
1306 uint32_t residual_length; /* Residual transfer length. */
1307 uint8_t rsp_info[8]; /* FCP response information. */
1308 uint8_t req_sense_data[32]; /* Request sense data. */
1312 * Status entry entry status
1314 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1315 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1316 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1317 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1318 #define RF_BUSY BIT_1 /* Busy */
1321 * Status entry SCSI status bit definitions.
1323 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1324 #define SS_RESIDUAL_UNDER BIT_11
1325 #define SS_RESIDUAL_OVER BIT_10
1326 #define SS_SENSE_LEN_VALID BIT_9
1327 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1329 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1330 #define SS_BUSY_CONDITION BIT_3
1331 #define SS_CONDITION_MET BIT_2
1332 #define SS_CHECK_CONDITION BIT_1
1335 * Status entry completion status
1337 #define CS_COMPLETE 0x0 /* No errors */
1338 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1339 #define CS_DMA 0x2 /* A DMA direction error. */
1340 #define CS_TRANSPORT 0x3 /* Transport error. */
1341 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1342 #define CS_ABORTED 0x5 /* System aborted command. */
1343 #define CS_TIMEOUT 0x6 /* Timeout error. */
1344 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1346 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1347 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1348 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1349 /* (selection timeout) */
1350 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1351 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1352 #define CS_PORT_BUSY 0x2B /* Port Busy */
1353 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1354 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1355 #define CS_UNKNOWN 0x81 /* Driver defined */
1356 #define CS_RETRY 0x82 /* Driver defined */
1357 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1360 * Status entry status flags
1362 #define SF_LOGOUT_SENT BIT_13
1365 * ISP queue - status continuation entry structure definition.
1367 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1369 uint8_t entry_type; /* Entry type. */
1370 uint8_t entry_count; /* Entry count. */
1371 uint8_t sys_define; /* System defined. */
1372 uint8_t entry_status; /* Entry Status. */
1373 uint8_t data[60]; /* data */
1377 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1378 * structure definition.
1380 #define STATUS_TYPE_21 0x21 /* Status entry. */
1382 uint8_t entry_type; /* Entry type. */
1383 uint8_t entry_count; /* Entry count. */
1384 uint8_t handle_count; /* Handle count. */
1385 uint8_t entry_status; /* Entry Status. */
1386 uint32_t handle[15]; /* System handles. */
1390 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1391 * structure definition.
1393 #define STATUS_TYPE_22 0x22 /* Status entry. */
1395 uint8_t entry_type; /* Entry type. */
1396 uint8_t entry_count; /* Entry count. */
1397 uint8_t handle_count; /* Handle count. */
1398 uint8_t entry_status; /* Entry Status. */
1399 uint16_t handle[30]; /* System handles. */
1403 * ISP queue - marker entry structure definition.
1405 #define MARKER_TYPE 0x04 /* Marker entry. */
1407 uint8_t entry_type; /* Entry type. */
1408 uint8_t entry_count; /* Entry count. */
1409 uint8_t handle_count; /* Handle count. */
1410 uint8_t entry_status; /* Entry Status. */
1411 uint32_t sys_define_2; /* System defined. */
1412 target_id_t target; /* SCSI ID */
1413 uint8_t modifier; /* Modifier (7-0). */
1414 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1415 #define MK_SYNC_ID 1 /* Synchronize ID */
1416 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1417 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1418 /* clear port changed, */
1419 /* use sequence number. */
1421 uint16_t sequence_number; /* Sequence number of event */
1422 uint16_t lun; /* SCSI LUN */
1423 uint8_t reserved_2[48];
1427 * ISP queue - Management Server entry structure definition.
1429 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1431 uint8_t entry_type; /* Entry type. */
1432 uint8_t entry_count; /* Entry count. */
1433 uint8_t handle_count; /* Handle count. */
1434 uint8_t entry_status; /* Entry Status. */
1435 uint32_t handle1; /* System handle. */
1436 target_id_t loop_id;
1438 uint16_t control_flags; /* Control flags. */
1441 uint16_t cmd_dsd_count;
1442 uint16_t total_dsd_count;
1448 uint32_t rsp_bytecount;
1449 uint32_t req_bytecount;
1450 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1451 uint32_t dseg_req_length; /* Data segment 0 length. */
1452 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1453 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1458 * ISP queue - Mailbox Command entry structure definition.
1460 #define MBX_IOCB_TYPE 0x39
1463 uint8_t entry_count;
1464 uint8_t sys_define1;
1465 /* Use sys_define1 for source type */
1466 #define SOURCE_SCSI 0x00
1467 #define SOURCE_IP 0x01
1468 #define SOURCE_VI 0x02
1469 #define SOURCE_SCTP 0x03
1470 #define SOURCE_MP 0x04
1471 #define SOURCE_MPIOCTL 0x05
1472 #define SOURCE_ASYNC_IOCB 0x07
1474 uint8_t entry_status;
1477 target_id_t loop_id;
1480 uint16_t state_flags;
1481 uint16_t status_flags;
1483 uint32_t sys_define2[2];
1493 uint32_t reserved_2[2];
1494 uint8_t node_name[WWN_SIZE];
1495 uint8_t port_name[WWN_SIZE];
1499 * ISP request and response queue entry sizes
1501 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1502 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1506 * 24 bit port ID type definition.
1523 #define INVALID_PORT_ID 0xFFFFFF
1526 * Switch info gathering structure.
1530 uint8_t node_name[WWN_SIZE];
1531 uint8_t port_name[WWN_SIZE];
1533 #define SW_TYPE_IP BIT_1
1534 #define SW_TYPE_SCSI BIT_0
1538 * Inquiry command structure.
1540 #define INQ_DATA_SIZE 36
1543 * Inquiry mailbox IOCB packet definition.
1547 cmd_a64_entry_t cmd;
1550 uint8_t inq[INQ_DATA_SIZE];
1554 * Report LUN command structure.
1556 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1566 uint8_t address_method : 2;
1574 rpt_lun_t lst[MAX_LUNS];
1578 * Report Lun mailbox IOCB packet definition.
1582 cmd_a64_entry_t cmd;
1586 } rpt_lun_cmd_rsp_t;
1589 * SCSI Target Queue structure
1591 typedef struct os_tgt {
1592 struct os_lun *olun[MAX_LUNS]; /* LUN context pointer. */
1593 struct fc_port *fcport;
1594 unsigned long flags;
1595 uint8_t port_down_retry_count;
1596 uint32_t down_timer;
1597 struct scsi_qla_host *ha;
1599 /* Persistent binding information */
1601 uint8_t node_name[WWN_SIZE];
1602 uint8_t port_name[WWN_SIZE];
1606 * SCSI Target Queue flags
1608 #define TQF_ONLINE 0 /* Device online to OS. */
1609 #define TQF_SUSPENDED 1
1610 #define TQF_RETRY_CMDS 2
1613 * SCSI LUN Queue structure
1615 typedef struct os_lun {
1616 struct fc_lun *fclun; /* FC LUN context pointer. */
1617 spinlock_t q_lock; /* Lun Lock */
1619 unsigned long q_flag;
1620 #define LUN_MPIO_BUSY 2 /* Lun is changing paths */
1621 #define LUN_EXEC_DELAYED 7 /* Lun execution is delayed */
1623 u_long q_timeout; /* total command timeouts */
1624 atomic_t q_timer; /* suspend timer */
1625 uint32_t q_count; /* current count */
1626 uint32_t q_max; /* maxmum count lun can be suspended */
1627 uint8_t q_state; /* lun State */
1628 #define LUN_STATE_READY 1 /* lun is ready for i/o */
1629 #define LUN_STATE_RUN 2 /* lun has a timer running */
1630 #define LUN_STATE_WAIT 3 /* lun is suspended */
1631 #define LUN_STATE_TIMEOUT 4 /* lun has timed out */
1633 u_long io_cnt; /* total xfer count since boot */
1634 u_long out_cnt; /* total outstanding IO count */
1635 u_long w_cnt; /* total writes */
1636 u_long r_cnt; /* total reads */
1637 u_long avg_time; /* */
1641 /* LUN BitMask structure definition, array of 32bit words,
1642 * 1 bit per lun. When bit == 1, the lun is masked.
1643 * Most significant bit of mask[0] is lun 0, bit 24 is lun 7.
1645 typedef struct lun_bit_mask {
1646 /* Must allocate at least enough bits to accomodate all LUNs */
1647 #if ((MAX_FIBRE_LUNS & 0x7) == 0)
1648 uint8_t mask[MAX_FIBRE_LUNS >> 3];
1650 uint8_t mask[(MAX_FIBRE_LUNS + 8) >> 3];
1655 * Fibre channel port type.
1667 * Fibre channel port structure.
1669 typedef struct fc_port {
1670 struct list_head list;
1671 struct list_head fcluns;
1673 struct scsi_qla_host *ha;
1674 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1676 uint8_t node_name[WWN_SIZE];
1677 uint8_t port_name[WWN_SIZE];
1680 uint16_t old_loop_id;
1682 fc_port_type_t port_type;
1687 os_tgt_t *tgt_queue;
1688 uint16_t os_target_id;
1690 uint16_t iodesc_idx_sent;
1692 int port_login_retry_count;
1694 atomic_t port_down_timer;
1696 uint8_t device_type;
1699 uint8_t mp_byte; /* multi-path byte (not used) */
1700 uint8_t cur_path; /* current path id */
1702 lun_bit_mask_t lun_mask;
1706 * Fibre channel port/lun states.
1708 #define FCS_UNCONFIGURED 1
1709 #define FCS_DEVICE_DEAD 2
1710 #define FCS_DEVICE_LOST 3
1711 #define FCS_ONLINE 4
1712 #define FCS_NOT_SUPPORTED 5
1713 #define FCS_FAILOVER 6
1714 #define FCS_FAILOVER_FAILED 7
1719 #define FCF_FABRIC_DEVICE BIT_0
1720 #define FCF_LOGIN_NEEDED BIT_1
1721 #define FCF_FO_MASKED BIT_2
1722 #define FCF_FAILOVER_NEEDED BIT_3
1723 #define FCF_RESET_NEEDED BIT_4
1724 #define FCF_PERSISTENT_BOUND BIT_5
1725 #define FCF_TAPE_PRESENT BIT_6
1726 #define FCF_FARP_DONE BIT_7
1727 #define FCF_FARP_FAILED BIT_8
1728 #define FCF_FARP_REPLY_NEEDED BIT_9
1729 #define FCF_AUTH_REQ BIT_10
1730 #define FCF_SEND_AUTH_REQ BIT_11
1731 #define FCF_RECEIVE_AUTH_REQ BIT_12
1732 #define FCF_AUTH_SUCCESS BIT_13
1733 #define FCF_RLC_SUPPORT BIT_14
1734 #define FCF_CONFIG BIT_15 /* Needed? */
1735 #define FCF_RESCAN_NEEDED BIT_16
1736 #define FCF_XP_DEVICE BIT_17
1737 #define FCF_MSA_DEVICE BIT_18
1738 #define FCF_EVA_DEVICE BIT_19
1739 #define FCF_MSA_PORT_ACTIVE BIT_20
1740 #define FCF_FAILBACK_DISABLE BIT_21
1741 #define FCF_FAILOVER_DISABLE BIT_22
1743 /* No loop ID flag. */
1744 #define FC_NO_LOOP_ID 0x1000
1747 * Fibre channel LUN structure.
1749 typedef struct fc_lun {
1750 struct list_head list;
1753 fc_port_t *o_fcport;
1756 uint8_t device_type;
1758 uint8_t max_path_retries;
1762 #define FLF_VISIBLE_LUN BIT_0
1763 #define FLF_ACTIVE_LUN BIT_1
1768 * NOTE: All structures are big-endian in form.
1771 #define CT_REJECT_RESPONSE 0x8001
1772 #define CT_ACCEPT_RESPONSE 0x8002
1774 #define NS_N_PORT_TYPE 0x01
1775 #define NS_NL_PORT_TYPE 0x02
1776 #define NS_NX_PORT_TYPE 0x7F
1778 #define GA_NXT_CMD 0x100
1779 #define GA_NXT_REQ_SIZE (16 + 4)
1780 #define GA_NXT_RSP_SIZE (16 + 620)
1782 #define GID_PT_CMD 0x1A1
1783 #define GID_PT_REQ_SIZE (16 + 4)
1784 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1786 #define GPN_ID_CMD 0x112
1787 #define GPN_ID_REQ_SIZE (16 + 4)
1788 #define GPN_ID_RSP_SIZE (16 + 8)
1790 #define GNN_ID_CMD 0x113
1791 #define GNN_ID_REQ_SIZE (16 + 4)
1792 #define GNN_ID_RSP_SIZE (16 + 8)
1794 #define GFT_ID_CMD 0x117
1795 #define GFT_ID_REQ_SIZE (16 + 4)
1796 #define GFT_ID_RSP_SIZE (16 + 32)
1798 #define RFT_ID_CMD 0x217
1799 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1800 #define RFT_ID_RSP_SIZE 16
1802 #define RFF_ID_CMD 0x21F
1803 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1804 #define RFF_ID_RSP_SIZE 16
1806 #define RNN_ID_CMD 0x213
1807 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1808 #define RNN_ID_RSP_SIZE 16
1810 #define RSNN_NN_CMD 0x239
1811 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1812 #define RSNN_NN_RSP_SIZE 16
1814 /* CT command header -- request/response common fields */
1824 /* CT command request */
1826 struct ct_cmd_hdr header;
1828 uint16_t max_rsp_size;
1829 uint8_t fragment_id;
1830 uint8_t reserved[3];
1833 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1849 uint8_t fc4_types[32];
1856 uint8_t fc4_feature;
1863 uint8_t node_name[8];
1867 uint8_t node_name[8];
1869 uint8_t sym_node_name[255];
1874 /* CT command response header */
1876 struct ct_cmd_hdr header;
1879 uint8_t fragment_id;
1880 uint8_t reason_code;
1881 uint8_t explanation_code;
1882 uint8_t vendor_unique;
1885 struct ct_sns_gid_pt_data {
1886 uint8_t control_byte;
1891 struct ct_rsp_hdr header;
1897 uint8_t port_name[8];
1898 uint8_t sym_port_name_len;
1899 uint8_t sym_port_name[255];
1900 uint8_t node_name[8];
1901 uint8_t sym_node_name_len;
1902 uint8_t sym_node_name[255];
1903 uint8_t init_proc_assoc[8];
1904 uint8_t node_ip_addr[16];
1905 uint8_t class_of_service[4];
1906 uint8_t fc4_types[32];
1907 uint8_t ip_address[16];
1908 uint8_t fabric_port_name[8];
1910 uint8_t hard_address[3];
1914 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1918 uint8_t port_name[8];
1922 uint8_t node_name[8];
1926 uint8_t fc4_types[32];
1933 struct ct_sns_req req;
1934 struct ct_sns_rsp rsp;
1939 * SNS command structures -- for 2200 compatability.
1941 #define RFT_ID_SNS_SCMD_LEN 22
1942 #define RFT_ID_SNS_CMD_SIZE 60
1943 #define RFT_ID_SNS_DATA_SIZE 16
1945 #define RNN_ID_SNS_SCMD_LEN 10
1946 #define RNN_ID_SNS_CMD_SIZE 36
1947 #define RNN_ID_SNS_DATA_SIZE 16
1949 #define GA_NXT_SNS_SCMD_LEN 6
1950 #define GA_NXT_SNS_CMD_SIZE 28
1951 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1953 #define GID_PT_SNS_SCMD_LEN 6
1954 #define GID_PT_SNS_CMD_SIZE 28
1955 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1957 #define GPN_ID_SNS_SCMD_LEN 6
1958 #define GPN_ID_SNS_CMD_SIZE 28
1959 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1961 #define GNN_ID_SNS_SCMD_LEN 6
1962 #define GNN_ID_SNS_CMD_SIZE 28
1963 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1965 struct sns_cmd_pkt {
1968 uint16_t buffer_length;
1969 uint16_t reserved_1;
1970 uint32_t buffer_address[2];
1971 uint16_t subcommand_length;
1972 uint16_t reserved_2;
1973 uint16_t subcommand;
1975 uint32_t reserved_3;
1979 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1980 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1981 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1982 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1983 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1984 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1988 /* IO descriptors */
1989 #define MAX_IO_DESCRIPTORS 32
1991 #define ABORT_IOCB_CB 0
1992 #define ADISC_PORT_IOCB_CB 1
1993 #define LOGOUT_PORT_IOCB_CB 2
1994 #define LOGIN_PORT_IOCB_CB 3
1995 #define LAST_IOCB_CB 4
1997 #define IODESC_INVALID_INDEX 0xFFFF
1998 #define IODESC_ADISC_NEEDED 0xFFFE
1999 #define IODESC_LOGIN_NEEDED 0xFFFD
2001 struct io_descriptor {
2006 struct timer_list timer;
2008 struct scsi_qla_host *ha;
2011 fc_port_t *remote_fcport;
2016 struct qla_fw_info {
2017 unsigned short addressing; /* addressing method used to load fw */
2018 #define FW_INFO_ADDR_NORMAL 0
2019 #define FW_INFO_ADDR_EXTENDED 1
2020 #define FW_INFO_ADDR_NOMORE 0xffff
2021 unsigned short *fwcode; /* pointer to FW array */
2022 unsigned short *fwlen; /* number of words in array */
2023 unsigned short *fwstart; /* start address for F/W */
2024 unsigned long *lfwstart; /* start address (long) for F/W */
2027 struct qla_board_info {
2031 struct qla_fw_info *fw_info;
2034 /* Return data from MBC_GET_ID_LIST call. */
2035 struct gid_list_info {
2039 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2040 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2042 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2045 * Linux Host Adapter structure
2047 typedef struct scsi_qla_host {
2048 struct list_head list;
2050 /* Commonly used flags and state information. */
2051 struct Scsi_Host *host;
2052 struct pci_dev *pdev;
2054 unsigned long host_no;
2055 unsigned long instance;
2058 uint32_t init_done :1;
2060 uint32_t mbox_int :1;
2061 uint32_t mbox_busy :1;
2062 uint32_t rscn_queue_overflow :1;
2063 uint32_t reset_active :1;
2065 uint32_t management_server_logged_in :1;
2066 uint32_t process_response_queue :1;
2068 uint32_t disable_risc_code_load :1;
2069 uint32_t enable_64bit_addressing :1;
2070 uint32_t enable_lip_reset :1;
2071 uint32_t enable_lip_full_login :1;
2072 uint32_t enable_target_reset :1;
2075 atomic_t loop_state;
2076 #define LOOP_TIMEOUT 1
2079 #define LOOP_UPDATE 4
2080 #define LOOP_READY 5
2083 unsigned long dpc_flags;
2084 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2085 #define RESET_ACTIVE 1
2086 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2087 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2088 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2089 #define LOOP_RESYNC_ACTIVE 5
2090 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2091 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2092 #define MAILBOX_RETRY 8
2093 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2094 #define FAILOVER_EVENT_NEEDED 10
2095 #define FAILOVER_EVENT 11
2096 #define FAILOVER_NEEDED 12
2097 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2098 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2099 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2100 #define ABORT_QUEUES_NEEDED 16
2101 #define RELOGIN_NEEDED 17
2102 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2103 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2104 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2105 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2106 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2107 #define IOCTL_ERROR_RECOVERY 23
2109 uint32_t device_flags;
2110 #define DFLG_LOCAL_DEVICES BIT_0
2111 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2112 #define DFLG_FABRIC_DEVICES BIT_2
2113 #define SWITCH_FOUND BIT_3
2114 #define DFLG_NO_CABLE BIT_4
2117 #define SRB_MIN_REQ 128
2118 mempool_t *srb_mempool;
2120 /* This spinlock is used to protect "io transactions", you must
2121 * aquire it before doing any IO to the card, eg with RD_REG*() and
2122 * WRT_REG*() for the duration of your entire commandtransaction.
2124 * This spinlock is of lower priority than the io request lock.
2127 spinlock_t hardware_lock ____cacheline_aligned;
2129 device_reg_t __iomem *iobase; /* Base I/O address */
2130 unsigned long pio_address;
2131 unsigned long pio_length;
2132 #define MIN_IOBASE_LEN 0x100
2134 /* ISP ring lock, rings, and indexes */
2135 dma_addr_t request_dma; /* Physical address. */
2136 request_t *request_ring; /* Base virtual address */
2137 request_t *request_ring_ptr; /* Current address. */
2138 uint16_t req_ring_index; /* Current index. */
2139 uint16_t req_q_cnt; /* Number of available entries. */
2140 uint16_t request_q_length;
2142 dma_addr_t response_dma; /* Physical address. */
2143 response_t *response_ring; /* Base virtual address */
2144 response_t *response_ring_ptr; /* Current address. */
2145 uint16_t rsp_ring_index; /* Current index. */
2146 uint16_t response_q_length;
2148 uint16_t (*calc_request_entries)(uint16_t);
2149 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2151 /* Outstandings ISP commands. */
2152 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2153 uint32_t current_outstanding_cmd;
2154 srb_t *status_srb; /* Status continuation entry. */
2157 * Need to hold the list_lock with irq's disabled in order to access
2158 * the following list.
2160 * This list_lock is of lower priority than the host_lock.
2162 spinlock_t list_lock ____cacheline_aligned;
2163 /* lock to guard lists which
2165 struct list_head retry_queue; /* watchdog queue */
2166 struct list_head done_queue; /* job on done queue */
2167 struct list_head failover_queue; /* failover list link. */
2168 struct list_head scsi_retry_queue; /* SCSI retry queue */
2169 struct list_head pending_queue; /* SCSI command pending queue */
2171 unsigned long done_q_cnt;
2172 unsigned long pending_in_q;
2173 uint32_t retry_q_cnt;
2174 uint32_t scsi_retry_q_cnt;
2175 uint32_t failover_cnt;
2177 unsigned long last_irq_cpu; /* cpu where we got our last irq */
2185 uint32_t total_isr_cnt; /* Interrupt count */
2186 uint32_t total_isp_aborts; /* controller err cnt */
2187 uint32_t total_lip_cnt; /* LIP cnt */
2188 uint32_t total_dev_errs; /* device error cnt */
2189 uint32_t total_ios; /* IO cnt */
2190 uint64_t total_bytes; /* xfr byte cnt */
2191 uint32_t total_mbx_timeout; /* mailbox timeout cnt */
2192 uint32_t total_loop_resync; /* loop resyn cnt */
2193 uint32_t dropped_frame_error_cnt;
2195 /* ISP configuration data. */
2196 uint16_t loop_id; /* Host adapter loop id */
2199 port_id_t d_id; /* Host adapter port id */
2200 uint16_t max_public_loop_ids;
2201 uint16_t min_external_loopid; /* First external loop Id */
2203 uint16_t link_data_rate; /* F/W operating speed */
2205 uint8_t current_topology;
2206 uint8_t prev_topology;
2207 #define ISP_CFG_NL 1
2209 #define ISP_CFG_FL 4
2212 uint8_t operating_mode; /* F/W operating mode */
2218 uint8_t marker_needed;
2219 uint8_t sns_retry_cnt;
2222 uint8_t interrupts_on;
2224 /* HBA serial number */
2229 /* NVRAM configuration data */
2230 uint16_t nvram_base;
2232 uint16_t loop_reset_delay;
2233 uint16_t minimum_timeout;
2234 uint8_t retry_count;
2235 uint8_t login_timeout;
2237 int port_down_retry_count;
2238 uint8_t loop_down_timeout;
2240 uint16_t max_probe_luns;
2242 uint16_t max_targets;
2243 uint16_t last_loop_id;
2245 uint32_t login_retry_count;
2247 /* Fibre Channel Device List. */
2248 struct list_head fcports;
2249 struct list_head rscn_fcports;
2251 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2252 uint16_t iodesc_signature;
2254 /* OS target queue pointers. */
2255 os_tgt_t *otgt[MAX_FIBRE_DEVICES];
2258 uint32_t rscn_queue[MAX_RSCN_COUNT];
2259 uint8_t rscn_in_ptr;
2260 uint8_t rscn_out_ptr;
2262 /* SNS command interfaces. */
2263 ms_iocb_entry_t *ms_iocb;
2264 dma_addr_t ms_iocb_dma;
2265 struct ct_sns_pkt *ct_sns;
2266 dma_addr_t ct_sns_dma;
2267 /* SNS command interfaces for 2200. */
2268 struct sns_cmd_pkt *sns_cmd;
2269 dma_addr_t sns_cmd_dma;
2273 struct completion dpc_inited;
2274 struct completion dpc_exited;
2275 struct semaphore *dpc_wait;
2276 uint8_t dpc_active; /* DPC routine is active */
2278 /* Timeout timers. */
2279 uint8_t queue_restart_timer;
2280 uint8_t loop_down_abort_time; /* port down timer */
2281 atomic_t loop_down_timer; /* loop down timer */
2282 uint8_t link_down_timeout; /* link down timeout */
2284 uint32_t timer_active;
2285 struct timer_list timer;
2287 dma_addr_t gid_list_dma;
2288 struct gid_list_info *gid_list;
2290 dma_addr_t rlc_rsp_dma;
2291 rpt_lun_cmd_rsp_t *rlc_rsp;
2293 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2294 #define DMA_POOL_SIZE 256
2295 struct dma_pool *s_dma_pool;
2297 dma_addr_t init_cb_dma;
2300 dma_addr_t iodesc_pd_dma;
2301 port_database_t *iodesc_pd;
2303 /* These are used by mailbox operations. */
2304 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2307 unsigned long mbx_cmd_flags;
2308 #define MBX_INTERRUPT 1
2309 #define MBX_INTR_WAIT 2
2310 #define MBX_UPDATE_FLASH_ACTIVE 3
2312 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2314 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2315 struct semaphore mbx_intr_sem; /* Used for completion notification */
2318 #define MBX_IN_PROGRESS BIT_0
2319 #define MBX_BUSY BIT_1 /* Got the Access */
2320 #define MBX_SLEEPING_ON_SEM BIT_2
2321 #define MBX_POLLING_FOR_COMP BIT_3
2322 #define MBX_COMPLETED BIT_4
2323 #define MBX_TIMEDOUT BIT_5
2324 #define MBX_ACCESS_TIMEDOUT BIT_6
2330 uint32_t failover_type;
2331 uint32_t failback_delay;
2332 unsigned long cfg_flags;
2333 #define CFG_ACTIVE 0 /* CFG during a failover, event update, or ioctl */
2334 #define CFG_FAILOVER 1 /* CFG during path change */
2336 uint32_t binding_type;
2337 #define BIND_BY_PORT_NAME 0
2338 #define BIND_BY_PORT_ID 1
2340 /* Basic firmware related information. */
2341 struct qla_board_info *brd_info;
2342 uint16_t fw_major_version;
2343 uint16_t fw_minor_version;
2344 uint16_t fw_subminor_version;
2345 uint16_t fw_attributes;
2346 uint32_t fw_memory_size;
2347 uint32_t fw_transfer_size;
2349 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2350 uint8_t fw_seriallink_options[2];
2352 /* Firmware dump information. */
2355 int fw_dump_reading;
2356 char *fw_dump_buffer;
2357 int fw_dump_buffer_len;
2359 uint8_t host_str[16];
2362 uint16_t product_id[4];
2364 uint8_t model_number[16+1];
2365 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2368 uint8_t node_name[WWN_SIZE];
2369 uint8_t nvram_version;
2370 uint32_t isp_abort_cnt;
2372 /* Adapter I/O statistics for failover */
2373 uint64_t IosRequested;
2374 uint64_t BytesRequested;
2375 uint64_t IosExecuted;
2376 uint64_t BytesExecuted;
2378 /* Needed for BEACON */
2379 uint16_t beacon_blink_led;
2380 uint16_t beacon_green_on;
2385 * Macros to help code, maintain, etc.
2387 #define LOOP_TRANSITION(ha) \
2388 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2389 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2391 #define LOOP_NOT_READY(ha) \
2392 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2393 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2394 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2395 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2396 atomic_read(&ha->loop_state) == LOOP_DOWN)
2398 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2400 #define TGT_Q(ha, t) (ha->otgt[t])
2401 #define LUN_Q(ha, t, l) (TGT_Q(ha, t)->olun[l])
2402 #define GET_LU_Q(ha, t, l) ((TGT_Q(ha,t) != NULL)? TGT_Q(ha, t)->olun[l] : NULL)
2404 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2406 #define qla_printk(level, ha, format, arg...) \
2407 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2410 * qla2x00 local function return status codes
2412 #define MBS_MASK 0x3fff
2414 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2415 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2416 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2417 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2418 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2419 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2420 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2421 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2422 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2423 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2425 #define QLA_FUNCTION_TIMEOUT 0x100
2426 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2427 #define QLA_FUNCTION_FAILED 0x102
2428 #define QLA_MEMORY_ALLOC_FAILED 0x103
2429 #define QLA_LOCK_TIMEOUT 0x104
2430 #define QLA_ABORTED 0x105
2431 #define QLA_SUSPENDED 0x106
2432 #define QLA_BUSY 0x107
2433 #define QLA_RSCNS_HANDLED 0x108
2436 * Stat info for all adpaters
2438 struct _qla2x00stats {
2439 unsigned long mboxtout; /* mailbox timeouts */
2440 unsigned long mboxerr; /* mailbox errors */
2441 unsigned long ispAbort; /* ISP aborts */
2442 unsigned long debugNo;
2443 unsigned long loop_resync;
2444 unsigned long outarray_full;
2445 unsigned long retry_q_cnt;
2448 #define NVRAM_DELAY() udelay(10)
2450 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2453 * Flash support definitions
2455 #define FLASH_IMAGE_SIZE 131072
2457 #include "qla_gbl.h"
2458 #include "qla_dbg.h"
2459 #include "qla_inline.h"
2460 #include "qla_listops.h"
2465 #define LINESIZE 256
2468 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2469 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2470 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2471 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2472 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2473 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)