drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <asm/uaccess.h>
  11
  12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  13 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  14 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  15
  16 /*
  17  * NVRAM support routines
  18  */
  19
  20 /**
  21  * qla2x00_lock_nvram_access() -
  22  * @ha: HA context
  23  */
  24 void
  25 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  26 {
  27         uint16_t data;
  28         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  29
  30         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  31                 data = RD_REG_WORD(&reg->nvram);
  32                 while (data & NVR_BUSY) {
  33                         udelay(100);
  34                         data = RD_REG_WORD(&reg->nvram);
  35                 }
  36
  37                 /* Lock resource */
  38                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  39                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 udelay(5);
  41                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  42                 while ((data & BIT_0) == 0) {
  43                         /* Lock failed */
  44                         udelay(100);
  45                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  46                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                         udelay(5);
  48                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  49                 }
  50         }
  51 }
  52
  53 /**
  54  * qla2x00_unlock_nvram_access() -
  55  * @ha: HA context
  56  */
  57 void
  58 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  59 {
  60         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  61
  62         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  63                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  64                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  65         }
  66 }
  67
  68 /**
  69  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  70  *      request routine to get the word from NVRAM.
  71  * @ha: HA context
  72  * @addr: Address in NVRAM to read
  73  *
  74  * Returns the word read from nvram @addr.
  75  */
  76 uint16_t
  77 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  78 {
  79         uint16_t        data;
  80         uint32_t        nv_cmd;
  81
  82         nv_cmd = addr << 16;
  83         nv_cmd |= NV_READ_OP;
  84         data = qla2x00_nvram_request(ha, nv_cmd);
  85
  86         return (data);
  87 }
  88
  89 /**
  90  * qla2x00_write_nvram_word() - Write NVRAM data.
  91  * @ha: HA context
  92  * @addr: Address in NVRAM to write
  93  * @data: word to program
  94  */
  95 void
  96 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  97 {
  98         int count;
  99         uint16_t word;
 100         uint32_t nv_cmd;
 101         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 102
 103         qla2x00_nv_write(ha, NVR_DATA_OUT);
 104         qla2x00_nv_write(ha, 0);
 105         qla2x00_nv_write(ha, 0);
 106
 107         for (word = 0; word < 8; word++)
 108                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 109
 110         qla2x00_nv_deselect(ha);
 111
 112         /* Write data */
 113         nv_cmd = (addr << 16) | NV_WRITE_OP;
 114         nv_cmd |= data;
 115         nv_cmd <<= 5;
 116         for (count = 0; count < 27; count++) {
 117                 if (nv_cmd & BIT_31)
 118                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 119                 else
 120                         qla2x00_nv_write(ha, 0);
 121
 122                 nv_cmd <<= 1;
 123         }
 124
 125         qla2x00_nv_deselect(ha);
 126
 127         /* Wait for NVRAM to become ready */
 128         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 129         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 130         do {
 131                 NVRAM_DELAY();
 132                 word = RD_REG_WORD(&reg->nvram);
 133         } while ((word & NVR_DATA_IN) == 0);
 134
 135         qla2x00_nv_deselect(ha);
 136
 137         /* Disable writes */
 138         qla2x00_nv_write(ha, NVR_DATA_OUT);
 139         for (count = 0; count < 10; count++)
 140                 qla2x00_nv_write(ha, 0);
 141
 142         qla2x00_nv_deselect(ha);
 143 }
 144
 145 static int
 146 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 147     uint32_t tmo)
 148 {
 149         int ret, count;
 150         uint16_t word;
 151         uint32_t nv_cmd;
 152         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 153
 154         ret = QLA_SUCCESS;
 155
 156         qla2x00_nv_write(ha, NVR_DATA_OUT);
 157         qla2x00_nv_write(ha, 0);
 158         qla2x00_nv_write(ha, 0);
 159
 160         for (word = 0; word < 8; word++)
 161                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 162
 163         qla2x00_nv_deselect(ha);
 164
 165         /* Write data */
 166         nv_cmd = (addr << 16) | NV_WRITE_OP;
 167         nv_cmd |= data;
 168         nv_cmd <<= 5;
 169         for (count = 0; count < 27; count++) {
 170                 if (nv_cmd & BIT_31)
 171                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 172                 else
 173                         qla2x00_nv_write(ha, 0);
 174
 175                 nv_cmd <<= 1;
 176         }
 177
 178         qla2x00_nv_deselect(ha);
 179
 180         /* Wait for NVRAM to become ready */
 181         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 182         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 183         do {
 184                 NVRAM_DELAY();
 185                 word = RD_REG_WORD(&reg->nvram);
 186                 if (!--tmo) {
 187                         ret = QLA_FUNCTION_FAILED;
 188                         break;
 189                 }
 190         } while ((word & NVR_DATA_IN) == 0);
 191
 192         qla2x00_nv_deselect(ha);
 193
 194         /* Disable writes */
 195         qla2x00_nv_write(ha, NVR_DATA_OUT);
 196         for (count = 0; count < 10; count++)
 197                 qla2x00_nv_write(ha, 0);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         return ret;
 202 }
 203
 204 /**
 205  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 206  *      NVRAM.
 207  * @ha: HA context
 208  * @nv_cmd: NVRAM command
 209  *
 210  * Bit definitions for NVRAM command:
 211  *
 212  *      Bit 26     = start bit
 213  *      Bit 25, 24 = opcode
 214  *      Bit 23-16  = address
 215  *      Bit 15-0   = write data
 216  *
 217  * Returns the word read from nvram @addr.
 218  */
 219 static uint16_t
 220 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 221 {
 222         uint8_t         cnt;
 223         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 224         uint16_t        data = 0;
 225         uint16_t        reg_data;
 226
 227         /* Send command to NVRAM. */
 228         nv_cmd <<= 5;
 229         for (cnt = 0; cnt < 11; cnt++) {
 230                 if (nv_cmd & BIT_31)
 231                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 232                 else
 233                         qla2x00_nv_write(ha, 0);
 234                 nv_cmd <<= 1;
 235         }
 236
 237         /* Read data from NVRAM. */
 238         for (cnt = 0; cnt < 16; cnt++) {
 239                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 240                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 241                 NVRAM_DELAY();
 242                 data <<= 1;
 243                 reg_data = RD_REG_WORD(&reg->nvram);
 244                 if (reg_data & NVR_DATA_IN)
 245                         data |= BIT_0;
 246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 248                 NVRAM_DELAY();
 249         }
 250
 251         /* Deselect chip. */
 252         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 253         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 254         NVRAM_DELAY();
 255
 256         return (data);
 257 }
 258
 259 /**
 260  * qla2x00_nv_write() - Clean NVRAM operations.
 261  * @ha: HA context
 262  */
 263 static void
 264 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 265 {
 266         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 267
 268         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 269         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 270         NVRAM_DELAY();
 271 }
 272
 273 /**
 274  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 275  * @ha: HA context
 276  * @data: Serial interface selector
 277  */
 278 static void
 279 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 280 {
 281         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 282
 283         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 284         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 285         NVRAM_DELAY();
 286         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 287             NVR_WRT_ENABLE);
 288         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 289         NVRAM_DELAY();
 290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 292         NVRAM_DELAY();
 293 }
 294
 295 /**
 296  * qla2x00_clear_nvram_protection() -
 297  * @ha: HA context
 298  */
 299 static int
 300 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 301 {
 302         int ret, stat;
 303         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 304         uint32_t word;
 305         uint16_t wprot, wprot_old;
 306
 307         /* Clear NVRAM write protection. */
 308         ret = QLA_FUNCTION_FAILED;
 309         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
 310         stat = qla2x00_write_nvram_word_tmo(ha, 0,
 311             __constant_cpu_to_le16(0x1234), 100000);
 312         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
 313         if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
 314                 /* Write enable. */
 315                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 316                 qla2x00_nv_write(ha, 0);
 317                 qla2x00_nv_write(ha, 0);
 318                 for (word = 0; word < 8; word++)
 319                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 320
 321                 qla2x00_nv_deselect(ha);
 322
 323                 /* Enable protection register. */
 324                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 325                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 326                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 327                 for (word = 0; word < 8; word++)
 328                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 329
 330                 qla2x00_nv_deselect(ha);
 331
 332                 /* Clear protection register (ffff is cleared). */
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 335                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 336                 for (word = 0; word < 8; word++)
 337                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 338
 339                 qla2x00_nv_deselect(ha);
 340
 341                 /* Wait for NVRAM to become ready. */
 342                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 343                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 344                 do {
 345                         NVRAM_DELAY();
 346                         word = RD_REG_WORD(&reg->nvram);
 347                 } while ((word & NVR_DATA_IN) == 0);
 348
 349                 ret = QLA_SUCCESS;
 350         } else
 351                 qla2x00_write_nvram_word(ha, 0, wprot_old);
 352
 353         return ret;
 354 }
 355
 356 static void
 357 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 358 {
 359         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 360         uint32_t word;
 361
 362         if (stat != QLA_SUCCESS)
 363                 return;
 364
 365         /* Set NVRAM write protection. */
 366         /* Write enable. */
 367         qla2x00_nv_write(ha, NVR_DATA_OUT);
 368         qla2x00_nv_write(ha, 0);
 369         qla2x00_nv_write(ha, 0);
 370         for (word = 0; word < 8; word++)
 371                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 372
 373         qla2x00_nv_deselect(ha);
 374
 375         /* Enable protection register. */
 376         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 377         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 378         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 379         for (word = 0; word < 8; word++)
 380                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 381
 382         qla2x00_nv_deselect(ha);
 383
 384         /* Enable protection register. */
 385         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 386         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 387         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 388         for (word = 0; word < 8; word++)
 389                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 390
 391         qla2x00_nv_deselect(ha);
 392
 393         /* Wait for NVRAM to become ready. */
 394         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 395         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 396         do {
 397                 NVRAM_DELAY();
 398                 word = RD_REG_WORD(&reg->nvram);
 399         } while ((word & NVR_DATA_IN) == 0);
 400 }
 401
 402
 403 /*****************************************************************************/
 404 /* Flash Manipulation Routines                                               */
 405 /*****************************************************************************/
 406
 407 static inline uint32_t
 408 flash_conf_to_access_addr(uint32_t faddr)
 409 {
 410         return FARX_ACCESS_FLASH_CONF | faddr;
 411 }
 412
 413 static inline uint32_t
 414 flash_data_to_access_addr(uint32_t faddr)
 415 {
 416         return FARX_ACCESS_FLASH_DATA | faddr;
 417 }
 418
 419 static inline uint32_t
 420 nvram_conf_to_access_addr(uint32_t naddr)
 421 {
 422         return FARX_ACCESS_NVRAM_CONF | naddr;
 423 }
 424
 425 static inline uint32_t
 426 nvram_data_to_access_addr(uint32_t naddr)
 427 {
 428         return FARX_ACCESS_NVRAM_DATA | naddr;
 429 }
 430
 431 uint32_t
 432 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 433 {
 434         int rval;
 435         uint32_t cnt, data;
 436         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 437
 438         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 439         /* Wait for READ cycle to complete. */
 440         rval = QLA_SUCCESS;
 441         for (cnt = 3000;
 442             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 443             rval == QLA_SUCCESS; cnt--) {
 444                 if (cnt)
 445                         udelay(10);
 446                 else
 447                         rval = QLA_FUNCTION_TIMEOUT;
 448         }
 449
 450         /* TODO: What happens if we time out? */
 451         data = 0xDEADDEAD;
 452         if (rval == QLA_SUCCESS)
 453                 data = RD_REG_DWORD(&reg->flash_data);
 454
 455         return data;
 456 }
 457
 458 uint32_t *
 459 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 460     uint32_t dwords)
 461 {
 462         uint32_t i;
 463
 464         /* Dword reads to flash. */
 465         for (i = 0; i < dwords; i++, faddr++)
 466                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 467                     flash_data_to_access_addr(faddr)));
 468
 469         return dwptr;
 470 }
 471
 472 int
 473 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 474 {
 475         int rval;
 476         uint32_t cnt;
 477         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 478
 479         WRT_REG_DWORD(&reg->flash_data, data);
 480         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 481         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 482         /* Wait for Write cycle to complete. */
 483         rval = QLA_SUCCESS;
 484         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 485             rval == QLA_SUCCESS; cnt--) {
 486                 if (cnt)
 487                         udelay(10);
 488                 else
 489                         rval = QLA_FUNCTION_TIMEOUT;
 490         }
 491         return rval;
 492 }
 493
 494 void
 495 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 496     uint8_t *flash_id)
 497 {
 498         uint32_t ids;
 499
 500         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 501         *man_id = LSB(ids);
 502         *flash_id = MSB(ids);
 503 }
 504
 505 int
 506 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 507     uint32_t dwords)
 508 {
 509         int ret;
 510         uint32_t liter;
 511         uint32_t sec_mask, rest_addr, conf_addr;
 512         uint32_t fdata;
 513         uint8_t man_id, flash_id;
 514         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 515
 516         ret = QLA_SUCCESS;
 517
 518         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 519         DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
 520             ha->host_no, man_id, flash_id));
 521
 522         conf_addr = flash_conf_to_access_addr(0x03d8);
 523         switch (man_id) {
 524         case 0xbf: /* STT flash. */
 525                 rest_addr = 0x1fff;
 526                 sec_mask = 0x3e000;
 527                 if (flash_id == 0x80)
 528                         conf_addr = flash_conf_to_access_addr(0x0352);
 529                 break;
 530         case 0x13: /* ST M25P80. */
 531                 rest_addr = 0x3fff;
 532                 sec_mask = 0x3c000;
 533                 break;
 534         default:
 535                 /* Default to 64 kb sector size. */
 536                 rest_addr = 0x3fff;
 537                 sec_mask = 0x3c000;
 538                 break;
 539         }
 540
 541         /* Enable flash write. */
 542         WRT_REG_DWORD(&reg->ctrl_status,
 543             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 544         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 545
 546         /* Disable flash write-protection. */
 547         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 548
 549         do {    /* Loop once to provide quick error exit. */
 550                 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 551                         /* Are we at the beginning of a sector? */
 552                         if ((faddr & rest_addr) == 0) {
 553                                 fdata = (faddr & sec_mask) << 2;
 554                                 ret = qla24xx_write_flash_dword(ha, conf_addr,
 555                                     (fdata & 0xff00) |((fdata << 16) &
 556                                     0xff0000) | ((fdata >> 16) & 0xff));
 557                                 if (ret != QLA_SUCCESS) {
 558                                         DEBUG9(printk("%s(%ld) Unable to flash "
 559                                             "sector: address=%x.\n", __func__,
 560                                             ha->host_no, faddr));
 561                                         break;
 562                                 }
 563                         }
 564                         ret = qla24xx_write_flash_dword(ha,
 565                             flash_data_to_access_addr(faddr),
 566                             cpu_to_le32(*dwptr));
 567                         if (ret != QLA_SUCCESS) {
 568                                 DEBUG9(printk("%s(%ld) Unable to program flash "
 569                                     "address=%x data=%x.\n", __func__,
 570                                     ha->host_no, faddr, *dwptr));
 571                                 break;
 572                         }
 573                 }
 574         } while (0);
 575
 576         /* Enable flash write-protection. */
 577         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
 578
 579         /* Disable flash write. */
 580         WRT_REG_DWORD(&reg->ctrl_status,
 581             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 582         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 583
 584         return ret;
 585 }
 586
 587 uint8_t *
 588 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 589     uint32_t bytes)
 590 {
 591         uint32_t i;
 592         uint16_t *wptr;
 593
 594         /* Word reads to NVRAM via registers. */
 595         wptr = (uint16_t *)buf;
 596         qla2x00_lock_nvram_access(ha);
 597         for (i = 0; i < bytes >> 1; i++, naddr++)
 598                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
 599                     naddr));
 600         qla2x00_unlock_nvram_access(ha);
 601
 602         return buf;
 603 }
 604
 605 uint8_t *
 606 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 607     uint32_t bytes)
 608 {
 609         uint32_t i;
 610         uint32_t *dwptr;
 611
 612         /* Dword reads to flash. */
 613         dwptr = (uint32_t *)buf;
 614         for (i = 0; i < bytes >> 2; i++, naddr++)
 615                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 616                     nvram_data_to_access_addr(naddr)));
 617
 618         return buf;
 619 }
 620
 621 int
 622 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 623     uint32_t bytes)
 624 {
 625         int ret, stat;
 626         uint32_t i;
 627         uint16_t *wptr;
 628
 629         ret = QLA_SUCCESS;
 630
 631         qla2x00_lock_nvram_access(ha);
 632
 633         /* Disable NVRAM write-protection. */
 634         stat = qla2x00_clear_nvram_protection(ha);
 635
 636         wptr = (uint16_t *)buf;
 637         for (i = 0; i < bytes >> 1; i++, naddr++) {
 638                 qla2x00_write_nvram_word(ha, naddr,
 639                     cpu_to_le16(*wptr));
 640                 wptr++;
 641         }
 642
 643         /* Enable NVRAM write-protection. */
 644         qla2x00_set_nvram_protection(ha, stat);
 645
 646         qla2x00_unlock_nvram_access(ha);
 647
 648         return ret;
 649 }
 650
 651 int
 652 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 653     uint32_t bytes)
 654 {
 655         int ret;
 656         uint32_t i;
 657         uint32_t *dwptr;
 658         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 659
 660         ret = QLA_SUCCESS;
 661
 662         /* Enable flash write. */
 663         WRT_REG_DWORD(&reg->ctrl_status,
 664             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 665         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 666
 667         /* Disable NVRAM write-protection. */
 668         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 669             0);
 670         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 671             0);
 672
 673         /* Dword writes to flash. */
 674         dwptr = (uint32_t *)buf;
 675         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
 676                 ret = qla24xx_write_flash_dword(ha,
 677                     nvram_data_to_access_addr(naddr),
 678                     cpu_to_le32(*dwptr));
 679                 if (ret != QLA_SUCCESS) {
 680                         DEBUG9(printk("%s(%ld) Unable to program "
 681                             "nvram address=%x data=%x.\n", __func__,
 682                             ha->host_no, naddr, *dwptr));
 683                         break;
 684                 }
 685         }
 686
 687         /* Enable NVRAM write-protection. */
 688         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 689             0x8c);
 690
 691         /* Disable flash write. */
 692         WRT_REG_DWORD(&reg->ctrl_status,
 693             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 694         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 695
 696         return ret;
 697 }
 698
 699
 700 static inline void
 701 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
 702 {
 703         if (IS_QLA2322(ha)) {
 704                 /* Flip all colors. */
 705                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
 706                         /* Turn off. */
 707                         ha->beacon_color_state = 0;
 708                         *pflags = GPIO_LED_ALL_OFF;
 709                 } else {
 710                         /* Turn on. */
 711                         ha->beacon_color_state = QLA_LED_ALL_ON;
 712                         *pflags = GPIO_LED_RGA_ON;
 713                 }
 714         } else {
 715                 /* Flip green led only. */
 716                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
 717                         /* Turn off. */
 718                         ha->beacon_color_state = 0;
 719                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
 720                 } else {
 721                         /* Turn on. */
 722                         ha->beacon_color_state = QLA_LED_GRN_ON;
 723                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
 724                 }
 725         }
 726 }
 727
 728 void
 729 qla2x00_beacon_blink(struct scsi_qla_host *ha)
 730 {
 731         uint16_t gpio_enable;
 732         uint16_t gpio_data;
 733         uint16_t led_color = 0;
 734         unsigned long flags;
 735         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 736
 737         if (ha->pio_address)
 738                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
 739
 740         spin_lock_irqsave(&ha->hardware_lock, flags);
 741
 742         /* Save the Original GPIOE. */
 743         if (ha->pio_address) {
 744                 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
 745                 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
 746         } else {
 747                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 748                 gpio_data = RD_REG_WORD(&reg->gpiod);
 749         }
 750
 751         /* Set the modified gpio_enable values */
 752         gpio_enable |= GPIO_LED_MASK;
 753
 754         if (ha->pio_address) {
 755                 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
 756         } else {
 757                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 758                 RD_REG_WORD(&reg->gpioe);
 759         }
 760
 761         qla2x00_flip_colors(ha, &led_color);
 762
 763         /* Clear out any previously set LED color. */
 764         gpio_data &= ~GPIO_LED_MASK;
 765
 766         /* Set the new input LED color to GPIOD. */
 767         gpio_data |= led_color;
 768
 769         /* Set the modified gpio_data values */
 770         if (ha->pio_address) {
 771                 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
 772         } else {
 773                 WRT_REG_WORD(&reg->gpiod, gpio_data);
 774                 RD_REG_WORD(&reg->gpiod);
 775         }
 776
 777         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 778 }
 779
 780 int
 781 qla2x00_beacon_on(struct scsi_qla_host *ha)
 782 {
 783         uint16_t gpio_enable;
 784         uint16_t gpio_data;
 785         unsigned long flags;
 786         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 787
 788         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
 789         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
 790
 791         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
 792                 qla_printk(KERN_WARNING, ha,
 793                     "Unable to update fw options (beacon on).\n");
 794                 return QLA_FUNCTION_FAILED;
 795         }
 796
 797         if (ha->pio_address)
 798                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
 799
 800         /* Turn off LEDs. */
 801         spin_lock_irqsave(&ha->hardware_lock, flags);
 802         if (ha->pio_address) {
 803                 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
 804                 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
 805         } else {
 806                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 807                 gpio_data = RD_REG_WORD(&reg->gpiod);
 808         }
 809         gpio_enable |= GPIO_LED_MASK;
 810
 811         /* Set the modified gpio_enable values. */
 812         if (ha->pio_address) {
 813                 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
 814         } else {
 815                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 816                 RD_REG_WORD(&reg->gpioe);
 817         }
 818
 819         /* Clear out previously set LED colour. */
 820         gpio_data &= ~GPIO_LED_MASK;
 821         if (ha->pio_address) {
 822                 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
 823         } else {
 824                 WRT_REG_WORD(&reg->gpiod, gpio_data);
 825                 RD_REG_WORD(&reg->gpiod);
 826         }
 827         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 828
 829         /*
 830          * Let the per HBA timer kick off the blinking process based on
 831          * the following flags. No need to do anything else now.
 832          */
 833         ha->beacon_blink_led = 1;
 834         ha->beacon_color_state = 0;
 835
 836         return QLA_SUCCESS;
 837 }
 838
 839 int
 840 qla2x00_beacon_off(struct scsi_qla_host *ha)
 841 {
 842         int rval = QLA_SUCCESS;
 843
 844         ha->beacon_blink_led = 0;
 845
 846         /* Set the on flag so when it gets flipped it will be off. */
 847         if (IS_QLA2322(ha))
 848                 ha->beacon_color_state = QLA_LED_ALL_ON;
 849         else
 850                 ha->beacon_color_state = QLA_LED_GRN_ON;
 851
 852         ha->isp_ops.beacon_blink(ha);   /* This turns green LED off */
 853
 854         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
 855         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
 856
 857         rval = qla2x00_set_fw_options(ha, ha->fw_options);
 858         if (rval != QLA_SUCCESS)
 859                 qla_printk(KERN_WARNING, ha,
 860                     "Unable to update fw options (beacon off).\n");
 861         return rval;
 862 }
 863
 864
 865 static inline void
 866 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
 867 {
 868         /* Flip all colors. */
 869         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
 870                 /* Turn off. */
 871                 ha->beacon_color_state = 0;
 872                 *pflags = 0;
 873         } else {
 874                 /* Turn on. */
 875                 ha->beacon_color_state = QLA_LED_ALL_ON;
 876                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
 877         }
 878 }
 879
 880 void
 881 qla24xx_beacon_blink(struct scsi_qla_host *ha)
 882 {
 883         uint16_t led_color = 0;
 884         uint32_t gpio_data;
 885         unsigned long flags;
 886         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 887
 888         /* Save the Original GPIOD. */
 889         spin_lock_irqsave(&ha->hardware_lock, flags);
 890         gpio_data = RD_REG_DWORD(&reg->gpiod);
 891
 892         /* Enable the gpio_data reg for update. */
 893         gpio_data |= GPDX_LED_UPDATE_MASK;
 894
 895         WRT_REG_DWORD(&reg->gpiod, gpio_data);
 896         gpio_data = RD_REG_DWORD(&reg->gpiod);
 897
 898         /* Set the color bits. */
 899         qla24xx_flip_colors(ha, &led_color);
 900
 901         /* Clear out any previously set LED color. */
 902         gpio_data &= ~GPDX_LED_COLOR_MASK;
 903
 904         /* Set the new input LED color to GPIOD. */
 905         gpio_data |= led_color;
 906
 907         /* Set the modified gpio_data values. */
 908         WRT_REG_DWORD(&reg->gpiod, gpio_data);
 909         gpio_data = RD_REG_DWORD(&reg->gpiod);
 910         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 911 }
 912
 913 int
 914 qla24xx_beacon_on(struct scsi_qla_host *ha)
 915 {
 916         uint32_t gpio_data;
 917         unsigned long flags;
 918         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 919
 920         if (ha->beacon_blink_led == 0) {
 921                 /* Enable firmware for update */
 922                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
 923
 924                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
 925                         return QLA_FUNCTION_FAILED;
 926
 927                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
 928                     QLA_SUCCESS) {
 929                         qla_printk(KERN_WARNING, ha,
 930                             "Unable to update fw options (beacon on).\n");
 931                         return QLA_FUNCTION_FAILED;
 932                 }
 933
 934                 spin_lock_irqsave(&ha->hardware_lock, flags);
 935                 gpio_data = RD_REG_DWORD(&reg->gpiod);
 936
 937                 /* Enable the gpio_data reg for update. */
 938                 gpio_data |= GPDX_LED_UPDATE_MASK;
 939                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
 940                 RD_REG_DWORD(&reg->gpiod);
 941
 942                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 943         }
 944
 945         /* So all colors blink together. */
 946         ha->beacon_color_state = 0;
 947
 948         /* Let the per HBA timer kick off the blinking process. */
 949         ha->beacon_blink_led = 1;
 950
 951         return QLA_SUCCESS;
 952 }
 953
 954 int
 955 qla24xx_beacon_off(struct scsi_qla_host *ha)
 956 {
 957         uint32_t gpio_data;
 958         unsigned long flags;
 959         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 960
 961         ha->beacon_blink_led = 0;
 962         ha->beacon_color_state = QLA_LED_ALL_ON;
 963
 964         ha->isp_ops.beacon_blink(ha);   /* Will flip to all off. */
 965
 966         /* Give control back to firmware. */
 967         spin_lock_irqsave(&ha->hardware_lock, flags);
 968         gpio_data = RD_REG_DWORD(&reg->gpiod);
 969
 970         /* Disable the gpio_data reg for update. */
 971         gpio_data &= ~GPDX_LED_UPDATE_MASK;
 972         WRT_REG_DWORD(&reg->gpiod, gpio_data);
 973         RD_REG_DWORD(&reg->gpiod);
 974         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 975
 976         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
 977
 978         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
 979                 qla_printk(KERN_WARNING, ha,
 980                     "Unable to update fw options (beacon off).\n");
 981                 return QLA_FUNCTION_FAILED;
 982         }
 983
 984         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
 985                 qla_printk(KERN_WARNING, ha,
 986                     "Unable to get fw options (beacon off).\n");
 987                 return QLA_FUNCTION_FAILED;
 988         }
 989
 990         return QLA_SUCCESS;
 991 }
 992
 993
 994 /*
 995  * Flash support routines
 996  */
 997
 998 /**
 999  * qla2x00_flash_enable() - Setup flash for reading and writing.
1000  * @ha: HA context
1001  */
1002 static void
1003 qla2x00_flash_enable(scsi_qla_host_t *ha)
1004 {
1005         uint16_t data;
1006         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1007
1008         data = RD_REG_WORD(&reg->ctrl_status);
1009         data |= CSR_FLASH_ENABLE;
1010         WRT_REG_WORD(&reg->ctrl_status, data);
1011         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1012 }
1013
1014 /**
1015  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1016  * @ha: HA context
1017  */
1018 static void
1019 qla2x00_flash_disable(scsi_qla_host_t *ha)
1020 {
1021         uint16_t data;
1022         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1023
1024         data = RD_REG_WORD(&reg->ctrl_status);
1025         data &= ~(CSR_FLASH_ENABLE);
1026         WRT_REG_WORD(&reg->ctrl_status, data);
1027         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1028 }
1029
1030 /**
1031  * qla2x00_read_flash_byte() - Reads a byte from flash
1032  * @ha: HA context
1033  * @addr: Address in flash to read
1034  *
1035  * A word is read from the chip, but, only the lower byte is valid.
1036  *
1037  * Returns the byte read from flash @addr.
1038  */
1039 static uint8_t
1040 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1041 {
1042         uint16_t data;
1043         uint16_t bank_select;
1044         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1045
1046         bank_select = RD_REG_WORD(&reg->ctrl_status);
1047
1048         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1049                 /* Specify 64K address range: */
1050                 /*  clear out Module Select and Flash Address bits [19:16]. */
1051                 bank_select &= ~0xf8;
1052                 bank_select |= addr >> 12 & 0xf0;
1053                 bank_select |= CSR_FLASH_64K_BANK;
1054                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1055                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1056
1057                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1058                 data = RD_REG_WORD(&reg->flash_data);
1059
1060                 return (uint8_t)data;
1061         }
1062
1063         /* Setup bit 16 of flash address. */
1064         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1065                 bank_select |= CSR_FLASH_64K_BANK;
1066                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1067                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1068         } else if (((addr & BIT_16) == 0) &&
1069             (bank_select & CSR_FLASH_64K_BANK)) {
1070                 bank_select &= ~(CSR_FLASH_64K_BANK);
1071                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1072                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1073         }
1074
1075         /* Always perform IO mapped accesses to the FLASH registers. */
1076         if (ha->pio_address) {
1077                 uint16_t data2;
1078
1079                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1080                 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1081                 do {
1082                         data = RD_REG_WORD_PIO(&reg->flash_data);
1083                         barrier();
1084                         cpu_relax();
1085                         data2 = RD_REG_WORD_PIO(&reg->flash_data);
1086                 } while (data != data2);
1087         } else {
1088                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1089                 data = qla2x00_debounce_register(&reg->flash_data);
1090         }
1091
1092         return (uint8_t)data;
1093 }
1094
1095 /**
1096  * qla2x00_write_flash_byte() - Write a byte to flash
1097  * @ha: HA context
1098  * @addr: Address in flash to write
1099  * @data: Data to write
1100  */
1101 static void
1102 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1103 {
1104         uint16_t bank_select;
1105         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1106
1107         bank_select = RD_REG_WORD(&reg->ctrl_status);
1108         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1109                 /* Specify 64K address range: */
1110                 /*  clear out Module Select and Flash Address bits [19:16]. */
1111                 bank_select &= ~0xf8;
1112                 bank_select |= addr >> 12 & 0xf0;
1113                 bank_select |= CSR_FLASH_64K_BANK;
1114                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1115                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1116
1117                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1118                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1119                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1120                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1121
1122                 return;
1123         }
1124
1125         /* Setup bit 16 of flash address. */
1126         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1127                 bank_select |= CSR_FLASH_64K_BANK;
1128                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1129                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1130         } else if (((addr & BIT_16) == 0) &&
1131             (bank_select & CSR_FLASH_64K_BANK)) {
1132                 bank_select &= ~(CSR_FLASH_64K_BANK);
1133                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1134                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1135         }
1136
1137         /* Always perform IO mapped accesses to the FLASH registers. */
1138         if (ha->pio_address) {
1139                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1140                 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1141                 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1142         } else {
1143                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1144                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1145                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1146                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1147         }
1148 }
1149
1150 /**
1151  * qla2x00_poll_flash() - Polls flash for completion.
1152  * @ha: HA context
1153  * @addr: Address in flash to poll
1154  * @poll_data: Data to be polled
1155  * @man_id: Flash manufacturer ID
1156  * @flash_id: Flash ID
1157  *
1158  * This function polls the device until bit 7 of what is read matches data
1159  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1160  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1161  * reading bit 5 as a 1.
1162  *
1163  * Returns 0 on success, else non-zero.
1164  */
1165 static int
1166 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1167     uint8_t man_id, uint8_t flash_id)
1168 {
1169         int status;
1170         uint8_t flash_data;
1171         uint32_t cnt;
1172
1173         status = 1;
1174
1175         /* Wait for 30 seconds for command to finish. */
1176         poll_data &= BIT_7;
1177         for (cnt = 3000000; cnt; cnt--) {
1178                 flash_data = qla2x00_read_flash_byte(ha, addr);
1179                 if ((flash_data & BIT_7) == poll_data) {
1180                         status = 0;
1181                         break;
1182                 }
1183
1184                 if (man_id != 0x40 && man_id != 0xda) {
1185                         if ((flash_data & BIT_5) && cnt > 2)
1186                                 cnt = 2;
1187                 }
1188                 udelay(10);
1189                 barrier();
1190         }
1191         return status;
1192 }
1193
1194 #define IS_OEM_001(ha) \
1195         ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322 && \
1196          (ha)->pdev->subsystem_vendor == 0x1028 && \
1197          (ha)->pdev->subsystem_device == 0x0170)
1198
1199 /**
1200  * qla2x00_program_flash_address() - Programs a flash address
1201  * @ha: HA context
1202  * @addr: Address in flash to program
1203  * @data: Data to be written in flash
1204  * @man_id: Flash manufacturer ID
1205  * @flash_id: Flash ID
1206  *
1207  * Returns 0 on success, else non-zero.
1208  */
1209 static int
1210 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1211     uint8_t man_id, uint8_t flash_id)
1212 {
1213         /* Write Program Command Sequence. */
1214         if (IS_OEM_001(ha)) {
1215                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1216                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1217                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1218                 qla2x00_write_flash_byte(ha, addr, data);
1219         } else {
1220                 if (man_id == 0xda && flash_id == 0xc1) {
1221                         qla2x00_write_flash_byte(ha, addr, data);
1222                         if (addr & 0x7e)
1223                                 return 0;
1224                 } else {
1225                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1226                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1227                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1228                         qla2x00_write_flash_byte(ha, addr, data);
1229                 }
1230         }
1231
1232         udelay(150);
1233
1234         /* Wait for write to complete. */
1235         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1236 }
1237
1238 /**
1239  * qla2x00_erase_flash() - Erase the flash.
1240  * @ha: HA context
1241  * @man_id: Flash manufacturer ID
1242  * @flash_id: Flash ID
1243  *
1244  * Returns 0 on success, else non-zero.
1245  */
1246 static int
1247 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1248 {
1249         /* Individual Sector Erase Command Sequence */
1250         if (IS_OEM_001(ha)) {
1251                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1252                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1253                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1254                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1255                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1256                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1257         } else {
1258                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1259                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1260                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1261                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1262                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1263                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1264         }
1265
1266         udelay(150);
1267
1268         /* Wait for erase to complete. */
1269         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1270 }
1271
1272 /**
1273  * qla2x00_erase_flash_sector() - Erase a flash sector.
1274  * @ha: HA context
1275  * @addr: Flash sector to erase
1276  * @sec_mask: Sector address mask
1277  * @man_id: Flash manufacturer ID
1278  * @flash_id: Flash ID
1279  *
1280  * Returns 0 on success, else non-zero.
1281  */
1282 static int
1283 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1284     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1285 {
1286         /* Individual Sector Erase Command Sequence */
1287         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1288         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1289         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1290         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1291         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1292         if (man_id == 0x1f && flash_id == 0x13)
1293                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1294         else
1295                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1296
1297         udelay(150);
1298
1299         /* Wait for erase to complete. */
1300         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1301 }
1302
1303 /**
1304  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1305  * @man_id: Flash manufacturer ID
1306  * @flash_id: Flash ID
1307  */
1308 static void
1309 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1310     uint8_t *flash_id)
1311 {
1312         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1313         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1314         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1315         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1316         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1317         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1318         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1319         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1320 }
1321
1322
1323 static inline void
1324 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1325 {
1326         int cnt;
1327         unsigned long flags;
1328         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1329
1330         /* Suspend HBA. */
1331         scsi_block_requests(ha->host);
1332         ha->isp_ops.disable_intrs(ha);
1333         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1334
1335         /* Pause RISC. */
1336         spin_lock_irqsave(&ha->hardware_lock, flags);
1337         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1338         RD_REG_WORD(&reg->hccr);
1339         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1340                 for (cnt = 0; cnt < 30000; cnt++) {
1341                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1342                                 break;
1343                         udelay(100);
1344                 }
1345         } else {
1346                 udelay(10);
1347         }
1348         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1349 }
1350
1351 static inline void
1352 qla2x00_resume_hba(struct scsi_qla_host *ha)
1353 {
1354         /* Resume HBA. */
1355         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1356         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1357         up(ha->dpc_wait);
1358         qla2x00_wait_for_hba_online(ha);
1359         scsi_unblock_requests(ha->host);
1360 }
1361
1362 uint8_t *
1363 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1364     uint32_t offset, uint32_t length)
1365 {
1366         unsigned long flags;
1367         uint32_t addr, midpoint;
1368         uint8_t *data;
1369         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1370
1371         /* Suspend HBA. */
1372         qla2x00_suspend_hba(ha);
1373
1374         /* Go with read. */
1375         spin_lock_irqsave(&ha->hardware_lock, flags);
1376         midpoint = ha->optrom_size / 2;
1377
1378         qla2x00_flash_enable(ha);
1379         WRT_REG_WORD(&reg->nvram, 0);
1380         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1381         for (addr = offset, data = buf; addr < length; addr++, data++) {
1382                 if (addr == midpoint) {
1383                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1384                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1385                 }
1386
1387                 *data = qla2x00_read_flash_byte(ha, addr);
1388         }
1389         qla2x00_flash_disable(ha);
1390         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1391
1392         /* Resume HBA. */
1393         qla2x00_resume_hba(ha);
1394
1395         return buf;
1396 }
1397
1398 int
1399 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1400     uint32_t offset, uint32_t length)
1401 {
1402
1403         int rval;
1404         unsigned long flags;
1405         uint8_t man_id, flash_id, sec_number, data;
1406         uint16_t wd;
1407         uint32_t addr, liter, sec_mask, rest_addr;
1408         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1409
1410         /* Suspend HBA. */
1411         qla2x00_suspend_hba(ha);
1412
1413         rval = QLA_SUCCESS;
1414         sec_number = 0;
1415
1416         /* Reset ISP chip. */
1417         spin_lock_irqsave(&ha->hardware_lock, flags);
1418         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1419         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1420
1421         /* Go with write. */
1422         qla2x00_flash_enable(ha);
1423         do {    /* Loop once to provide quick error exit */
1424                 /* Structure of flash memory based on manufacturer */
1425                 if (IS_OEM_001(ha)) {
1426                         /* OEM variant with special flash part. */
1427                         man_id = flash_id = 0;
1428                         rest_addr = 0xffff;
1429                         sec_mask   = 0x10000;
1430                         goto update_flash;
1431                 }
1432                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1433                 switch (man_id) {
1434                 case 0x20: /* ST flash. */
1435                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1436                                 /*
1437                                  * ST m29w008at part - 64kb sector size with
1438                                  * 32kb,8kb,8kb,16kb sectors at memory address
1439                                  * 0xf0000.
1440                                  */
1441                                 rest_addr = 0xffff;
1442                                 sec_mask = 0x10000;
1443                                 break;
1444                         }
1445                         /*
1446                          * ST m29w010b part - 16kb sector size
1447                          * Default to 16kb sectors
1448                          */
1449                         rest_addr = 0x3fff;
1450                         sec_mask = 0x1c000;
1451                         break;
1452                 case 0x40: /* Mostel flash. */
1453                         /* Mostel v29c51001 part - 512 byte sector size. */
1454                         rest_addr = 0x1ff;
1455                         sec_mask = 0x1fe00;
1456                         break;
1457                 case 0xbf: /* SST flash. */
1458                         /* SST39sf10 part - 4kb sector size. */
1459                         rest_addr = 0xfff;
1460                         sec_mask = 0x1f000;
1461                         break;
1462                 case 0xda: /* Winbond flash. */
1463                         /* Winbond W29EE011 part - 256 byte sector size. */
1464                         rest_addr = 0x7f;
1465                         sec_mask = 0x1ff80;
1466                         break;
1467                 case 0xc2: /* Macronix flash. */
1468                         /* 64k sector size. */
1469                         if (flash_id == 0x38 || flash_id == 0x4f) {
1470                                 rest_addr = 0xffff;
1471                                 sec_mask = 0x10000;
1472                                 break;
1473                         }
1474                         /* Fall through... */
1475
1476                 case 0x1f: /* Atmel flash. */
1477                         /* 512k sector size. */
1478                         if (flash_id == 0x13) {
1479                                 rest_addr = 0x7fffffff;
1480                                 sec_mask =   0x80000000;
1481                                 break;
1482                         }
1483                         /* Fall through... */
1484
1485                 case 0x01: /* AMD flash. */
1486                         if (flash_id == 0x38 || flash_id == 0x40 ||
1487                             flash_id == 0x4f) {
1488                                 /* Am29LV081 part - 64kb sector size. */
1489                                 /* Am29LV002BT part - 64kb sector size. */
1490                                 rest_addr = 0xffff;
1491                                 sec_mask = 0x10000;
1492                                 break;
1493                         } else if (flash_id == 0x3e) {
1494                                 /*
1495                                  * Am29LV008b part - 64kb sector size with
1496                                  * 32kb,8kb,8kb,16kb sector at memory address
1497                                  * h0xf0000.
1498                                  */
1499                                 rest_addr = 0xffff;
1500                                 sec_mask = 0x10000;
1501                                 break;
1502                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
1503                                 /*
1504                                  * Am29LV010 part or AM29f010 - 16kb sector
1505                                  * size.
1506                                  */
1507                                 rest_addr = 0x3fff;
1508                                 sec_mask = 0x1c000;
1509                                 break;
1510                         } else if (flash_id == 0x6d) {
1511                                 /* Am29LV001 part - 8kb sector size. */
1512                                 rest_addr = 0x1fff;
1513                                 sec_mask = 0x1e000;
1514                                 break;
1515                         }
1516                 default:
1517                         /* Default to 16 kb sector size. */
1518                         rest_addr = 0x3fff;
1519                         sec_mask = 0x1c000;
1520                         break;
1521                 }
1522
1523 update_flash:
1524                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1525                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1526                                 rval = QLA_FUNCTION_FAILED;
1527                                 break;
1528                         }
1529                 }
1530
1531                 for (addr = offset, liter = 0; liter < length; liter++,
1532                     addr++) {
1533                         data = buf[liter];
1534                         /* Are we at the beginning of a sector? */
1535                         if ((addr & rest_addr) == 0) {
1536                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1537                                         if (addr >= 0x10000UL) {
1538                                                 if (((addr >> 12) & 0xf0) &&
1539                                                     ((man_id == 0x01 &&
1540                                                         flash_id == 0x3e) ||
1541                                                      (man_id == 0x20 &&
1542                                                          flash_id == 0xd2))) {
1543                                                         sec_number++;
1544                                                         if (sec_number == 1) {
1545                                                                 rest_addr =
1546                                                                     0x7fff;
1547                                                                 sec_mask =
1548                                                                     0x18000;
1549                                                         } else if (
1550                                                             sec_number == 2 ||
1551                                                             sec_number == 3) {
1552                                                                 rest_addr =
1553                                                                     0x1fff;
1554                                                                 sec_mask =
1555                                                                     0x1e000;
1556                                                         } else if (
1557                                                             sec_number == 4) {
1558                                                                 rest_addr =
1559                                                                     0x3fff;
1560                                                                 sec_mask =
1561                                                                     0x1c000;
1562                                                         }
1563                                                 }
1564                                         }
1565                                 } else if (addr == ha->optrom_size / 2) {
1566                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1567                                         RD_REG_WORD(&reg->nvram);
1568                                 }
1569
1570                                 if (flash_id == 0xda && man_id == 0xc1) {
1571                                         qla2x00_write_flash_byte(ha, 0x5555,
1572                                             0xaa);
1573                                         qla2x00_write_flash_byte(ha, 0x2aaa,
1574                                             0x55);
1575                                         qla2x00_write_flash_byte(ha, 0x5555,
1576                                             0xa0);
1577                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1578                                         /* Then erase it */
1579                                         if (qla2x00_erase_flash_sector(ha,
1580                                             addr, sec_mask, man_id,
1581                                             flash_id)) {
1582                                                 rval = QLA_FUNCTION_FAILED;
1583                                                 break;
1584                                         }
1585                                         if (man_id == 0x01 && flash_id == 0x6d)
1586                                                 sec_number++;
1587                                 }
1588                         }
1589
1590                         if (man_id == 0x01 && flash_id == 0x6d) {
1591                                 if (sec_number == 1 &&
1592                                     addr == (rest_addr - 1)) {
1593                                         rest_addr = 0x0fff;
1594                                         sec_mask   = 0x1f000;
1595                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1596                                         rest_addr = 0x3fff;
1597                                         sec_mask   = 0x1c000;
1598                                 }
1599                         }
1600
1601                         if (qla2x00_program_flash_address(ha, addr, data,
1602                             man_id, flash_id)) {
1603                                 rval = QLA_FUNCTION_FAILED;
1604                                 break;
1605                         }
1606                 }
1607         } while (0);
1608         qla2x00_flash_disable(ha);
1609         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1610
1611         /* Resume HBA. */
1612         qla2x00_resume_hba(ha);
1613
1614         return rval;
1615 }
1616
1617 uint8_t *
1618 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1619     uint32_t offset, uint32_t length)
1620 {
1621         /* Suspend HBA. */
1622         scsi_block_requests(ha->host);
1623         ha->isp_ops.disable_intrs(ha);
1624         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1625
1626         /* Go with read. */
1627         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1628
1629         /* Resume HBA. */
1630         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1631         ha->isp_ops.enable_intrs(ha);
1632         scsi_unblock_requests(ha->host);
1633
1634         return buf;
1635 }
1636
1637 int
1638 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1639     uint32_t offset, uint32_t length)
1640 {
1641         int rval;
1642
1643         /* Suspend HBA. */
1644         scsi_block_requests(ha->host);
1645         ha->isp_ops.disable_intrs(ha);
1646         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1647
1648         /* Go with write. */
1649         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1650             length >> 2);
1651
1652         /* Resume HBA -- RISC reset needed. */
1653         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1654         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1655         up(ha->dpc_wait);
1656         qla2x00_wait_for_hba_online(ha);
1657         scsi_unblock_requests(ha->host);
1658
1659         return rval;
1660 }