2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
24 * - Added generic SATA support by using a pci_device_id that filters on
25 * the IDE storage class code.
28 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
29 * mmio_base, which is only set for the CK804/MCP04 case.
32 * - Added support for CK804 SATA controller.
38 #include <linux/config.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
47 #include <scsi/scsi_host.h>
48 #include <linux/libata.h>
50 #define DRV_NAME "sata_nv"
51 #define DRV_VERSION "0.6"
54 #define NV_PIO_MASK 0x1f
55 #define NV_MWDMA_MASK 0x07
56 #define NV_UDMA_MASK 0x7f
57 #define NV_PORT0_SCR_REG_OFFSET 0x00
58 #define NV_PORT1_SCR_REG_OFFSET 0x40
60 #define NV_INT_STATUS 0x10
61 #define NV_INT_STATUS_CK804 0x440
62 #define NV_INT_STATUS_PDEV_INT 0x01
63 #define NV_INT_STATUS_PDEV_PM 0x02
64 #define NV_INT_STATUS_PDEV_ADDED 0x04
65 #define NV_INT_STATUS_PDEV_REMOVED 0x08
66 #define NV_INT_STATUS_SDEV_INT 0x10
67 #define NV_INT_STATUS_SDEV_PM 0x20
68 #define NV_INT_STATUS_SDEV_ADDED 0x40
69 #define NV_INT_STATUS_SDEV_REMOVED 0x80
70 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
71 NV_INT_STATUS_PDEV_REMOVED)
72 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
73 NV_INT_STATUS_SDEV_REMOVED)
74 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
75 NV_INT_STATUS_SDEV_HOTPLUG)
77 #define NV_INT_ENABLE 0x11
78 #define NV_INT_ENABLE_CK804 0x441
79 #define NV_INT_ENABLE_PDEV_MASK 0x01
80 #define NV_INT_ENABLE_PDEV_PM 0x02
81 #define NV_INT_ENABLE_PDEV_ADDED 0x04
82 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
83 #define NV_INT_ENABLE_SDEV_MASK 0x10
84 #define NV_INT_ENABLE_SDEV_PM 0x20
85 #define NV_INT_ENABLE_SDEV_ADDED 0x40
86 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
87 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
88 NV_INT_ENABLE_PDEV_REMOVED)
89 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
90 NV_INT_ENABLE_SDEV_REMOVED)
91 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
92 NV_INT_ENABLE_SDEV_HOTPLUG)
94 #define NV_INT_CONFIG 0x12
95 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
97 // For PCI config register 20
98 #define NV_MCP_SATA_CFG_20 0x50
99 #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
101 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
102 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
103 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
104 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
105 static void nv_host_stop (struct ata_host_set *host_set);
106 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
107 static void nv_disable_hotplug(struct ata_host_set *host_set);
108 static void nv_check_hotplug(struct ata_host_set *host_set);
109 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
110 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
111 static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
121 static struct pci_device_id nv_pci_tbl[] = {
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
137 PCI_ANY_ID, PCI_ANY_ID,
138 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
139 { 0, } /* terminate list */
142 #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
146 enum nv_host_type host_type;
147 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
148 void (*disable_hotplug)(struct ata_host_set *host_set);
149 void (*check_hotplug)(struct ata_host_set *host_set);
152 static struct nv_host_desc nv_device_tbl[] = {
154 .host_type = GENERIC,
155 .enable_hotplug = NULL,
156 .disable_hotplug= NULL,
157 .check_hotplug = NULL,
160 .host_type = NFORCE2,
161 .enable_hotplug = nv_enable_hotplug,
162 .disable_hotplug= nv_disable_hotplug,
163 .check_hotplug = nv_check_hotplug,
166 .host_type = NFORCE3,
167 .enable_hotplug = nv_enable_hotplug,
168 .disable_hotplug= nv_disable_hotplug,
169 .check_hotplug = nv_check_hotplug,
171 { .host_type = CK804,
172 .enable_hotplug = nv_enable_hotplug_ck804,
173 .disable_hotplug= nv_disable_hotplug_ck804,
174 .check_hotplug = nv_check_hotplug_ck804,
180 struct nv_host_desc *host_desc;
181 unsigned long host_flags;
184 static struct pci_driver nv_pci_driver = {
186 .id_table = nv_pci_tbl,
187 .probe = nv_init_one,
188 .remove = ata_pci_remove_one,
191 static Scsi_Host_Template nv_sht = {
192 .module = THIS_MODULE,
194 .ioctl = ata_scsi_ioctl,
195 .queuecommand = ata_scsi_queuecmd,
196 .eh_strategy_handler = ata_scsi_error,
197 .can_queue = ATA_DEF_QUEUE,
198 .this_id = ATA_SHT_THIS_ID,
199 .sg_tablesize = LIBATA_MAX_PRD,
200 .max_sectors = ATA_MAX_SECTORS,
201 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
202 .emulated = ATA_SHT_EMULATED,
203 .use_clustering = ATA_SHT_USE_CLUSTERING,
204 .proc_name = DRV_NAME,
205 .dma_boundary = ATA_DMA_BOUNDARY,
206 .slave_configure = ata_scsi_slave_config,
207 .bios_param = ata_std_bios_param,
210 static struct ata_port_operations nv_ops = {
211 .port_disable = ata_port_disable,
212 .tf_load = ata_tf_load,
213 .tf_read = ata_tf_read,
214 .exec_command = ata_exec_command,
215 .check_status = ata_check_status,
216 .dev_select = ata_std_dev_select,
217 .phy_reset = sata_phy_reset,
218 .bmdma_setup = ata_bmdma_setup,
219 .bmdma_start = ata_bmdma_start,
220 .bmdma_stop = ata_bmdma_stop,
221 .bmdma_status = ata_bmdma_status,
222 .qc_prep = ata_qc_prep,
223 .qc_issue = ata_qc_issue_prot,
224 .eng_timeout = ata_eng_timeout,
225 .irq_handler = nv_interrupt,
226 .irq_clear = ata_bmdma_irq_clear,
227 .scr_read = nv_scr_read,
228 .scr_write = nv_scr_write,
229 .port_start = ata_port_start,
230 .port_stop = ata_port_stop,
231 .host_stop = nv_host_stop,
234 /* FIXME: The hardware provides the necessary SATA PHY controls
235 * to support ATA_FLAG_SATA_RESET. However, it is currently
236 * necessary to disable that flag, to solve misdetection problems.
237 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
239 * This problem really needs to be investigated further. But in the
240 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
242 static struct ata_port_info nv_port_info = {
244 .host_flags = ATA_FLAG_SATA |
245 /* ATA_FLAG_SATA_RESET | */
248 .pio_mask = NV_PIO_MASK,
249 .mwdma_mask = NV_MWDMA_MASK,
250 .udma_mask = NV_UDMA_MASK,
254 MODULE_AUTHOR("NVIDIA");
255 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
256 MODULE_LICENSE("GPL");
257 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
258 MODULE_VERSION(DRV_VERSION);
260 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
262 struct ata_host_set *host_set = dev_instance;
263 struct nv_host *host = host_set->private_data;
265 unsigned int handled = 0;
268 spin_lock_irqsave(&host_set->lock, flags);
270 for (i = 0; i < host_set->n_ports; i++) {
273 ap = host_set->ports[i];
274 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
275 struct ata_queued_cmd *qc;
277 qc = ata_qc_from_tag(ap, ap->active_tag);
278 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
279 handled += ata_host_intr(ap, qc);
284 if (host->host_desc->check_hotplug)
285 host->host_desc->check_hotplug(host_set);
287 spin_unlock_irqrestore(&host_set->lock, flags);
289 return IRQ_RETVAL(handled);
292 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
294 struct ata_host_set *host_set = ap->host_set;
295 struct nv_host *host = host_set->private_data;
297 if (sc_reg > SCR_CONTROL)
300 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
301 return readl((void*)ap->ioaddr.scr_addr + (sc_reg * 4));
303 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
306 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
308 struct ata_host_set *host_set = ap->host_set;
309 struct nv_host *host = host_set->private_data;
311 if (sc_reg > SCR_CONTROL)
314 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
315 writel(val, (void*)ap->ioaddr.scr_addr + (sc_reg * 4));
317 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
320 static void nv_host_stop (struct ata_host_set *host_set)
322 struct nv_host *host = host_set->private_data;
324 // Disable hotplug event interrupts.
325 if (host->host_desc->disable_hotplug)
326 host->host_desc->disable_hotplug(host_set);
331 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
333 static int printed_version = 0;
334 struct nv_host *host;
335 struct ata_port_info *ppi;
336 struct ata_probe_ent *probe_ent;
337 int pci_dev_busy = 0;
341 // Make sure this is a SATA controller by counting the number of bars
342 // (NVIDIA SATA controllers will always have six bars). Otherwise,
343 // it's an IDE controller and we ignore it.
344 for (bar=0; bar<6; bar++)
345 if (pci_resource_start(pdev, bar) == 0)
348 if (!printed_version++)
349 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
351 rc = pci_enable_device(pdev);
355 rc = pci_request_regions(pdev, DRV_NAME);
358 goto err_out_disable;
361 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
363 goto err_out_regions;
364 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
366 goto err_out_regions;
371 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
373 goto err_out_regions;
375 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
377 goto err_out_free_ent;
379 memset(host, 0, sizeof(struct nv_host));
380 host->host_desc = &nv_device_tbl[ent->driver_data];
382 probe_ent->private_data = host;
384 if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
385 host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
387 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
390 probe_ent->mmio_base = ioremap(pci_resource_start(pdev, 5),
391 pci_resource_len(pdev, 5));
392 if (probe_ent->mmio_base == NULL) {
394 goto err_out_free_host;
397 base = (unsigned long)probe_ent->mmio_base;
399 probe_ent->port[0].scr_addr =
400 base + NV_PORT0_SCR_REG_OFFSET;
401 probe_ent->port[1].scr_addr =
402 base + NV_PORT1_SCR_REG_OFFSET;
405 probe_ent->port[0].scr_addr =
406 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
407 probe_ent->port[1].scr_addr =
408 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
411 pci_set_master(pdev);
413 rc = ata_device_add(probe_ent);
415 goto err_out_iounmap;
417 // Enable hotplug event interrupts.
418 if (host->host_desc->enable_hotplug)
419 host->host_desc->enable_hotplug(probe_ent);
426 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
427 iounmap(probe_ent->mmio_base);
433 pci_release_regions(pdev);
436 pci_disable_device(pdev);
441 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
445 outb(NV_INT_STATUS_HOTPLUG,
446 probe_ent->port[0].scr_addr + NV_INT_STATUS);
448 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
449 intr_mask |= NV_INT_ENABLE_HOTPLUG;
451 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
454 static void nv_disable_hotplug(struct ata_host_set *host_set)
458 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
460 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
462 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
465 static void nv_check_hotplug(struct ata_host_set *host_set)
469 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
471 // Clear interrupt status.
472 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
474 if (intr_status & NV_INT_STATUS_HOTPLUG) {
475 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
476 printk(KERN_WARNING "nv_sata: "
477 "Primary device added\n");
479 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
480 printk(KERN_WARNING "nv_sata: "
481 "Primary device removed\n");
483 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
484 printk(KERN_WARNING "nv_sata: "
485 "Secondary device added\n");
487 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
488 printk(KERN_WARNING "nv_sata: "
489 "Secondary device removed\n");
493 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
495 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
499 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
500 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
501 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
503 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
505 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
506 intr_mask |= NV_INT_ENABLE_HOTPLUG;
508 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
511 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
513 struct pci_dev *pdev = to_pci_dev(host_set->dev);
517 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
519 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
521 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
523 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
524 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
525 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
528 static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
532 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
534 // Clear interrupt status.
535 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
537 if (intr_status & NV_INT_STATUS_HOTPLUG) {
538 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
539 printk(KERN_WARNING "nv_sata: "
540 "Primary device added\n");
542 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
543 printk(KERN_WARNING "nv_sata: "
544 "Primary device removed\n");
546 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
547 printk(KERN_WARNING "nv_sata: "
548 "Secondary device added\n");
550 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
551 printk(KERN_WARNING "nv_sata: "
552 "Secondary device removed\n");
556 static int __init nv_init(void)
558 return pci_module_init(&nv_pci_driver);
561 static void __exit nv_exit(void)
563 pci_unregister_driver(&nv_pci_driver);
566 module_init(nv_init);
567 module_exit(nv_exit);