2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
25 #include <linux/config.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
34 #include <scsi/scsi_host.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "sata_nv"
38 #define DRV_VERSION "0.01"
41 #define NV_PIO_MASK 0x1f
42 #define NV_UDMA_MASK 0x7f
43 #define NV_PORT0_BMDMA_REG_OFFSET 0x00
44 #define NV_PORT1_BMDMA_REG_OFFSET 0x08
45 #define NV_PORT0_SCR_REG_OFFSET 0x00
46 #define NV_PORT1_SCR_REG_OFFSET 0x40
48 #define NV_INT_STATUS 0x10
49 #define NV_INT_STATUS_PDEV_INT 0x01
50 #define NV_INT_STATUS_PDEV_PM 0x02
51 #define NV_INT_STATUS_PDEV_ADDED 0x04
52 #define NV_INT_STATUS_PDEV_REMOVED 0x08
53 #define NV_INT_STATUS_SDEV_INT 0x10
54 #define NV_INT_STATUS_SDEV_PM 0x20
55 #define NV_INT_STATUS_SDEV_ADDED 0x40
56 #define NV_INT_STATUS_SDEV_REMOVED 0x80
57 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
58 NV_INT_STATUS_PDEV_REMOVED)
59 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
60 NV_INT_STATUS_SDEV_REMOVED)
61 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
62 NV_INT_STATUS_SDEV_HOTPLUG)
64 #define NV_INT_ENABLE 0x11
65 #define NV_INT_ENABLE_PDEV_MASK 0x01
66 #define NV_INT_ENABLE_PDEV_PM 0x02
67 #define NV_INT_ENABLE_PDEV_ADDED 0x04
68 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
69 #define NV_INT_ENABLE_SDEV_MASK 0x10
70 #define NV_INT_ENABLE_SDEV_PM 0x20
71 #define NV_INT_ENABLE_SDEV_ADDED 0x40
72 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
73 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
74 NV_INT_ENABLE_PDEV_REMOVED)
75 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
76 NV_INT_ENABLE_SDEV_REMOVED)
77 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
78 NV_INT_ENABLE_SDEV_HOTPLUG)
80 #define NV_INT_CONFIG 0x12
81 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
83 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
85 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
86 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
87 static void nv_host_stop (struct ata_host_set *host_set);
89 static struct pci_device_id nv_pci_tbl[] = {
90 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
91 PCI_ANY_ID, PCI_ANY_ID, },
92 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
93 PCI_ANY_ID, PCI_ANY_ID, },
94 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
95 PCI_ANY_ID, PCI_ANY_ID, },
96 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
97 PCI_ANY_ID, PCI_ANY_ID, },
98 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
99 PCI_ANY_ID, PCI_ANY_ID, },
100 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
101 PCI_ANY_ID, PCI_ANY_ID, },
102 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
103 PCI_ANY_ID, PCI_ANY_ID, },
104 { 0, } /* terminate list */
107 static struct pci_driver nv_pci_driver = {
109 .id_table = nv_pci_tbl,
110 .probe = nv_init_one,
111 .remove = ata_pci_remove_one,
114 static Scsi_Host_Template nv_sht = {
115 .module = THIS_MODULE,
117 .queuecommand = ata_scsi_queuecmd,
118 .eh_strategy_handler = ata_scsi_error,
119 .can_queue = ATA_DEF_QUEUE,
120 .this_id = ATA_SHT_THIS_ID,
121 .sg_tablesize = ATA_MAX_PRD,
122 .max_sectors = ATA_MAX_SECTORS,
123 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
124 .emulated = ATA_SHT_EMULATED,
125 .use_clustering = ATA_SHT_USE_CLUSTERING,
126 .proc_name = DRV_NAME,
127 .dma_boundary = ATA_DMA_BOUNDARY,
128 .slave_configure = ata_scsi_slave_config,
129 .bios_param = ata_std_bios_param,
132 static struct ata_port_operations nv_ops = {
133 .port_disable = ata_port_disable,
134 .tf_load = ata_tf_load_pio,
135 .tf_read = ata_tf_read_pio,
136 .exec_command = ata_exec_command_pio,
137 .check_status = ata_check_status_pio,
138 .phy_reset = sata_phy_reset,
139 .bmdma_setup = ata_bmdma_setup_pio,
140 .bmdma_start = ata_bmdma_start_pio,
141 .qc_prep = ata_qc_prep,
142 .qc_issue = ata_qc_issue_prot,
143 .eng_timeout = ata_eng_timeout,
144 .irq_handler = nv_interrupt,
145 .irq_clear = ata_bmdma_irq_clear,
146 .scr_read = nv_scr_read,
147 .scr_write = nv_scr_write,
148 .port_start = ata_port_start,
149 .port_stop = ata_port_stop,
150 .host_stop = nv_host_stop,
153 MODULE_AUTHOR("NVIDIA");
154 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
155 MODULE_LICENSE("GPL");
156 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
158 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
160 struct ata_host_set *host_set = dev_instance;
162 unsigned int handled = 0;
167 spin_lock_irqsave(&host_set->lock, flags);
169 for (i = 0; i < host_set->n_ports; i++) {
172 ap = host_set->ports[i];
173 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
174 struct ata_queued_cmd *qc;
176 qc = ata_qc_from_tag(ap, ap->active_tag);
177 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
178 handled += ata_host_intr(ap, qc);
181 intr_status = inb(ap->ioaddr.scr_addr + NV_INT_STATUS);
182 intr_enable = inb(ap->ioaddr.scr_addr + NV_INT_ENABLE);
184 // Clear interrupt status.
185 outb(0xff, ap->ioaddr.scr_addr + NV_INT_STATUS);
187 if (intr_status & NV_INT_STATUS_HOTPLUG) {
188 if (intr_status & NV_INT_STATUS_PDEV_ADDED) {
189 printk(KERN_WARNING "ata%u: "
190 "Primary device added\n", ap->id);
193 if (intr_status & NV_INT_STATUS_PDEV_REMOVED) {
194 printk(KERN_WARNING "ata%u: "
195 "Primary device removed\n", ap->id);
198 if (intr_status & NV_INT_STATUS_SDEV_ADDED) {
199 printk(KERN_WARNING "ata%u: "
200 "Secondary device added\n", ap->id);
203 if (intr_status & NV_INT_STATUS_SDEV_REMOVED) {
204 printk(KERN_WARNING "ata%u: "
205 "Secondary device removed\n", ap->id);
210 spin_unlock_irqrestore(&host_set->lock, flags);
212 return IRQ_RETVAL(handled);
215 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
217 if (sc_reg > SCR_CONTROL)
220 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
223 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
225 if (sc_reg > SCR_CONTROL)
228 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
231 static void nv_host_stop (struct ata_host_set *host_set)
235 for (i=0; i<host_set->n_ports; i++) {
238 // Disable hotplug event interrupts.
239 intr_mask = inb(host_set->ports[i]->ioaddr.scr_addr +
241 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
242 outb(intr_mask, host_set->ports[i]->ioaddr.scr_addr +
247 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
249 static int printed_version = 0;
250 struct ata_probe_ent *probe_ent = NULL;
254 if (!printed_version++)
255 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
257 rc = pci_enable_device(pdev);
261 rc = pci_request_regions(pdev, DRV_NAME);
265 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
267 goto err_out_regions;
268 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
270 goto err_out_regions;
272 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
275 goto err_out_regions;
278 memset(probe_ent, 0, sizeof(*probe_ent));
279 INIT_LIST_HEAD(&probe_ent->node);
281 probe_ent->pdev = pdev;
282 probe_ent->sht = &nv_sht;
283 probe_ent->host_flags = ATA_FLAG_SATA |
284 ATA_FLAG_SATA_RESET |
287 probe_ent->port_ops = &nv_ops;
288 probe_ent->n_ports = NV_PORTS;
289 probe_ent->irq = pdev->irq;
290 probe_ent->irq_flags = SA_SHIRQ;
291 probe_ent->pio_mask = NV_PIO_MASK;
292 probe_ent->udma_mask = NV_UDMA_MASK;
294 probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
295 ata_std_ports(&probe_ent->port[0]);
296 probe_ent->port[0].altstatus_addr =
297 probe_ent->port[0].ctl_addr =
298 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
299 probe_ent->port[0].bmdma_addr =
300 pci_resource_start(pdev, 4) | NV_PORT0_BMDMA_REG_OFFSET;
301 probe_ent->port[0].scr_addr =
302 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
304 probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
305 ata_std_ports(&probe_ent->port[1]);
306 probe_ent->port[1].altstatus_addr =
307 probe_ent->port[1].ctl_addr =
308 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
309 probe_ent->port[1].bmdma_addr =
310 pci_resource_start(pdev, 4) | NV_PORT1_BMDMA_REG_OFFSET;
311 probe_ent->port[1].scr_addr =
312 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
314 pci_set_master(pdev);
316 rc = ata_device_add(probe_ent);
318 goto err_out_regions;
320 // Enable hotplug event interrupts.
321 for (i=0; i<probe_ent->n_ports; i++) {
324 outb(NV_INT_STATUS_HOTPLUG, probe_ent->port[i].scr_addr +
327 intr_mask = inb(probe_ent->port[i].scr_addr + NV_INT_ENABLE);
328 intr_mask |= NV_INT_ENABLE_HOTPLUG;
329 outb(intr_mask, probe_ent->port[i].scr_addr + NV_INT_ENABLE);
337 pci_release_regions(pdev);
340 pci_disable_device(pdev);
344 static int __init nv_init(void)
346 return pci_module_init(&nv_pci_driver);
349 static void __exit nv_exit(void)
351 pci_unregister_driver(&nv_pci_driver);
354 module_init(nv_init);
355 module_exit(nv_exit);