2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.01"
47 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE = 0x41, /* TBG mode */
50 PDC_FLASH_CTL = 0x44, /* Flash control register */
51 PDC_PCI_CTL = 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
57 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
60 board_2037x = 0, /* FastTrak S150 TX2plus */
61 board_20319 = 1, /* FastTrak S150 TX4 */
63 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
65 PDC_RESET = (1 << 11), /* HDMA reset */
69 struct pdc_port_priv {
74 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
75 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
77 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
78 static void pdc_eng_timeout(struct ata_port *ap);
79 static int pdc_port_start(struct ata_port *ap);
80 static void pdc_port_stop(struct ata_port *ap);
81 static void pdc_phy_reset(struct ata_port *ap);
82 static void pdc_qc_prep(struct ata_queued_cmd *qc);
83 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
84 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
85 static void pdc_irq_clear(struct ata_port *ap);
86 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
88 static Scsi_Host_Template pdc_ata_sht = {
89 .module = THIS_MODULE,
91 .ioctl = ata_scsi_ioctl,
92 .queuecommand = ata_scsi_queuecmd,
93 .eh_strategy_handler = ata_scsi_error,
94 .can_queue = ATA_DEF_QUEUE,
95 .this_id = ATA_SHT_THIS_ID,
96 .sg_tablesize = LIBATA_MAX_PRD,
97 .max_sectors = ATA_MAX_SECTORS,
98 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
99 .emulated = ATA_SHT_EMULATED,
100 .use_clustering = ATA_SHT_USE_CLUSTERING,
101 .proc_name = DRV_NAME,
102 .dma_boundary = ATA_DMA_BOUNDARY,
103 .slave_configure = ata_scsi_slave_config,
104 .bios_param = ata_std_bios_param,
107 static struct ata_port_operations pdc_ata_ops = {
108 .port_disable = ata_port_disable,
109 .tf_load = pdc_tf_load_mmio,
110 .tf_read = ata_tf_read,
111 .check_status = ata_check_status,
112 .exec_command = pdc_exec_command_mmio,
113 .dev_select = ata_std_dev_select,
114 .phy_reset = pdc_phy_reset,
115 .qc_prep = pdc_qc_prep,
116 .qc_issue = pdc_qc_issue_prot,
117 .eng_timeout = pdc_eng_timeout,
118 .irq_handler = pdc_interrupt,
119 .irq_clear = pdc_irq_clear,
120 .scr_read = pdc_sata_scr_read,
121 .scr_write = pdc_sata_scr_write,
122 .port_start = pdc_port_start,
123 .port_stop = pdc_port_stop,
126 static struct ata_port_info pdc_port_info[] = {
130 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
131 ATA_FLAG_SRST | ATA_FLAG_MMIO,
132 .pio_mask = 0x1f, /* pio0-4 */
133 .mwdma_mask = 0x07, /* mwdma0-2 */
134 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
135 .port_ops = &pdc_ata_ops,
141 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
142 ATA_FLAG_SRST | ATA_FLAG_MMIO,
143 .pio_mask = 0x1f, /* pio0-4 */
144 .mwdma_mask = 0x07, /* mwdma0-2 */
145 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
146 .port_ops = &pdc_ata_ops,
150 static struct pci_device_id pdc_ata_pci_tbl[] = {
151 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
153 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
155 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
157 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
159 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
161 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
164 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
166 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
168 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
171 { } /* terminate list */
175 static struct pci_driver pdc_ata_pci_driver = {
177 .id_table = pdc_ata_pci_tbl,
178 .probe = pdc_ata_init_one,
179 .remove = ata_pci_remove_one,
183 static int pdc_port_start(struct ata_port *ap)
185 struct device *dev = ap->host_set->dev;
186 struct pdc_port_priv *pp;
189 rc = ata_port_start(ap);
193 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
198 memset(pp, 0, sizeof(*pp));
200 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
206 ap->private_data = pp;
218 static void pdc_port_stop(struct ata_port *ap)
220 struct device *dev = ap->host_set->dev;
221 struct pdc_port_priv *pp = ap->private_data;
223 ap->private_data = NULL;
224 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
230 static void pdc_reset_port(struct ata_port *ap)
232 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
236 for (i = 11; i > 0; i--) {
249 readl(mmio); /* flush */
252 static void pdc_phy_reset(struct ata_port *ap)
258 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
260 if (sc_reg > SCR_CONTROL)
262 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
266 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
269 if (sc_reg > SCR_CONTROL)
271 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
274 static void pdc_qc_prep(struct ata_queued_cmd *qc)
276 struct pdc_port_priv *pp = qc->ap->private_data;
281 switch (qc->tf.protocol) {
286 case ATA_PROT_NODATA:
287 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
288 qc->dev->devno, pp->pkt);
290 if (qc->tf.flags & ATA_TFLAG_LBA48)
291 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
293 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
295 pdc_pkt_footer(&qc->tf, pp->pkt, i);
303 static void pdc_eng_timeout(struct ata_port *ap)
306 struct ata_queued_cmd *qc;
310 qc = ata_qc_from_tag(ap, ap->active_tag);
312 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
317 /* hack alert! We cannot use the supplied completion
318 * function from inside the ->eh_strategy_handler() thread.
319 * libata is the only user of ->eh_strategy_handler() in
320 * any kernel, so the default scsi_done() assumes it is
321 * not being called from the SCSI EH.
323 qc->scsidone = scsi_finish_command;
325 switch (qc->tf.protocol) {
327 case ATA_PROT_NODATA:
328 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
329 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
333 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
335 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
336 ap->id, qc->tf.command, drv_stat);
338 ata_qc_complete(qc, drv_stat);
346 static inline unsigned int pdc_host_intr( struct ata_port *ap,
347 struct ata_queued_cmd *qc)
350 unsigned int handled = 0, have_err = 0;
352 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
355 if (tmp & PDC_ERR_MASK) {
360 switch (qc->tf.protocol) {
362 case ATA_PROT_NODATA:
363 status = ata_wait_idle(ap);
366 ata_qc_complete(qc, status);
371 ap->stats.idle_irq++;
378 static void pdc_irq_clear(struct ata_port *ap)
380 struct ata_host_set *host_set = ap->host_set;
381 void *mmio = host_set->mmio_base;
383 readl(mmio + PDC_INT_SEQMASK);
386 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
388 struct ata_host_set *host_set = dev_instance;
392 unsigned int handled = 0;
397 if (!host_set || !host_set->mmio_base) {
398 VPRINTK("QUICK EXIT\n");
402 mmio_base = host_set->mmio_base;
404 /* reading should also clear interrupts */
405 mask = readl(mmio_base + PDC_INT_SEQMASK);
407 if (mask == 0xffffffff) {
408 VPRINTK("QUICK EXIT 2\n");
411 mask &= 0xffff; /* only 16 tags possible */
413 VPRINTK("QUICK EXIT 3\n");
417 spin_lock(&host_set->lock);
419 writel(mask, mmio_base + PDC_INT_SEQMASK);
421 for (i = 0; i < host_set->n_ports; i++) {
422 VPRINTK("port %u\n", i);
423 ap = host_set->ports[i];
424 tmp = mask & (1 << (i + 1));
425 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
426 struct ata_queued_cmd *qc;
428 qc = ata_qc_from_tag(ap, ap->active_tag);
429 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
430 handled += pdc_host_intr(ap, qc);
434 spin_unlock(&host_set->lock);
438 return IRQ_RETVAL(handled);
441 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
443 struct ata_port *ap = qc->ap;
444 struct pdc_port_priv *pp = ap->private_data;
445 unsigned int port_no = ap->port_no;
446 u8 seq = (u8) (port_no + 1);
448 VPRINTK("ENTER, ap %p\n", ap);
450 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
451 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
454 wmb(); /* flush PRD, pkt writes */
455 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
456 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
459 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
461 switch (qc->tf.protocol) {
463 case ATA_PROT_NODATA:
464 pdc_packet_start(qc);
467 case ATA_PROT_ATAPI_DMA:
475 return ata_qc_issue_prot(qc);
478 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
480 WARN_ON (tf->protocol == ATA_PROT_DMA ||
481 tf->protocol == ATA_PROT_NODATA);
486 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
488 WARN_ON (tf->protocol == ATA_PROT_DMA ||
489 tf->protocol == ATA_PROT_NODATA);
490 ata_exec_command(ap, tf);
494 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
496 port->cmd_addr = base;
497 port->data_addr = base;
499 port->error_addr = base + 0x4;
500 port->nsect_addr = base + 0x8;
501 port->lbal_addr = base + 0xc;
502 port->lbam_addr = base + 0x10;
503 port->lbah_addr = base + 0x14;
504 port->device_addr = base + 0x18;
506 port->status_addr = base + 0x1c;
507 port->altstatus_addr =
508 port->ctl_addr = base + 0x38;
512 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
514 void *mmio = pe->mmio_base;
518 * Except for the hotplug stuff, this is voodoo from the
519 * Promise driver. Label this entire section
520 * "TODO: figure out why we do this"
523 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
524 tmp = readl(mmio + PDC_FLASH_CTL);
525 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
526 writel(tmp, mmio + PDC_FLASH_CTL);
528 /* clear plug/unplug flags for all ports */
529 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
530 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
532 /* mask plug/unplug ints */
533 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
534 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
536 /* reduce TBG clock to 133 Mhz. */
537 tmp = readl(mmio + PDC_TBG_MODE);
538 tmp &= ~0x30000; /* clear bit 17, 16*/
539 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
540 writel(tmp, mmio + PDC_TBG_MODE);
542 readl(mmio + PDC_TBG_MODE); /* flush */
545 /* adjust slew rate control register. */
546 tmp = readl(mmio + PDC_SLEW_CTL);
547 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
548 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
549 writel(tmp, mmio + PDC_SLEW_CTL);
552 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
554 static int printed_version;
555 struct ata_probe_ent *probe_ent = NULL;
558 unsigned int board_idx = (unsigned int) ent->driver_data;
559 int pci_dev_busy = 0;
562 if (!printed_version++)
563 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
566 * If this driver happens to only be useful on Apple's K2, then
567 * we should check that here as it has a normal Serverworks ID
569 rc = pci_enable_device(pdev);
573 rc = pci_request_regions(pdev, DRV_NAME);
579 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
581 goto err_out_regions;
582 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
584 goto err_out_regions;
586 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
587 if (probe_ent == NULL) {
589 goto err_out_regions;
592 memset(probe_ent, 0, sizeof(*probe_ent));
593 probe_ent->dev = pci_dev_to_dev(pdev);
594 INIT_LIST_HEAD(&probe_ent->node);
596 mmio_base = ioremap(pci_resource_start(pdev, 3),
597 pci_resource_len(pdev, 3));
598 if (mmio_base == NULL) {
600 goto err_out_free_ent;
602 base = (unsigned long) mmio_base;
604 probe_ent->sht = pdc_port_info[board_idx].sht;
605 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
606 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
607 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
608 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
609 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
611 probe_ent->irq = pdev->irq;
612 probe_ent->irq_flags = SA_SHIRQ;
613 probe_ent->mmio_base = mmio_base;
615 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
616 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
618 probe_ent->port[0].scr_addr = base + 0x400;
619 probe_ent->port[1].scr_addr = base + 0x500;
621 /* notice 4-port boards */
624 probe_ent->n_ports = 4;
626 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
627 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
629 probe_ent->port[2].scr_addr = base + 0x600;
630 probe_ent->port[3].scr_addr = base + 0x700;
633 probe_ent->n_ports = 2;
640 pci_set_master(pdev);
642 /* initialize adapter */
643 pdc_host_init(board_idx, probe_ent);
645 /* FIXME: check ata_device_add return value */
646 ata_device_add(probe_ent);
654 pci_release_regions(pdev);
657 pci_disable_device(pdev);
662 static int __init pdc_ata_init(void)
664 return pci_module_init(&pdc_ata_pci_driver);
668 static void __exit pdc_ata_exit(void)
670 pci_unregister_driver(&pdc_ata_pci_driver);
674 MODULE_AUTHOR("Jeff Garzik");
675 MODULE_DESCRIPTION("Promise SATA TX2/TX4 low-level driver");
676 MODULE_LICENSE("GPL");
677 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
678 MODULE_VERSION(DRV_VERSION);
680 module_init(pdc_ata_init);
681 module_exit(pdc_ata_exit);