2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.03"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69 board_20771 = 3, /* FastTrak TX2300 */
71 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
73 PDC_RESET = (1 << 11), /* HDMA reset */
75 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
76 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
80 struct pdc_port_priv {
85 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
86 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
87 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
88 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
89 static void pdc_eng_timeout(struct ata_port *ap);
90 static int pdc_port_start(struct ata_port *ap);
91 static void pdc_port_stop(struct ata_port *ap);
92 static void pdc_pata_phy_reset(struct ata_port *ap);
93 static void pdc_sata_phy_reset(struct ata_port *ap);
94 static void pdc_qc_prep(struct ata_queued_cmd *qc);
95 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
96 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
97 static void pdc_irq_clear(struct ata_port *ap);
98 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
101 static struct scsi_host_template pdc_ata_sht = {
102 .module = THIS_MODULE,
104 .ioctl = ata_scsi_ioctl,
105 .queuecommand = ata_scsi_queuecmd,
106 .eh_strategy_handler = ata_scsi_error,
107 .can_queue = ATA_DEF_QUEUE,
108 .this_id = ATA_SHT_THIS_ID,
109 .sg_tablesize = LIBATA_MAX_PRD,
110 .max_sectors = ATA_MAX_SECTORS,
111 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
112 .emulated = ATA_SHT_EMULATED,
113 .use_clustering = ATA_SHT_USE_CLUSTERING,
114 .proc_name = DRV_NAME,
115 .dma_boundary = ATA_DMA_BOUNDARY,
116 .slave_configure = ata_scsi_slave_config,
117 .bios_param = ata_std_bios_param,
120 static const struct ata_port_operations pdc_sata_ops = {
121 .port_disable = ata_port_disable,
122 .tf_load = pdc_tf_load_mmio,
123 .tf_read = ata_tf_read,
124 .check_status = ata_check_status,
125 .exec_command = pdc_exec_command_mmio,
126 .dev_select = ata_std_dev_select,
128 .phy_reset = pdc_sata_phy_reset,
130 .qc_prep = pdc_qc_prep,
131 .qc_issue = pdc_qc_issue_prot,
132 .eng_timeout = pdc_eng_timeout,
133 .irq_handler = pdc_interrupt,
134 .irq_clear = pdc_irq_clear,
136 .scr_read = pdc_sata_scr_read,
137 .scr_write = pdc_sata_scr_write,
138 .port_start = pdc_port_start,
139 .port_stop = pdc_port_stop,
140 .host_stop = ata_pci_host_stop,
143 static const struct ata_port_operations pdc_pata_ops = {
144 .port_disable = ata_port_disable,
145 .tf_load = pdc_tf_load_mmio,
146 .tf_read = ata_tf_read,
147 .check_status = ata_check_status,
148 .exec_command = pdc_exec_command_mmio,
149 .dev_select = ata_std_dev_select,
151 .phy_reset = pdc_pata_phy_reset,
153 .qc_prep = pdc_qc_prep,
154 .qc_issue = pdc_qc_issue_prot,
155 .eng_timeout = pdc_eng_timeout,
156 .irq_handler = pdc_interrupt,
157 .irq_clear = pdc_irq_clear,
159 .port_start = pdc_port_start,
160 .port_stop = pdc_port_stop,
161 .host_stop = ata_pci_host_stop,
164 static const struct ata_port_info pdc_port_info[] = {
168 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
169 .pio_mask = 0x1f, /* pio0-4 */
170 .mwdma_mask = 0x07, /* mwdma0-2 */
171 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
172 .port_ops = &pdc_sata_ops,
178 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
179 .pio_mask = 0x1f, /* pio0-4 */
180 .mwdma_mask = 0x07, /* mwdma0-2 */
181 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
182 .port_ops = &pdc_sata_ops,
188 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
189 .pio_mask = 0x1f, /* pio0-4 */
190 .mwdma_mask = 0x07, /* mwdma0-2 */
191 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
192 .port_ops = &pdc_pata_ops,
198 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
199 .pio_mask = 0x1f, /* pio0-4 */
200 .mwdma_mask = 0x07, /* mwdma0-2 */
201 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
202 .port_ops = &pdc_sata_ops,
206 static const struct pci_device_id pdc_ata_pci_tbl[] = {
207 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
209 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
211 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
213 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
215 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
217 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
219 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
221 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
223 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
226 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
228 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
230 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
232 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
234 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
236 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
239 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 { } /* terminate list */
248 static struct pci_driver pdc_ata_pci_driver = {
250 .id_table = pdc_ata_pci_tbl,
251 .probe = pdc_ata_init_one,
252 .remove = ata_pci_remove_one,
256 static int pdc_port_start(struct ata_port *ap)
258 struct device *dev = ap->host_set->dev;
259 struct pdc_port_priv *pp;
262 rc = ata_port_start(ap);
266 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
271 memset(pp, 0, sizeof(*pp));
273 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
279 ap->private_data = pp;
291 static void pdc_port_stop(struct ata_port *ap)
293 struct device *dev = ap->host_set->dev;
294 struct pdc_port_priv *pp = ap->private_data;
296 ap->private_data = NULL;
297 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
303 static void pdc_reset_port(struct ata_port *ap)
305 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
309 for (i = 11; i > 0; i--) {
322 readl(mmio); /* flush */
325 static void pdc_sata_phy_reset(struct ata_port *ap)
331 static void pdc_pata_phy_reset(struct ata_port *ap)
333 /* FIXME: add cable detect. Don't assume 40-pin cable */
334 ap->cbl = ATA_CBL_PATA40;
335 ap->udma_mask &= ATA_UDMA_MASK_40C;
342 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
344 if (sc_reg > SCR_CONTROL)
346 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
350 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
353 if (sc_reg > SCR_CONTROL)
355 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
358 static void pdc_qc_prep(struct ata_queued_cmd *qc)
360 struct pdc_port_priv *pp = qc->ap->private_data;
365 switch (qc->tf.protocol) {
370 case ATA_PROT_NODATA:
371 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
372 qc->dev->devno, pp->pkt);
374 if (qc->tf.flags & ATA_TFLAG_LBA48)
375 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
377 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
379 pdc_pkt_footer(&qc->tf, pp->pkt, i);
387 static void pdc_eng_timeout(struct ata_port *ap)
389 struct ata_host_set *host_set = ap->host_set;
391 struct ata_queued_cmd *qc;
396 spin_lock_irqsave(&host_set->lock, flags);
398 qc = ata_qc_from_tag(ap, ap->active_tag);
400 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
405 /* hack alert! We cannot use the supplied completion
406 * function from inside the ->eh_strategy_handler() thread.
407 * libata is the only user of ->eh_strategy_handler() in
408 * any kernel, so the default scsi_done() assumes it is
409 * not being called from the SCSI EH.
411 qc->scsidone = scsi_finish_command;
413 switch (qc->tf.protocol) {
415 case ATA_PROT_NODATA:
416 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
417 drv_stat = ata_wait_idle(ap);
418 qc->err_mask |= __ac_err_mask(drv_stat);
423 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
425 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
426 ap->id, qc->tf.command, drv_stat);
428 qc->err_mask |= ac_err_mask(drv_stat);
434 spin_unlock_irqrestore(&host_set->lock, flags);
438 static inline unsigned int pdc_host_intr( struct ata_port *ap,
439 struct ata_queued_cmd *qc)
441 unsigned int handled = 0;
443 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
446 if (tmp & PDC_ERR_MASK) {
447 qc->err_mask |= AC_ERR_DEV;
451 switch (qc->tf.protocol) {
453 case ATA_PROT_NODATA:
454 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
460 ap->stats.idle_irq++;
467 static void pdc_irq_clear(struct ata_port *ap)
469 struct ata_host_set *host_set = ap->host_set;
470 void __iomem *mmio = host_set->mmio_base;
472 readl(mmio + PDC_INT_SEQMASK);
475 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
477 struct ata_host_set *host_set = dev_instance;
481 unsigned int handled = 0;
482 void __iomem *mmio_base;
486 if (!host_set || !host_set->mmio_base) {
487 VPRINTK("QUICK EXIT\n");
491 mmio_base = host_set->mmio_base;
493 /* reading should also clear interrupts */
494 mask = readl(mmio_base + PDC_INT_SEQMASK);
496 if (mask == 0xffffffff) {
497 VPRINTK("QUICK EXIT 2\n");
500 mask &= 0xffff; /* only 16 tags possible */
502 VPRINTK("QUICK EXIT 3\n");
506 spin_lock(&host_set->lock);
508 writel(mask, mmio_base + PDC_INT_SEQMASK);
510 for (i = 0; i < host_set->n_ports; i++) {
511 VPRINTK("port %u\n", i);
512 ap = host_set->ports[i];
513 tmp = mask & (1 << (i + 1));
515 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
516 struct ata_queued_cmd *qc;
518 qc = ata_qc_from_tag(ap, ap->active_tag);
519 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
520 handled += pdc_host_intr(ap, qc);
524 spin_unlock(&host_set->lock);
528 return IRQ_RETVAL(handled);
531 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
533 struct ata_port *ap = qc->ap;
534 struct pdc_port_priv *pp = ap->private_data;
535 unsigned int port_no = ap->port_no;
536 u8 seq = (u8) (port_no + 1);
538 VPRINTK("ENTER, ap %p\n", ap);
540 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
541 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
544 wmb(); /* flush PRD, pkt writes */
545 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
546 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
549 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
551 switch (qc->tf.protocol) {
553 case ATA_PROT_NODATA:
554 pdc_packet_start(qc);
557 case ATA_PROT_ATAPI_DMA:
565 return ata_qc_issue_prot(qc);
568 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
570 WARN_ON (tf->protocol == ATA_PROT_DMA ||
571 tf->protocol == ATA_PROT_NODATA);
576 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
578 WARN_ON (tf->protocol == ATA_PROT_DMA ||
579 tf->protocol == ATA_PROT_NODATA);
580 ata_exec_command(ap, tf);
584 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
586 port->cmd_addr = base;
587 port->data_addr = base;
589 port->error_addr = base + 0x4;
590 port->nsect_addr = base + 0x8;
591 port->lbal_addr = base + 0xc;
592 port->lbam_addr = base + 0x10;
593 port->lbah_addr = base + 0x14;
594 port->device_addr = base + 0x18;
596 port->status_addr = base + 0x1c;
597 port->altstatus_addr =
598 port->ctl_addr = base + 0x38;
602 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
604 void __iomem *mmio = pe->mmio_base;
608 * Except for the hotplug stuff, this is voodoo from the
609 * Promise driver. Label this entire section
610 * "TODO: figure out why we do this"
613 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
614 tmp = readl(mmio + PDC_FLASH_CTL);
615 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
616 writel(tmp, mmio + PDC_FLASH_CTL);
618 /* clear plug/unplug flags for all ports */
619 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
620 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
622 /* mask plug/unplug ints */
623 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
624 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
626 /* reduce TBG clock to 133 Mhz. */
627 tmp = readl(mmio + PDC_TBG_MODE);
628 tmp &= ~0x30000; /* clear bit 17, 16*/
629 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
630 writel(tmp, mmio + PDC_TBG_MODE);
632 readl(mmio + PDC_TBG_MODE); /* flush */
635 /* adjust slew rate control register. */
636 tmp = readl(mmio + PDC_SLEW_CTL);
637 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
638 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
639 writel(tmp, mmio + PDC_SLEW_CTL);
642 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
644 static int printed_version;
645 struct ata_probe_ent *probe_ent = NULL;
647 void __iomem *mmio_base;
648 unsigned int board_idx = (unsigned int) ent->driver_data;
649 int pci_dev_busy = 0;
652 if (!printed_version++)
653 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
656 * If this driver happens to only be useful on Apple's K2, then
657 * we should check that here as it has a normal Serverworks ID
659 rc = pci_enable_device(pdev);
663 rc = pci_request_regions(pdev, DRV_NAME);
669 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
671 goto err_out_regions;
672 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
674 goto err_out_regions;
676 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
677 if (probe_ent == NULL) {
679 goto err_out_regions;
682 memset(probe_ent, 0, sizeof(*probe_ent));
683 probe_ent->dev = pci_dev_to_dev(pdev);
684 INIT_LIST_HEAD(&probe_ent->node);
686 mmio_base = pci_iomap(pdev, 3, 0);
687 if (mmio_base == NULL) {
689 goto err_out_free_ent;
691 base = (unsigned long) mmio_base;
693 probe_ent->sht = pdc_port_info[board_idx].sht;
694 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
695 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
696 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
697 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
698 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
700 probe_ent->irq = pdev->irq;
701 probe_ent->irq_flags = SA_SHIRQ;
702 probe_ent->mmio_base = mmio_base;
704 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
705 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
707 probe_ent->port[0].scr_addr = base + 0x400;
708 probe_ent->port[1].scr_addr = base + 0x500;
710 /* notice 4-port boards */
713 probe_ent->n_ports = 4;
715 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
716 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
718 probe_ent->port[2].scr_addr = base + 0x600;
719 probe_ent->port[3].scr_addr = base + 0x700;
722 probe_ent->n_ports = 2;
725 probe_ent->n_ports = 2;
728 probe_ent->n_ports = 4;
730 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
731 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
733 probe_ent->port[2].scr_addr = base + 0x600;
734 probe_ent->port[3].scr_addr = base + 0x700;
741 pci_set_master(pdev);
743 /* initialize adapter */
744 pdc_host_init(board_idx, probe_ent);
746 /* FIXME: check ata_device_add return value */
747 ata_device_add(probe_ent);
755 pci_release_regions(pdev);
758 pci_disable_device(pdev);
763 static int __init pdc_ata_init(void)
765 return pci_module_init(&pdc_ata_pci_driver);
769 static void __exit pdc_ata_exit(void)
771 pci_unregister_driver(&pdc_ata_pci_driver);
775 MODULE_AUTHOR("Jeff Garzik");
776 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
777 MODULE_LICENSE("GPL");
778 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
779 MODULE_VERSION(DRV_VERSION);
781 module_init(pdc_ata_init);
782 module_exit(pdc_ata_exit);