2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
9 * The contents of this file are subject to the Open
10 * Software License version 1.1 that can be found at
11 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
14 * Alternatively, the contents of this file may be used under the terms
15 * of the GNU General Public License version 2 (the "GPL") as distributed
16 * in the kernel source COPYING file, in which case the provisions of
17 * the GPL are applicable instead of the above. If you wish to allow
18 * the use of your version of this file only under the terms of the
19 * GPL and not to allow others to use your version of this file under
20 * the OSL, indicate your decision by deleting the provisions above and
21 * replace them with the notice and other provisions required by the GPL.
22 * If you do not delete the provisions above, a recipient may use your
23 * version of this file under either the OSL or the GPL.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
36 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #define DRV_NAME "sata_qstor"
41 #define DRV_VERSION "0.03"
45 QS_MAX_PRD = LIBATA_MAX_PRD,
47 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
48 QS_PRD_BYTES = QS_MAX_PRD * 16,
49 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
51 QS_DMA_BOUNDARY = ~0UL,
53 /* global register offsets */
54 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
55 QS_HID_HPHY = 0x0004, /* host physical interface info */
56 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
57 QS_HST_SFF = 0x0100, /* host status fifo offset */
58 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60 /* global control bits */
61 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
62 QS_CNFG3_GSRST = 0x01, /* global chip reset */
63 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65 /* per-channel register offsets */
66 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
67 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
68 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
69 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
70 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
71 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
72 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
73 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
74 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76 /* channel control bits */
77 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
78 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
79 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
80 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
81 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83 /* pkt sub-field headers */
84 QS_HCB_HDR = 0x01, /* Host Control Block header */
85 QS_DCB_HDR = 0x02, /* Device Control Block header */
87 /* pkt HCB flag bits */
88 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
89 QS_HF_DAT = (1 << 3), /* DATa pkt */
90 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
91 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93 /* pkt DCB flag bits */
94 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
95 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
98 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
101 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
103 struct qs_port_priv {
109 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
110 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
111 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
112 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
113 static int qs_port_start(struct ata_port *ap);
114 static void qs_host_stop(struct ata_host_set *host_set);
115 static void qs_port_stop(struct ata_port *ap);
116 static void qs_phy_reset(struct ata_port *ap);
117 static void qs_qc_prep(struct ata_queued_cmd *qc);
118 static int qs_qc_issue(struct ata_queued_cmd *qc);
119 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
120 static void qs_bmdma_stop(struct ata_port *ap);
121 static u8 qs_bmdma_status(struct ata_port *ap);
122 static void qs_irq_clear(struct ata_port *ap);
124 static Scsi_Host_Template qs_ata_sht = {
125 .module = THIS_MODULE,
127 .ioctl = ata_scsi_ioctl,
128 .queuecommand = ata_scsi_queuecmd,
129 .eh_strategy_handler = ata_scsi_error,
130 .can_queue = ATA_DEF_QUEUE,
131 .this_id = ATA_SHT_THIS_ID,
132 .sg_tablesize = QS_MAX_PRD,
133 .max_sectors = ATA_MAX_SECTORS,
134 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
135 .emulated = ATA_SHT_EMULATED,
136 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
137 .use_clustering = ENABLE_CLUSTERING,
138 .proc_name = DRV_NAME,
139 .dma_boundary = QS_DMA_BOUNDARY,
140 .slave_configure = ata_scsi_slave_config,
141 .bios_param = ata_std_bios_param,
144 static struct ata_port_operations qs_ata_ops = {
145 .port_disable = ata_port_disable,
146 .tf_load = ata_tf_load,
147 .tf_read = ata_tf_read,
148 .check_status = ata_check_status,
149 .check_atapi_dma = qs_check_atapi_dma,
150 .exec_command = ata_exec_command,
151 .dev_select = ata_std_dev_select,
152 .phy_reset = qs_phy_reset,
153 .qc_prep = qs_qc_prep,
154 .qc_issue = qs_qc_issue,
155 .eng_timeout = ata_eng_timeout,
156 .irq_handler = qs_intr,
157 .irq_clear = qs_irq_clear,
158 .scr_read = qs_scr_read,
159 .scr_write = qs_scr_write,
160 .port_start = qs_port_start,
161 .port_stop = qs_port_stop,
162 .host_stop = qs_host_stop,
163 .bmdma_stop = qs_bmdma_stop,
164 .bmdma_status = qs_bmdma_status,
167 static struct ata_port_info qs_port_info[] = {
171 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
172 ATA_FLAG_SATA_RESET |
173 //FIXME ATA_FLAG_SRST |
175 .pio_mask = 0x10, /* pio4 */
176 .udma_mask = 0x7f, /* udma0-6 */
177 .port_ops = &qs_ata_ops,
181 static struct pci_device_id qs_ata_pci_tbl[] = {
182 { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
185 { } /* terminate list */
188 static struct pci_driver qs_ata_pci_driver = {
190 .id_table = qs_ata_pci_tbl,
191 .probe = qs_ata_init_one,
192 .remove = ata_pci_remove_one,
195 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
197 return 1; /* ATAPI DMA not supported */
200 static void qs_bmdma_stop(struct ata_port *ap)
205 static u8 qs_bmdma_status(struct ata_port *ap)
210 static void qs_irq_clear(struct ata_port *ap)
215 static void qs_enter_reg_mode(struct ata_port *ap)
217 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
219 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
220 readb(chan + QS_CCT_CTR0); /* flush */
223 static void qs_phy_reset(struct ata_port *ap)
225 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
226 struct qs_port_priv *pp = ap->private_data;
228 pp->state = qs_state_idle;
229 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
230 qs_enter_reg_mode(ap);
234 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
236 if (sc_reg > SCR_CONTROL)
238 return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
241 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
243 if (sc_reg > SCR_CONTROL)
245 writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
248 static void qs_fill_sg(struct ata_queued_cmd *qc)
250 struct scatterlist *sg = qc->sg;
251 struct ata_port *ap = qc->ap;
252 struct qs_port_priv *pp = ap->private_data;
254 u8 *prd = pp->pkt + QS_CPB_BYTES;
257 assert(qc->n_elem > 0);
259 for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
263 addr = sg_dma_address(sg);
264 *(u64 *)prd = cpu_to_le64(addr);
267 len = sg_dma_len(sg);
268 *(u32 *)prd = cpu_to_le32(len);
271 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
272 (unsigned long long)addr, len);
276 static void qs_qc_prep(struct ata_queued_cmd *qc)
278 struct qs_port_priv *pp = qc->ap->private_data;
279 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
280 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
285 qs_enter_reg_mode(qc->ap);
286 if (qc->tf.protocol != ATA_PROT_DMA) {
293 if ((qc->tf.flags & ATA_TFLAG_WRITE))
294 hflags |= QS_HF_DIRO;
295 if ((qc->tf.flags & ATA_TFLAG_LBA48))
296 dflags |= QS_DF_ELBA;
298 /* host control block (HCB) */
299 buf[ 0] = QS_HCB_HDR;
301 *(u32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
302 *(u32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem);
303 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
304 *(u64 *)(&buf[16]) = cpu_to_le64(addr);
306 /* device control block (DCB) */
307 buf[24] = QS_DCB_HDR;
310 /* frame information structure (FIS) */
311 ata_tf_to_fis(&qc->tf, &buf[32], 0);
314 static inline void qs_packet_start(struct ata_queued_cmd *qc)
316 struct ata_port *ap = qc->ap;
317 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
319 VPRINTK("ENTER, ap %p\n", ap);
321 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
322 wmb(); /* flush PRDs and pkt to memory */
323 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
324 readl(chan + QS_CCT_CFF); /* flush */
327 static int qs_qc_issue(struct ata_queued_cmd *qc)
329 struct qs_port_priv *pp = qc->ap->private_data;
331 switch (qc->tf.protocol) {
334 pp->state = qs_state_pkt;
338 case ATA_PROT_ATAPI_DMA:
346 pp->state = qs_state_mmio;
347 return ata_qc_issue_prot(qc);
350 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
352 unsigned int handled = 0;
354 u8 __iomem *mmio_base = host_set->mmio_base;
357 u32 sff0 = readl(mmio_base + QS_HST_SFF);
358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
359 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
360 sFFE = sff1 >> 31; /* empty flag */
363 u8 sDST = sff0 >> 16; /* dev status */
364 u8 sHST = sff1 & 0x3f; /* host status */
365 unsigned int port_no = (sff1 >> 8) & 0x03;
366 struct ata_port *ap = host_set->ports[port_no];
368 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
369 sff1, sff0, port_no, sHST, sDST);
371 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
372 struct ata_queued_cmd *qc;
373 struct qs_port_priv *pp = ap->private_data;
374 if (!pp || pp->state != qs_state_pkt)
376 qc = ata_qc_from_tag(ap, ap->active_tag);
377 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
379 case 0: /* sucessful CPB */
380 case 3: /* device error */
381 pp->state = qs_state_idle;
382 qs_enter_reg_mode(qc->ap);
383 ata_qc_complete(qc, sDST);
395 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
397 unsigned int handled = 0, port_no;
399 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
401 ap = host_set->ports[port_no];
402 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
403 struct ata_queued_cmd *qc;
404 struct qs_port_priv *pp = ap->private_data;
405 if (!pp || pp->state != qs_state_mmio)
407 qc = ata_qc_from_tag(ap, ap->active_tag);
408 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
410 /* check main status, clearing INTRQ */
411 u8 status = ata_chk_status(ap);
412 if ((status & ATA_BUSY))
414 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
415 ap->id, qc->tf.protocol, status);
417 /* complete taskfile transaction */
418 pp->state = qs_state_idle;
419 ata_qc_complete(qc, status);
427 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
429 struct ata_host_set *host_set = dev_instance;
430 unsigned int handled = 0;
434 spin_lock(&host_set->lock);
435 handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
436 spin_unlock(&host_set->lock);
440 return IRQ_RETVAL(handled);
443 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
446 port->data_addr = base + 0x400;
448 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
449 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
450 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
451 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
452 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
453 port->device_addr = base + 0x430;
455 port->command_addr = base + 0x438;
456 port->altstatus_addr =
457 port->ctl_addr = base + 0x440;
458 port->scr_addr = base + 0xc00;
461 static int qs_port_start(struct ata_port *ap)
463 struct device *dev = ap->host_set->dev;
464 struct qs_port_priv *pp;
465 void __iomem *mmio_base = ap->host_set->mmio_base;
466 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
470 rc = ata_port_start(ap);
473 qs_enter_reg_mode(ap);
474 pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
479 pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
485 memset(pp->pkt, 0, QS_PKT_BYTES);
486 ap->private_data = pp;
488 addr = (u64)pp->pkt_dma;
489 writel((u32) addr, chan + QS_CCF_CPBA);
490 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
500 static void qs_port_stop(struct ata_port *ap)
502 struct device *dev = ap->host_set->dev;
503 struct qs_port_priv *pp = ap->private_data;
506 ap->private_data = NULL;
508 dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
515 static void qs_host_stop(struct ata_host_set *host_set)
517 void __iomem *mmio_base = host_set->mmio_base;
519 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
520 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
523 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
525 void __iomem *mmio_base = pe->mmio_base;
526 unsigned int port_no;
528 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
529 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
531 /* reset each channel in turn */
532 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
533 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
534 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
535 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
536 readb(chan + QS_CCT_CTR0); /* flush */
538 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
540 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
541 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
542 /* set FIFO depths to same settings as Windows driver */
543 writew(32, chan + QS_CFC_HUFT);
544 writew(32, chan + QS_CFC_HDFT);
545 writew(10, chan + QS_CFC_DUFT);
546 writew( 8, chan + QS_CFC_DDFT);
547 /* set CPB size in bytes, as a power of two */
548 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
550 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
554 * The QStor understands 64-bit buses, and uses 64-bit fields
555 * for DMA pointers regardless of bus width. We just have to
556 * make sure our DMA masks are set appropriately for whatever
557 * bridge lies between us and the QStor, and then the DMA mapping
558 * code will ensure we only ever "see" appropriate buffer addresses.
559 * If we're 32-bit limited somewhere, then our 64-bit fields will
560 * just end up with zeros in the upper 32-bits, without any special
561 * logic required outside of this routine (below).
563 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
565 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
566 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
568 if (have_64bit_bus &&
569 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
570 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
572 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
574 printk(KERN_ERR DRV_NAME
575 "(%s): 64-bit DMA enable failed\n",
581 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
583 printk(KERN_ERR DRV_NAME
584 "(%s): 32-bit DMA enable failed\n",
588 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
590 printk(KERN_ERR DRV_NAME
591 "(%s): 32-bit consistent DMA enable failed\n",
599 static int qs_ata_init_one(struct pci_dev *pdev,
600 const struct pci_device_id *ent)
602 static int printed_version;
603 struct ata_probe_ent *probe_ent = NULL;
604 void __iomem *mmio_base;
605 unsigned int board_idx = (unsigned int) ent->driver_data;
608 if (!printed_version++)
609 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
611 rc = pci_enable_device(pdev);
615 rc = pci_request_regions(pdev, DRV_NAME);
619 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
621 goto err_out_regions;
624 mmio_base = ioremap(pci_resource_start(pdev, 4),
625 pci_resource_len(pdev, 4));
626 if (mmio_base == NULL) {
628 goto err_out_regions;
631 rc = qs_set_dma_masks(pdev, mmio_base);
633 goto err_out_iounmap;
635 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
636 if (probe_ent == NULL) {
638 goto err_out_iounmap;
641 memset(probe_ent, 0, sizeof(*probe_ent));
642 probe_ent->dev = pci_dev_to_dev(pdev);
643 INIT_LIST_HEAD(&probe_ent->node);
645 probe_ent->sht = qs_port_info[board_idx].sht;
646 probe_ent->host_flags = qs_port_info[board_idx].host_flags;
647 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
648 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
649 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
650 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
652 probe_ent->irq = pdev->irq;
653 probe_ent->irq_flags = SA_SHIRQ;
654 probe_ent->mmio_base = mmio_base;
655 probe_ent->n_ports = QS_PORTS;
657 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
658 unsigned long chan = (unsigned long)mmio_base +
660 qs_ata_setup_port(&probe_ent->port[port_no], chan);
663 pci_set_master(pdev);
665 /* initialize adapter */
666 qs_host_init(board_idx, probe_ent);
668 rc = ata_device_add(probe_ent);
671 goto err_out_iounmap;
677 pci_release_regions(pdev);
679 pci_disable_device(pdev);
683 static int __init qs_ata_init(void)
685 return pci_module_init(&qs_ata_pci_driver);
688 static void __exit qs_ata_exit(void)
690 pci_unregister_driver(&qs_ata_pci_driver);
693 MODULE_AUTHOR("Mark Lord");
694 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
695 MODULE_LICENSE("GPL");
696 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
697 MODULE_VERSION(DRV_VERSION);
699 module_init(qs_ata_init);
700 module_exit(qs_ata_exit);