2 * ata_sil.c - Silicon Image SATA
4 * Copyright 2003 Red Hat, Inc.
5 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
34 #include <linux/libata.h>
36 #define DRV_NAME "sata_sil"
37 #define DRV_VERSION "0.54"
44 SIL_MASK_IDE0_INT = (1 << 22),
45 SIL_MASK_IDE1_INT = (1 << 23),
46 SIL_MASK_IDE2_INT = (1 << 24),
47 SIL_MASK_IDE3_INT = (1 << 25),
48 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
49 SIL_MASK_4PORT = SIL_MASK_2PORT |
50 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
52 SIL_IDE2_BMDMA = 0x200,
54 SIL_INTR_STEERING = (1 << 1),
55 SIL_QUIRK_MOD15WRITE = (1 << 0),
56 SIL_QUIRK_UDMA5MAX = (1 << 1),
59 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
60 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
61 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
62 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
63 static void sil_post_set_mode (struct ata_port *ap);
65 static struct pci_device_id sil_pci_tbl[] = {
66 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
67 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
68 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
69 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
70 { } /* terminate list */
74 /* TODO firmware versions should be added - eric */
75 struct sil_drivelist {
78 } sil_blacklist [] = {
79 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
80 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
81 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
82 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
83 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
84 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
85 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
86 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
87 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
88 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
89 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
90 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
94 static struct pci_driver sil_pci_driver = {
96 .id_table = sil_pci_tbl,
97 .probe = sil_init_one,
98 .remove = ata_pci_remove_one,
101 static Scsi_Host_Template sil_sht = {
102 .module = THIS_MODULE,
104 .queuecommand = ata_scsi_queuecmd,
105 .eh_strategy_handler = ata_scsi_error,
106 .can_queue = ATA_DEF_QUEUE,
107 .this_id = ATA_SHT_THIS_ID,
108 .sg_tablesize = LIBATA_MAX_PRD,
109 .max_sectors = ATA_MAX_SECTORS,
110 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
111 .emulated = ATA_SHT_EMULATED,
112 .use_clustering = ATA_SHT_USE_CLUSTERING,
113 .proc_name = DRV_NAME,
114 .dma_boundary = ATA_DMA_BOUNDARY,
115 .slave_configure = ata_scsi_slave_config,
116 .bios_param = ata_std_bios_param,
119 static struct ata_port_operations sil_ops = {
120 .port_disable = ata_port_disable,
121 .dev_config = sil_dev_config,
122 .tf_load = ata_tf_load_mmio,
123 .tf_read = ata_tf_read_mmio,
124 .check_status = ata_check_status_mmio,
125 .exec_command = ata_exec_command_mmio,
126 .phy_reset = sata_phy_reset,
127 .post_set_mode = sil_post_set_mode,
128 .bmdma_start = ata_bmdma_start_mmio,
129 .fill_sg = ata_fill_sg,
130 .eng_timeout = ata_eng_timeout,
131 .irq_handler = ata_interrupt,
132 .scr_read = sil_scr_read,
133 .scr_write = sil_scr_write,
134 .port_start = ata_port_start,
135 .port_stop = ata_port_stop,
138 static struct ata_port_info sil_port_info[] = {
142 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
143 ATA_FLAG_SRST | ATA_FLAG_MMIO,
144 .pio_mask = 0x03, /* pio3-4 */
145 .udma_mask = 0x3f, /* udma0-5 */
146 .port_ops = &sil_ops,
150 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
151 ATA_FLAG_SRST | ATA_FLAG_MMIO,
152 .pio_mask = 0x03, /* pio3-4 */
153 .udma_mask = 0x3f, /* udma0-5 */
154 .port_ops = &sil_ops,
158 /* per-port register offsets */
159 /* TODO: we can probably calculate rather than use a table */
160 static const struct {
161 unsigned long tf; /* ATA taskfile register block */
162 unsigned long ctl; /* ATA control/altstatus register block */
163 unsigned long bmdma; /* DMA register block */
164 unsigned long scr; /* SATA control register block */
165 unsigned long sien; /* SATA Interrupt Enable register */
166 unsigned long xfer_mode;/* data transfer mode register */
169 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
170 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
171 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
172 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
176 MODULE_AUTHOR("Jeff Garzik");
177 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
178 MODULE_LICENSE("GPL");
179 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
181 static void sil_post_set_mode (struct ata_port *ap)
183 struct ata_host_set *host_set = ap->host_set;
184 struct ata_device *dev;
185 void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
186 u32 tmp, dev_mode[2];
189 for (i = 0; i < 2; i++) {
190 dev = &ap->device[i];
191 if (!ata_dev_present(dev))
192 dev_mode[i] = 0; /* PIO0/1/2 */
193 else if (dev->flags & ATA_DFLAG_PIO)
194 dev_mode[i] = 1; /* PIO3/4 */
196 dev_mode[i] = 3; /* UDMA */
197 /* value 2 indicates MDMA */
201 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
203 tmp |= (dev_mode[1] << 4);
205 readl(addr); /* flush */
208 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
210 unsigned long offset = ap->ioaddr.scr_addr;
227 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
229 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
235 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
237 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
243 * sil_dev_config - Apply device/host-specific errata fixups
244 * @ap: Port containing device to be examined
245 * @dev: Device to be examined
247 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
248 * device is known to be present, this function is called.
249 * We apply two errata fixups which are specific to Silicon Image,
250 * a Seagate and a Maxtor fixup.
252 * For certain Seagate devices, we must limit the maximum sectors
255 * For certain Maxtor devices, we must not program the drive
258 * Both fixups are unfairly pessimistic. As soon as I get more
259 * information on these errata, I will create a more exhaustive
260 * list, and apply the fixups to only the specific
261 * devices/hosts/firmwares that need it.
263 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
264 * The Maxtor quirk is in the blacklist, but I'm keeping the original
265 * pessimistic fix for the following reasons:
266 * - There seems to be less info on it, only one device gleaned off the
267 * Windows driver, maybe only one is affected. More info would be greatly
269 * - But then again UDMA5 is hardly anything to complain about
271 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
273 unsigned int n, quirks = 0;
274 const char *s = &dev->product[0];
275 unsigned int len = strnlen(s, sizeof(dev->product));
277 /* ATAPI specifies that empty space is blank-filled; remove blanks */
278 while ((len > 0) && (s[len - 1] == ' '))
281 for (n = 0; sil_blacklist[n].product; n++)
282 if (!memcmp(sil_blacklist[n].product, s,
283 strlen(sil_blacklist[n].product))) {
284 quirks = sil_blacklist[n].quirk;
288 /* limit requests to 15 sectors */
289 if (quirks & SIL_QUIRK_MOD15WRITE) {
290 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
292 ap->host->max_sectors = 15;
293 ap->host->hostt->max_sectors = 15;
298 if (quirks & SIL_QUIRK_UDMA5MAX) {
299 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
300 ap->id, dev->devno, s);
301 ap->udma_mask &= ATA_UDMA5;
306 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
308 static int printed_version;
309 struct ata_probe_ent *probe_ent = NULL;
316 if (!printed_version++)
317 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
320 * If this driver happens to only be useful on Apple's K2, then
321 * we should check that here as it has a normal Serverworks ID
323 rc = pci_enable_device(pdev);
327 rc = pci_request_regions(pdev, DRV_NAME);
331 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
333 goto err_out_regions;
334 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
336 goto err_out_regions;
338 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
339 if (probe_ent == NULL) {
341 goto err_out_regions;
344 memset(probe_ent, 0, sizeof(*probe_ent));
345 INIT_LIST_HEAD(&probe_ent->node);
346 probe_ent->pdev = pdev;
347 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
348 probe_ent->sht = sil_port_info[ent->driver_data].sht;
349 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
350 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
351 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
352 probe_ent->irq = pdev->irq;
353 probe_ent->irq_flags = SA_SHIRQ;
354 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
356 mmio_base = ioremap(pci_resource_start(pdev, 5),
357 pci_resource_len(pdev, 5));
358 if (mmio_base == NULL) {
360 goto err_out_free_ent;
363 probe_ent->mmio_base = mmio_base;
365 base = (unsigned long) mmio_base;
367 for (i = 0; i < probe_ent->n_ports; i++) {
368 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
369 probe_ent->port[i].altstatus_addr =
370 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
371 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
372 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
373 ata_std_ports(&probe_ent->port[i]);
376 if (ent->driver_data == sil_3114) {
377 irq_mask = SIL_MASK_4PORT;
379 /* flip the magic "make 4 ports work" bit */
380 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
381 if ((tmp & SIL_INTR_STEERING) == 0)
382 writel(tmp | SIL_INTR_STEERING,
383 mmio_base + SIL_IDE2_BMDMA);
386 irq_mask = SIL_MASK_2PORT;
389 /* make sure IDE0/1/2/3 interrupts are not masked */
390 tmp = readl(mmio_base + SIL_SYSCFG);
391 if (tmp & irq_mask) {
393 writel(tmp, mmio_base + SIL_SYSCFG);
394 readl(mmio_base + SIL_SYSCFG); /* flush */
397 /* mask all SATA phy-related interrupts */
398 /* TODO: unmask bit 6 (SError N bit) for hotplug */
399 for (i = 0; i < probe_ent->n_ports; i++)
400 writel(0, mmio_base + sil_port[i].sien);
402 pci_set_master(pdev);
404 /* FIXME: check ata_device_add return value */
405 ata_device_add(probe_ent);
413 pci_release_regions(pdev);
415 pci_disable_device(pdev);
419 static int __init sil_init(void)
421 return pci_module_init(&sil_pci_driver);
424 static void __exit sil_exit(void)
426 pci_unregister_driver(&sil_pci_driver);
430 module_init(sil_init);
431 module_exit(sil_exit);