2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004 Uwe Koziolek
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/config.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #define DRV_NAME "sata_sis"
41 #define DRV_VERSION "0.10"
47 /* PCI configuration registers */
48 SIS_GENCTL = 0x54, /* IDE General Control register */
49 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
50 SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
53 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
55 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
58 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
59 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
60 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
62 static struct pci_device_id sis_pci_tbl[] = {
63 { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
64 { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
65 { } /* terminate list */
69 static struct pci_driver sis_pci_driver = {
71 .id_table = sis_pci_tbl,
72 .probe = sis_init_one,
73 .remove = ata_pci_remove_one,
76 static Scsi_Host_Template sis_sht = {
77 .module = THIS_MODULE,
79 .queuecommand = ata_scsi_queuecmd,
80 .eh_strategy_handler = ata_scsi_error,
81 .can_queue = ATA_DEF_QUEUE,
82 .this_id = ATA_SHT_THIS_ID,
83 .sg_tablesize = ATA_MAX_PRD,
84 .max_sectors = ATA_MAX_SECTORS,
85 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
86 .emulated = ATA_SHT_EMULATED,
87 .use_clustering = ATA_SHT_USE_CLUSTERING,
88 .proc_name = DRV_NAME,
89 .dma_boundary = ATA_DMA_BOUNDARY,
90 .slave_configure = ata_scsi_slave_config,
91 .bios_param = ata_std_bios_param,
94 static struct ata_port_operations sis_ops = {
95 .port_disable = ata_port_disable,
96 .tf_load = ata_tf_load_pio,
97 .tf_read = ata_tf_read_pio,
98 .check_status = ata_check_status_pio,
99 .exec_command = ata_exec_command_pio,
100 .phy_reset = sata_phy_reset,
101 .bmdma_setup = ata_bmdma_setup_pio,
102 .bmdma_start = ata_bmdma_start_pio,
103 .fill_sg = ata_fill_sg,
104 .eng_timeout = ata_eng_timeout,
105 .irq_handler = ata_interrupt,
106 .scr_read = sis_scr_read,
107 .scr_write = sis_scr_write,
108 .port_start = ata_port_start,
109 .port_stop = ata_port_stop,
113 MODULE_AUTHOR("Uwe Koziolek");
114 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
115 MODULE_LICENSE("GPL");
116 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
118 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
120 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
123 addr += SIS_SATA1_OFS;
127 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
129 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
132 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
134 pci_read_config_dword(ap->host_set->pdev, cfg_addr, &val);
138 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
140 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
142 if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
144 pci_write_config_dword(ap->host_set->pdev, cfg_addr, val);
147 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
149 if (sc_reg > SCR_CONTROL)
152 if (ap->flags & SIS_FLAG_CFGSCR)
153 return sis_scr_cfg_read(ap, sc_reg);
154 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
157 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
159 if (sc_reg > SCR_CONTROL)
162 if (ap->flags & SIS_FLAG_CFGSCR)
163 sis_scr_cfg_write(ap, sc_reg, val);
165 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
168 /* move to PCI layer, integrate w/ MSI stuff */
169 static void pci_enable_intx(struct pci_dev *pdev)
173 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
174 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
175 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
176 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
180 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
182 struct ata_probe_ent *probe_ent = NULL;
186 rc = pci_enable_device(pdev);
190 rc = pci_request_regions(pdev, DRV_NAME);
194 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
196 goto err_out_regions;
197 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
199 goto err_out_regions;
201 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
204 goto err_out_regions;
207 memset(probe_ent, 0, sizeof(*probe_ent));
208 probe_ent->pdev = pdev;
209 INIT_LIST_HEAD(&probe_ent->node);
211 probe_ent->sht = &sis_sht;
212 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
215 /* check and see if the SCRs are in IO space or PCI cfg space */
216 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
217 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
218 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
220 /* if hardware thinks SCRs are in IO space, but there are
221 * no IO resources assigned, change to PCI cfg space.
223 if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
224 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
225 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
226 genctl &= ~GENCTL_IOMAPPED_SCR;
227 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
228 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
231 probe_ent->pio_mask = 0x03;
232 probe_ent->udma_mask = 0x7f;
233 probe_ent->port_ops = &sis_ops;
235 probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
236 ata_std_ports(&probe_ent->port[0]);
237 probe_ent->port[0].ctl_addr =
238 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
239 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4);
240 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR))
241 probe_ent->port[0].scr_addr =
242 pci_resource_start(pdev, SIS_SCR_PCI_BAR);
244 probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
245 ata_std_ports(&probe_ent->port[1]);
246 probe_ent->port[1].ctl_addr =
247 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
248 probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8;
249 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR))
250 probe_ent->port[1].scr_addr =
251 pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
253 probe_ent->n_ports = 2;
254 probe_ent->irq = pdev->irq;
255 probe_ent->irq_flags = SA_SHIRQ;
257 pci_set_master(pdev);
258 pci_enable_intx(pdev);
260 /* FIXME: check ata_device_add return value */
261 ata_device_add(probe_ent);
267 pci_release_regions(pdev);
270 pci_disable_device(pdev);
275 static int __init sis_init(void)
277 return pci_module_init(&sis_pci_driver);
280 static void __exit sis_exit(void)
282 pci_unregister_driver(&sis_pci_driver);
286 module_init(sis_init);
287 module_exit(sis_exit);