2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Copyright 2004 Uwe Koziolek
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
34 #include <linux/libata.h>
36 #define DRV_NAME "sata_sis"
37 #define DRV_VERSION "0.10"
43 /* PCI configuration registers */
44 SIS_GENCTL = 0x54, /* IDE General Control register */
45 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
46 SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
49 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
51 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
54 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
55 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
56 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
58 static struct pci_device_id sis_pci_tbl[] = {
59 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
60 { } /* terminate list */
64 static struct pci_driver sis_pci_driver = {
66 .id_table = sis_pci_tbl,
67 .probe = sis_init_one,
68 .remove = ata_pci_remove_one,
71 static Scsi_Host_Template sis_sht = {
72 .module = THIS_MODULE,
74 .queuecommand = ata_scsi_queuecmd,
75 .eh_strategy_handler = ata_scsi_error,
76 .can_queue = ATA_DEF_QUEUE,
77 .this_id = ATA_SHT_THIS_ID,
78 .sg_tablesize = ATA_MAX_PRD,
79 .max_sectors = ATA_MAX_SECTORS,
80 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
81 .emulated = ATA_SHT_EMULATED,
82 .use_clustering = ATA_SHT_USE_CLUSTERING,
83 .proc_name = DRV_NAME,
84 .dma_boundary = ATA_DMA_BOUNDARY,
85 .slave_configure = ata_scsi_slave_config,
86 .bios_param = ata_std_bios_param,
89 static struct ata_port_operations sis_ops = {
90 .port_disable = ata_port_disable,
91 .tf_load = ata_tf_load_pio,
92 .tf_read = ata_tf_read_pio,
93 .check_status = ata_check_status_pio,
94 .exec_command = ata_exec_command_pio,
95 .phy_reset = sata_phy_reset,
96 .bmdma_start = ata_bmdma_start_pio,
97 .fill_sg = ata_fill_sg,
98 .eng_timeout = ata_eng_timeout,
99 .irq_handler = ata_interrupt,
100 .scr_read = sis_scr_read,
101 .scr_write = sis_scr_write,
102 .port_start = ata_port_start,
103 .port_stop = ata_port_stop,
107 MODULE_AUTHOR("Uwe Koziolek");
108 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
109 MODULE_LICENSE("GPL");
110 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
112 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
114 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
117 addr += SIS_SATA1_OFS;
121 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
123 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
126 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
128 pci_read_config_dword(ap->host_set->pdev, cfg_addr, &val);
132 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
134 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
136 if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
138 pci_write_config_dword(ap->host_set->pdev, cfg_addr, val);
141 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
143 if (sc_reg > SCR_CONTROL)
146 if (ap->flags & SIS_FLAG_CFGSCR)
147 return sis_scr_cfg_read(ap, sc_reg);
148 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
151 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
153 if (sc_reg > SCR_CONTROL)
156 if (ap->flags & SIS_FLAG_CFGSCR)
157 sis_scr_cfg_write(ap, sc_reg, val);
159 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
162 /* move to PCI layer, integrate w/ MSI stuff */
163 static void pci_enable_intx(struct pci_dev *pdev)
167 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
168 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
169 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
170 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
174 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
176 struct ata_probe_ent *probe_ent = NULL;
180 rc = pci_enable_device(pdev);
184 rc = pci_request_regions(pdev, DRV_NAME);
188 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
190 goto err_out_regions;
191 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
193 goto err_out_regions;
195 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
198 goto err_out_regions;
201 memset(probe_ent, 0, sizeof(*probe_ent));
202 probe_ent->pdev = pdev;
203 INIT_LIST_HEAD(&probe_ent->node);
205 probe_ent->sht = &sis_sht;
206 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
209 /* check and see if the SCRs are in IO space or PCI cfg space */
210 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
211 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
212 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
214 /* if hardware thinks SCRs are in IO space, but there are
215 * no IO resources assigned, change to PCI cfg space.
217 if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
218 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
219 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
220 genctl &= ~GENCTL_IOMAPPED_SCR;
221 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
222 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
225 probe_ent->pio_mask = 0x03;
226 probe_ent->udma_mask = 0x7f;
227 probe_ent->port_ops = &sis_ops;
229 probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
230 ata_std_ports(&probe_ent->port[0]);
231 probe_ent->port[0].ctl_addr =
232 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
233 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4);
234 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR))
235 probe_ent->port[0].scr_addr =
236 pci_resource_start(pdev, SIS_SCR_PCI_BAR);
238 probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
239 ata_std_ports(&probe_ent->port[1]);
240 probe_ent->port[1].ctl_addr =
241 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
242 probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8;
243 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR))
244 probe_ent->port[1].scr_addr =
245 pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
247 probe_ent->n_ports = 2;
248 probe_ent->irq = pdev->irq;
249 probe_ent->irq_flags = SA_SHIRQ;
251 pci_set_master(pdev);
252 pci_enable_intx(pdev);
254 /* FIXME: check ata_device_add return value */
255 ata_device_add(probe_ent);
261 pci_release_regions(pdev);
264 pci_disable_device(pdev);
269 static int __init sis_init(void)
271 return pci_module_init(&sis_pci_driver);
274 static void __exit sis_exit(void)
276 pci_unregister_driver(&sis_pci_driver);
280 module_init(sis_init);
281 module_exit(sis_exit);