2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
6 * Bits from Jeff Garzik, Copyright RedHat, Inc.
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/blkdev.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
22 #include <linux/libata.h>
24 #define DRV_NAME "sata_vsc"
25 #define DRV_VERSION "0.01"
27 /* Interrupt register offsets (from chip base address) */
28 #define VSC_SATA_INT_STAT_OFFSET 0x00
29 #define VSC_SATA_INT_MASK_OFFSET 0x04
31 /* Taskfile registers offsets */
32 #define VSC_SATA_TF_CMD_OFFSET 0x00
33 #define VSC_SATA_TF_DATA_OFFSET 0x00
34 #define VSC_SATA_TF_ERROR_OFFSET 0x04
35 #define VSC_SATA_TF_FEATURE_OFFSET 0x06
36 #define VSC_SATA_TF_NSECT_OFFSET 0x08
37 #define VSC_SATA_TF_LBAL_OFFSET 0x0c
38 #define VSC_SATA_TF_LBAM_OFFSET 0x10
39 #define VSC_SATA_TF_LBAH_OFFSET 0x14
40 #define VSC_SATA_TF_DEVICE_OFFSET 0x18
41 #define VSC_SATA_TF_STATUS_OFFSET 0x1c
42 #define VSC_SATA_TF_COMMAND_OFFSET 0x1d
43 #define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
44 #define VSC_SATA_TF_CTL_OFFSET 0x29
47 #define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
48 #define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
49 #define VSC_SATA_DMA_CMD_OFFSET 0x70
52 #define VSC_SATA_SCR_STATUS_OFFSET 0x100
53 #define VSC_SATA_SCR_ERROR_OFFSET 0x104
54 #define VSC_SATA_SCR_CONTROL_OFFSET 0x108
57 #define VSC_SATA_PORT_OFFSET 0x200
60 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
62 if (sc_reg > SCR_CONTROL)
64 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
68 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
71 if (sc_reg > SCR_CONTROL)
73 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
77 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
79 unsigned long mask_addr;
82 mask_addr = (unsigned long) ap->host_set->mmio_base +
83 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
84 mask = readb(mask_addr);
89 writeb(mask, mask_addr);
93 static void vsc_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
95 struct ata_ioports *ioaddr = &ap->ioaddr;
96 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
99 * The only thing the ctl register is used for is SRST.
100 * That is not enabled or disabled via tf_load.
101 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
103 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
104 ap->last_ctl = tf->ctl;
105 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
107 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
108 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
109 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
110 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
111 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
112 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
113 } else if (is_addr) {
114 writew(tf->feature, ioaddr->feature_addr);
115 writew(tf->nsect, ioaddr->nsect_addr);
116 writew(tf->lbal, ioaddr->lbal_addr);
117 writew(tf->lbam, ioaddr->lbam_addr);
118 writew(tf->lbah, ioaddr->lbah_addr);
121 if (tf->flags & ATA_TFLAG_DEVICE)
122 writeb(tf->device, ioaddr->device_addr);
128 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
130 struct ata_ioports *ioaddr = &ap->ioaddr;
131 u16 nsect, lbal, lbam, lbah;
133 nsect = tf->nsect = readw(ioaddr->nsect_addr);
134 lbal = tf->lbal = readw(ioaddr->lbal_addr);
135 lbam = tf->lbam = readw(ioaddr->lbam_addr);
136 lbah = tf->lbah = readw(ioaddr->lbah_addr);
137 tf->device = readw(ioaddr->device_addr);
139 if (tf->flags & ATA_TFLAG_LBA48) {
140 tf->hob_feature = readb(ioaddr->error_addr);
141 tf->hob_nsect = nsect >> 8;
142 tf->hob_lbal = lbal >> 8;
143 tf->hob_lbam = lbam >> 8;
144 tf->hob_lbah = lbah >> 8;
152 * Read the interrupt register and process for the devices that have them pending.
154 irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
156 struct ata_host_set *host_set = dev_instance;
158 unsigned int handled = 0;
161 spin_lock(&host_set->lock);
163 int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
165 for (i = 0; i < host_set->n_ports; i++) {
166 if (int_status & ((u32) 0xFF << (8 * i))) {
169 ap = host_set->ports[i];
170 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
171 struct ata_queued_cmd *qc;
173 qc = ata_qc_from_tag(ap, ap->active_tag);
174 if (qc && ((qc->flags & ATA_QCFLAG_POLL) == 0))
175 handled += ata_host_intr(ap, qc);
180 spin_unlock(&host_set->lock);
182 return IRQ_RETVAL(handled);
186 static Scsi_Host_Template vsc_sata_sht = {
187 .module = THIS_MODULE,
189 .queuecommand = ata_scsi_queuecmd,
190 .eh_strategy_handler = ata_scsi_error,
191 .can_queue = ATA_DEF_QUEUE,
192 .this_id = ATA_SHT_THIS_ID,
193 .sg_tablesize = LIBATA_MAX_PRD,
194 .max_sectors = ATA_MAX_SECTORS,
195 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
196 .emulated = ATA_SHT_EMULATED,
197 .use_clustering = ATA_SHT_USE_CLUSTERING,
198 .proc_name = DRV_NAME,
199 .dma_boundary = ATA_DMA_BOUNDARY,
200 .slave_configure = ata_scsi_slave_config,
201 .bios_param = ata_std_bios_param,
205 static struct ata_port_operations vsc_sata_ops = {
206 .port_disable = ata_port_disable,
207 .tf_load = vsc_sata_tf_load,
208 .tf_read = vsc_sata_tf_read,
209 .exec_command = ata_exec_command_mmio,
210 .check_status = ata_check_status_mmio,
211 .phy_reset = sata_phy_reset,
212 .bmdma_start = ata_bmdma_start_mmio,
213 .fill_sg = ata_fill_sg,
214 .eng_timeout = ata_eng_timeout,
215 .irq_handler = vsc_sata_interrupt,
216 .scr_read = vsc_sata_scr_read,
217 .scr_write = vsc_sata_scr_write,
218 .port_start = ata_port_start,
219 .port_stop = ata_port_stop,
222 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
224 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
225 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
226 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
227 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
228 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
229 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
230 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
231 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
232 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
233 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
234 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
235 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
236 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
237 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
238 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
239 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
240 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
244 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
246 static int printed_version;
247 struct ata_probe_ent *probe_ent = NULL;
252 if (!printed_version++)
253 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
255 rc = pci_enable_device(pdev);
260 * Check if we have needed resource mapped.
262 if (pci_resource_len(pdev, 0) == 0) {
267 rc = pci_request_regions(pdev, DRV_NAME);
272 * Use 32 bit DMA mask, because 64 bit address support is poor.
274 rc = pci_set_dma_mask(pdev, 0xFFFFFFFFULL);
276 goto err_out_regions;
277 rc = pci_set_consistent_dma_mask(pdev, 0xFFFFFFFFULL);
279 goto err_out_regions;
281 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
282 if (probe_ent == NULL) {
284 goto err_out_regions;
286 memset(probe_ent, 0, sizeof(*probe_ent));
287 probe_ent->pdev = pdev;
288 INIT_LIST_HEAD(&probe_ent->node);
290 mmio_base = ioremap(pci_resource_start(pdev, 0),
291 pci_resource_len(pdev, 0));
292 if (mmio_base == NULL) {
294 goto err_out_free_ent;
296 base = (unsigned long) mmio_base;
299 * Due to a bug in the chip, the default cache line size can't be used
301 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
303 probe_ent->sht = &vsc_sata_sht;
304 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
305 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
306 probe_ent->port_ops = &vsc_sata_ops;
307 probe_ent->n_ports = 4;
308 probe_ent->irq = pdev->irq;
309 probe_ent->irq_flags = SA_SHIRQ;
310 probe_ent->mmio_base = mmio_base;
312 /* We don't care much about the PIO/UDMA masks, but the core won't like us
313 * if we don't fill these
315 probe_ent->pio_mask = 0x1f;
316 probe_ent->udma_mask = 0x7f;
318 /* We have 4 ports per PCI function */
319 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
320 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
321 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
322 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
324 pci_set_master(pdev);
326 /* FIXME: check ata_device_add return value */
327 ata_device_add(probe_ent);
335 pci_release_regions(pdev);
337 pci_disable_device(pdev);
343 * 0x1725/0x7174 is the Vitesse VSC-7174
344 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
345 * compatibility is untested as of yet
347 static struct pci_device_id vsc_sata_pci_tbl[] = {
348 { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
349 { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
354 static struct pci_driver vsc_sata_pci_driver = {
356 .id_table = vsc_sata_pci_tbl,
357 .probe = vsc_sata_init_one,
358 .remove = ata_pci_remove_one,
362 static int __init vsc_sata_init(void)
364 return pci_module_init(&vsc_sata_pci_driver);
368 static void __exit vsc_sata_exit(void)
370 pci_unregister_driver(&vsc_sata_pci_driver);
374 MODULE_AUTHOR("Jeremy Higdon");
375 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
376 MODULE_LICENSE("GPL");
377 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
379 module_init(vsc_sata_init);
380 module_exit(vsc_sata_exit);