2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
18 * Other major contributions:
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *-----------------------------------------------------------------------------
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. The name of the author may not be used to endorse or promote products
31 * derived from this software without specific prior written permission.
33 * Where this Software is combined with software released under the terms of
34 * the GNU Public License ("GPL") and the terms of the GPL would require the
35 * combined work to also be released under the terms of the GPL, the terms
36 * and conditions of this License will apply in addition to those of the
37 * GPL with the exception of any terms or conditions of this License that
38 * conflict with, or are expressly prohibited by, the GPL.
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
44 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 #include <linux/config.h>
57 #include <linux/delay.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/string.h>
61 #include <linux/timer.h>
62 #include <linux/types.h>
69 #include <scsi/scsi.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <scsi/scsi_host.h>
75 #define bzero(d, n) memset((d), 0, (n))
79 * General driver includes.
86 * Configuration addendum for Linux.
88 #define SYM_CONF_TIMER_INTERVAL ((HZ+1)/2)
90 #define SYM_OPT_HANDLE_DIR_UNKNOWN
91 #define SYM_OPT_HANDLE_DEVICE_QUEUEING
92 #define SYM_OPT_NVRAM_PRE_READ
93 #define SYM_OPT_SNIFF_INQUIRY
94 #define SYM_OPT_LIMIT_COMMAND_REORDERING
95 #define SYM_OPT_ANNOUNCE_TRANSFER_RATE
98 * Print a message with severity.
100 #define printf_emerg(args...) printk(KERN_EMERG args)
101 #define printf_alert(args...) printk(KERN_ALERT args)
102 #define printf_crit(args...) printk(KERN_CRIT args)
103 #define printf_err(args...) printk(KERN_ERR args)
104 #define printf_warning(args...) printk(KERN_WARNING args)
105 #define printf_notice(args...) printk(KERN_NOTICE args)
106 #define printf_info(args...) printk(KERN_INFO args)
107 #define printf_debug(args...) printk(KERN_DEBUG args)
108 #define printf(args...) printk(args)
111 * Insert a delay in micro-seconds and milli-seconds.
113 #define sym_udelay(us) udelay(us)
114 #define sym_mdelay(ms) mdelay(ms)
117 * A 'read barrier' flushes any data that have been prefetched
118 * by the processor due to out of order execution. Such a barrier
119 * must notably be inserted prior to looking at data that have
120 * been DMAed, assuming that program does memory READs in proper
121 * order and that the device ensured proper ordering of WRITEs.
123 * A 'write barrier' prevents any previous WRITEs to pass further
124 * WRITEs. Such barriers must be inserted each time another agent
125 * relies on ordering of WRITEs.
127 * Note that, due to posting of PCI memory writes, we also must
128 * insert dummy PCI read transactions when some ordering involving
129 * both directions over the PCI does matter. PCI transactions are
130 * fully ordered in each direction.
133 #define MEMORY_READ_BARRIER() rmb()
134 #define MEMORY_WRITE_BARRIER() wmb()
137 * Let the compiler know about driver data structure names.
139 typedef struct sym_tcb *tcb_p;
140 typedef struct sym_lcb *lcb_p;
141 typedef struct sym_ccb *ccb_p;
142 typedef struct sym_hcb *hcb_p;
145 * Define a reference to the O/S dependent IO request.
147 typedef struct scsi_cmnd *cam_ccb_p; /* Generic */
148 typedef struct scsi_cmnd *cam_scsiio_p;/* SCSI I/O */
152 * IO functions definition for big/little endian CPU support.
153 * For now, PCI chips are only supported in little endian addressing mode,
160 #define outw_b2l outw
161 #define outl_b2l outl
162 #define readw_l2b readw
163 #define readl_l2b readl
164 #define writew_b2l writew
165 #define writel_b2l writel
167 #else /* little endian */
171 #define outw_raw outw
172 #define outl_raw outl
174 #define readw_raw readw
175 #define readl_raw readl
176 #define writew_raw writew
177 #define writel_raw writel
181 #ifdef SYM_CONF_CHIP_BIG_ENDIAN
182 #error "Chips in BIG ENDIAN addressing mode are not (yet) supported"
187 * If the chip uses big endian addressing mode over the
188 * PCI, actual io register addresses for byte and word
189 * accesses must be changed according to lane routing.
190 * Btw, sym_offb() and sym_offw() macros only apply to
191 * constants and so donnot generate bloated code.
194 #if defined(SYM_CONF_CHIP_BIG_ENDIAN)
196 #define sym_offb(o) (((o)&~3)+((~((o)&3))&3))
197 #define sym_offw(o) (((o)&~3)+((~((o)&3))&2))
201 #define sym_offb(o) (o)
202 #define sym_offw(o) (o)
207 * If the CPU and the chip use same endian-ness addressing,
208 * no byte reordering is needed for script patching.
209 * Macro cpu_to_scr() is to be used for script patching.
210 * Macro scr_to_cpu() is to be used for getting a DWORD
214 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
216 #define cpu_to_scr(dw) cpu_to_le32(dw)
217 #define scr_to_cpu(dw) le32_to_cpu(dw)
219 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
221 #define cpu_to_scr(dw) cpu_to_be32(dw)
222 #define scr_to_cpu(dw) be32_to_cpu(dw)
226 #define cpu_to_scr(dw) (dw)
227 #define scr_to_cpu(dw) (dw)
232 * Access to the controller chip.
234 * If SYM_CONF_IOMAPPED is defined, the driver will use
235 * normal IOs instead of the MEMORY MAPPED IO method
236 * recommended by PCI specifications.
237 * If all PCI bridges, host brigdes and architectures
238 * would have been correctly designed for PCI, this
239 * option would be useless.
241 * If the CPU and the chip use same endian-ness addressing,
242 * no byte reordering is needed for accessing chip io
243 * registers. Functions suffixed by '_raw' are assumed
244 * to access the chip over the PCI without doing byte
245 * reordering. Functions suffixed by '_l2b' are
246 * assumed to perform little-endian to big-endian byte
247 * reordering, those suffixed by '_b2l' blah, blah,
251 #if defined(SYM_CONF_IOMAPPED)
254 * IO mapped only input / ouput
257 #define INB_OFF(o) inb (np->s.io_port + sym_offb(o))
258 #define OUTB_OFF(o, val) outb ((val), np->s.io_port + sym_offb(o))
260 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
262 #define INW_OFF(o) inw_l2b (np->s.io_port + sym_offw(o))
263 #define INL_OFF(o) inl_l2b (np->s.io_port + (o))
265 #define OUTW_OFF(o, val) outw_b2l ((val), np->s.io_port + sym_offw(o))
266 #define OUTL_OFF(o, val) outl_b2l ((val), np->s.io_port + (o))
268 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
270 #define INW_OFF(o) inw_b2l (np->s.io_port + sym_offw(o))
271 #define INL_OFF(o) inl_b2l (np->s.io_port + (o))
273 #define OUTW_OFF(o, val) outw_l2b ((val), np->s.io_port + sym_offw(o))
274 #define OUTL_OFF(o, val) outl_l2b ((val), np->s.io_port + (o))
278 #define INW_OFF(o) inw_raw (np->s.io_port + sym_offw(o))
279 #define INL_OFF(o) inl_raw (np->s.io_port + (o))
281 #define OUTW_OFF(o, val) outw_raw ((val), np->s.io_port + sym_offw(o))
282 #define OUTL_OFF(o, val) outl_raw ((val), np->s.io_port + (o))
286 #else /* defined SYM_CONF_IOMAPPED */
289 * MEMORY mapped IO input / output
292 #define INB_OFF(o) readb((char *)np->s.mmio_va + sym_offb(o))
293 #define OUTB_OFF(o, val) writeb((val), (char *)np->s.mmio_va + sym_offb(o))
295 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
297 #define INW_OFF(o) readw_l2b((char *)np->s.mmio_va + sym_offw(o))
298 #define INL_OFF(o) readl_l2b((char *)np->s.mmio_va + (o))
300 #define OUTW_OFF(o, val) writew_b2l((val), (char *)np->s.mmio_va + sym_offw(o))
301 #define OUTL_OFF(o, val) writel_b2l((val), (char *)np->s.mmio_va + (o))
303 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
305 #define INW_OFF(o) readw_b2l((char *)np->s.mmio_va + sym_offw(o))
306 #define INL_OFF(o) readl_b2l((char *)np->s.mmio_va + (o))
308 #define OUTW_OFF(o, val) writew_l2b((val), (char *)np->s.mmio_va + sym_offw(o))
309 #define OUTL_OFF(o, val) writel_l2b((val), (char *)np->s.mmio_va + (o))
313 #define INW_OFF(o) readw_raw((char *)np->s.mmio_va + sym_offw(o))
314 #define INL_OFF(o) readl_raw((char *)np->s.mmio_va + (o))
316 #define OUTW_OFF(o, val) writew_raw((val), (char *)np->s.mmio_va + sym_offw(o))
317 #define OUTL_OFF(o, val) writel_raw((val), (char *)np->s.mmio_va + (o))
321 #endif /* defined SYM_CONF_IOMAPPED */
323 #define OUTRAM_OFF(o, a, l) memcpy_toio(np->s.ram_va + (o), (a), (l))
326 * Remap some status field values.
328 #define CAM_REQ_CMP DID_OK
329 #define CAM_SEL_TIMEOUT DID_NO_CONNECT
330 #define CAM_CMD_TIMEOUT DID_TIME_OUT
331 #define CAM_REQ_ABORTED DID_ABORT
332 #define CAM_UNCOR_PARITY DID_PARITY
333 #define CAM_SCSI_BUS_RESET DID_RESET
334 #define CAM_REQUEUE_REQ DID_SOFT_ERROR
335 #define CAM_UNEXP_BUSFREE DID_ERROR
336 #define CAM_SCSI_BUSY DID_BUS_BUSY
338 #define CAM_DEV_NOT_THERE DID_NO_CONNECT
339 #define CAM_REQ_INVALID DID_ERROR
340 #define CAM_REQ_TOO_BIG DID_ERROR
342 #define CAM_RESRC_UNAVAIL DID_ERROR
345 * Remap data direction values.
347 #define CAM_DIR_NONE DMA_NONE
348 #define CAM_DIR_IN DMA_FROM_DEVICE
349 #define CAM_DIR_OUT DMA_TO_DEVICE
350 #define CAM_DIR_UNKNOWN DMA_BIDIRECTIONAL
353 * These ones are used as return code from
354 * error recovery handlers under Linux.
356 #define SCSI_SUCCESS SUCCESS
357 #define SCSI_FAILED FAILED
360 * System specific target data structure.
361 * None for now, under Linux.
363 /* #define SYM_HAVE_STCB */
366 * System specific lun data structure.
368 #define SYM_HAVE_SLCB
370 u_short reqtags; /* Number of tags requested by user */
371 u_short scdev_depth; /* Queue depth set in select_queue_depth() */
375 * System specific command data structure.
376 * Not needed under Linux.
378 /* struct sym_sccb */
381 * System specific host data structure.
385 * Chip and controller indentification.
390 struct pci_dev *device;
392 struct Scsi_Host *host;
394 void * mmio_va; /* MMIO kernel virtual address */
395 void * ram_va; /* RAM kernel virtual address */
396 u_long io_port; /* IO port address cookie */
397 u_short io_ws; /* IO window size */
398 int irq; /* IRQ number */
400 SYM_QUEHEAD wait_cmdq; /* Awaiting SCSI commands */
401 SYM_QUEHEAD busy_cmdq; /* Enqueued SCSI commands */
403 struct timer_list timer; /* Timer handler link header */
405 u_long settle_time; /* Resetting the SCSI BUS */
406 u_char settle_time_valid;
410 * Return the name of the controller.
412 #define sym_name(np) (np)->s.inst_name
415 * Data structure used as input for the NVRAM reading.
416 * Must resolve the IO macros and sym_name(), when
417 * used as sub-field 's' of another structure.
425 /* port and address fields to fit INB, OUTB macros */
434 struct pci_dev *pdev;
436 struct sym_pci_chip chip;
437 struct sym_nvram *nvram;
443 * The driver definitions (sym_hipd.h) must know about a
444 * couple of things related to the memory allocator.
446 typedef u_long m_addr_t; /* Enough bits to represent any address */
447 #define SYM_MEM_PAGE_ORDER 0 /* 1 PAGE maximum */
448 #define SYM_MEM_CLUSTER_SHIFT (PAGE_SHIFT+SYM_MEM_PAGE_ORDER)
450 #define SYM_MEM_FREE_UNUSED /* Free unused pages immediately */
452 typedef struct pci_dev *m_pool_ident_t;
455 * Include driver soft definitions.
458 #include "sym_hipd.h"
461 * Memory allocator related stuff.
464 #define SYM_MEM_GFP_FLAGS GFP_ATOMIC
465 #define SYM_MEM_WARN 1 /* Warn on failed operations */
467 #define sym_get_mem_cluster() \
468 __get_free_pages(SYM_MEM_GFP_FLAGS, SYM_MEM_PAGE_ORDER)
469 #define sym_free_mem_cluster(p) \
470 free_pages(p, SYM_MEM_PAGE_ORDER)
472 void *sym_calloc(int size, char *name);
473 void sym_mfree(void *m, int size, char *name);
476 * We have to provide the driver memory allocator with methods for
477 * it to maintain virtual to bus physical address translations.
480 #define sym_m_pool_match(mp_id1, mp_id2) (mp_id1 == mp_id2)
482 static __inline m_addr_t sym_m_get_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
485 dma_addr_t baddr = 0;
487 vaddr = pci_alloc_consistent(mp->dev_dmat,SYM_MEM_CLUSTER_SIZE, &baddr);
489 vbp->vaddr = (m_addr_t) vaddr;
490 vbp->baddr = (m_addr_t) baddr;
492 return (m_addr_t) vaddr;
495 static __inline void sym_m_free_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
497 pci_free_consistent(mp->dev_dmat, SYM_MEM_CLUSTER_SIZE,
498 (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
501 #define sym_m_create_dma_mem_tag(mp) (0)
502 #define sym_m_delete_dma_mem_tag(mp) do { ; } while (0)
504 void *__sym_calloc_dma(m_pool_ident_t dev_dmat, int size, char *name);
505 void __sym_mfree_dma(m_pool_ident_t dev_dmat, void *m, int size, char *name);
506 m_addr_t __vtobus(m_pool_ident_t dev_dmat, void *m);
509 * Set the status field of a CAM CCB.
512 sym_set_cam_status(struct scsi_cmnd *ccb, int status)
514 ccb->result &= ~(0xff << 16);
515 ccb->result |= (status << 16);
519 * Get the status field of a CAM CCB.
522 sym_get_cam_status(struct scsi_cmnd *ccb)
524 return ((ccb->result >> 16) & 0xff);
528 * The dma mapping is mostly handled by the
529 * SCSI layer and the driver glue under Linux.
531 #define sym_data_dmamap_create(np, cp) (0)
532 #define sym_data_dmamap_destroy(np, cp) do { ; } while (0)
533 #define sym_data_dmamap_unload(np, cp) do { ; } while (0)
534 #define sym_data_dmamap_presync(np, cp) do { ; } while (0)
535 #define sym_data_dmamap_postsync(np, cp) do { ; } while (0)
538 * Async handler for negotiations.
540 void sym_xpt_async_nego_wide(hcb_p np, int target);
541 #define sym_xpt_async_nego_sync(np, target) \
542 sym_announce_transfer_rate(np, target)
543 #define sym_xpt_async_nego_ppr(np, target) \
544 sym_announce_transfer_rate(np, target)
547 * Build CAM result for a successful IO and for a failed IO.
549 static __inline void sym_set_cam_result_ok(hcb_p np, ccb_p cp, int resid)
551 struct scsi_cmnd *cmd = cp->cam_ccb;
554 cmd->result = (((DID_OK) << 16) + ((cp->ssss_status) & 0x7f));
556 void sym_set_cam_result_error(hcb_p np, ccb_p cp, int resid);
559 * Other O/S specific methods.
561 #define sym_cam_target_id(ccb) (ccb)->target
562 #define sym_cam_target_lun(ccb) (ccb)->lun
563 #define sym_freeze_cam_ccb(ccb) do { ; } while (0)
564 void sym_xpt_done(hcb_p np, cam_ccb_p ccb);
565 void sym_xpt_done2(hcb_p np, cam_ccb_p ccb, int cam_status);
566 void sym_print_addr (ccb_p cp);
567 void sym_xpt_async_bus_reset(hcb_p np);
568 void sym_xpt_async_sent_bdr(hcb_p np, int target);
569 int sym_setup_data_and_start (hcb_p np, cam_scsiio_p csio, ccb_p cp);
570 void sym_log_bus_error(hcb_p np);
571 void sym_sniff_inquiry(hcb_p np, struct scsi_cmnd *cmd, int resid);
573 #endif /* SYM_GLUE_H */