1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
4 ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
14 **-----------------------------------------------------------------------------
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30 **-----------------------------------------------------------------------------
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
35 ** Gerard Roudier <groudier@free.fr>
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
46 **-----------------------------------------------------------------------------
48 ** Major contributions:
49 ** --------------------
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
54 ** Added support for MIPS big endian systems.
55 ** Carsten Langgaard, carstenl@mips.com
56 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
58 ** Added support for HP PARISC big endian systems.
59 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
61 *******************************************************************************
64 #ifndef SYM53C8XX_DEFS_H
65 #define SYM53C8XX_DEFS_H
68 ** Check supported Linux versions
71 #include <linux/config.h>
74 * NCR PQS/PDS special device support.
76 #ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
77 #define SCSI_NCR_PQS_PDS_SUPPORT
81 * No more an option, enabled by default.
83 #ifndef CONFIG_SCSI_NCR53C8XX_NO_NVRAM
84 # ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
85 # define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
90 ** These options are not tunable from 'make config'
92 #define SCSI_NCR_PROC_INFO_SUPPORT
95 ** If you want a driver as small as possible, donnot define the
98 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
99 #define SCSI_NCR_DEBUG_INFO_SUPPORT
100 #define SCSI_NCR_PCI_FIX_UP_SUPPORT
101 #ifdef SCSI_NCR_PROC_INFO_SUPPORT
102 # define SCSI_NCR_USER_COMMAND_SUPPORT
103 # define SCSI_NCR_USER_INFO_SUPPORT
107 ** To disable integrity checking, do not define the
110 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
111 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
114 /*==========================================================
116 ** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
118 **==========================================================
121 #ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
122 #define SCSI_NCR_NVRAM_SUPPORT
123 /* #define SCSI_NCR_DEBUG_NVRAM */
126 /* ---------------------------------------------------------------------
127 ** Take into account kernel configured parameters.
128 ** Most of these options can be overridden at startup by a command line.
129 ** ---------------------------------------------------------------------
133 * For Ultra2 and Ultra3 SCSI support option, use special features.
135 * Value (default) means:
136 * bit 0 : all features enabled, except:
137 * bit 1 : PCI Write And Invalidate.
138 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
140 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
141 * enabled by the driver.
143 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
145 #define SCSI_NCR_MAX_SYNC (80)
148 * Allow tags from 2 to 256, default 8
150 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
151 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
152 #define SCSI_NCR_MAX_TAGS (2)
153 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
154 #define SCSI_NCR_MAX_TAGS (256)
156 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
159 #define SCSI_NCR_MAX_TAGS (8)
163 * Allow tagged command queuing support if configured with default number
164 * of tags set to max (see above).
166 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
167 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
168 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
169 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
171 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
175 * Use normal IO if configured. Forced for alpha.
177 #if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
178 #define SCSI_NCR_IOMAPPED
179 #elif defined(__alpha__)
180 #define SCSI_NCR_IOMAPPED
184 * Immediate arbitration
186 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
187 #define SCSI_NCR_IARB_SUPPORT
191 * Sync transfer frequency at startup.
192 * Allow from 5Mhz to 80Mhz default 20 Mhz.
194 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
195 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
196 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
197 #undef CONFIG_SCSI_NCR53C8XX_SYNC
198 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
201 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
202 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
203 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
204 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
205 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
206 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
207 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
208 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
209 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
210 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
212 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
216 * Disallow disconnections at boot-up
218 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
219 #define SCSI_NCR_SETUP_DISCONNECTION (0)
221 #define SCSI_NCR_SETUP_DISCONNECTION (1)
225 * Force synchronous negotiation for all targets
227 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
228 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
230 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
234 * Disable master parity checking (flawed hardwares need that)
236 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
237 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
239 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
243 * Disable scsi parity checking (flawed devices may need that)
245 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
246 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
248 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
252 * Settle time after reset at boot-up
254 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
257 ** Bridge quirks work-around option defaulted to 1.
259 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
260 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
264 ** Work-around common bridge misbehaviour.
266 ** - Do not flush posted writes in the opposite
267 ** direction on read.
268 ** - May reorder DMA writes to memory.
270 ** This option should not affect performances
271 ** significantly, so it is the default.
273 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
274 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
275 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
276 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
279 ** Same as option 1, but also deal with
280 ** misconfigured interrupts.
282 ** - Edge triggerred instead of level sensitive.
283 ** - No interrupt line connected.
284 ** - IRQ number misconfigured.
286 ** If no interrupt is delivered, the driver will
287 ** catch the interrupt conditions 10 times per
288 ** second. No need to say that this option is
291 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
292 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
293 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
294 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
295 #define SCSI_NCR_PCIQ_BROKEN_INTR
298 ** Some bridge designers decided to flush
299 ** everything prior to deliver the interrupt.
300 ** This option tries to deal with such a
303 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
304 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
308 ** Other parameters not configurable with "make config"
309 ** Avoid to change these constants, unless you know what you are doing.
312 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
313 #define SCSI_NCR_MAX_SCATTER (127)
314 #define SCSI_NCR_MAX_TARGET (16)
317 ** Compute some desirable value for CAN_QUEUE
319 ** The driver will use lower values if these
320 ** ones appear to be too large.
322 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
323 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
325 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
326 #define SCSI_NCR_TIMER_INTERVAL (HZ)
328 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
329 #define SCSI_NCR_MAX_LUN (16)
331 #define SCSI_NCR_MAX_LUN (1)
337 ** These simple macros limit expression involving
338 ** kernel time values (jiffies) to some that have
339 ** chance not to be too much incorrect. :-)
341 #define ktime_get(o) (jiffies + (u_long) o)
342 #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
343 #define ktime_dif(a, b) ((long)(a) - (long)(b))
344 /* These ones are not used in this driver */
345 #define ktime_add(a, o) ((a) + (u_long)(o))
346 #define ktime_sub(a, o) ((a) - (u_long)(o))
350 * IO functions definition for big/little endian CPU support.
351 * For now, the NCR is only supported in little endian addressing mode,
358 #define outw_b2l outw
359 #define outl_b2l outl
361 #define readb_raw readb
362 #define writeb_raw writeb
364 #if defined(SCSI_NCR_BIG_ENDIAN)
365 #define readw_l2b __raw_readw
366 #define readl_l2b __raw_readl
367 #define writew_b2l __raw_writew
368 #define writel_b2l __raw_writel
369 #define readw_raw __raw_readw
370 #define readl_raw(a) __raw_readl((unsigned long)(a))
371 #define writew_raw __raw_writew
372 #define writel_raw(v,a) __raw_writel(v,(unsigned long)(a))
373 #else /* Other big-endian */
374 #define readw_l2b readw
375 #define readl_l2b readl
376 #define writew_b2l writew
377 #define writel_b2l writel
378 #define readw_raw readw
379 #define readl_raw readl
380 #define writew_raw writew
381 #define writel_raw writel
384 #else /* little endian */
388 #define outw_raw outw
389 #define outl_raw outl
391 #if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
392 #define readb_raw(a) (*(volatile unsigned char *) (a))
393 #define readw_raw(a) (*(volatile unsigned short *) (a))
394 #define readl_raw(a) (*(volatile unsigned int *) (a))
395 #define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
396 #define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
397 #define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
399 #else /* Other little-endian */
400 #define readb_raw readb
401 #define readw_raw readw
402 #define readl_raw readl
403 #define writeb_raw writeb
404 #define writew_raw writew
405 #define writel_raw writel
410 #if !defined(__hppa__) && !defined(__mips__)
411 #ifdef SCSI_NCR_BIG_ENDIAN
412 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
418 * IA32 architecture does not reorder STORES and prevents
419 * LOADS from passing STORES. It is called `program order'
420 * by Intel and allows device drivers to deal with memory
421 * ordering by only ensuring that the code is not reordered
422 * by the compiler when ordering is required.
423 * Other architectures implement a weaker ordering that
424 * requires memory barriers (and also IO barriers when they
425 * make sense) to be used.
428 #define MEMORY_BARRIER() mb()
432 * If the NCR uses big endian addressing mode over the
433 * PCI, actual io register addresses for byte and word
434 * accesses must be changed according to lane routing.
435 * Btw, ncr_offb() and ncr_offw() macros only apply to
436 * constants and so donnot generate bloated code.
439 #if defined(SCSI_NCR_BIG_ENDIAN)
441 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
442 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
446 #define ncr_offb(o) (o)
447 #define ncr_offw(o) (o)
452 * If the CPU and the NCR use same endian-ness addressing,
453 * no byte reordering is needed for script patching.
454 * Macro cpu_to_scr() is to be used for script patching.
455 * Macro scr_to_cpu() is to be used for getting a DWORD
459 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
461 #define cpu_to_scr(dw) cpu_to_le32(dw)
462 #define scr_to_cpu(dw) le32_to_cpu(dw)
464 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
466 #define cpu_to_scr(dw) cpu_to_be32(dw)
467 #define scr_to_cpu(dw) be32_to_cpu(dw)
471 #define cpu_to_scr(dw) (dw)
472 #define scr_to_cpu(dw) (dw)
477 * Access to the controller chip.
479 * If SCSI_NCR_IOMAPPED is defined, the driver will use
480 * normal IOs instead of the MEMORY MAPPED IO method
481 * recommended by PCI specifications.
482 * If all PCI bridges, host brigdes and architectures
483 * would have been correctly designed for PCI, this
484 * option would be useless.
486 * If the CPU and the NCR use same endian-ness addressing,
487 * no byte reordering is needed for accessing chip io
488 * registers. Functions suffixed by '_raw' are assumed
489 * to access the chip over the PCI without doing byte
490 * reordering. Functions suffixed by '_l2b' are
491 * assumed to perform little-endian to big-endian byte
492 * reordering, those suffixed by '_b2l' blah, blah,
496 #if defined(SCSI_NCR_IOMAPPED)
498 * IO mapped only input / ouput
501 #define INB_OFF(o) inb (np->base_io + ncr_offb(o))
502 #define OUTB_OFF(o, val) outb ((val), np->base_io + ncr_offb(o))
504 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
506 #define INW_OFF(o) inw_l2b (np->base_io + ncr_offw(o))
507 #define INL_OFF(o) inl_l2b (np->base_io + (o))
509 #define OUTW_OFF(o, val) outw_b2l ((val), np->base_io + ncr_offw(o))
510 #define OUTL_OFF(o, val) outl_b2l ((val), np->base_io + (o))
512 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
514 #define INW_OFF(o) inw_b2l (np->base_io + ncr_offw(o))
515 #define INL_OFF(o) inl_b2l (np->base_io + (o))
517 #define OUTW_OFF(o, val) outw_l2b ((val), np->base_io + ncr_offw(o))
518 #define OUTL_OFF(o, val) outl_l2b ((val), np->base_io + (o))
522 #define INW_OFF(o) inw_raw (np->base_io + ncr_offw(o))
523 #define INL_OFF(o) inl_raw (np->base_io + (o))
525 #define OUTW_OFF(o, val) outw_raw ((val), np->base_io + ncr_offw(o))
526 #define OUTL_OFF(o, val) outl_raw ((val), np->base_io + (o))
530 #else /* defined SCSI_NCR_IOMAPPED */
533 * MEMORY mapped IO input / output
536 #define INB_OFF(o) readb_raw((char *)np->reg + ncr_offb(o))
537 #define OUTB_OFF(o, val) writeb_raw((val), (char *)np->reg + ncr_offb(o))
539 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
541 #define INW_OFF(o) readw_l2b((char *)np->reg + ncr_offw(o))
542 #define INL_OFF(o) readl_l2b((char *)np->reg + (o))
544 #define OUTW_OFF(o, val) writew_b2l((val), (char *)np->reg + ncr_offw(o))
545 #define OUTL_OFF(o, val) writel_b2l((val), (char *)np->reg + (o))
547 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
549 #define INW_OFF(o) readw_b2l((char *)np->reg + ncr_offw(o))
550 #define INL_OFF(o) readl_b2l((char *)np->reg + (o))
552 #define OUTW_OFF(o, val) writew_l2b((val), (char *)np->reg + ncr_offw(o))
553 #define OUTL_OFF(o, val) writel_l2b((val), (char *)np->reg + (o))
557 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
558 /* Only 8 or 32 bit transfers allowed */
559 #define INW_OFF(o) (readb((char *)np->reg + ncr_offw(o)) << 8 | readb((char *)np->reg + ncr_offw(o) + 1))
561 #define INW_OFF(o) readw_raw((char *)np->reg + ncr_offw(o))
563 #define INL_OFF(o) readl_raw((char *)np->reg + (o))
565 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
566 /* Only 8 or 32 bit transfers allowed */
567 #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char *)np->reg + ncr_offw(o)); writeb((char)(val), (char *)np->reg + ncr_offw(o) + 1); } while (0)
569 #define OUTW_OFF(o, val) writew_raw((val), (char *)np->reg + ncr_offw(o))
571 #define OUTL_OFF(o, val) writel_raw((val), (char *)np->reg + (o))
575 #endif /* defined SCSI_NCR_IOMAPPED */
577 #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
578 #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
579 #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
581 #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
582 #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
583 #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
586 * Set bit field ON, OFF
589 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
590 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
591 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
592 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
593 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
594 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
597 * We normally want the chip to have a consistent view
598 * of driver internal data structures when we restart it.
601 #define OUTL_DSP(v) \
604 OUTL (nc_dsp, (v)); \
607 #define OUTONB_STD() \
610 OUTONB (nc_dcntl, (STD|NOCOM)); \
615 ** NCR53C8XX Device Ids
618 #ifndef PSEUDO_720_ID
619 #define PSEUDO_720_ID 0x5a00
622 #ifndef PCI_DEVICE_ID_NCR_53C810
623 #define PCI_DEVICE_ID_NCR_53C810 1
626 #ifndef PCI_DEVICE_ID_NCR_53C810AP
627 #define PCI_DEVICE_ID_NCR_53C810AP 5
630 #ifndef PCI_DEVICE_ID_NCR_53C815
631 #define PCI_DEVICE_ID_NCR_53C815 4
634 #ifndef PCI_DEVICE_ID_NCR_53C820
635 #define PCI_DEVICE_ID_NCR_53C820 2
638 #ifndef PCI_DEVICE_ID_NCR_53C825
639 #define PCI_DEVICE_ID_NCR_53C825 3
642 #ifndef PCI_DEVICE_ID_NCR_53C860
643 #define PCI_DEVICE_ID_NCR_53C860 6
646 #ifndef PCI_DEVICE_ID_NCR_53C875
647 #define PCI_DEVICE_ID_NCR_53C875 0xf
650 #ifndef PCI_DEVICE_ID_NCR_53C875J
651 #define PCI_DEVICE_ID_NCR_53C875J 0x8f
654 #ifndef PCI_DEVICE_ID_NCR_53C885
655 #define PCI_DEVICE_ID_NCR_53C885 0xd
658 #ifndef PCI_DEVICE_ID_NCR_53C895
659 #define PCI_DEVICE_ID_NCR_53C895 0xc
662 #ifndef PCI_DEVICE_ID_NCR_53C896
663 #define PCI_DEVICE_ID_NCR_53C896 0xb
666 #ifndef PCI_DEVICE_ID_NCR_53C895A
667 #define PCI_DEVICE_ID_NCR_53C895A 0x12
670 #ifndef PCI_DEVICE_ID_NCR_53C875A
671 #define PCI_DEVICE_ID_NCR_53C875A 0x13
674 #ifndef PCI_DEVICE_ID_NCR_53C1510D
675 #define PCI_DEVICE_ID_NCR_53C1510D 0xa
678 #ifndef PCI_DEVICE_ID_LSI_53C1010
679 #define PCI_DEVICE_ID_LSI_53C1010 0x20
682 #ifndef PCI_DEVICE_ID_LSI_53C1010_66
683 #define PCI_DEVICE_ID_LSI_53C1010_66 0x21
688 ** NCR53C8XX devices features table.
691 unsigned short device_id;
692 unsigned short revision_id;
694 unsigned char burst_max; /* log-base-2 of max burst */
695 unsigned char offset_max;
696 unsigned char nr_divisor;
697 unsigned int features;
698 #define FE_LED0 (1<<0)
699 #define FE_WIDE (1<<1) /* Wide data transfers */
700 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
701 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
702 #define FE_DBLR (1<<4) /* Clock doubler present */
703 #define FE_QUAD (1<<5) /* Clock quadrupler present */
704 #define FE_ERL (1<<6) /* Enable read line */
705 #define FE_CLSE (1<<7) /* Cache line size enable */
706 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
707 #define FE_ERMP (1<<9) /* Enable read multiple */
708 #define FE_BOF (1<<10) /* Burst opcode fetch */
709 #define FE_DFS (1<<11) /* DMA fifo size */
710 #define FE_PFEN (1<<12) /* Prefetch enable */
711 #define FE_LDSTR (1<<13) /* Load/Store supported */
712 #define FE_RAM (1<<14) /* On chip RAM present */
713 #define FE_VARCLK (1<<15) /* SCSI clock may vary */
714 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
715 #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
716 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
717 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
718 #define FE_LEDC (1<<20) /* Hardware control of LED */
719 #define FE_DIFF (1<<21) /* Support Differential SCSI */
720 #define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */
721 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
722 #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
723 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
724 #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
725 #define FE_EHP (1<<27) /* 720: Even host parity */
726 #define FE_MUX (1<<28) /* 720: Multiplexed bus */
727 #define FE_EA (1<<29) /* 720: Enable Ack */
729 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
730 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
731 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
735 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
736 ** Memory Read transaction terminated by a retry followed by
737 ** Memory Read Line command.
739 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
742 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
743 ** On paper, this errata is harmless. But it is a good reason for
744 ** using a shorter programmed burst length (64 DWORDS instead of 128).
747 #define SCSI_NCR_CHIP_TABLE \
749 {PSEUDO_720_ID, 0x0f, "720", 3, 8, 4, \
750 FE_WIDE|FE_DIFF|FE_EHP|FE_MUX|FE_EA} \
752 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
755 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
756 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
758 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
761 {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
764 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
765 FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \
767 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
768 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \
770 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
771 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
773 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
774 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
775 FE_RAM|FE_DIFF|FE_VARCLK} \
777 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, \
778 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
779 FE_RAM|FE_DIFF|FE_VARCLK} \
781 {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
782 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
785 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
786 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
787 FE_RAM|FE_DIFF|FE_VARCLK} \
789 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
790 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
793 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \
794 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
795 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ISTAT1} \
797 {PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \
798 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
799 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
801 {PCI_DEVICE_ID_NCR_53C875A, 0xff, "875a", 6, 31, 7, \
802 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
803 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
805 {PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \
806 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
809 {PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010-33", 6, 62, 7, \
810 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
811 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \
813 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 62, 7, \
814 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
815 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3| \
820 * List of supported NCR chip ids
822 #define SCSI_NCR_CHIP_IDS \
825 PCI_DEVICE_ID_NCR_53C810, \
826 PCI_DEVICE_ID_NCR_53C815, \
827 PCI_DEVICE_ID_NCR_53C820, \
828 PCI_DEVICE_ID_NCR_53C825, \
829 PCI_DEVICE_ID_NCR_53C860, \
830 PCI_DEVICE_ID_NCR_53C875, \
831 PCI_DEVICE_ID_NCR_53C875J, \
832 PCI_DEVICE_ID_NCR_53C885, \
833 PCI_DEVICE_ID_NCR_53C895, \
834 PCI_DEVICE_ID_NCR_53C896, \
835 PCI_DEVICE_ID_NCR_53C895A, \
836 PCI_DEVICE_ID_NCR_53C1510D, \
837 PCI_DEVICE_ID_LSI_53C1010, \
838 PCI_DEVICE_ID_LSI_53C1010_66 \
842 ** Driver setup structure.
844 ** This structure is initialized from linux config options.
845 ** It can be overridden at boot-up by the boot command line.
847 #define SCSI_NCR_MAX_EXCLUDES 8
848 struct ncr_driver_setup {
849 u_char master_parity;
851 u_char disconnection;
852 u_char special_features;
853 u_char force_sync_nego;
854 u_char reverse_probe;
859 u_short default_sync;
872 u_long excludes[SCSI_NCR_MAX_EXCLUDES];
878 ** Can be overriden at startup by a command line.
880 #define SCSI_NCR_DRIVER_SETUP \
882 SCSI_NCR_SETUP_MASTER_PARITY, \
883 SCSI_NCR_SETUP_SCSI_PARITY, \
884 SCSI_NCR_SETUP_DISCONNECTION, \
885 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
886 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
891 SCSI_NCR_SETUP_DEFAULT_TAGS, \
892 SCSI_NCR_SETUP_DEFAULT_SYNC, \
897 SCSI_NCR_SETUP_SETTLE_TIME, \
908 ** Boot fail safe setup.
909 ** Override initial setup from boot command line:
912 #define SCSI_NCR_DRIVER_SAFE_SETUP \
938 #ifdef SCSI_NCR_NVRAM_SUPPORT
940 ** Symbios NvRAM data format
942 #define SYMBIOS_NVRAM_SIZE 368
943 #define SYMBIOS_NVRAM_ADDRESS 0x100
945 struct Symbios_nvram {
947 u_short type; /* 0x0000 */
948 u_short byte_count; /* excluding header/trailer */
951 /* Controller set up 20 bytes */
952 u_char v_major; /* 0x00 */
953 u_char v_minor; /* 0x30 */
956 #define SYMBIOS_SCAM_ENABLE (1)
957 #define SYMBIOS_PARITY_ENABLE (1<<1)
958 #define SYMBIOS_VERBOSE_MSGS (1<<2)
959 #define SYMBIOS_CHS_MAPPING (1<<3)
960 #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
962 #define SYMBIOS_SCAN_HI_LO (1)
964 #define SYMBIOS_TERM_CANT_PROGRAM (0)
965 #define SYMBIOS_TERM_ENABLED (1)
966 #define SYMBIOS_TERM_DISABLED (2)
968 #define SYMBIOS_RMVBL_NO_SUPPORT (0)
969 #define SYMBIOS_RMVBL_BOOT_DEVICE (1)
970 #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
972 u_char num_hba; /* 0x04 */
973 u_char num_devices; /* 0x10 */
974 u_char max_scam_devices; /* 0x04 */
975 u_char num_valid_scam_devives; /* 0x00 */
978 /* Boot order 14 bytes * 4 */
980 u_short type; /* 4:8xx / 0:nok */
981 u_short device_id; /* PCI device id */
982 u_short vendor_id; /* PCI vendor id */
983 u_char bus_nr; /* PCI bus number */
984 u_char device_fn; /* PCI device/function number << 3*/
987 #define SYMBIOS_INIT_SCAN_AT_BOOT (1)
988 u_short io_port; /* PCI io_port address */
991 /* Targets 8 bytes * 16 */
992 struct Symbios_target {
994 #define SYMBIOS_DISCONNECT_ENABLE (1)
995 #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
996 #define SYMBIOS_SCAN_LUNS (1<<2)
997 #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
999 u_char bus_width; /* 0x08/0x10 */
1001 u_short sync_period; /* 4*period factor */
1004 /* Scam table 8 bytes * 4 */
1005 struct Symbios_scam {
1008 #define SYMBIOS_SCAM_DEFAULT_METHOD (0)
1009 #define SYMBIOS_SCAM_DONT_ASSIGN (1)
1010 #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
1011 #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
1013 #define SYMBIOS_SCAM_UNKNOWN (0)
1014 #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
1015 #define SYMBIOS_SCAM_ID_NOT_SET (2)
1016 #define SYMBIOS_SCAM_ID_VALID (3)
1021 u_char spare_devices[15*8];
1022 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
1024 typedef struct Symbios_nvram Symbios_nvram;
1025 typedef struct Symbios_host Symbios_host;
1026 typedef struct Symbios_target Symbios_target;
1027 typedef struct Symbios_scam Symbios_scam;
1030 ** Tekram NvRAM data format.
1032 #define TEKRAM_NVRAM_SIZE 64
1033 #define TEKRAM_93C46_NVRAM_ADDRESS 0
1034 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40
1036 struct Tekram_nvram {
1037 struct Tekram_target {
1039 #define TEKRAM_PARITY_CHECK (1)
1040 #define TEKRAM_SYNC_NEGO (1<<1)
1041 #define TEKRAM_DISCONNECT_ENABLE (1<<2)
1042 #define TEKRAM_START_CMD (1<<3)
1043 #define TEKRAM_TAGGED_COMMANDS (1<<4)
1044 #define TEKRAM_WIDE_NEGO (1<<5)
1050 #define TEKRAM_MORE_THAN_2_DRIVES (1)
1051 #define TEKRAM_DRIVES_SUP_1GB (1<<1)
1052 #define TEKRAM_RESET_ON_POWER_ON (1<<2)
1053 #define TEKRAM_ACTIVE_NEGATION (1<<3)
1054 #define TEKRAM_IMMEDIATE_SEEK (1<<4)
1055 #define TEKRAM_SCAN_LUNS (1<<5)
1056 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
1057 u_char boot_delay_index;
1058 u_char max_tags_index;
1060 #define TEKRAM_F2_F6_ENABLED (1)
1063 typedef struct Tekram_nvram Tekram_nvram;
1064 typedef struct Tekram_target Tekram_target;
1066 #endif /* SCSI_NCR_NVRAM_SUPPORT */
1068 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
1070 /*-----------------------------------------------------------------
1072 ** The ncr 53c810 register structure.
1074 **-----------------------------------------------------------------
1078 /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
1080 /*01*/ u_char nc_scntl1; /* no reset */
1081 #define ISCON 0x10 /* connected to scsi */
1082 #define CRST 0x08 /* force reset */
1083 #define IARB 0x02 /* immediate arbitration */
1085 /*02*/ u_char nc_scntl2; /* no disconnect expected */
1086 #define SDU 0x80 /* cmd: disconnect will raise error */
1087 #define CHM 0x40 /* sta: chained mode */
1088 #define WSS 0x08 /* sta: wide scsi send [W]*/
1089 #define WSR 0x01 /* sta: wide scsi received [W]*/
1091 /*03*/ u_char nc_scntl3; /* cnf system clock dependent */
1092 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
1093 #define ULTRA 0x80 /* cmd: ULTRA enable */
1094 /* bits 0-2, 7 rsvd for C1010 */
1096 /*04*/ u_char nc_scid; /* cnf host adapter scsi address */
1097 #define RRE 0x40 /* r/w:e enable response to resel. */
1098 #define SRE 0x20 /* r/w:e enable response to select */
1100 /*05*/ u_char nc_sxfer; /* ### Sync speed and count */
1101 /* bits 6-7 rsvd for C1010 */
1103 /*06*/ u_char nc_sdid; /* ### Destination-ID */
1105 /*07*/ u_char nc_gpreg; /* ??? IO-Pins */
1107 /*08*/ u_char nc_sfbr; /* ### First byte in phase */
1109 /*09*/ u_char nc_socl;
1110 #define CREQ 0x80 /* r/w: SCSI-REQ */
1111 #define CACK 0x40 /* r/w: SCSI-ACK */
1112 #define CBSY 0x20 /* r/w: SCSI-BSY */
1113 #define CSEL 0x10 /* r/w: SCSI-SEL */
1114 #define CATN 0x08 /* r/w: SCSI-ATN */
1115 #define CMSG 0x04 /* r/w: SCSI-MSG */
1116 #define CC_D 0x02 /* r/w: SCSI-C_D */
1117 #define CI_O 0x01 /* r/w: SCSI-I_O */
1119 /*0a*/ u_char nc_ssid;
1121 /*0b*/ u_char nc_sbcl;
1123 /*0c*/ u_char nc_dstat;
1124 #define DFE 0x80 /* sta: dma fifo empty */
1125 #define MDPE 0x40 /* int: master data parity error */
1126 #define BF 0x20 /* int: script: bus fault */
1127 #define ABRT 0x10 /* int: script: command aborted */
1128 #define SSI 0x08 /* int: script: single step */
1129 #define SIR 0x04 /* int: script: interrupt instruct. */
1130 #define IID 0x01 /* int: script: illegal instruct. */
1132 /*0d*/ u_char nc_sstat0;
1133 #define ILF 0x80 /* sta: data in SIDL register lsb */
1134 #define ORF 0x40 /* sta: data in SODR register lsb */
1135 #define OLF 0x20 /* sta: data in SODL register lsb */
1136 #define AIP 0x10 /* sta: arbitration in progress */
1137 #define LOA 0x08 /* sta: arbitration lost */
1138 #define WOA 0x04 /* sta: arbitration won */
1139 #define IRST 0x02 /* sta: scsi reset signal */
1140 #define SDP 0x01 /* sta: scsi parity signal */
1142 /*0e*/ u_char nc_sstat1;
1143 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
1145 /*0f*/ u_char nc_sstat2;
1146 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
1147 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
1148 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
1149 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
1150 #define LDSC 0x02 /* sta: disconnect & reconnect */
1152 /*10*/ u_char nc_dsa; /* --> Base page */
1153 /*11*/ u_char nc_dsa1;
1154 /*12*/ u_char nc_dsa2;
1155 /*13*/ u_char nc_dsa3;
1157 /*14*/ u_char nc_istat; /* --> Main Command and status */
1158 #define CABRT 0x80 /* cmd: abort current operation */
1159 #define SRST 0x40 /* mod: reset chip */
1160 #define SIGP 0x20 /* r/w: message from host to ncr */
1161 #define SEM 0x10 /* r/w: message between host + ncr */
1162 #define CON 0x08 /* sta: connected to scsi */
1163 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
1164 #define SIP 0x02 /* sta: scsi-interrupt */
1165 #define DIP 0x01 /* sta: host/script interrupt */
1167 /*15*/ u_char nc_istat1; /* 896 and later cores only */
1168 #define FLSH 0x04 /* sta: chip is flushing */
1169 #define SRUN 0x02 /* sta: scripts are running */
1170 #define SIRQD 0x01 /* r/w: disable INT pin */
1172 /*16*/ u_char nc_mbox0; /* 896 and later cores only */
1173 /*17*/ u_char nc_mbox1; /* 896 and later cores only */
1175 /*18*/ u_char nc_ctest0;
1176 #define EHP 0x04 /* 720 even host parity */
1177 /*19*/ u_char nc_ctest1;
1179 /*1a*/ u_char nc_ctest2;
1181 /* bits 0-2,7 rsvd for C1010 */
1183 /*1b*/ u_char nc_ctest3;
1184 #define FLF 0x08 /* cmd: flush dma fifo */
1185 #define CLF 0x04 /* cmd: clear dma fifo */
1186 #define FM 0x02 /* mod: fetch pin mode */
1187 #define WRIE 0x01 /* mod: write and invalidate enable */
1188 /* bits 4-7 rsvd for C1010 */
1190 /*1c*/ u32 nc_temp; /* ### Temporary stack */
1192 /*20*/ u_char nc_dfifo;
1193 /*21*/ u_char nc_ctest4;
1194 #define MUX 0x80 /* 720 host bus multiplex mode */
1195 #define BDIS 0x80 /* mod: burst disable */
1196 #define MPEE 0x08 /* mod: master parity error enable */
1198 /*22*/ u_char nc_ctest5;
1199 #define DFS 0x20 /* mod: dma fifo size */
1200 /* bits 0-1, 3-7 rsvd for C1010 */
1201 /*23*/ u_char nc_ctest6;
1203 /*24*/ u32 nc_dbc; /* ### Byte count and command */
1204 /*28*/ u32 nc_dnad; /* ### Next command register */
1205 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
1206 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
1208 /*34*/ u_char nc_scratcha; /* Temporary register a */
1209 /*35*/ u_char nc_scratcha1;
1210 /*36*/ u_char nc_scratcha2;
1211 /*37*/ u_char nc_scratcha3;
1213 /*38*/ u_char nc_dmode;
1214 #define BL_2 0x80 /* mod: burst length shift value +2 */
1215 #define BL_1 0x40 /* mod: burst length shift value +1 */
1216 #define ERL 0x08 /* mod: enable read line */
1217 #define ERMP 0x04 /* mod: enable read multiple */
1218 #define BOF 0x02 /* mod: burst op code fetch */
1220 /*39*/ u_char nc_dien;
1221 /*3a*/ u_char nc_sbr;
1223 /*3b*/ u_char nc_dcntl; /* --> Script execution control */
1224 #define CLSE 0x80 /* mod: cache line size enable */
1225 #define PFF 0x40 /* cmd: pre-fetch flush */
1226 #define PFEN 0x20 /* mod: pre-fetch enable */
1227 #define EA 0x20 /* mod: 720 enable-ack */
1228 #define SSM 0x10 /* mod: single step mode */
1229 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
1230 #define STD 0x04 /* cmd: start dma mode */
1231 #define IRQD 0x02 /* mod: irq disable */
1232 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
1233 /* bits 0-1 rsvd for C1010 */
1235 /*3c*/ u32 nc_adder;
1237 /*40*/ u_short nc_sien; /* -->: interrupt enable */
1238 /*42*/ u_short nc_sist; /* <--: interrupt status */
1239 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
1240 #define STO 0x0400/* sta: timeout (select) */
1241 #define GEN 0x0200/* sta: timeout (general) */
1242 #define HTH 0x0100/* sta: timeout (handshake) */
1243 #define MA 0x80 /* sta: phase mismatch */
1244 #define CMP 0x40 /* sta: arbitration complete */
1245 #define SEL 0x20 /* sta: selected by another device */
1246 #define RSL 0x10 /* sta: reselected by another device*/
1247 #define SGE 0x08 /* sta: gross error (over/underflow)*/
1248 #define UDC 0x04 /* sta: unexpected disconnect */
1249 #define RST 0x02 /* sta: scsi bus reset detected */
1250 #define PAR 0x01 /* sta: scsi parity error */
1252 /*44*/ u_char nc_slpar;
1253 /*45*/ u_char nc_swide;
1254 /*46*/ u_char nc_macntl;
1255 /*47*/ u_char nc_gpcntl;
1256 /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
1257 /*49*/ u_char nc_stime1; /* cmd: timeout user defined */
1258 /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
1260 /*4c*/ u_char nc_stest0;
1262 /*4d*/ u_char nc_stest1;
1263 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
1264 #define DBLEN 0x08 /* clock doubler running */
1265 #define DBLSEL 0x04 /* clock doubler selected */
1268 /*4e*/ u_char nc_stest2;
1269 #define ROF 0x40 /* reset scsi offset (after gross error!) */
1270 #define DIF 0x20 /* 720 SCSI differential mode */
1271 #define EXT 0x02 /* extended filtering */
1273 /*4f*/ u_char nc_stest3;
1274 #define TE 0x80 /* c: tolerAnt enable */
1275 #define HSC 0x20 /* c: Halt SCSI Clock */
1276 #define CSF 0x02 /* c: clear scsi fifo */
1278 /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
1279 /*52*/ u_char nc_stest4;
1280 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
1281 #define SMODE_HVD 0x40 /* High Voltage Differential */
1282 #define SMODE_SE 0x80 /* Single Ended */
1283 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
1284 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
1285 /* bits 0-5 rsvd for C1010 */
1287 /*53*/ u_char nc_53_;
1288 /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
1289 /*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
1290 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
1291 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
1292 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
1293 #define DISFC 0x10 /* Disable Auto FIFO Clear */
1294 #define DILS 0x02 /* Disable Internal Load/Store */
1295 #define DPR 0x01 /* Disable Pipe Req */
1297 /*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
1298 #define ZMOD 0x80 /* High Impedance Mode */
1299 #define DIC 0x10 /* Disable Internal Cycles */
1300 #define DDAC 0x08 /* Disable Dual Address Cycle */
1301 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
1302 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
1303 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
1305 /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
1306 /*5a*/ u_short nc_5a_;
1308 /*5c*/ u_char nc_scr0; /* Working register B */
1309 /*5d*/ u_char nc_scr1; /* */
1310 /*5e*/ u_char nc_scr2; /* */
1311 /*5f*/ u_char nc_scr3; /* */
1313 /*60*/ u_char nc_scrx[64]; /* Working register C-R */
1314 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
1315 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
1316 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
1317 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
1318 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
1319 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
1320 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
1321 /*bc*/ u_short nc_scntl4; /* C1010 only */
1322 #define U3EN 0x80 /* Enable Ultra 3 */
1323 #define AIPEN 0x40 /* Allow check upper byte lanes */
1324 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
1326 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
1329 /*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */
1330 /*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */
1332 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
1333 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
1334 /*c8*/ u_char nc_rbc; /* Remaining Byte Count */
1335 /*c9*/ u_char nc_rbc1; /* */
1336 /*ca*/ u_char nc_rbc2; /* */
1337 /*cb*/ u_char nc_rbc3; /* */
1339 /*cc*/ u_char nc_ua; /* Updated Address */
1340 /*cd*/ u_char nc_ua1; /* */
1341 /*ce*/ u_char nc_ua2; /* */
1342 /*cf*/ u_char nc_ua3; /* */
1343 /*d0*/ u32 nc_esa; /* Entry Storage Address */
1344 /*d4*/ u_char nc_ia; /* Instruction Address */
1345 /*d5*/ u_char nc_ia1;
1346 /*d6*/ u_char nc_ia2;
1347 /*d7*/ u_char nc_ia3;
1348 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
1349 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
1351 /* Following for C1010 only */
1352 /*e0*/ u_short nc_crcpad; /* CRC Value */
1353 /*e2*/ u_char nc_crccntl0; /* CRC control register */
1354 #define SNDCRC 0x10 /* Send CRC Request */
1355 /*e3*/ u_char nc_crccntl1; /* CRC control register */
1356 /*e4*/ u32 nc_crcdata; /* CRC data register */
1357 /*e8*/ u32 nc_e8_; /* rsvd */
1358 /*ec*/ u32 nc_ec_; /* rsvd */
1359 /*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */
1363 /*-----------------------------------------------------------
1365 ** Utility macros for the script.
1367 **-----------------------------------------------------------
1370 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
1371 #define REG(r) REGJ (nc_, r)
1375 /*-----------------------------------------------------------
1379 ** DT phases illegal for ncr driver.
1381 **-----------------------------------------------------------
1384 #define SCR_DATA_OUT 0x00000000
1385 #define SCR_DATA_IN 0x01000000
1386 #define SCR_COMMAND 0x02000000
1387 #define SCR_STATUS 0x03000000
1388 #define SCR_DT_DATA_OUT 0x04000000
1389 #define SCR_DT_DATA_IN 0x05000000
1390 #define SCR_MSG_OUT 0x06000000
1391 #define SCR_MSG_IN 0x07000000
1393 #define SCR_ILG_OUT 0x04000000
1394 #define SCR_ILG_IN 0x05000000
1396 /*-----------------------------------------------------------
1398 ** Data transfer via SCSI.
1400 **-----------------------------------------------------------
1403 ** <<start address>>
1411 **-----------------------------------------------------------
1414 #define OPC_MOVE 0x08000000
1416 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
1417 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
1418 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
1420 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
1421 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
1422 #define SCR_CHMOV_TBL (0x10000000)
1424 struct scr_tblmove {
1429 /*-----------------------------------------------------------
1433 **-----------------------------------------------------------
1435 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
1436 ** <<alternate_address>>
1438 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
1439 ** <<alternate_address>>
1441 **-----------------------------------------------------------
1444 #define SCR_SEL_ABS 0x40000000
1445 #define SCR_SEL_ABS_ATN 0x41000000
1446 #define SCR_SEL_TBL 0x42000000
1447 #define SCR_SEL_TBL_ATN 0x43000000
1450 #ifdef SCSI_NCR_BIG_ENDIAN
1466 #define SCR_JMP_REL 0x04000000
1467 #define SCR_ID(id) (((u32)(id)) << 16)
1469 /*-----------------------------------------------------------
1471 ** Waiting for Disconnect or Reselect
1473 **-----------------------------------------------------------
1476 ** dummy: <<alternate_address>>
1479 ** <<alternate_address>>
1481 **-----------------------------------------------------------
1484 #define SCR_WAIT_DISC 0x48000000
1485 #define SCR_WAIT_RESEL 0x50000000
1487 /*-----------------------------------------------------------
1491 **-----------------------------------------------------------
1493 ** SET (flags {|.. })
1495 ** CLR (flags {|.. })
1497 **-----------------------------------------------------------
1500 #define SCR_SET(f) (0x58000000 | (f))
1501 #define SCR_CLR(f) (0x60000000 | (f))
1503 #define SCR_CARRY 0x00000400
1504 #define SCR_TRG 0x00000200
1505 #define SCR_ACK 0x00000040
1506 #define SCR_ATN 0x00000008
1511 /*-----------------------------------------------------------
1513 ** Memory to memory move
1515 **-----------------------------------------------------------
1518 ** << source_address >>
1519 ** << destination_address >>
1521 ** SCR_COPY sets the NO FLUSH option by default.
1522 ** SCR_COPY_F does not set this option.
1524 ** For chips which do not support this option,
1525 ** ncr_copy_and_bind() will remove this bit.
1526 **-----------------------------------------------------------
1529 #define SCR_NO_FLUSH 0x01000000
1531 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1532 #define SCR_COPY_F(n) (0xc0000000 | (n))
1534 /*-----------------------------------------------------------
1536 ** Register move and binary operations
1538 **-----------------------------------------------------------
1540 ** SFBR_REG (reg, op, data) reg = SFBR op data
1543 ** REG_SFBR (reg, op, data) SFBR = reg op data
1546 ** REG_REG (reg, op, data) reg = reg op data
1549 **-----------------------------------------------------------
1550 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1551 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1552 ** The 896 has additionnal IO registers starting at
1553 ** offset 0x80. Bit 7 of register offset is stored in
1554 ** bit 7 of the SCRIPTS instruction first DWORD.
1555 **-----------------------------------------------------------
1558 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1560 #define SCR_SFBR_REG(reg,op,data) \
1561 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1563 #define SCR_REG_SFBR(reg,op,data) \
1564 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1566 #define SCR_REG_REG(reg,op,data) \
1567 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1570 #define SCR_LOAD 0x00000000
1571 #define SCR_SHL 0x01000000
1572 #define SCR_OR 0x02000000
1573 #define SCR_XOR 0x03000000
1574 #define SCR_AND 0x04000000
1575 #define SCR_SHR 0x05000000
1576 #define SCR_ADD 0x06000000
1577 #define SCR_ADDC 0x07000000
1579 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1581 /*-----------------------------------------------------------
1583 ** FROM_REG (reg) SFBR = reg
1586 ** TO_REG (reg) reg = SFBR
1589 ** LOAD_REG (reg, data) reg = <data>
1592 ** LOAD_SFBR(data) SFBR = <data>
1595 **-----------------------------------------------------------
1598 #define SCR_FROM_REG(reg) \
1599 SCR_REG_SFBR(reg,SCR_OR,0)
1601 #define SCR_TO_REG(reg) \
1602 SCR_SFBR_REG(reg,SCR_OR,0)
1604 #define SCR_LOAD_REG(reg,data) \
1605 SCR_REG_REG(reg,SCR_LOAD,data)
1607 #define SCR_LOAD_SFBR(data) \
1608 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1610 /*-----------------------------------------------------------
1612 ** LOAD from memory to register.
1613 ** STORE from register to memory.
1615 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1617 **-----------------------------------------------------------
1620 ** <<start address>>
1622 ** LOAD_REL (LEN) (DSA relative)
1625 **-----------------------------------------------------------
1628 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1629 #define SCR_NO_FLUSH2 0x02000000
1630 #define SCR_DSA_REL2 0x10000000
1632 #define SCR_LOAD_R(reg, how, n) \
1633 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1635 #define SCR_STORE_R(reg, how, n) \
1636 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1638 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1639 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1640 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1641 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1643 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1644 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1645 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1646 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1649 /*-----------------------------------------------------------
1651 ** Waiting for Disconnect or Reselect
1653 **-----------------------------------------------------------
1655 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1658 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1661 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1664 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1667 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1670 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1673 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1680 ** DATA (data, mask)
1682 **-----------------------------------------------------------
1685 #define SCR_NO_OP 0x80000000
1686 #define SCR_JUMP 0x80080000
1687 #define SCR_JUMP64 0x80480000
1688 #define SCR_JUMPR 0x80880000
1689 #define SCR_CALL 0x88080000
1690 #define SCR_CALLR 0x88880000
1691 #define SCR_RETURN 0x90080000
1692 #define SCR_INT 0x98080000
1693 #define SCR_INT_FLY 0x98180000
1695 #define IFFALSE(arg) (0x00080000 | (arg))
1696 #define IFTRUE(arg) (0x00000000 | (arg))
1698 #define WHEN(phase) (0x00030000 | (phase))
1699 #define IF(phase) (0x00020000 | (phase))
1701 #define DATA(D) (0x00040000 | ((D) & 0xff))
1702 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1704 #define CARRYSET (0x00200000)
1706 /*-----------------------------------------------------------
1710 **-----------------------------------------------------------
1717 #define M_COMPLETE (0x00)
1718 #define M_EXTENDED (0x01)
1719 #define M_SAVE_DP (0x02)
1720 #define M_RESTORE_DP (0x03)
1721 #define M_DISCONNECT (0x04)
1722 #define M_ID_ERROR (0x05)
1723 #define M_ABORT (0x06)
1724 #define M_REJECT (0x07)
1725 #define M_NOOP (0x08)
1726 #define M_PARITY (0x09)
1727 #define M_LCOMPLETE (0x0a)
1728 #define M_FCOMPLETE (0x0b)
1729 #define M_RESET (0x0c)
1730 #define M_ABORT_TAG (0x0d)
1731 #define M_CLEAR_QUEUE (0x0e)
1732 #define M_INIT_REC (0x0f)
1733 #define M_REL_REC (0x10)
1734 #define M_TERMINATE (0x11)
1735 #define M_SIMPLE_TAG (0x20)
1736 #define M_HEAD_TAG (0x21)
1737 #define M_ORDERED_TAG (0x22)
1738 #define M_IGN_RESIDUE (0x23)
1739 #define M_IDENTIFY (0x80)
1741 #define M_X_MODIFY_DP (0x00)
1742 #define M_X_SYNC_REQ (0x01)
1743 #define M_X_WIDE_REQ (0x03)
1744 #define M_X_PPR_REQ (0x04)
1750 #define S_GOOD (0x00)
1751 #define S_CHECK_COND (0x02)
1752 #define S_COND_MET (0x04)
1753 #define S_BUSY (0x08)
1754 #define S_INT (0x10)
1755 #define S_INT_COND_MET (0x14)
1756 #define S_CONFLICT (0x18)
1757 #define S_TERMINATED (0x20)
1758 #define S_QUEUE_FULL (0x28)
1759 #define S_ILLEGAL (0xff)
1760 #define S_SENSE (0x80)
1763 * End of ncrreg from FreeBSD
1766 #endif /* !defined HOSTS_C */
1768 #endif /* defined SYM53C8XX_DEFS_H */