1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
4 ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
14 **-----------------------------------------------------------------------------
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30 **-----------------------------------------------------------------------------
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
35 ** Gerard Roudier <groudier@free.fr>
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
46 **-----------------------------------------------------------------------------
48 ** Major contributions:
49 ** --------------------
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
54 ** Added support for MIPS big endian systems.
55 ** Carsten Langgaard, carstenl@mips.com
56 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
58 ** Added support for HP PARISC big endian systems.
59 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
61 *******************************************************************************
64 #ifndef SYM53C8XX_DEFS_H
65 #define SYM53C8XX_DEFS_H
67 #include <linux/config.h>
69 /* These options are not tunable from 'make config' */
70 #define SCSI_NCR_PROC_INFO_SUPPORT
73 ** If you want a driver as small as possible, donnot define the
76 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
77 #define SCSI_NCR_DEBUG_INFO_SUPPORT
78 #ifdef SCSI_NCR_PROC_INFO_SUPPORT
79 # define SCSI_NCR_USER_COMMAND_SUPPORT
80 # define SCSI_NCR_USER_INFO_SUPPORT
84 ** To disable integrity checking, do not define the
87 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
88 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
91 /* ---------------------------------------------------------------------
92 ** Take into account kernel configured parameters.
93 ** Most of these options can be overridden at startup by a command line.
94 ** ---------------------------------------------------------------------
98 * For Ultra2 and Ultra3 SCSI support option, use special features.
100 * Value (default) means:
101 * bit 0 : all features enabled, except:
102 * bit 1 : PCI Write And Invalidate.
103 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
105 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
106 * enabled by the driver.
108 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
110 #define SCSI_NCR_MAX_SYNC (80)
113 * Allow tags from 2 to 256, default 8
115 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
116 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
117 #define SCSI_NCR_MAX_TAGS (2)
118 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
119 #define SCSI_NCR_MAX_TAGS (256)
121 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
124 #define SCSI_NCR_MAX_TAGS (8)
128 * Allow tagged command queuing support if configured with default number
129 * of tags set to max (see above).
131 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
132 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
133 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
134 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
136 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
140 * Immediate arbitration
142 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
143 #define SCSI_NCR_IARB_SUPPORT
147 * Sync transfer frequency at startup.
148 * Allow from 5Mhz to 80Mhz default 20 Mhz.
150 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
151 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
152 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
153 #undef CONFIG_SCSI_NCR53C8XX_SYNC
154 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
157 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
158 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
159 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
160 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
161 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
162 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
163 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
164 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
165 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
166 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
168 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
172 * Disallow disconnections at boot-up
174 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
175 #define SCSI_NCR_SETUP_DISCONNECTION (0)
177 #define SCSI_NCR_SETUP_DISCONNECTION (1)
181 * Force synchronous negotiation for all targets
183 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
184 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
186 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
190 * Disable master parity checking (flawed hardwares need that)
192 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
193 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
195 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
199 * Disable scsi parity checking (flawed devices may need that)
201 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
202 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
204 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
208 * Settle time after reset at boot-up
210 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
213 ** Bridge quirks work-around option defaulted to 1.
215 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
216 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
220 ** Work-around common bridge misbehaviour.
222 ** - Do not flush posted writes in the opposite
223 ** direction on read.
224 ** - May reorder DMA writes to memory.
226 ** This option should not affect performances
227 ** significantly, so it is the default.
229 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
230 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
231 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
232 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
235 ** Same as option 1, but also deal with
236 ** misconfigured interrupts.
238 ** - Edge triggerred instead of level sensitive.
239 ** - No interrupt line connected.
240 ** - IRQ number misconfigured.
242 ** If no interrupt is delivered, the driver will
243 ** catch the interrupt conditions 10 times per
244 ** second. No need to say that this option is
247 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
248 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
249 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
250 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
251 #define SCSI_NCR_PCIQ_BROKEN_INTR
254 ** Some bridge designers decided to flush
255 ** everything prior to deliver the interrupt.
256 ** This option tries to deal with such a
259 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
260 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
264 ** Other parameters not configurable with "make config"
265 ** Avoid to change these constants, unless you know what you are doing.
268 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
269 #define SCSI_NCR_MAX_SCATTER (127)
270 #define SCSI_NCR_MAX_TARGET (16)
273 ** Compute some desirable value for CAN_QUEUE
275 ** The driver will use lower values if these
276 ** ones appear to be too large.
278 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
279 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
281 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
282 #define SCSI_NCR_TIMER_INTERVAL (HZ)
284 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
285 #define SCSI_NCR_MAX_LUN (16)
287 #define SCSI_NCR_MAX_LUN (1)
291 ** These simple macros limit expression involving
292 ** kernel time values (jiffies) to some that have
293 ** chance not to be too much incorrect. :-)
295 #define ktime_get(o) (jiffies + (u_long) o)
296 #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
297 #define ktime_dif(a, b) ((long)(a) - (long)(b))
298 /* These ones are not used in this driver */
299 #define ktime_add(a, o) ((a) + (u_long)(o))
300 #define ktime_sub(a, o) ((a) - (u_long)(o))
304 * IO functions definition for big/little endian CPU support.
305 * For now, the NCR is only supported in little endian addressing mode,
312 #define outw_b2l outw
313 #define outl_b2l outl
315 #define readb_raw readb
316 #define writeb_raw writeb
318 #if defined(SCSI_NCR_BIG_ENDIAN)
319 #define readw_l2b __raw_readw
320 #define readl_l2b __raw_readl
321 #define writew_b2l __raw_writew
322 #define writel_b2l __raw_writel
323 #define readw_raw __raw_readw
324 #define readl_raw(a) __raw_readl((unsigned long)(a))
325 #define writew_raw __raw_writew
326 #define writel_raw(v,a) __raw_writel(v,(unsigned long)(a))
327 #else /* Other big-endian */
328 #define readw_l2b readw
329 #define readl_l2b readl
330 #define writew_b2l writew
331 #define writel_b2l writel
332 #define readw_raw readw
333 #define readl_raw readl
334 #define writew_raw writew
335 #define writel_raw writel
338 #else /* little endian */
342 #define outw_raw outw
343 #define outl_raw outl
345 #define readb_raw readb
346 #define readw_raw readw
347 #define readl_raw readl
348 #define writeb_raw writeb
349 #define writew_raw writew
350 #define writel_raw writel
354 #if !defined(__hppa__) && !defined(__mips__)
355 #ifdef SCSI_NCR_BIG_ENDIAN
356 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
360 #define MEMORY_BARRIER() mb()
364 * If the NCR uses big endian addressing mode over the
365 * PCI, actual io register addresses for byte and word
366 * accesses must be changed according to lane routing.
367 * Btw, ncr_offb() and ncr_offw() macros only apply to
368 * constants and so donnot generate bloated code.
371 #if defined(SCSI_NCR_BIG_ENDIAN)
373 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
374 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
378 #define ncr_offb(o) (o)
379 #define ncr_offw(o) (o)
384 * If the CPU and the NCR use same endian-ness addressing,
385 * no byte reordering is needed for script patching.
386 * Macro cpu_to_scr() is to be used for script patching.
387 * Macro scr_to_cpu() is to be used for getting a DWORD
391 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
393 #define cpu_to_scr(dw) cpu_to_le32(dw)
394 #define scr_to_cpu(dw) le32_to_cpu(dw)
396 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
398 #define cpu_to_scr(dw) cpu_to_be32(dw)
399 #define scr_to_cpu(dw) be32_to_cpu(dw)
403 #define cpu_to_scr(dw) (dw)
404 #define scr_to_cpu(dw) (dw)
409 * Access to the controller chip.
411 * If the CPU and the NCR use same endian-ness addressing,
412 * no byte reordering is needed for accessing chip io
413 * registers. Functions suffixed by '_raw' are assumed
414 * to access the chip over the PCI without doing byte
415 * reordering. Functions suffixed by '_l2b' are
416 * assumed to perform little-endian to big-endian byte
417 * reordering, those suffixed by '_b2l' blah, blah,
422 * MEMORY mapped IO input / output
425 #define INB_OFF(o) readb_raw((char *)np->reg + ncr_offb(o))
426 #define OUTB_OFF(o, val) writeb_raw((val), (char *)np->reg + ncr_offb(o))
428 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
430 #define INW_OFF(o) readw_l2b((char *)np->reg + ncr_offw(o))
431 #define INL_OFF(o) readl_l2b((char *)np->reg + (o))
433 #define OUTW_OFF(o, val) writew_b2l((val), (char *)np->reg + ncr_offw(o))
434 #define OUTL_OFF(o, val) writel_b2l((val), (char *)np->reg + (o))
436 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
438 #define INW_OFF(o) readw_b2l((char *)np->reg + ncr_offw(o))
439 #define INL_OFF(o) readl_b2l((char *)np->reg + (o))
441 #define OUTW_OFF(o, val) writew_l2b((val), (char *)np->reg + ncr_offw(o))
442 #define OUTL_OFF(o, val) writel_l2b((val), (char *)np->reg + (o))
446 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
447 /* Only 8 or 32 bit transfers allowed */
448 #define INW_OFF(o) (readb((char *)np->reg + ncr_offw(o)) << 8 | readb((char *)np->reg + ncr_offw(o) + 1))
450 #define INW_OFF(o) readw_raw((char *)np->reg + ncr_offw(o))
452 #define INL_OFF(o) readl_raw((char *)np->reg + (o))
454 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
455 /* Only 8 or 32 bit transfers allowed */
456 #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char *)np->reg + ncr_offw(o)); writeb((char)(val), (char *)np->reg + ncr_offw(o) + 1); } while (0)
458 #define OUTW_OFF(o, val) writew_raw((val), (char *)np->reg + ncr_offw(o))
460 #define OUTL_OFF(o, val) writel_raw((val), (char *)np->reg + (o))
464 #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
465 #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
466 #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
468 #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
469 #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
470 #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
473 * Set bit field ON, OFF
476 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
477 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
478 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
479 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
480 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
481 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
484 * We normally want the chip to have a consistent view
485 * of driver internal data structures when we restart it.
488 #define OUTL_DSP(v) \
491 OUTL (nc_dsp, (v)); \
494 #define OUTONB_STD() \
497 OUTONB (nc_dcntl, (STD|NOCOM)); \
502 ** NCR53C8XX devices features table.
505 unsigned short revision_id;
506 unsigned char burst_max; /* log-base-2 of max burst */
507 unsigned char offset_max;
508 unsigned char nr_divisor;
509 unsigned int features;
510 #define FE_LED0 (1<<0)
511 #define FE_WIDE (1<<1) /* Wide data transfers */
512 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
513 #define FE_DBLR (1<<4) /* Clock doubler present */
514 #define FE_QUAD (1<<5) /* Clock quadrupler present */
515 #define FE_ERL (1<<6) /* Enable read line */
516 #define FE_CLSE (1<<7) /* Cache line size enable */
517 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
518 #define FE_ERMP (1<<9) /* Enable read multiple */
519 #define FE_BOF (1<<10) /* Burst opcode fetch */
520 #define FE_DFS (1<<11) /* DMA fifo size */
521 #define FE_PFEN (1<<12) /* Prefetch enable */
522 #define FE_LDSTR (1<<13) /* Load/Store supported */
523 #define FE_RAM (1<<14) /* On chip RAM present */
524 #define FE_VARCLK (1<<15) /* SCSI clock may vary */
525 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
526 #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
527 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
528 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
529 #define FE_LEDC (1<<20) /* Hardware control of LED */
530 #define FE_DIFF (1<<21) /* Support Differential SCSI */
531 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
532 #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
533 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
534 #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
535 #define FE_EHP (1<<27) /* 720: Even host parity */
536 #define FE_MUX (1<<28) /* 720: Multiplexed bus */
537 #define FE_EA (1<<29) /* 720: Enable Ack */
539 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
540 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
541 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
546 ** Driver setup structure.
548 ** This structure is initialized from linux config options.
549 ** It can be overridden at boot-up by the boot command line.
551 #define SCSI_NCR_MAX_EXCLUDES 8
552 struct ncr_driver_setup {
576 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
582 ** Can be overriden at startup by a command line.
584 #define SCSI_NCR_DRIVER_SETUP \
586 SCSI_NCR_SETUP_MASTER_PARITY, \
587 SCSI_NCR_SETUP_SCSI_PARITY, \
588 SCSI_NCR_SETUP_DISCONNECTION, \
589 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
590 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
595 SCSI_NCR_SETUP_DEFAULT_TAGS, \
596 SCSI_NCR_SETUP_DEFAULT_SYNC, \
601 SCSI_NCR_SETUP_SETTLE_TIME, \
612 ** Boot fail safe setup.
613 ** Override initial setup from boot command line:
616 #define SCSI_NCR_DRIVER_SAFE_SETUP \
642 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
644 /*-----------------------------------------------------------------
646 ** The ncr 53c810 register structure.
648 **-----------------------------------------------------------------
652 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
654 /*01*/ u8 nc_scntl1; /* no reset */
655 #define ISCON 0x10 /* connected to scsi */
656 #define CRST 0x08 /* force reset */
657 #define IARB 0x02 /* immediate arbitration */
659 /*02*/ u8 nc_scntl2; /* no disconnect expected */
660 #define SDU 0x80 /* cmd: disconnect will raise error */
661 #define CHM 0x40 /* sta: chained mode */
662 #define WSS 0x08 /* sta: wide scsi send [W]*/
663 #define WSR 0x01 /* sta: wide scsi received [W]*/
665 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
666 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
667 #define ULTRA 0x80 /* cmd: ULTRA enable */
668 /* bits 0-2, 7 rsvd for C1010 */
670 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
671 #define RRE 0x40 /* r/w:e enable response to resel. */
672 #define SRE 0x20 /* r/w:e enable response to select */
674 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
675 /* bits 6-7 rsvd for C1010 */
677 /*06*/ u8 nc_sdid; /* ### Destination-ID */
679 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
681 /*08*/ u8 nc_sfbr; /* ### First byte in phase */
684 #define CREQ 0x80 /* r/w: SCSI-REQ */
685 #define CACK 0x40 /* r/w: SCSI-ACK */
686 #define CBSY 0x20 /* r/w: SCSI-BSY */
687 #define CSEL 0x10 /* r/w: SCSI-SEL */
688 #define CATN 0x08 /* r/w: SCSI-ATN */
689 #define CMSG 0x04 /* r/w: SCSI-MSG */
690 #define CC_D 0x02 /* r/w: SCSI-C_D */
691 #define CI_O 0x01 /* r/w: SCSI-I_O */
698 #define DFE 0x80 /* sta: dma fifo empty */
699 #define MDPE 0x40 /* int: master data parity error */
700 #define BF 0x20 /* int: script: bus fault */
701 #define ABRT 0x10 /* int: script: command aborted */
702 #define SSI 0x08 /* int: script: single step */
703 #define SIR 0x04 /* int: script: interrupt instruct. */
704 #define IID 0x01 /* int: script: illegal instruct. */
707 #define ILF 0x80 /* sta: data in SIDL register lsb */
708 #define ORF 0x40 /* sta: data in SODR register lsb */
709 #define OLF 0x20 /* sta: data in SODL register lsb */
710 #define AIP 0x10 /* sta: arbitration in progress */
711 #define LOA 0x08 /* sta: arbitration lost */
712 #define WOA 0x04 /* sta: arbitration won */
713 #define IRST 0x02 /* sta: scsi reset signal */
714 #define SDP 0x01 /* sta: scsi parity signal */
717 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
720 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
721 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
722 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
723 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
724 #define LDSC 0x02 /* sta: disconnect & reconnect */
726 /*10*/ u8 nc_dsa; /* --> Base page */
731 /*14*/ u8 nc_istat; /* --> Main Command and status */
732 #define CABRT 0x80 /* cmd: abort current operation */
733 #define SRST 0x40 /* mod: reset chip */
734 #define SIGP 0x20 /* r/w: message from host to ncr */
735 #define SEM 0x10 /* r/w: message between host + ncr */
736 #define CON 0x08 /* sta: connected to scsi */
737 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
738 #define SIP 0x02 /* sta: scsi-interrupt */
739 #define DIP 0x01 /* sta: host/script interrupt */
741 /*15*/ u8 nc_istat1; /* 896 and later cores only */
742 #define FLSH 0x04 /* sta: chip is flushing */
743 #define SRUN 0x02 /* sta: scripts are running */
744 #define SIRQD 0x01 /* r/w: disable INT pin */
746 /*16*/ u8 nc_mbox0; /* 896 and later cores only */
747 /*17*/ u8 nc_mbox1; /* 896 and later cores only */
750 #define EHP 0x04 /* 720 even host parity */
755 /* bits 0-2,7 rsvd for C1010 */
758 #define FLF 0x08 /* cmd: flush dma fifo */
759 #define CLF 0x04 /* cmd: clear dma fifo */
760 #define FM 0x02 /* mod: fetch pin mode */
761 #define WRIE 0x01 /* mod: write and invalidate enable */
762 /* bits 4-7 rsvd for C1010 */
764 /*1c*/ u32 nc_temp; /* ### Temporary stack */
768 #define MUX 0x80 /* 720 host bus multiplex mode */
769 #define BDIS 0x80 /* mod: burst disable */
770 #define MPEE 0x08 /* mod: master parity error enable */
773 #define DFS 0x20 /* mod: dma fifo size */
774 /* bits 0-1, 3-7 rsvd for C1010 */
777 /*24*/ u32 nc_dbc; /* ### Byte count and command */
778 /*28*/ u32 nc_dnad; /* ### Next command register */
779 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
780 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
782 /*34*/ u8 nc_scratcha; /* Temporary register a */
783 /*35*/ u8 nc_scratcha1;
784 /*36*/ u8 nc_scratcha2;
785 /*37*/ u8 nc_scratcha3;
788 #define BL_2 0x80 /* mod: burst length shift value +2 */
789 #define BL_1 0x40 /* mod: burst length shift value +1 */
790 #define ERL 0x08 /* mod: enable read line */
791 #define ERMP 0x04 /* mod: enable read multiple */
792 #define BOF 0x02 /* mod: burst op code fetch */
797 /*3b*/ u8 nc_dcntl; /* --> Script execution control */
798 #define CLSE 0x80 /* mod: cache line size enable */
799 #define PFF 0x40 /* cmd: pre-fetch flush */
800 #define PFEN 0x20 /* mod: pre-fetch enable */
801 #define EA 0x20 /* mod: 720 enable-ack */
802 #define SSM 0x10 /* mod: single step mode */
803 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
804 #define STD 0x04 /* cmd: start dma mode */
805 #define IRQD 0x02 /* mod: irq disable */
806 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
807 /* bits 0-1 rsvd for C1010 */
811 /*40*/ u16 nc_sien; /* -->: interrupt enable */
812 /*42*/ u16 nc_sist; /* <--: interrupt status */
813 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
814 #define STO 0x0400/* sta: timeout (select) */
815 #define GEN 0x0200/* sta: timeout (general) */
816 #define HTH 0x0100/* sta: timeout (handshake) */
817 #define MA 0x80 /* sta: phase mismatch */
818 #define CMP 0x40 /* sta: arbitration complete */
819 #define SEL 0x20 /* sta: selected by another device */
820 #define RSL 0x10 /* sta: reselected by another device*/
821 #define SGE 0x08 /* sta: gross error (over/underflow)*/
822 #define UDC 0x04 /* sta: unexpected disconnect */
823 #define RST 0x02 /* sta: scsi bus reset detected */
824 #define PAR 0x01 /* sta: scsi parity error */
830 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
831 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
832 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
837 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
838 #define DBLEN 0x08 /* clock doubler running */
839 #define DBLSEL 0x04 /* clock doubler selected */
843 #define ROF 0x40 /* reset scsi offset (after gross error!) */
844 #define DIF 0x20 /* 720 SCSI differential mode */
845 #define EXT 0x02 /* extended filtering */
848 #define TE 0x80 /* c: tolerAnt enable */
849 #define HSC 0x20 /* c: Halt SCSI Clock */
850 #define CSF 0x02 /* c: clear scsi fifo */
852 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
854 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
855 #define SMODE_HVD 0x40 /* High Voltage Differential */
856 #define SMODE_SE 0x80 /* Single Ended */
857 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
858 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
859 /* bits 0-5 rsvd for C1010 */
862 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
863 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
864 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
865 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
866 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
867 #define DISFC 0x10 /* Disable Auto FIFO Clear */
868 #define DILS 0x02 /* Disable Internal Load/Store */
869 #define DPR 0x01 /* Disable Pipe Req */
871 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
872 #define ZMOD 0x80 /* High Impedance Mode */
873 #define DIC 0x10 /* Disable Internal Cycles */
874 #define DDAC 0x08 /* Disable Dual Address Cycle */
875 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
876 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
877 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
879 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
882 /*5c*/ u8 nc_scr0; /* Working register B */
883 /*5d*/ u8 nc_scr1; /* */
884 /*5e*/ u8 nc_scr2; /* */
885 /*5f*/ u8 nc_scr3; /* */
887 /*60*/ u8 nc_scrx[64]; /* Working register C-R */
888 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
889 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
890 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
891 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
892 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
893 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
894 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
895 /*bc*/ u16 nc_scntl4; /* C1010 only */
896 #define U3EN 0x80 /* Enable Ultra 3 */
897 #define AIPEN 0x40 /* Allow check upper byte lanes */
898 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
900 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
903 /*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
904 /*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
906 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
907 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
908 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
909 /*c9*/ u8 nc_rbc1; /* */
910 /*ca*/ u8 nc_rbc2; /* */
911 /*cb*/ u8 nc_rbc3; /* */
913 /*cc*/ u8 nc_ua; /* Updated Address */
914 /*cd*/ u8 nc_ua1; /* */
915 /*ce*/ u8 nc_ua2; /* */
916 /*cf*/ u8 nc_ua3; /* */
917 /*d0*/ u32 nc_esa; /* Entry Storage Address */
918 /*d4*/ u8 nc_ia; /* Instruction Address */
922 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
923 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
925 /* Following for C1010 only */
926 /*e0*/ u16 nc_crcpad; /* CRC Value */
927 /*e2*/ u8 nc_crccntl0; /* CRC control register */
928 #define SNDCRC 0x10 /* Send CRC Request */
929 /*e3*/ u8 nc_crccntl1; /* CRC control register */
930 /*e4*/ u32 nc_crcdata; /* CRC data register */
931 /*e8*/ u32 nc_e8_; /* rsvd */
932 /*ec*/ u32 nc_ec_; /* rsvd */
933 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
937 /*-----------------------------------------------------------
939 ** Utility macros for the script.
941 **-----------------------------------------------------------
944 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
945 #define REG(r) REGJ (nc_, r)
949 /*-----------------------------------------------------------
953 ** DT phases illegal for ncr driver.
955 **-----------------------------------------------------------
958 #define SCR_DATA_OUT 0x00000000
959 #define SCR_DATA_IN 0x01000000
960 #define SCR_COMMAND 0x02000000
961 #define SCR_STATUS 0x03000000
962 #define SCR_DT_DATA_OUT 0x04000000
963 #define SCR_DT_DATA_IN 0x05000000
964 #define SCR_MSG_OUT 0x06000000
965 #define SCR_MSG_IN 0x07000000
967 #define SCR_ILG_OUT 0x04000000
968 #define SCR_ILG_IN 0x05000000
970 /*-----------------------------------------------------------
972 ** Data transfer via SCSI.
974 **-----------------------------------------------------------
985 **-----------------------------------------------------------
988 #define OPC_MOVE 0x08000000
990 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
991 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
992 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
994 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
995 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
996 #define SCR_CHMOV_TBL (0x10000000)
1003 /*-----------------------------------------------------------
1007 **-----------------------------------------------------------
1009 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
1010 ** <<alternate_address>>
1012 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
1013 ** <<alternate_address>>
1015 **-----------------------------------------------------------
1018 #define SCR_SEL_ABS 0x40000000
1019 #define SCR_SEL_ABS_ATN 0x41000000
1020 #define SCR_SEL_TBL 0x42000000
1021 #define SCR_SEL_TBL_ATN 0x43000000
1024 #ifdef SCSI_NCR_BIG_ENDIAN
1040 #define SCR_JMP_REL 0x04000000
1041 #define SCR_ID(id) (((u32)(id)) << 16)
1043 /*-----------------------------------------------------------
1045 ** Waiting for Disconnect or Reselect
1047 **-----------------------------------------------------------
1050 ** dummy: <<alternate_address>>
1053 ** <<alternate_address>>
1055 **-----------------------------------------------------------
1058 #define SCR_WAIT_DISC 0x48000000
1059 #define SCR_WAIT_RESEL 0x50000000
1061 /*-----------------------------------------------------------
1065 **-----------------------------------------------------------
1067 ** SET (flags {|.. })
1069 ** CLR (flags {|.. })
1071 **-----------------------------------------------------------
1074 #define SCR_SET(f) (0x58000000 | (f))
1075 #define SCR_CLR(f) (0x60000000 | (f))
1077 #define SCR_CARRY 0x00000400
1078 #define SCR_TRG 0x00000200
1079 #define SCR_ACK 0x00000040
1080 #define SCR_ATN 0x00000008
1085 /*-----------------------------------------------------------
1087 ** Memory to memory move
1089 **-----------------------------------------------------------
1092 ** << source_address >>
1093 ** << destination_address >>
1095 ** SCR_COPY sets the NO FLUSH option by default.
1096 ** SCR_COPY_F does not set this option.
1098 ** For chips which do not support this option,
1099 ** ncr_copy_and_bind() will remove this bit.
1100 **-----------------------------------------------------------
1103 #define SCR_NO_FLUSH 0x01000000
1105 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1106 #define SCR_COPY_F(n) (0xc0000000 | (n))
1108 /*-----------------------------------------------------------
1110 ** Register move and binary operations
1112 **-----------------------------------------------------------
1114 ** SFBR_REG (reg, op, data) reg = SFBR op data
1117 ** REG_SFBR (reg, op, data) SFBR = reg op data
1120 ** REG_REG (reg, op, data) reg = reg op data
1123 **-----------------------------------------------------------
1124 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1125 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1126 ** The 896 has additionnal IO registers starting at
1127 ** offset 0x80. Bit 7 of register offset is stored in
1128 ** bit 7 of the SCRIPTS instruction first DWORD.
1129 **-----------------------------------------------------------
1132 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1134 #define SCR_SFBR_REG(reg,op,data) \
1135 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1137 #define SCR_REG_SFBR(reg,op,data) \
1138 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1140 #define SCR_REG_REG(reg,op,data) \
1141 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1144 #define SCR_LOAD 0x00000000
1145 #define SCR_SHL 0x01000000
1146 #define SCR_OR 0x02000000
1147 #define SCR_XOR 0x03000000
1148 #define SCR_AND 0x04000000
1149 #define SCR_SHR 0x05000000
1150 #define SCR_ADD 0x06000000
1151 #define SCR_ADDC 0x07000000
1153 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1155 /*-----------------------------------------------------------
1157 ** FROM_REG (reg) SFBR = reg
1160 ** TO_REG (reg) reg = SFBR
1163 ** LOAD_REG (reg, data) reg = <data>
1166 ** LOAD_SFBR(data) SFBR = <data>
1169 **-----------------------------------------------------------
1172 #define SCR_FROM_REG(reg) \
1173 SCR_REG_SFBR(reg,SCR_OR,0)
1175 #define SCR_TO_REG(reg) \
1176 SCR_SFBR_REG(reg,SCR_OR,0)
1178 #define SCR_LOAD_REG(reg,data) \
1179 SCR_REG_REG(reg,SCR_LOAD,data)
1181 #define SCR_LOAD_SFBR(data) \
1182 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1184 /*-----------------------------------------------------------
1186 ** LOAD from memory to register.
1187 ** STORE from register to memory.
1189 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1191 **-----------------------------------------------------------
1194 ** <<start address>>
1196 ** LOAD_REL (LEN) (DSA relative)
1199 **-----------------------------------------------------------
1202 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1203 #define SCR_NO_FLUSH2 0x02000000
1204 #define SCR_DSA_REL2 0x10000000
1206 #define SCR_LOAD_R(reg, how, n) \
1207 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1209 #define SCR_STORE_R(reg, how, n) \
1210 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1212 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1213 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1214 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1215 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1217 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1218 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1219 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1220 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1223 /*-----------------------------------------------------------
1225 ** Waiting for Disconnect or Reselect
1227 **-----------------------------------------------------------
1229 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1232 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1235 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1238 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1241 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1244 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1247 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1254 ** DATA (data, mask)
1256 **-----------------------------------------------------------
1259 #define SCR_NO_OP 0x80000000
1260 #define SCR_JUMP 0x80080000
1261 #define SCR_JUMP64 0x80480000
1262 #define SCR_JUMPR 0x80880000
1263 #define SCR_CALL 0x88080000
1264 #define SCR_CALLR 0x88880000
1265 #define SCR_RETURN 0x90080000
1266 #define SCR_INT 0x98080000
1267 #define SCR_INT_FLY 0x98180000
1269 #define IFFALSE(arg) (0x00080000 | (arg))
1270 #define IFTRUE(arg) (0x00000000 | (arg))
1272 #define WHEN(phase) (0x00030000 | (phase))
1273 #define IF(phase) (0x00020000 | (phase))
1275 #define DATA(D) (0x00040000 | ((D) & 0xff))
1276 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1278 #define CARRYSET (0x00200000)
1280 /*-----------------------------------------------------------
1284 **-----------------------------------------------------------
1291 #define M_COMPLETE (0x00)
1292 #define M_EXTENDED (0x01)
1293 #define M_SAVE_DP (0x02)
1294 #define M_RESTORE_DP (0x03)
1295 #define M_DISCONNECT (0x04)
1296 #define M_ID_ERROR (0x05)
1297 #define M_ABORT (0x06)
1298 #define M_REJECT (0x07)
1299 #define M_NOOP (0x08)
1300 #define M_PARITY (0x09)
1301 #define M_LCOMPLETE (0x0a)
1302 #define M_FCOMPLETE (0x0b)
1303 #define M_RESET (0x0c)
1304 #define M_ABORT_TAG (0x0d)
1305 #define M_CLEAR_QUEUE (0x0e)
1306 #define M_INIT_REC (0x0f)
1307 #define M_REL_REC (0x10)
1308 #define M_TERMINATE (0x11)
1309 #define M_SIMPLE_TAG (0x20)
1310 #define M_HEAD_TAG (0x21)
1311 #define M_ORDERED_TAG (0x22)
1312 #define M_IGN_RESIDUE (0x23)
1313 #define M_IDENTIFY (0x80)
1315 #define M_X_MODIFY_DP (0x00)
1316 #define M_X_SYNC_REQ (0x01)
1317 #define M_X_WIDE_REQ (0x03)
1318 #define M_X_PPR_REQ (0x04)
1324 #define S_GOOD (0x00)
1325 #define S_CHECK_COND (0x02)
1326 #define S_COND_MET (0x04)
1327 #define S_BUSY (0x08)
1328 #define S_INT (0x10)
1329 #define S_INT_COND_MET (0x14)
1330 #define S_CONFLICT (0x18)
1331 #define S_TERMINATED (0x20)
1332 #define S_QUEUE_FULL (0x28)
1333 #define S_ILLEGAL (0xff)
1334 #define S_SENSE (0x80)
1337 * End of ncrreg from FreeBSD
1340 #endif /* defined SYM53C8XX_DEFS_H */