1 /***********************************************************************
2 ;* File Name : TMSCSIM.H *
3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
5 ;***********************************************************************/
6 /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */
11 #include <linux/types.h>
12 #include <linux/config.h>
14 #define SCSI_IRQ_NONE 255
16 #define MAX_ADAPTER_NUM 4
17 #define MAX_SG_LIST_BUF 16 /* Not used */
18 #define MAX_CMD_PER_LUN 32
19 #define MAX_CMD_QUEUE MAX_CMD_PER_LUN+MAX_CMD_PER_LUN/2+1
21 #define MAX_SRB_CNT MAX_CMD_QUEUE+1 /* Max number of started commands */
23 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
25 #define pci_dma_lo32(a) (a & 0xffffffff)
27 typedef u8 UCHAR; /* 8 bits */
28 typedef u16 USHORT; /* 16 bits */
29 typedef u32 UINT; /* 32 bits */
30 typedef unsigned long ULONG; /* 32/64 bits */
34 ;-----------------------------------------------------------------------
36 ;-----------------------------------------------------------------------
42 struct dc390_srb *pNextSRB;
43 struct dc390_dcb *pSRBDCB;
44 struct scsi_cmnd *pcmd;
45 struct scatterlist *pSegmentList;
48 struct scatterlist Segmentx; /* make a one entry of S/G list table */
51 unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A*/
52 unsigned long SGToBeXferLen; /*; to be xfer length */
53 unsigned long TotalXferredLen;
54 unsigned long SavedTotXLen;
59 u8 SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */
60 /*; b4-settimeout,b5-Residual valid */
75 unsigned long Saved_Ptr;
81 //u8 IORBFlag; /*;81h-Reset, 2-retry */
87 ;-----------------------------------------------------------------------
88 ; Device Control Block
89 ;-----------------------------------------------------------------------
93 struct dc390_dcb *pNextDCB;
94 struct dc390_acb *pDCBACB;
98 struct dc390_srb *pWaitingSRB;
99 struct dc390_srb *pWaitLast;
100 struct dc390_srb *pGoingSRB;
101 struct dc390_srb *pGoingLast;
102 struct dc390_srb *pActiveSRB;
103 u8 WaitSRBCnt; /* Not used */
112 u8 TargetID; /*; SCSI Target ID (SCSI Only) */
113 u8 TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
123 u8 SyncMode; /*; 0:async mode */
124 u8 NegoPeriod; /*;for nego. */
125 u8 SyncPeriod; /*;for reg. */
126 u8 SyncOffset; /*;for reg. and nego.(low nibble) */
136 ;-----------------------------------------------------------------------
137 ; Adapter Control Block
138 ;-----------------------------------------------------------------------
142 struct Scsi_Host *pScsiHost;
143 struct dc390_acb *pNextACB;
149 u8 AdapterIndex; /*; nth Adapter this driver */
157 struct dc390_dcb *pLinkDCB;
158 struct dc390_dcb *pLastDCB;
159 struct dc390_dcb *pDCBRunRobin;
161 struct dc390_dcb *pActiveDCB;
162 struct dc390_srb *pFreeSRB;
163 struct dc390_srb *pTmpSRB;
169 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
176 u8 Ignore_IRQ; /* Not used */
178 struct pci_dev *pdev;
186 struct timer_list Waiting_Timer;
188 struct dc390_srb TmpSRB;
189 struct dc390_srb SRB_array[MAX_SRB_CNT]; /* 50 SRBs */
193 /*;-----------------------------------------------------------------------*/
196 #define BIT31 0x80000000
197 #define BIT30 0x40000000
198 #define BIT29 0x20000000
199 #define BIT28 0x10000000
200 #define BIT27 0x08000000
201 #define BIT26 0x04000000
202 #define BIT25 0x02000000
203 #define BIT24 0x01000000
204 #define BIT23 0x00800000
205 #define BIT22 0x00400000
206 #define BIT21 0x00200000
207 #define BIT20 0x00100000
208 #define BIT19 0x00080000
209 #define BIT18 0x00040000
210 #define BIT17 0x00020000
211 #define BIT16 0x00010000
212 #define BIT15 0x00008000
213 #define BIT14 0x00004000
214 #define BIT13 0x00002000
215 #define BIT12 0x00001000
216 #define BIT11 0x00000800
217 #define BIT10 0x00000400
218 #define BIT9 0x00000200
219 #define BIT8 0x00000100
220 #define BIT7 0x00000080
221 #define BIT6 0x00000040
222 #define BIT5 0x00000020
223 #define BIT4 0x00000010
224 #define BIT3 0x00000008
225 #define BIT2 0x00000004
226 #define BIT1 0x00000002
227 #define BIT0 0x00000001
229 /*;---UnitCtrlFlag */
230 #define UNIT_ALLOCATED BIT0
231 #define UNIT_INFO_CHANGED BIT1
232 #define FORMATING_MEDIA BIT2
233 #define UNIT_RETRY BIT3
236 #define DASD_SUPPORT BIT0
237 #define SCSI_SUPPORT BIT1
238 #define ASPI_SUPPORT BIT2
240 /*;----SRBState machine definition */
242 #define SRB_WAIT BIT0
243 #define SRB_READY BIT1
244 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
245 #define SRB_MSGIN BIT3
246 #define SRB_MSGIN_MULTI BIT4
247 #define SRB_COMMAND BIT5
248 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
249 #define SRB_DISCONNECT BIT7
250 #define SRB_DATA_XFER BIT8
251 #define SRB_XFERPAD BIT9
252 #define SRB_STATUS BIT10
253 #define SRB_COMPLETED BIT11
254 #define SRB_ABORT_SENT BIT12
255 #define DO_SYNC_NEGO BIT13
256 #define SRB_UNEXPECT_RESEL BIT14
260 #define ABORTION BIT1
261 #define OVER_RUN BIT2
262 #define UNDER_RUN BIT3
263 #define PARITY_ERROR BIT4
264 #define SRB_ERROR BIT5
267 #define RESET_DEV BIT0
268 #define RESET_DETECT BIT1
269 #define RESET_DONE BIT2
272 #define ABORT_DEV_ BIT0
277 #define RESIDUAL_VALID BIT5
278 #define ENABLE_TIMER BIT4
279 #define RESET_DEV0 BIT2
280 #define ABORT_DEV BIT1
281 #define AUTO_REQSENSE BIT0
283 /*;---Adapter status */
284 #define H_STATUS_GOOD 0
285 #define H_SEL_TIMEOUT 0x11
286 #define H_OVER_UNDER_RUN 0x12
287 #define H_UNEXP_BUS_FREE 0x13
288 #define H_TARGET_PHASE_F 0x14
289 #define H_INVALID_CCB_OP 0x16
290 #define H_LINK_CCB_BAD 0x17
291 #define H_BAD_TARGET_DIR 0x18
292 #define H_DUPLICATE_CCB 0x19
293 #define H_BAD_CCB_OR_SG 0x1A
294 #define H_ABORT 0x0FF
296 /*; SCSI Status byte codes*/
297 /* The values defined in include/scsi/scsi.h, to be shifted << 1 */
299 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
300 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
301 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
304 #define RES_TARGET 0x000000FF /* Target State */
305 #define RES_TARGET_LNX STATUS_MASK /* Only official ... */
306 #define RES_ENDMSG 0x0000FF00 /* End Message */
307 #define RES_DID 0x00FF0000 /* DID_ codes */
308 #define RES_DRV 0xFF000000 /* DRIVER_ codes */
310 #define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
311 #define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1)
313 #define SET_RES_TARGET(who,tgt) { who &= ~RES_TARGET; who |= (int)(tgt); }
314 #define SET_RES_TARGET_LNX(who,tgt) { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; }
315 #define SET_RES_MSG(who,msg) { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; }
316 #define SET_RES_DID(who,did) { who &= ~RES_DID; who |= (int)(did) << 16; }
317 #define SET_RES_DRV(who,drv) { who &= ~RES_DRV; who |= (int)(drv) << 24; }
320 #define SYNC_DISABLE 0
321 #define SYNC_ENABLE BIT0
322 #define SYNC_NEGO_DONE BIT1
323 #define WIDE_ENABLE BIT2 /* Not used ;-) */
324 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */
325 #define EN_TAG_QUEUEING BIT4
326 #define EN_ATN_STOP BIT5
328 #define SYNC_NEGO_OFFSET 15
330 /*;---SCSI bus phase*/
331 #define SCSI_DATA_OUT 0
332 #define SCSI_DATA_IN 1
333 #define SCSI_COMMAND 2
334 #define SCSI_STATUS_ 3
337 #define SCSI_MSG_OUT 6
338 #define SCSI_MSG_IN 7
340 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */
341 #define ABORT_TAG 0x0d
347 dma_addr_t saved_dma_handle;
351 ** Inquiry Data format
354 typedef struct _SCSIInqData { /* INQUIRY */
356 u8 DevType; /* Periph Qualifier & Periph Dev Type*/
357 u8 RMB_TypeMod; /* rem media bit & Dev Type Modifier */
358 u8 Vers; /* ISO, ECMA, & ANSI versions */
359 u8 RDF; /* AEN, TRMIOP, & response data format*/
360 u8 AddLen; /* length of additional data */
361 u8 Res1; /* reserved */
362 u8 Res2; /* reserved */
363 u8 Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
364 u8 VendorID[8]; /* Vendor Identification */
365 u8 ProductID[16]; /* Product Identification */
366 u8 ProductRev[4]; /* Product Revision */
369 } SCSI_INQDATA, *PSCSI_INQDATA;
372 /* Inquiry byte 0 masks */
375 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
376 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
377 #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
380 /* Inquiry byte 1 mask */
382 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
385 /* Peripheral Device Type definitions */
386 /* see include/scsi/scsi.h for the rest */
389 # define TYPE_PRINTER 0x02 /* Printer device */
392 # define TYPE_COMM 0x09 /* Communications device */
396 ** Inquiry flag definitions (Inq data byte 7)
399 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
400 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
401 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
402 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
403 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
404 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
405 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
409 ;==========================================================
411 ;==========================================================
413 typedef struct _EEprom
421 #define REAL_EE_ADAPT_SCSI_ID 64
422 #define REAL_EE_MODE2 65
423 #define REAL_EE_DELAY 66
424 #define REAL_EE_TAG_CMD_NUM 67
426 #define EE_ADAPT_SCSI_ID 32
429 #define EE_TAG_CMD_NUM 35
433 /*; EE_MODE1 bits definition*/
434 #define PARITY_CHK_ BIT0
435 #define SYNC_NEGO_ BIT1
436 #define EN_DISCONNECT_ BIT2
437 #define SEND_START_ BIT3
438 #define TAG_QUEUEING_ BIT4
440 /*; EE_MODE2 bits definition*/
441 #define MORE2_DRV BIT0
442 #define GREATER_1G BIT1
443 #define RST_SCSI_BUS BIT2
444 #define ACTIVE_NEGATION BIT3
446 #define LUN_CHECK BIT5
450 #define EEPROM_READ 0x80
453 ;==========================================================
454 ; AMD 53C974 Registers bit Definition
455 ;==========================================================
458 ;====================
460 ;====================
463 /*; Command Reg.(+0CH) (rw) */
464 #define DMA_COMMAND BIT7
466 #define CLEAR_FIFO_CMD 1
467 #define RST_DEVICE_CMD 2
468 #define RST_SCSI_BUS_CMD 3
470 #define INFO_XFER_CMD 0x10
471 #define INITIATOR_CMD_CMPLTE 0x11
472 #define MSG_ACCEPTED_CMD 0x12
473 #define XFER_PAD_BYTE 0x18
474 #define SET_ATN_CMD 0x1A
475 #define RESET_ATN_CMD 0x1B
477 #define SEL_WO_ATN 0x41 /* currently not used */
478 #define SEL_W_ATN 0x42
479 #define SEL_W_ATN_STOP 0x43
480 #define SEL_W_ATN3 0x46
481 #define EN_SEL_RESEL 0x44
482 #define DIS_SEL_RESEL 0x45 /* currently not used */
483 #define RESEL 0x40 /* " */
484 #define RESEL_ATN3 0x47 /* " */
486 #define DATA_XFER_CMD INFO_XFER_CMD
489 /*; SCSI Status Reg.(+10H) (r) */
490 #define INTERRUPT BIT7
491 #define ILLEGAL_OP_ERR BIT6
492 #define PARITY_ERR BIT5
493 #define COUNT_2_ZERO BIT4
494 #define GROUP_CODE_VALID BIT3
495 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
496 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
498 /*; Interrupt Status Reg.(+14H) (r) */
499 #define SCSI_RESET BIT7
500 #define INVALID_CMD BIT6
501 #define DISCONNECTED BIT5
502 #define SERVICE_REQUEST BIT4
503 #define SUCCESSFUL_OP BIT3
504 #define RESELECTED BIT2
505 #define SEL_ATTENTION BIT1
506 #define SELECTED BIT0
508 /*; Internal State Reg.(+18H) (r) */
509 #define SYNC_OFFSET_FLAG BIT3
510 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
511 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
513 /*; Clock Factor Reg.(+24H) (w) */
514 #define CLK_FREQ_40MHZ 0
515 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
516 #define CLK_FREQ_30MHZ (BIT2+BIT1)
517 #define CLK_FREQ_25MHZ (BIT2+BIT0)
518 #define CLK_FREQ_20MHZ BIT2
519 #define CLK_FREQ_15MHZ (BIT1+BIT0)
520 #define CLK_FREQ_10MHZ BIT1
522 /*; Control Reg. 1(+20H) (rw) */
523 #define EXTENDED_TIMING BIT7
524 #define DIS_INT_ON_SCSI_RST BIT6
525 #define PARITY_ERR_REPO BIT4
526 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */
528 /*; Control Reg. 2(+2CH) (rw) */
529 #define EN_FEATURE BIT6
530 #define EN_SCSI2_CMD BIT3
532 /*; Control Reg. 3(+30H) (rw) */
533 #define ID_MSG_CHECK BIT7
534 #define EN_QTAG_MSG BIT6
535 #define EN_GRP2_CMD BIT5
536 #define FAST_SCSI BIT4 /* ;10MB/SEC */
537 #define FAST_CLK BIT3 /* ;25 - 40 MHZ */
539 /*; Control Reg. 4(+34H) (rw) */
541 #define EATER_25NS BIT7
542 #define EATER_35NS BIT6
543 #define EATER_0NS (BIT7+BIT6)
544 #define REDUCED_POWER BIT5
545 #define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */
546 #define NEGATE_REQACKDATA BIT2
547 #define NEGATE_REQACK BIT3
549 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
550 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
553 ;====================
555 ;====================
557 /*; DMA Command Reg.(+40H) (rw) */
558 #define READ_DIRECTION BIT7
559 #define WRITE_DIRECTION 0
560 #define EN_DMA_INT BIT6
561 #define EN_PAGE_INT BIT5 /* page transfer interrupt enable */
562 #define MAP_TO_MDL BIT4
563 #define DIAGNOSTIC BIT2
564 #define DMA_IDLE_CMD 0
565 #define DMA_BLAST_CMD BIT0
566 #define DMA_ABORT_CMD BIT1
567 #define DMA_START_CMD (BIT1+BIT0)
569 /*; DMA Status Reg.(+54H) (r) */
570 #define PCI_MS_ABORT BIT6
571 #define BLAST_COMPLETE BIT5
572 #define SCSI_INTERRUPT BIT4
573 #define DMA_XFER_DONE BIT3
574 #define DMA_XFER_ABORT BIT2
575 #define DMA_XFER_ERROR BIT1
576 #define POWER_DOWN BIT0
578 /*; DMA SCSI Bus and Ctrl.(+70H) */
579 #define EN_INT_ON_PCI_ABORT BIT25
580 #define WRT_ERASE_DMA_STAT BIT24
581 #define PW_DOWN_CTRL BIT21
582 #define SCSI_BUSY BIT20
585 #define SCSI_LINES 0x0003ffff
588 ;==========================================================
589 ; SCSI Chip register address offset
590 ;==========================================================
591 ;Registers are rw unless declared otherwise
593 #define CtcReg_Low 0x00 /* r curr. transfer count */
594 #define CtcReg_Mid 0x04 /* r */
595 #define CtcReg_High 0x38 /* r */
596 #define ScsiFifo 0x08
598 #define Scsi_Status 0x10 /* r */
599 #define INT_Status 0x14 /* r */
600 #define Sync_Period 0x18 /* w */
601 #define Sync_Offset 0x1C /* w */
602 #define Clk_Factor 0x24 /* w */
603 #define CtrlReg1 0x20
604 #define CtrlReg2 0x2C
605 #define CtrlReg3 0x30
606 #define CtrlReg4 0x34
608 #define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */
609 #define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */
610 #define DMA_Wk_ByteCntr 0x4C /* r working byte counter */
611 #define DMA_Wk_AddrCntr 0x50 /* r working address counter */
612 #define DMA_Status 0x54 /* r */
613 #define DMA_MDL_Addr 0x58 /* rw starting MDL address */
614 #define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */
615 #define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */
617 #define StcReg_Low CtcReg_Low /* w start transfer count */
618 #define StcReg_Mid CtcReg_Mid /* w */
619 #define StcReg_High CtcReg_High /* w */
620 #define Scsi_Dest_ID Scsi_Status /* w */
621 #define Scsi_TimeOut INT_Status /* w */
622 #define Intern_State Sync_Period /* r */
623 #define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */
626 #define DC390_read8(address) \
627 (inb (pACB->IOPortBase + (address)))
629 #define DC390_read8_(address, base) \
630 (inb ((u16)(base) + (address)))
632 #define DC390_read16(address) \
633 (inw (pACB->IOPortBase + (address)))
635 #define DC390_read32(address) \
636 (inl (pACB->IOPortBase + (address)))
638 #define DC390_write8(address,value) \
639 outb ((value), pACB->IOPortBase + (address))
641 #define DC390_write8_(address,value,base) \
642 outb ((value), (u16)(base) + (address))
644 #define DC390_write16(address,value) \
645 outw ((value), pACB->IOPortBase + (address))
647 #define DC390_write32(address,value) \
648 outl ((value), pACB->IOPortBase + (address))
651 #endif /* _TMSCSIM_H */