2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * 2005/09/16: Enabled higher baud rates for 16C95x.
11 * (Mathias Adam <a2@adamis.de>)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
20 * A note about mapbase / membase
22 * mapbase is the physical address of the IO port.
23 * membase is an 'ioremapped' cookie.
26 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/delay.h>
37 #include <linux/platform_device.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_reg.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/serial_8250.h>
44 #include <linux/nmi.h>
45 #include <linux/mutex.h>
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
57 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
59 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
65 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
67 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
71 #define DEBUG_INTR(fmt...) printk(fmt)
73 #define DEBUG_INTR(fmt...) do { } while (0)
76 #define PASS_LIMIT 256
79 * We default to IRQ0 for the "no irq" hack. Some
80 * machine types want others as well - they're free
81 * to redefine this in their header file.
83 #define is_real_interrupt(irq) ((irq) != 0)
85 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
86 #define CONFIG_SERIAL_DETECT_IRQ 1
88 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
89 #define CONFIG_SERIAL_MANY_PORTS 1
93 * HUB6 is always on. This will be removed once the header
94 * files have been cleaned.
98 #include <asm/serial.h>
101 * SERIAL_PORT_DFNS tells us about built-in ports that have no
102 * standard enumeration mechanism. Platforms that can find all
103 * serial ports via mechanisms like ACPI or PCI need not supply it.
105 #ifndef SERIAL_PORT_DFNS
106 #define SERIAL_PORT_DFNS
109 static const struct old_serial_port old_serial_port[] = {
110 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
115 #ifdef CONFIG_SERIAL_8250_RSA
117 #define PORT_RSA_MAX 4
118 static unsigned long probe_rsa[PORT_RSA_MAX];
119 static unsigned int probe_rsa_count;
120 #endif /* CONFIG_SERIAL_8250_RSA */
122 struct uart_8250_port {
123 struct uart_port port;
124 struct timer_list timer; /* "no irq" timer */
125 struct list_head list; /* ports on this IRQ */
126 unsigned short capabilities; /* port capabilities */
127 unsigned short bugs; /* port bugs */
128 unsigned int tx_loadsz; /* transmit fifo load size */
133 unsigned char mcr_mask; /* mask of user bits */
134 unsigned char mcr_force; /* mask of forced bits */
135 unsigned char lsr_break_flag;
138 * We provide a per-port pm hook.
140 void (*pm)(struct uart_port *port,
141 unsigned int state, unsigned int old);
146 struct list_head *head;
149 static struct irq_info irq_lists[NR_IRQS];
152 * Here we define the default xmit fifo size used for each type of UART.
154 static const struct serial8250_config uart_config[] = {
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
180 .flags = UART_CAP_FIFO,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
199 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
207 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
215 .name = "16C950/954",
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
241 .flags = UART_CAP_FIFO,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_NATSEMI,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_UUE,
259 #ifdef CONFIG_SERIAL_8250_AU1X00
261 /* Au1x00 UART hardware has a weird register layout */
262 static const u8 au_io_in_map[] = {
272 static const u8 au_io_out_map[] = {
280 /* sane hardware needs no mapping */
281 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
283 if (up->port.iotype != UPIO_AU)
285 return au_io_in_map[offset];
288 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
290 if (up->port.iotype != UPIO_AU)
292 return au_io_out_map[offset];
297 /* sane hardware needs no mapping */
298 #define map_8250_in_reg(up, offset) (offset)
299 #define map_8250_out_reg(up, offset) (offset)
303 static unsigned int serial_in(struct uart_8250_port *up, int offset)
306 offset = map_8250_in_reg(up, offset) << up->port.regshift;
308 switch (up->port.iotype) {
310 outb(up->port.hub6 - 1 + offset, up->port.iobase);
311 return inb(up->port.iobase + 1);
314 return readb(up->port.membase + offset);
317 return readl(up->port.membase + offset);
319 #ifdef CONFIG_SERIAL_8250_AU1X00
321 return __raw_readl(up->port.membase + offset);
325 if (offset == UART_IIR) {
326 tmp = readl((u32 *)(up->port.membase + UART_RX));
327 return (cpu_to_le32(tmp) >> 8) & 0xff;
329 return readb(up->port.membase + offset);
332 return inb(up->port.iobase + offset);
337 serial_out(struct uart_8250_port *up, int offset, int value)
339 offset = map_8250_out_reg(up, offset) << up->port.regshift;
341 switch (up->port.iotype) {
343 outb(up->port.hub6 - 1 + offset, up->port.iobase);
344 outb(value, up->port.iobase + 1);
348 writeb(value, up->port.membase + offset);
352 writel(value, up->port.membase + offset);
355 #ifdef CONFIG_SERIAL_8250_AU1X00
357 __raw_writel(value, up->port.membase + offset);
361 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
362 writeb(value, up->port.membase + offset);
366 outb(value, up->port.iobase + offset);
371 * We used to support using pause I/O for certain machines. We
372 * haven't supported this for a while, but just in case it's badly
373 * needed for certain old 386 machines, I've left these #define's
376 #define serial_inp(up, offset) serial_in(up, offset)
377 #define serial_outp(up, offset, value) serial_out(up, offset, value)
379 /* Uart divisor latch read */
380 static inline int _serial_dl_read(struct uart_8250_port *up)
382 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
385 /* Uart divisor latch write */
386 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
388 serial_outp(up, UART_DLL, value & 0xff);
389 serial_outp(up, UART_DLM, value >> 8 & 0xff);
392 #ifdef CONFIG_SERIAL_8250_AU1X00
393 /* Au1x00 haven't got a standard divisor latch */
394 static int serial_dl_read(struct uart_8250_port *up)
396 if (up->port.iotype == UPIO_AU)
397 return __raw_readl(up->port.membase + 0x28);
399 return _serial_dl_read(up);
402 static void serial_dl_write(struct uart_8250_port *up, int value)
404 if (up->port.iotype == UPIO_AU)
405 __raw_writel(value, up->port.membase + 0x28);
407 _serial_dl_write(up, value);
410 #define serial_dl_read(up) _serial_dl_read(up)
411 #define serial_dl_write(up, value) _serial_dl_write(up, value)
417 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
419 serial_out(up, UART_SCR, offset);
420 serial_out(up, UART_ICR, value);
423 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
427 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
428 serial_out(up, UART_SCR, offset);
429 value = serial_in(up, UART_ICR);
430 serial_icr_write(up, UART_ACR, up->acr);
438 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
440 if (p->capabilities & UART_CAP_FIFO) {
441 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
442 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
443 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
444 serial_outp(p, UART_FCR, 0);
449 * IER sleep support. UARTs which have EFRs need the "extended
450 * capability" bit enabled. Note that on XR16C850s, we need to
451 * reset LCR to write to IER.
453 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
455 if (p->capabilities & UART_CAP_SLEEP) {
456 if (p->capabilities & UART_CAP_EFR) {
457 serial_outp(p, UART_LCR, 0xBF);
458 serial_outp(p, UART_EFR, UART_EFR_ECB);
459 serial_outp(p, UART_LCR, 0);
461 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
462 if (p->capabilities & UART_CAP_EFR) {
463 serial_outp(p, UART_LCR, 0xBF);
464 serial_outp(p, UART_EFR, 0);
465 serial_outp(p, UART_LCR, 0);
470 #ifdef CONFIG_SERIAL_8250_RSA
472 * Attempts to turn on the RSA FIFO. Returns zero on failure.
473 * We set the port uart clock rate if we succeed.
475 static int __enable_rsa(struct uart_8250_port *up)
480 mode = serial_inp(up, UART_RSA_MSR);
481 result = mode & UART_RSA_MSR_FIFO;
484 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
485 mode = serial_inp(up, UART_RSA_MSR);
486 result = mode & UART_RSA_MSR_FIFO;
490 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
495 static void enable_rsa(struct uart_8250_port *up)
497 if (up->port.type == PORT_RSA) {
498 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
499 spin_lock_irq(&up->port.lock);
501 spin_unlock_irq(&up->port.lock);
503 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
504 serial_outp(up, UART_RSA_FRR, 0);
509 * Attempts to turn off the RSA FIFO. Returns zero on failure.
510 * It is unknown why interrupts were disabled in here. However,
511 * the caller is expected to preserve this behaviour by grabbing
512 * the spinlock before calling this function.
514 static void disable_rsa(struct uart_8250_port *up)
519 if (up->port.type == PORT_RSA &&
520 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
521 spin_lock_irq(&up->port.lock);
523 mode = serial_inp(up, UART_RSA_MSR);
524 result = !(mode & UART_RSA_MSR_FIFO);
527 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
528 mode = serial_inp(up, UART_RSA_MSR);
529 result = !(mode & UART_RSA_MSR_FIFO);
533 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
534 spin_unlock_irq(&up->port.lock);
537 #endif /* CONFIG_SERIAL_8250_RSA */
540 * This is a quickie test to see how big the FIFO is.
541 * It doesn't work at all the time, more's the pity.
543 static int size_fifo(struct uart_8250_port *up)
545 unsigned char old_fcr, old_mcr, old_lcr;
546 unsigned short old_dl;
549 old_lcr = serial_inp(up, UART_LCR);
550 serial_outp(up, UART_LCR, 0);
551 old_fcr = serial_inp(up, UART_FCR);
552 old_mcr = serial_inp(up, UART_MCR);
553 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
554 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
555 serial_outp(up, UART_MCR, UART_MCR_LOOP);
556 serial_outp(up, UART_LCR, UART_LCR_DLAB);
557 old_dl = serial_dl_read(up);
558 serial_dl_write(up, 0x0001);
559 serial_outp(up, UART_LCR, 0x03);
560 for (count = 0; count < 256; count++)
561 serial_outp(up, UART_TX, count);
562 mdelay(20);/* FIXME - schedule_timeout */
563 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
564 (count < 256); count++)
565 serial_inp(up, UART_RX);
566 serial_outp(up, UART_FCR, old_fcr);
567 serial_outp(up, UART_MCR, old_mcr);
568 serial_outp(up, UART_LCR, UART_LCR_DLAB);
569 serial_dl_write(up, old_dl);
570 serial_outp(up, UART_LCR, old_lcr);
576 * Read UART ID using the divisor method - set DLL and DLM to zero
577 * and the revision will be in DLL and device type in DLM. We
578 * preserve the device state across this.
580 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
582 unsigned char old_dll, old_dlm, old_lcr;
585 old_lcr = serial_inp(p, UART_LCR);
586 serial_outp(p, UART_LCR, UART_LCR_DLAB);
588 old_dll = serial_inp(p, UART_DLL);
589 old_dlm = serial_inp(p, UART_DLM);
591 serial_outp(p, UART_DLL, 0);
592 serial_outp(p, UART_DLM, 0);
594 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
596 serial_outp(p, UART_DLL, old_dll);
597 serial_outp(p, UART_DLM, old_dlm);
598 serial_outp(p, UART_LCR, old_lcr);
604 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
605 * When this function is called we know it is at least a StarTech
606 * 16650 V2, but it might be one of several StarTech UARTs, or one of
607 * its clones. (We treat the broken original StarTech 16650 V1 as a
608 * 16550, and why not? Startech doesn't seem to even acknowledge its
611 * What evil have men's minds wrought...
613 static void autoconfig_has_efr(struct uart_8250_port *up)
615 unsigned int id1, id2, id3, rev;
618 * Everything with an EFR has SLEEP
620 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
623 * First we check to see if it's an Oxford Semiconductor UART.
625 * If we have to do this here because some non-National
626 * Semiconductor clone chips lock up if you try writing to the
627 * LSR register (which serial_icr_read does)
631 * Check for Oxford Semiconductor 16C950.
633 * EFR [4] must be set else this test fails.
635 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
636 * claims that it's needed for 952 dual UART's (which are not
637 * recommended for new designs).
640 serial_out(up, UART_LCR, 0xBF);
641 serial_out(up, UART_EFR, UART_EFR_ECB);
642 serial_out(up, UART_LCR, 0x00);
643 id1 = serial_icr_read(up, UART_ID1);
644 id2 = serial_icr_read(up, UART_ID2);
645 id3 = serial_icr_read(up, UART_ID3);
646 rev = serial_icr_read(up, UART_REV);
648 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
650 if (id1 == 0x16 && id2 == 0xC9 &&
651 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
652 up->port.type = PORT_16C950;
655 * Enable work around for the Oxford Semiconductor 952 rev B
656 * chip which causes it to seriously miscalculate baud rates
659 if (id3 == 0x52 && rev == 0x01)
660 up->bugs |= UART_BUG_QUOT;
665 * We check for a XR16C850 by setting DLL and DLM to 0, and then
666 * reading back DLL and DLM. The chip type depends on the DLM
668 * 0x10 - XR16C850 and the DLL contains the chip revision.
672 id1 = autoconfig_read_divisor_id(up);
673 DEBUG_AUTOCONF("850id=%04x ", id1);
676 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
677 up->port.type = PORT_16850;
682 * It wasn't an XR16C850.
684 * We distinguish between the '654 and the '650 by counting
685 * how many bytes are in the FIFO. I'm using this for now,
686 * since that's the technique that was sent to me in the
687 * serial driver update, but I'm not convinced this works.
688 * I've had problems doing this in the past. -TYT
690 if (size_fifo(up) == 64)
691 up->port.type = PORT_16654;
693 up->port.type = PORT_16650V2;
697 * We detected a chip without a FIFO. Only two fall into
698 * this category - the original 8250 and the 16450. The
699 * 16450 has a scratch register (accessible with LCR=0)
701 static void autoconfig_8250(struct uart_8250_port *up)
703 unsigned char scratch, status1, status2;
705 up->port.type = PORT_8250;
707 scratch = serial_in(up, UART_SCR);
708 serial_outp(up, UART_SCR, 0xa5);
709 status1 = serial_in(up, UART_SCR);
710 serial_outp(up, UART_SCR, 0x5a);
711 status2 = serial_in(up, UART_SCR);
712 serial_outp(up, UART_SCR, scratch);
714 if (status1 == 0xa5 && status2 == 0x5a)
715 up->port.type = PORT_16450;
718 static int broken_efr(struct uart_8250_port *up)
721 * Exar ST16C2550 "A2" devices incorrectly detect as
722 * having an EFR, and report an ID of 0x0201. See
723 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
725 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
732 * We know that the chip has FIFOs. Does it have an EFR? The
733 * EFR is located in the same register position as the IIR and
734 * we know the top two bits of the IIR are currently set. The
735 * EFR should contain zero. Try to read the EFR.
737 static void autoconfig_16550a(struct uart_8250_port *up)
739 unsigned char status1, status2;
740 unsigned int iersave;
742 up->port.type = PORT_16550A;
743 up->capabilities |= UART_CAP_FIFO;
746 * Check for presence of the EFR when DLAB is set.
747 * Only ST16C650V1 UARTs pass this test.
749 serial_outp(up, UART_LCR, UART_LCR_DLAB);
750 if (serial_in(up, UART_EFR) == 0) {
751 serial_outp(up, UART_EFR, 0xA8);
752 if (serial_in(up, UART_EFR) != 0) {
753 DEBUG_AUTOCONF("EFRv1 ");
754 up->port.type = PORT_16650;
755 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
757 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
759 serial_outp(up, UART_EFR, 0);
764 * Maybe it requires 0xbf to be written to the LCR.
765 * (other ST16C650V2 UARTs, TI16C752A, etc)
767 serial_outp(up, UART_LCR, 0xBF);
768 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
769 DEBUG_AUTOCONF("EFRv2 ");
770 autoconfig_has_efr(up);
775 * Check for a National Semiconductor SuperIO chip.
776 * Attempt to switch to bank 2, read the value of the LOOP bit
777 * from EXCR1. Switch back to bank 0, change it in MCR. Then
778 * switch back to bank 2, read it from EXCR1 again and check
779 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
781 serial_outp(up, UART_LCR, 0);
782 status1 = serial_in(up, UART_MCR);
783 serial_outp(up, UART_LCR, 0xE0);
784 status2 = serial_in(up, 0x02); /* EXCR1 */
786 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
787 serial_outp(up, UART_LCR, 0);
788 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
789 serial_outp(up, UART_LCR, 0xE0);
790 status2 = serial_in(up, 0x02); /* EXCR1 */
791 serial_outp(up, UART_LCR, 0);
792 serial_outp(up, UART_MCR, status1);
794 if ((status2 ^ status1) & UART_MCR_LOOP) {
797 serial_outp(up, UART_LCR, 0xE0);
799 quot = serial_dl_read(up);
802 status1 = serial_in(up, 0x04); /* EXCR1 */
803 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
804 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
805 serial_outp(up, 0x04, status1);
807 serial_dl_write(up, quot);
809 serial_outp(up, UART_LCR, 0);
811 up->port.uartclk = 921600*16;
812 up->port.type = PORT_NS16550A;
813 up->capabilities |= UART_NATSEMI;
819 * No EFR. Try to detect a TI16750, which only sets bit 5 of
820 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
821 * Try setting it with and without DLAB set. Cheap clones
822 * set bit 5 without DLAB set.
824 serial_outp(up, UART_LCR, 0);
825 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
826 status1 = serial_in(up, UART_IIR) >> 5;
827 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
828 serial_outp(up, UART_LCR, UART_LCR_DLAB);
829 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
830 status2 = serial_in(up, UART_IIR) >> 5;
831 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
832 serial_outp(up, UART_LCR, 0);
834 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
836 if (status1 == 6 && status2 == 7) {
837 up->port.type = PORT_16750;
838 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
843 * Try writing and reading the UART_IER_UUE bit (b6).
844 * If it works, this is probably one of the Xscale platform's
846 * We're going to explicitly set the UUE bit to 0 before
847 * trying to write and read a 1 just to make sure it's not
848 * already a 1 and maybe locked there before we even start start.
850 iersave = serial_in(up, UART_IER);
851 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
852 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
854 * OK it's in a known zero state, try writing and reading
855 * without disturbing the current state of the other bits.
857 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
858 if (serial_in(up, UART_IER) & UART_IER_UUE) {
861 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
863 DEBUG_AUTOCONF("Xscale ");
864 up->port.type = PORT_XSCALE;
865 up->capabilities |= UART_CAP_UUE;
870 * If we got here we couldn't force the IER_UUE bit to 0.
871 * Log it and continue.
873 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
875 serial_outp(up, UART_IER, iersave);
879 * This routine is called by rs_init() to initialize a specific serial
880 * port. It determines what type of UART chip this serial port is
881 * using: 8250, 16450, 16550, 16550A. The important question is
882 * whether or not this UART is a 16550A or not, since this will
883 * determine whether or not we can use its FIFO features or not.
885 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
887 unsigned char status1, scratch, scratch2, scratch3;
888 unsigned char save_lcr, save_mcr;
891 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
894 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
895 up->port.line, up->port.iobase, up->port.membase);
898 * We really do need global IRQs disabled here - we're going to
899 * be frobbing the chips IRQ enable register to see if it exists.
901 spin_lock_irqsave(&up->port.lock, flags);
902 // save_flags(flags); cli();
904 up->capabilities = 0;
907 if (!(up->port.flags & UPF_BUGGY_UART)) {
909 * Do a simple existence test first; if we fail this,
910 * there's no point trying anything else.
912 * 0x80 is used as a nonsense port to prevent against
913 * false positives due to ISA bus float. The
914 * assumption is that 0x80 is a non-existent port;
915 * which should be safe since include/asm/io.h also
916 * makes this assumption.
918 * Note: this is safe as long as MCR bit 4 is clear
919 * and the device is in "PC" mode.
921 scratch = serial_inp(up, UART_IER);
922 serial_outp(up, UART_IER, 0);
926 scratch2 = serial_inp(up, UART_IER);
927 serial_outp(up, UART_IER, 0x0F);
931 scratch3 = serial_inp(up, UART_IER);
932 serial_outp(up, UART_IER, scratch);
933 if (scratch2 != 0 || scratch3 != 0x0F) {
935 * We failed; there's nothing here
937 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
943 save_mcr = serial_in(up, UART_MCR);
944 save_lcr = serial_in(up, UART_LCR);
947 * Check to see if a UART is really there. Certain broken
948 * internal modems based on the Rockwell chipset fail this
949 * test, because they apparently don't implement the loopback
950 * test mode. So this test is skipped on the COM 1 through
951 * COM 4 ports. This *should* be safe, since no board
952 * manufacturer would be stupid enough to design a board
953 * that conflicts with COM 1-4 --- we hope!
955 if (!(up->port.flags & UPF_SKIP_TEST)) {
956 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
957 status1 = serial_inp(up, UART_MSR) & 0xF0;
958 serial_outp(up, UART_MCR, save_mcr);
959 if (status1 != 0x90) {
960 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
967 * We're pretty sure there's a port here. Lets find out what
968 * type of port it is. The IIR top two bits allows us to find
969 * out if it's 8250 or 16450, 16550, 16550A or later. This
970 * determines what we test for next.
972 * We also initialise the EFR (if any) to zero for later. The
973 * EFR occupies the same register location as the FCR and IIR.
975 serial_outp(up, UART_LCR, 0xBF);
976 serial_outp(up, UART_EFR, 0);
977 serial_outp(up, UART_LCR, 0);
979 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
980 scratch = serial_in(up, UART_IIR) >> 6;
982 DEBUG_AUTOCONF("iir=%d ", scratch);
989 up->port.type = PORT_UNKNOWN;
992 up->port.type = PORT_16550;
995 autoconfig_16550a(up);
999 #ifdef CONFIG_SERIAL_8250_RSA
1001 * Only probe for RSA ports if we got the region.
1003 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1006 for (i = 0 ; i < probe_rsa_count; ++i) {
1007 if (probe_rsa[i] == up->port.iobase &&
1009 up->port.type = PORT_RSA;
1016 #ifdef CONFIG_SERIAL_8250_AU1X00
1017 /* if access method is AU, it is a 16550 with a quirk */
1018 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1019 up->bugs |= UART_BUG_NOMSR;
1022 serial_outp(up, UART_LCR, save_lcr);
1024 if (up->capabilities != uart_config[up->port.type].flags) {
1026 "ttyS%d: detected caps %08x should be %08x\n",
1027 up->port.line, up->capabilities,
1028 uart_config[up->port.type].flags);
1031 up->port.fifosize = uart_config[up->port.type].fifo_size;
1032 up->capabilities = uart_config[up->port.type].flags;
1033 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1035 if (up->port.type == PORT_UNKNOWN)
1041 #ifdef CONFIG_SERIAL_8250_RSA
1042 if (up->port.type == PORT_RSA)
1043 serial_outp(up, UART_RSA_FRR, 0);
1045 serial_outp(up, UART_MCR, save_mcr);
1046 serial8250_clear_fifos(up);
1047 (void)serial_in(up, UART_RX);
1048 if (up->capabilities & UART_CAP_UUE)
1049 serial_outp(up, UART_IER, UART_IER_UUE);
1051 serial_outp(up, UART_IER, 0);
1054 spin_unlock_irqrestore(&up->port.lock, flags);
1055 // restore_flags(flags);
1056 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1059 static void autoconfig_irq(struct uart_8250_port *up)
1061 unsigned char save_mcr, save_ier;
1062 unsigned char save_ICP = 0;
1063 unsigned int ICP = 0;
1067 if (up->port.flags & UPF_FOURPORT) {
1068 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1069 save_ICP = inb_p(ICP);
1074 /* forget possible initially masked and pending IRQ */
1075 probe_irq_off(probe_irq_on());
1076 save_mcr = serial_inp(up, UART_MCR);
1077 save_ier = serial_inp(up, UART_IER);
1078 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1080 irqs = probe_irq_on();
1081 serial_outp(up, UART_MCR, 0);
1083 if (up->port.flags & UPF_FOURPORT) {
1084 serial_outp(up, UART_MCR,
1085 UART_MCR_DTR | UART_MCR_RTS);
1087 serial_outp(up, UART_MCR,
1088 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1090 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1091 (void)serial_inp(up, UART_LSR);
1092 (void)serial_inp(up, UART_RX);
1093 (void)serial_inp(up, UART_IIR);
1094 (void)serial_inp(up, UART_MSR);
1095 serial_outp(up, UART_TX, 0xFF);
1097 irq = probe_irq_off(irqs);
1099 serial_outp(up, UART_MCR, save_mcr);
1100 serial_outp(up, UART_IER, save_ier);
1102 if (up->port.flags & UPF_FOURPORT)
1103 outb_p(save_ICP, ICP);
1105 up->port.irq = (irq > 0) ? irq : 0;
1108 static inline void __stop_tx(struct uart_8250_port *p)
1110 if (p->ier & UART_IER_THRI) {
1111 p->ier &= ~UART_IER_THRI;
1112 serial_out(p, UART_IER, p->ier);
1116 static void serial8250_stop_tx(struct uart_port *port)
1118 struct uart_8250_port *up = (struct uart_8250_port *)port;
1123 * We really want to stop the transmitter from sending.
1125 if (up->port.type == PORT_16C950) {
1126 up->acr |= UART_ACR_TXDIS;
1127 serial_icr_write(up, UART_ACR, up->acr);
1131 static void transmit_chars(struct uart_8250_port *up);
1133 static void serial8250_start_tx(struct uart_port *port)
1135 struct uart_8250_port *up = (struct uart_8250_port *)port;
1137 if (!(up->ier & UART_IER_THRI)) {
1138 up->ier |= UART_IER_THRI;
1139 serial_out(up, UART_IER, up->ier);
1141 if (up->bugs & UART_BUG_TXEN) {
1142 unsigned char lsr, iir;
1143 lsr = serial_in(up, UART_LSR);
1144 iir = serial_in(up, UART_IIR);
1145 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1151 * Re-enable the transmitter if we disabled it.
1153 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1154 up->acr &= ~UART_ACR_TXDIS;
1155 serial_icr_write(up, UART_ACR, up->acr);
1159 static void serial8250_stop_rx(struct uart_port *port)
1161 struct uart_8250_port *up = (struct uart_8250_port *)port;
1163 up->ier &= ~UART_IER_RLSI;
1164 up->port.read_status_mask &= ~UART_LSR_DR;
1165 serial_out(up, UART_IER, up->ier);
1168 static void serial8250_enable_ms(struct uart_port *port)
1170 struct uart_8250_port *up = (struct uart_8250_port *)port;
1172 /* no MSR capabilities */
1173 if (up->bugs & UART_BUG_NOMSR)
1176 up->ier |= UART_IER_MSI;
1177 serial_out(up, UART_IER, up->ier);
1181 receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1183 struct tty_struct *tty = up->port.info->tty;
1184 unsigned char ch, lsr = *status;
1185 int max_count = 256;
1189 ch = serial_inp(up, UART_RX);
1191 up->port.icount.rx++;
1193 #ifdef CONFIG_SERIAL_8250_CONSOLE
1195 * Recover the break flag from console xmit
1197 if (up->port.line == up->port.cons->index) {
1198 lsr |= up->lsr_break_flag;
1199 up->lsr_break_flag = 0;
1203 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1204 UART_LSR_FE | UART_LSR_OE))) {
1206 * For statistics only
1208 if (lsr & UART_LSR_BI) {
1209 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1210 up->port.icount.brk++;
1212 * We do the SysRQ and SAK checking
1213 * here because otherwise the break
1214 * may get masked by ignore_status_mask
1215 * or read_status_mask.
1217 if (uart_handle_break(&up->port))
1219 } else if (lsr & UART_LSR_PE)
1220 up->port.icount.parity++;
1221 else if (lsr & UART_LSR_FE)
1222 up->port.icount.frame++;
1223 if (lsr & UART_LSR_OE)
1224 up->port.icount.overrun++;
1227 * Mask off conditions which should be ignored.
1229 lsr &= up->port.read_status_mask;
1231 if (lsr & UART_LSR_BI) {
1232 DEBUG_INTR("handling break....");
1234 } else if (lsr & UART_LSR_PE)
1236 else if (lsr & UART_LSR_FE)
1239 if (uart_handle_sysrq_char(&up->port, ch, regs))
1242 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1245 lsr = serial_inp(up, UART_LSR);
1246 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1247 spin_unlock(&up->port.lock);
1248 tty_flip_buffer_push(tty);
1249 spin_lock(&up->port.lock);
1253 static void transmit_chars(struct uart_8250_port *up)
1255 struct circ_buf *xmit = &up->port.info->xmit;
1258 if (up->port.x_char) {
1259 serial_outp(up, UART_TX, up->port.x_char);
1260 up->port.icount.tx++;
1261 up->port.x_char = 0;
1264 if (uart_tx_stopped(&up->port)) {
1265 serial8250_stop_tx(&up->port);
1268 if (uart_circ_empty(xmit)) {
1273 count = up->tx_loadsz;
1275 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1276 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1277 up->port.icount.tx++;
1278 if (uart_circ_empty(xmit))
1280 } while (--count > 0);
1282 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1283 uart_write_wakeup(&up->port);
1285 DEBUG_INTR("THRE...");
1287 if (uart_circ_empty(xmit))
1291 static unsigned int check_modem_status(struct uart_8250_port *up)
1293 unsigned int status = serial_in(up, UART_MSR);
1295 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1296 if (status & UART_MSR_TERI)
1297 up->port.icount.rng++;
1298 if (status & UART_MSR_DDSR)
1299 up->port.icount.dsr++;
1300 if (status & UART_MSR_DDCD)
1301 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1302 if (status & UART_MSR_DCTS)
1303 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1305 wake_up_interruptible(&up->port.info->delta_msr_wait);
1312 * This handles the interrupt from one port.
1315 serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1317 unsigned int status;
1319 spin_lock(&up->port.lock);
1321 status = serial_inp(up, UART_LSR);
1323 DEBUG_INTR("status = %x...", status);
1325 if (status & UART_LSR_DR)
1326 receive_chars(up, &status, regs);
1327 check_modem_status(up);
1328 if (status & UART_LSR_THRE)
1331 spin_unlock(&up->port.lock);
1335 * This is the serial driver's interrupt routine.
1337 * Arjan thinks the old way was overly complex, so it got simplified.
1338 * Alan disagrees, saying that need the complexity to handle the weird
1339 * nature of ISA shared interrupts. (This is a special exception.)
1341 * In order to handle ISA shared interrupts properly, we need to check
1342 * that all ports have been serviced, and therefore the ISA interrupt
1343 * line has been de-asserted.
1345 * This means we need to loop through all ports. checking that they
1346 * don't have an interrupt pending.
1348 static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1350 struct irq_info *i = dev_id;
1351 struct list_head *l, *end = NULL;
1352 int pass_counter = 0, handled = 0;
1354 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1356 spin_lock(&i->lock);
1360 struct uart_8250_port *up;
1363 up = list_entry(l, struct uart_8250_port, list);
1365 iir = serial_in(up, UART_IIR);
1366 if (!(iir & UART_IIR_NO_INT)) {
1367 serial8250_handle_port(up, regs);
1372 } else if (end == NULL)
1377 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1378 /* If we hit this, we're dead. */
1379 printk(KERN_ERR "serial8250: too much work for "
1385 spin_unlock(&i->lock);
1387 DEBUG_INTR("end.\n");
1389 return IRQ_RETVAL(handled);
1393 * To support ISA shared interrupts, we need to have one interrupt
1394 * handler that ensures that the IRQ line has been deasserted
1395 * before returning. Failing to do this will result in the IRQ
1396 * line being stuck active, and, since ISA irqs are edge triggered,
1397 * no more IRQs will be seen.
1399 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1401 spin_lock_irq(&i->lock);
1403 if (!list_empty(i->head)) {
1404 if (i->head == &up->list)
1405 i->head = i->head->next;
1406 list_del(&up->list);
1408 BUG_ON(i->head != &up->list);
1412 spin_unlock_irq(&i->lock);
1415 static int serial_link_irq_chain(struct uart_8250_port *up)
1417 struct irq_info *i = irq_lists + up->port.irq;
1418 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1420 spin_lock_irq(&i->lock);
1423 list_add(&up->list, i->head);
1424 spin_unlock_irq(&i->lock);
1428 INIT_LIST_HEAD(&up->list);
1429 i->head = &up->list;
1430 spin_unlock_irq(&i->lock);
1432 ret = request_irq(up->port.irq, serial8250_interrupt,
1433 irq_flags, "serial", i);
1435 serial_do_unlink(i, up);
1441 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1443 struct irq_info *i = irq_lists + up->port.irq;
1445 BUG_ON(i->head == NULL);
1447 if (list_empty(i->head))
1448 free_irq(up->port.irq, i);
1450 serial_do_unlink(i, up);
1454 * This function is used to handle ports that do not have an
1455 * interrupt. This doesn't work very well for 16450's, but gives
1456 * barely passable results for a 16550A. (Although at the expense
1457 * of much CPU overhead).
1459 static void serial8250_timeout(unsigned long data)
1461 struct uart_8250_port *up = (struct uart_8250_port *)data;
1462 unsigned int timeout;
1465 iir = serial_in(up, UART_IIR);
1466 if (!(iir & UART_IIR_NO_INT))
1467 serial8250_handle_port(up, NULL);
1469 timeout = up->port.timeout;
1470 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1471 mod_timer(&up->timer, jiffies + timeout);
1474 static unsigned int serial8250_tx_empty(struct uart_port *port)
1476 struct uart_8250_port *up = (struct uart_8250_port *)port;
1477 unsigned long flags;
1480 spin_lock_irqsave(&up->port.lock, flags);
1481 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1482 spin_unlock_irqrestore(&up->port.lock, flags);
1487 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1489 struct uart_8250_port *up = (struct uart_8250_port *)port;
1490 unsigned int status;
1493 status = check_modem_status(up);
1496 if (status & UART_MSR_DCD)
1498 if (status & UART_MSR_RI)
1500 if (status & UART_MSR_DSR)
1502 if (status & UART_MSR_CTS)
1507 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1509 struct uart_8250_port *up = (struct uart_8250_port *)port;
1510 unsigned char mcr = 0;
1512 if (mctrl & TIOCM_RTS)
1513 mcr |= UART_MCR_RTS;
1514 if (mctrl & TIOCM_DTR)
1515 mcr |= UART_MCR_DTR;
1516 if (mctrl & TIOCM_OUT1)
1517 mcr |= UART_MCR_OUT1;
1518 if (mctrl & TIOCM_OUT2)
1519 mcr |= UART_MCR_OUT2;
1520 if (mctrl & TIOCM_LOOP)
1521 mcr |= UART_MCR_LOOP;
1523 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1525 serial_out(up, UART_MCR, mcr);
1528 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1530 struct uart_8250_port *up = (struct uart_8250_port *)port;
1531 unsigned long flags;
1533 spin_lock_irqsave(&up->port.lock, flags);
1534 if (break_state == -1)
1535 up->lcr |= UART_LCR_SBC;
1537 up->lcr &= ~UART_LCR_SBC;
1538 serial_out(up, UART_LCR, up->lcr);
1539 spin_unlock_irqrestore(&up->port.lock, flags);
1542 static int serial8250_startup(struct uart_port *port)
1544 struct uart_8250_port *up = (struct uart_8250_port *)port;
1545 unsigned long flags;
1546 unsigned char lsr, iir;
1549 up->capabilities = uart_config[up->port.type].flags;
1552 if (up->port.type == PORT_16C950) {
1553 /* Wake up and initialize UART */
1555 serial_outp(up, UART_LCR, 0xBF);
1556 serial_outp(up, UART_EFR, UART_EFR_ECB);
1557 serial_outp(up, UART_IER, 0);
1558 serial_outp(up, UART_LCR, 0);
1559 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1560 serial_outp(up, UART_LCR, 0xBF);
1561 serial_outp(up, UART_EFR, UART_EFR_ECB);
1562 serial_outp(up, UART_LCR, 0);
1565 #ifdef CONFIG_SERIAL_8250_RSA
1567 * If this is an RSA port, see if we can kick it up to the
1568 * higher speed clock.
1574 * Clear the FIFO buffers and disable them.
1575 * (they will be reenabled in set_termios())
1577 serial8250_clear_fifos(up);
1580 * Clear the interrupt registers.
1582 (void) serial_inp(up, UART_LSR);
1583 (void) serial_inp(up, UART_RX);
1584 (void) serial_inp(up, UART_IIR);
1585 (void) serial_inp(up, UART_MSR);
1588 * At this point, there's no way the LSR could still be 0xff;
1589 * if it is, then bail out, because there's likely no UART
1592 if (!(up->port.flags & UPF_BUGGY_UART) &&
1593 (serial_inp(up, UART_LSR) == 0xff)) {
1594 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1599 * For a XR16C850, we need to set the trigger levels
1601 if (up->port.type == PORT_16850) {
1604 serial_outp(up, UART_LCR, 0xbf);
1606 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1607 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1608 serial_outp(up, UART_TRG, UART_TRG_96);
1609 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1610 serial_outp(up, UART_TRG, UART_TRG_96);
1612 serial_outp(up, UART_LCR, 0);
1616 * If the "interrupt" for this port doesn't correspond with any
1617 * hardware interrupt, we use a timer-based system. The original
1618 * driver used to do this with IRQ0.
1620 if (!is_real_interrupt(up->port.irq)) {
1621 unsigned int timeout = up->port.timeout;
1623 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1625 up->timer.data = (unsigned long)up;
1626 mod_timer(&up->timer, jiffies + timeout);
1628 retval = serial_link_irq_chain(up);
1634 * Now, initialize the UART
1636 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1638 spin_lock_irqsave(&up->port.lock, flags);
1639 if (up->port.flags & UPF_FOURPORT) {
1640 if (!is_real_interrupt(up->port.irq))
1641 up->port.mctrl |= TIOCM_OUT1;
1644 * Most PC uarts need OUT2 raised to enable interrupts.
1646 if (is_real_interrupt(up->port.irq))
1647 up->port.mctrl |= TIOCM_OUT2;
1649 serial8250_set_mctrl(&up->port, up->port.mctrl);
1652 * Do a quick test to see if we receive an
1653 * interrupt when we enable the TX irq.
1655 serial_outp(up, UART_IER, UART_IER_THRI);
1656 lsr = serial_in(up, UART_LSR);
1657 iir = serial_in(up, UART_IIR);
1658 serial_outp(up, UART_IER, 0);
1660 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1661 if (!(up->bugs & UART_BUG_TXEN)) {
1662 up->bugs |= UART_BUG_TXEN;
1663 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1667 up->bugs &= ~UART_BUG_TXEN;
1670 spin_unlock_irqrestore(&up->port.lock, flags);
1673 * Finally, enable interrupts. Note: Modem status interrupts
1674 * are set via set_termios(), which will be occurring imminently
1675 * anyway, so we don't enable them here.
1677 up->ier = UART_IER_RLSI | UART_IER_RDI;
1678 serial_outp(up, UART_IER, up->ier);
1680 if (up->port.flags & UPF_FOURPORT) {
1683 * Enable interrupts on the AST Fourport board
1685 icp = (up->port.iobase & 0xfe0) | 0x01f;
1691 * And clear the interrupt registers again for luck.
1693 (void) serial_inp(up, UART_LSR);
1694 (void) serial_inp(up, UART_RX);
1695 (void) serial_inp(up, UART_IIR);
1696 (void) serial_inp(up, UART_MSR);
1701 static void serial8250_shutdown(struct uart_port *port)
1703 struct uart_8250_port *up = (struct uart_8250_port *)port;
1704 unsigned long flags;
1707 * Disable interrupts from this port
1710 serial_outp(up, UART_IER, 0);
1712 spin_lock_irqsave(&up->port.lock, flags);
1713 if (up->port.flags & UPF_FOURPORT) {
1714 /* reset interrupts on the AST Fourport board */
1715 inb((up->port.iobase & 0xfe0) | 0x1f);
1716 up->port.mctrl |= TIOCM_OUT1;
1718 up->port.mctrl &= ~TIOCM_OUT2;
1720 serial8250_set_mctrl(&up->port, up->port.mctrl);
1721 spin_unlock_irqrestore(&up->port.lock, flags);
1724 * Disable break condition and FIFOs
1726 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1727 serial8250_clear_fifos(up);
1729 #ifdef CONFIG_SERIAL_8250_RSA
1731 * Reset the RSA board back to 115kbps compat mode.
1737 * Read data port to reset things, and then unlink from
1740 (void) serial_in(up, UART_RX);
1742 if (!is_real_interrupt(up->port.irq))
1743 del_timer_sync(&up->timer);
1745 serial_unlink_irq_chain(up);
1748 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1753 * Handle magic divisors for baud rates above baud_base on
1754 * SMSC SuperIO chips.
1756 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1757 baud == (port->uartclk/4))
1759 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1760 baud == (port->uartclk/8))
1763 * For 16C950s UART_TCR is used in combination with divisor==1
1764 * to achieve baud rates up to baud_base*4.
1766 else if ((port->type == PORT_16C950) &&
1767 baud > (port->uartclk/16))
1771 quot = uart_get_divisor(port, baud);
1777 serial8250_set_termios(struct uart_port *port, struct termios *termios,
1778 struct termios *old)
1780 struct uart_8250_port *up = (struct uart_8250_port *)port;
1781 unsigned char cval, fcr = 0;
1782 unsigned long flags;
1783 unsigned int baud, quot, max_baud;
1785 switch (termios->c_cflag & CSIZE) {
1787 cval = UART_LCR_WLEN5;
1790 cval = UART_LCR_WLEN6;
1793 cval = UART_LCR_WLEN7;
1797 cval = UART_LCR_WLEN8;
1801 if (termios->c_cflag & CSTOPB)
1802 cval |= UART_LCR_STOP;
1803 if (termios->c_cflag & PARENB)
1804 cval |= UART_LCR_PARITY;
1805 if (!(termios->c_cflag & PARODD))
1806 cval |= UART_LCR_EPAR;
1808 if (termios->c_cflag & CMSPAR)
1809 cval |= UART_LCR_SPAR;
1813 * Ask the core to calculate the divisor for us.
1815 max_baud = (up->port.type == PORT_16C950 ? port->uartclk/4 : port->uartclk/16);
1816 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1817 quot = serial8250_get_divisor(port, baud);
1820 * Oxford Semi 952 rev B workaround
1822 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1825 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1827 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1829 fcr = uart_config[up->port.type].fcr;
1833 * MCR-based auto flow control. When AFE is enabled, RTS will be
1834 * deasserted when the receive FIFO contains more characters than
1835 * the trigger, or the MCR RTS bit is cleared. In the case where
1836 * the remote UART is not using CTS auto flow control, we must
1837 * have sufficient FIFO entries for the latency of the remote
1838 * UART to respond. IOW, at least 32 bytes of FIFO.
1840 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1841 up->mcr &= ~UART_MCR_AFE;
1842 if (termios->c_cflag & CRTSCTS)
1843 up->mcr |= UART_MCR_AFE;
1847 * Ok, we're now changing the port state. Do it with
1848 * interrupts disabled.
1850 spin_lock_irqsave(&up->port.lock, flags);
1853 * 16C950 supports additional prescaler ratios between 1:16 and 1:4
1854 * thus increasing max baud rate to uartclk/4.
1856 if (up->port.type == PORT_16C950) {
1857 if (baud == port->uartclk/4)
1858 serial_icr_write(up, UART_TCR, 0x4);
1859 else if (baud == port->uartclk/8)
1860 serial_icr_write(up, UART_TCR, 0x8);
1862 serial_icr_write(up, UART_TCR, 0);
1866 * Update the per-port timeout.
1868 uart_update_timeout(port, termios->c_cflag, baud);
1870 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1871 if (termios->c_iflag & INPCK)
1872 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1873 if (termios->c_iflag & (BRKINT | PARMRK))
1874 up->port.read_status_mask |= UART_LSR_BI;
1877 * Characteres to ignore
1879 up->port.ignore_status_mask = 0;
1880 if (termios->c_iflag & IGNPAR)
1881 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1882 if (termios->c_iflag & IGNBRK) {
1883 up->port.ignore_status_mask |= UART_LSR_BI;
1885 * If we're ignoring parity and break indicators,
1886 * ignore overruns too (for real raw support).
1888 if (termios->c_iflag & IGNPAR)
1889 up->port.ignore_status_mask |= UART_LSR_OE;
1893 * ignore all characters if CREAD is not set
1895 if ((termios->c_cflag & CREAD) == 0)
1896 up->port.ignore_status_mask |= UART_LSR_DR;
1899 * CTS flow control flag and modem status interrupts
1901 up->ier &= ~UART_IER_MSI;
1902 if (!(up->bugs & UART_BUG_NOMSR) &&
1903 UART_ENABLE_MS(&up->port, termios->c_cflag))
1904 up->ier |= UART_IER_MSI;
1905 if (up->capabilities & UART_CAP_UUE)
1906 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1908 serial_out(up, UART_IER, up->ier);
1910 if (up->capabilities & UART_CAP_EFR) {
1911 unsigned char efr = 0;
1913 * TI16C752/Startech hardware flow control. FIXME:
1914 * - TI16C752 requires control thresholds to be set.
1915 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1917 if (termios->c_cflag & CRTSCTS)
1918 efr |= UART_EFR_CTS;
1920 serial_outp(up, UART_LCR, 0xBF);
1921 serial_outp(up, UART_EFR, efr);
1924 if (up->capabilities & UART_NATSEMI) {
1925 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1926 serial_outp(up, UART_LCR, 0xe0);
1928 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1931 serial_dl_write(up, quot);
1934 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1935 * is written without DLAB set, this mode will be disabled.
1937 if (up->port.type == PORT_16750)
1938 serial_outp(up, UART_FCR, fcr);
1940 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1941 up->lcr = cval; /* Save LCR */
1942 if (up->port.type != PORT_16750) {
1943 if (fcr & UART_FCR_ENABLE_FIFO) {
1944 /* emulated UARTs (Lucent Venus 167x) need two steps */
1945 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1947 serial_outp(up, UART_FCR, fcr); /* set fcr */
1949 serial8250_set_mctrl(&up->port, up->port.mctrl);
1950 spin_unlock_irqrestore(&up->port.lock, flags);
1954 serial8250_pm(struct uart_port *port, unsigned int state,
1955 unsigned int oldstate)
1957 struct uart_8250_port *p = (struct uart_8250_port *)port;
1959 serial8250_set_sleep(p, state != 0);
1962 p->pm(port, state, oldstate);
1966 * Resource handling.
1968 static int serial8250_request_std_resource(struct uart_8250_port *up)
1970 unsigned int size = 8 << up->port.regshift;
1973 switch (up->port.iotype) {
1978 if (!up->port.mapbase)
1981 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1986 if (up->port.flags & UPF_IOREMAP) {
1987 up->port.membase = ioremap(up->port.mapbase, size);
1988 if (!up->port.membase) {
1989 release_mem_region(up->port.mapbase, size);
1997 if (!request_region(up->port.iobase, size, "serial"))
2004 static void serial8250_release_std_resource(struct uart_8250_port *up)
2006 unsigned int size = 8 << up->port.regshift;
2008 switch (up->port.iotype) {
2013 if (!up->port.mapbase)
2016 if (up->port.flags & UPF_IOREMAP) {
2017 iounmap(up->port.membase);
2018 up->port.membase = NULL;
2021 release_mem_region(up->port.mapbase, size);
2026 release_region(up->port.iobase, size);
2031 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2033 unsigned long start = UART_RSA_BASE << up->port.regshift;
2034 unsigned int size = 8 << up->port.regshift;
2037 switch (up->port.iotype) {
2044 start += up->port.iobase;
2045 if (!request_region(start, size, "serial-rsa"))
2053 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2055 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2056 unsigned int size = 8 << up->port.regshift;
2058 switch (up->port.iotype) {
2064 release_region(up->port.iobase + offset, size);
2069 static void serial8250_release_port(struct uart_port *port)
2071 struct uart_8250_port *up = (struct uart_8250_port *)port;
2073 serial8250_release_std_resource(up);
2074 if (up->port.type == PORT_RSA)
2075 serial8250_release_rsa_resource(up);
2078 static int serial8250_request_port(struct uart_port *port)
2080 struct uart_8250_port *up = (struct uart_8250_port *)port;
2083 ret = serial8250_request_std_resource(up);
2084 if (ret == 0 && up->port.type == PORT_RSA) {
2085 ret = serial8250_request_rsa_resource(up);
2087 serial8250_release_std_resource(up);
2093 static void serial8250_config_port(struct uart_port *port, int flags)
2095 struct uart_8250_port *up = (struct uart_8250_port *)port;
2096 int probeflags = PROBE_ANY;
2100 * Find the region that we can probe for. This in turn
2101 * tells us whether we can probe for the type of port.
2103 ret = serial8250_request_std_resource(up);
2107 ret = serial8250_request_rsa_resource(up);
2109 probeflags &= ~PROBE_RSA;
2111 if (flags & UART_CONFIG_TYPE)
2112 autoconfig(up, probeflags);
2113 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2116 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2117 serial8250_release_rsa_resource(up);
2118 if (up->port.type == PORT_UNKNOWN)
2119 serial8250_release_std_resource(up);
2123 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2125 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2126 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2127 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2128 ser->type == PORT_STARTECH)
2134 serial8250_type(struct uart_port *port)
2136 int type = port->type;
2138 if (type >= ARRAY_SIZE(uart_config))
2140 return uart_config[type].name;
2143 static struct uart_ops serial8250_pops = {
2144 .tx_empty = serial8250_tx_empty,
2145 .set_mctrl = serial8250_set_mctrl,
2146 .get_mctrl = serial8250_get_mctrl,
2147 .stop_tx = serial8250_stop_tx,
2148 .start_tx = serial8250_start_tx,
2149 .stop_rx = serial8250_stop_rx,
2150 .enable_ms = serial8250_enable_ms,
2151 .break_ctl = serial8250_break_ctl,
2152 .startup = serial8250_startup,
2153 .shutdown = serial8250_shutdown,
2154 .set_termios = serial8250_set_termios,
2155 .pm = serial8250_pm,
2156 .type = serial8250_type,
2157 .release_port = serial8250_release_port,
2158 .request_port = serial8250_request_port,
2159 .config_port = serial8250_config_port,
2160 .verify_port = serial8250_verify_port,
2163 static struct uart_8250_port serial8250_ports[UART_NR];
2165 static void __init serial8250_isa_init_ports(void)
2167 struct uart_8250_port *up;
2168 static int first = 1;
2175 for (i = 0; i < nr_uarts; i++) {
2176 struct uart_8250_port *up = &serial8250_ports[i];
2179 spin_lock_init(&up->port.lock);
2181 init_timer(&up->timer);
2182 up->timer.function = serial8250_timeout;
2185 * ALPHA_KLUDGE_MCR needs to be killed.
2187 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2188 up->mcr_force = ALPHA_KLUDGE_MCR;
2190 up->port.ops = &serial8250_pops;
2193 for (i = 0, up = serial8250_ports;
2194 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2196 up->port.iobase = old_serial_port[i].port;
2197 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2198 up->port.uartclk = old_serial_port[i].baud_base * 16;
2199 up->port.flags = old_serial_port[i].flags;
2200 up->port.hub6 = old_serial_port[i].hub6;
2201 up->port.membase = old_serial_port[i].iomem_base;
2202 up->port.iotype = old_serial_port[i].io_type;
2203 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2205 up->port.flags |= UPF_SHARE_IRQ;
2210 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2214 serial8250_isa_init_ports();
2216 for (i = 0; i < nr_uarts; i++) {
2217 struct uart_8250_port *up = &serial8250_ports[i];
2220 uart_add_one_port(drv, &up->port);
2224 #ifdef CONFIG_SERIAL_8250_CONSOLE
2226 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2229 * Wait for transmitter & holding register to empty
2231 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
2233 unsigned int status, tmout = 10000;
2235 /* Wait up to 10ms for the character(s) to be sent. */
2237 status = serial_in(up, UART_LSR);
2239 if (status & UART_LSR_BI)
2240 up->lsr_break_flag = UART_LSR_BI;
2245 } while ((status & bits) != bits);
2247 /* Wait up to 1s for flow control if necessary */
2248 if (up->port.flags & UPF_CONS_FLOW) {
2250 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
2252 if ((tmout % 1000) == 0)
2253 touch_nmi_watchdog();
2258 static void serial8250_console_putchar(struct uart_port *port, int ch)
2260 struct uart_8250_port *up = (struct uart_8250_port *)port;
2262 wait_for_xmitr(up, UART_LSR_THRE);
2263 serial_out(up, UART_TX, ch);
2267 * Print a string to the serial port trying not to disturb
2268 * any possible real use of the port...
2270 * The console_lock must be held when we get here.
2273 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2275 struct uart_8250_port *up = &serial8250_ports[co->index];
2276 unsigned long flags;
2280 touch_nmi_watchdog();
2282 local_irq_save(flags);
2283 if (up->port.sysrq) {
2284 /* serial8250_handle_port() already took the lock */
2286 } else if (oops_in_progress) {
2287 locked = spin_trylock(&up->port.lock);
2289 spin_lock(&up->port.lock);
2292 * First save the IER then disable the interrupts
2294 ier = serial_in(up, UART_IER);
2296 if (up->capabilities & UART_CAP_UUE)
2297 serial_out(up, UART_IER, UART_IER_UUE);
2299 serial_out(up, UART_IER, 0);
2301 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2304 * Finally, wait for transmitter to become empty
2305 * and restore the IER
2307 wait_for_xmitr(up, BOTH_EMPTY);
2308 serial_out(up, UART_IER, ier);
2311 spin_unlock(&up->port.lock);
2312 local_irq_restore(flags);
2315 static int serial8250_console_setup(struct console *co, char *options)
2317 struct uart_port *port;
2324 * Check whether an invalid uart number has been specified, and
2325 * if so, search for the first available port that does have
2328 if (co->index >= nr_uarts)
2330 port = &serial8250_ports[co->index].port;
2331 if (!port->iobase && !port->membase)
2335 uart_parse_options(options, &baud, &parity, &bits, &flow);
2337 return uart_set_options(port, co, baud, parity, bits, flow);
2340 static struct uart_driver serial8250_reg;
2341 static struct console serial8250_console = {
2343 .write = serial8250_console_write,
2344 .device = uart_console_device,
2345 .setup = serial8250_console_setup,
2346 .flags = CON_PRINTBUFFER,
2348 .data = &serial8250_reg,
2351 static int __init serial8250_console_init(void)
2353 serial8250_isa_init_ports();
2354 register_console(&serial8250_console);
2357 console_initcall(serial8250_console_init);
2359 static int __init find_port(struct uart_port *p)
2362 struct uart_port *port;
2364 for (line = 0; line < nr_uarts; line++) {
2365 port = &serial8250_ports[line].port;
2366 if (uart_match_port(p, port))
2372 int __init serial8250_start_console(struct uart_port *port, char *options)
2376 line = find_port(port);
2380 add_preferred_console("ttyS", line, options);
2381 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2382 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2383 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2384 (unsigned long) port->iobase, options);
2385 if (!(serial8250_console.flags & CON_ENABLED)) {
2386 serial8250_console.flags &= ~CON_PRINTBUFFER;
2387 register_console(&serial8250_console);
2392 #define SERIAL8250_CONSOLE &serial8250_console
2394 #define SERIAL8250_CONSOLE NULL
2397 static struct uart_driver serial8250_reg = {
2398 .owner = THIS_MODULE,
2399 .driver_name = "serial",
2404 .cons = SERIAL8250_CONSOLE,
2408 * early_serial_setup - early registration for 8250 ports
2410 * Setup an 8250 port structure prior to console initialisation. Use
2411 * after console initialisation will cause undefined behaviour.
2413 int __init early_serial_setup(struct uart_port *port)
2415 if (port->line >= ARRAY_SIZE(serial8250_ports))
2418 serial8250_isa_init_ports();
2419 serial8250_ports[port->line].port = *port;
2420 serial8250_ports[port->line].port.ops = &serial8250_pops;
2425 * serial8250_suspend_port - suspend one serial port
2426 * @line: serial line number
2427 * @level: the level of port suspension, as per uart_suspend_port
2429 * Suspend one serial port.
2431 void serial8250_suspend_port(int line)
2433 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2437 * serial8250_resume_port - resume one serial port
2438 * @line: serial line number
2439 * @level: the level of port resumption, as per uart_resume_port
2441 * Resume one serial port.
2443 void serial8250_resume_port(int line)
2445 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2449 * Register a set of serial devices attached to a platform device. The
2450 * list is terminated with a zero flags entry, which means we expect
2451 * all entries to have at least UPF_BOOT_AUTOCONF set.
2453 static int __devinit serial8250_probe(struct platform_device *dev)
2455 struct plat_serial8250_port *p = dev->dev.platform_data;
2456 struct uart_port port;
2459 memset(&port, 0, sizeof(struct uart_port));
2461 for (i = 0; p && p->flags != 0; p++, i++) {
2462 port.iobase = p->iobase;
2463 port.membase = p->membase;
2465 port.uartclk = p->uartclk;
2466 port.regshift = p->regshift;
2467 port.iotype = p->iotype;
2468 port.flags = p->flags;
2469 port.mapbase = p->mapbase;
2470 port.hub6 = p->hub6;
2471 port.dev = &dev->dev;
2473 port.flags |= UPF_SHARE_IRQ;
2474 ret = serial8250_register_port(&port);
2476 dev_err(&dev->dev, "unable to register port at index %d "
2477 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2478 p->iobase, p->mapbase, p->irq, ret);
2485 * Remove serial ports registered against a platform device.
2487 static int __devexit serial8250_remove(struct platform_device *dev)
2491 for (i = 0; i < nr_uarts; i++) {
2492 struct uart_8250_port *up = &serial8250_ports[i];
2494 if (up->port.dev == &dev->dev)
2495 serial8250_unregister_port(i);
2500 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2504 for (i = 0; i < UART_NR; i++) {
2505 struct uart_8250_port *up = &serial8250_ports[i];
2507 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2508 uart_suspend_port(&serial8250_reg, &up->port);
2514 static int serial8250_resume(struct platform_device *dev)
2518 for (i = 0; i < UART_NR; i++) {
2519 struct uart_8250_port *up = &serial8250_ports[i];
2521 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2522 uart_resume_port(&serial8250_reg, &up->port);
2528 static struct platform_driver serial8250_isa_driver = {
2529 .probe = serial8250_probe,
2530 .remove = __devexit_p(serial8250_remove),
2531 .suspend = serial8250_suspend,
2532 .resume = serial8250_resume,
2534 .name = "serial8250",
2535 .owner = THIS_MODULE,
2540 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2541 * in the table in include/asm/serial.h
2543 static struct platform_device *serial8250_isa_devs;
2546 * serial8250_register_port and serial8250_unregister_port allows for
2547 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2548 * modems and PCI multiport cards.
2550 static DEFINE_MUTEX(serial_mutex);
2552 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2557 * First, find a port entry which matches.
2559 for (i = 0; i < nr_uarts; i++)
2560 if (uart_match_port(&serial8250_ports[i].port, port))
2561 return &serial8250_ports[i];
2564 * We didn't find a matching entry, so look for the first
2565 * free entry. We look for one which hasn't been previously
2566 * used (indicated by zero iobase).
2568 for (i = 0; i < nr_uarts; i++)
2569 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2570 serial8250_ports[i].port.iobase == 0)
2571 return &serial8250_ports[i];
2574 * That also failed. Last resort is to find any entry which
2575 * doesn't have a real port associated with it.
2577 for (i = 0; i < nr_uarts; i++)
2578 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2579 return &serial8250_ports[i];
2585 * serial8250_register_port - register a serial port
2586 * @port: serial port template
2588 * Configure the serial port specified by the request. If the
2589 * port exists and is in use, it is hung up and unregistered
2592 * The port is then probed and if necessary the IRQ is autodetected
2593 * If this fails an error is returned.
2595 * On success the port is ready to use and the line number is returned.
2597 int serial8250_register_port(struct uart_port *port)
2599 struct uart_8250_port *uart;
2602 if (port->uartclk == 0)
2605 mutex_lock(&serial_mutex);
2607 uart = serial8250_find_match_or_unused(port);
2609 uart_remove_one_port(&serial8250_reg, &uart->port);
2611 uart->port.iobase = port->iobase;
2612 uart->port.membase = port->membase;
2613 uart->port.irq = port->irq;
2614 uart->port.uartclk = port->uartclk;
2615 uart->port.fifosize = port->fifosize;
2616 uart->port.regshift = port->regshift;
2617 uart->port.iotype = port->iotype;
2618 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2619 uart->port.mapbase = port->mapbase;
2621 uart->port.dev = port->dev;
2623 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2625 ret = uart->port.line;
2627 mutex_unlock(&serial_mutex);
2631 EXPORT_SYMBOL(serial8250_register_port);
2634 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2635 * @line: serial line number
2637 * Remove one serial port. This may not be called from interrupt
2638 * context. We hand the port back to the our control.
2640 void serial8250_unregister_port(int line)
2642 struct uart_8250_port *uart = &serial8250_ports[line];
2644 mutex_lock(&serial_mutex);
2645 uart_remove_one_port(&serial8250_reg, &uart->port);
2646 if (serial8250_isa_devs) {
2647 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2648 uart->port.type = PORT_UNKNOWN;
2649 uart->port.dev = &serial8250_isa_devs->dev;
2650 uart_add_one_port(&serial8250_reg, &uart->port);
2652 uart->port.dev = NULL;
2654 mutex_unlock(&serial_mutex);
2656 EXPORT_SYMBOL(serial8250_unregister_port);
2658 static int __init serial8250_init(void)
2662 if (nr_uarts > UART_NR)
2665 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2666 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2667 share_irqs ? "en" : "dis");
2669 for (i = 0; i < NR_IRQS; i++)
2670 spin_lock_init(&irq_lists[i].lock);
2672 ret = uart_register_driver(&serial8250_reg);
2676 serial8250_isa_devs = platform_device_alloc("serial8250",
2677 PLAT8250_DEV_LEGACY);
2678 if (!serial8250_isa_devs) {
2680 goto unreg_uart_drv;
2683 ret = platform_device_add(serial8250_isa_devs);
2687 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2689 ret = platform_driver_register(&serial8250_isa_driver);
2693 platform_device_del(serial8250_isa_devs);
2695 platform_device_put(serial8250_isa_devs);
2697 uart_unregister_driver(&serial8250_reg);
2702 static void __exit serial8250_exit(void)
2704 struct platform_device *isa_dev = serial8250_isa_devs;
2707 * This tells serial8250_unregister_port() not to re-register
2708 * the ports (thereby making serial8250_isa_driver permanently
2711 serial8250_isa_devs = NULL;
2713 platform_driver_unregister(&serial8250_isa_driver);
2714 platform_device_unregister(isa_dev);
2716 uart_unregister_driver(&serial8250_reg);
2719 module_init(serial8250_init);
2720 module_exit(serial8250_exit);
2722 EXPORT_SYMBOL(serial8250_suspend_port);
2723 EXPORT_SYMBOL(serial8250_resume_port);
2725 MODULE_LICENSE("GPL");
2726 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2728 module_param(share_irqs, uint, 0644);
2729 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2732 module_param(nr_uarts, uint, 0644);
2733 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2735 #ifdef CONFIG_SERIAL_8250_RSA
2736 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2737 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2739 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);