2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial.h>
26 #include <linux/serial_core.h>
27 #include <linux/8250_pci.h>
29 #include <asm/bitops.h>
30 #include <asm/byteorder.h>
36 * Definitions for PCI support.
38 #define FL_BASE_MASK 0x0007
39 #define FL_BASE0 0x0000
40 #define FL_BASE1 0x0001
41 #define FL_BASE2 0x0002
42 #define FL_BASE3 0x0003
43 #define FL_BASE4 0x0004
44 #define FL_GET_BASE(x) (x & FL_BASE_MASK)
46 /* Use successive BARs (PCI base address registers),
47 else use offset into some specified BAR */
48 #define FL_BASE_BARS 0x0008
50 /* do not assign an irq */
51 #define FL_NOIRQ 0x0080
53 /* Use the Base address register size to cap number of ports */
54 #define FL_REGION_SZ_CAP 0x0100
58 unsigned int num_ports;
59 unsigned int base_baud;
60 unsigned int uart_offset;
61 unsigned int reg_shift;
62 unsigned int first_offset;
66 * init function returns:
67 * > 0 - number of ports
68 * = 0 - use board->num_ports
71 struct pci_serial_quirk {
76 int (*init)(struct pci_dev *dev);
77 int (*setup)(struct pci_dev *dev, struct pci_board *board,
78 struct serial_struct *req, int idx);
79 void (*exit)(struct pci_dev *dev);
82 #define PCI_NUM_BAR_RESOURCES 6
84 struct serial_private {
86 void *remapped_bar[PCI_NUM_BAR_RESOURCES];
87 struct pci_serial_quirk *quirk;
91 static void moan_device(const char *str, struct pci_dev *dev)
93 printk(KERN_WARNING "%s: %s\n"
94 KERN_WARNING "Please send the output of lspci -vv, this\n"
95 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
96 KERN_WARNING "manufacturer and name of serial board or\n"
97 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
98 pci_name(dev), str, dev->vendor, dev->device,
99 dev->subsystem_vendor, dev->subsystem_device);
103 setup_port(struct pci_dev *dev, struct serial_struct *req,
104 int bar, int offset, int regshift)
106 struct serial_private *priv = pci_get_drvdata(dev);
107 unsigned long port, len;
109 if (bar >= PCI_NUM_BAR_RESOURCES)
112 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
113 port = pci_resource_start(dev, bar);
114 len = pci_resource_len(dev, bar);
116 if (!priv->remapped_bar[bar])
117 priv->remapped_bar[bar] = ioremap(port, len);
118 if (!priv->remapped_bar[bar])
121 req->io_type = UPIO_MEM;
122 req->iomap_base = port + offset;
123 req->iomem_base = priv->remapped_bar[bar] + offset;
124 req->iomem_reg_shift = regshift;
126 port = pci_resource_start(dev, bar) + offset;
127 req->io_type = UPIO_PORT;
129 if (HIGH_BITS_OFFSET)
130 req->port_high = port >> HIGH_BITS_OFFSET;
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
140 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
141 struct serial_struct *req, int idx)
143 unsigned int bar, offset = board->first_offset;
145 bar = FL_GET_BASE(board->flags);
150 offset += (idx - 4) * board->uart_offset;
153 return setup_port(dev, req, bar, offset, board->reg_shift);
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
163 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
194 struct serial_struct *req, int idx)
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
199 switch (dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 offset += idx * board->uart_offset;
216 return setup_port(dev, req, bar, offset, board->reg_shift);
220 * Added for EKF Intel i960 serial boards
222 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
224 unsigned long oldval;
226 if (!(dev->subsystem_device & 0x1000))
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void*) &oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
244 static int __devinit pci_plx9050_init(struct pci_dev *dev)
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
254 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
256 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
257 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
259 * As the megawolf cards have the int pins active
260 * high, and have 2 UART chips, both ints must be
261 * enabled on the 9050. Also, the UARTS are set in
262 * 16450 mode by default, so we have to enable the
263 * 16C950 'enhanced' mode so that we can use the
270 * enable/disable interrupts
272 p = ioremap(pci_resource_start(dev, 0), 0x80);
275 writel(irq_config, (unsigned long)p + 0x4c);
278 * Read the register back to ensure that it took effect.
280 readl((unsigned long)p + 0x4c);
286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 p = ioremap(pci_resource_start(dev, 0), 0x80);
301 * Read the register back to ensure that it took effect.
308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310 sbs_setup(struct pci_dev *dev, struct pci_board *board,
311 struct serial_struct *req, int idx)
313 unsigned int bar, offset = board->first_offset;
318 /* first four channels map to 0, 0x100, 0x200, 0x300 */
319 offset += idx * board->uart_offset;
320 } else if (idx < 8) {
321 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
322 offset += idx * board->uart_offset + 0xC00;
323 } else /* we have only 8 ports on PMC-OCTALPRO */
326 return setup_port(dev, req, bar, offset, board->reg_shift);
330 * This does initialization for PMC OCTALPRO cards:
331 * maps the device memory, resets the UARTs (needed, bc
332 * if the module is removed and inserted again, the card
333 * is in the sleep mode) and enables global interrupt.
336 /* global control register offset for SBS PMC-OctalPro */
337 #define OCT_REG_CR_OFF 0x500
339 static int __devinit sbs_init(struct pci_dev *dev)
343 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10,p + OCT_REG_CR_OFF);
350 writeb(0x0,p + OCT_REG_CR_OFF);
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p + OCT_REG_CR_OFF);
360 * Disables the global interrupt of PMC-OctalPro
363 static void __devexit sbs_exit(struct pci_dev *dev)
367 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
369 writeb(0, p + OCT_REG_CR_OFF);
375 * SIIG serial cards have an PCI interface chip which also controls
376 * the UART clocking frequency. Each UART can be clocked independently
377 * (except cards equiped with 4 UARTs) and initial clocking settings
378 * are stored in the EEPROM chip. It can cause problems because this
379 * version of serial driver doesn't support differently clocked UART's
380 * on single PCI card. To prevent this, initialization functions set
381 * high frequency clocking for all UART's on given card. It is safe (I
382 * hope) because it doesn't touch EEPROM settings to prevent conflicts
383 * with other OSes (like M$ DOS).
385 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
387 * There is two family of SIIG serial cards with different PCI
388 * interface chip and different configuration methods:
389 * - 10x cards have control registers in IO and/or memory space;
390 * - 20x cards have control registers in standard PCI configuration space.
392 * Note: some SIIG cards are probed by the parport_serial object.
395 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
396 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
398 static int pci_siig10x_init(struct pci_dev *dev)
402 switch (dev->device & 0xfff8) {
403 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
406 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
409 default: /* 1S1P, 4S */
414 p = ioremap(pci_resource_start(dev, 0), 0x80);
418 writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
419 readw((unsigned long)p + 0x28);
424 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
425 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
427 static int pci_siig20x_init(struct pci_dev *dev)
431 /* Change clock frequency for the first UART. */
432 pci_read_config_byte(dev, 0x6f, &data);
433 pci_write_config_byte(dev, 0x6f, data & 0xef);
435 /* If this card has 2 UART, we have to do the same with second UART. */
436 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
437 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
438 pci_read_config_byte(dev, 0x73, &data);
439 pci_write_config_byte(dev, 0x73, data & 0xef);
444 int pci_siig10x_fn(struct pci_dev *dev, int enable)
448 ret = pci_siig10x_init(dev);
452 int pci_siig20x_fn(struct pci_dev *dev, int enable)
456 ret = pci_siig20x_init(dev);
460 EXPORT_SYMBOL(pci_siig10x_fn);
461 EXPORT_SYMBOL(pci_siig20x_fn);
464 * Timedia has an explosion of boards, and to avoid the PCI table from
465 * growing *huge*, we use this function to collapse some 70 entries
466 * in the PCI table into one, for sanity's and compactness's sake.
468 static unsigned short timedia_single_port[] = {
469 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
472 static unsigned short timedia_dual_port[] = {
473 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
474 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
475 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
476 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
480 static unsigned short timedia_quad_port[] = {
481 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
482 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
483 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
487 static unsigned short timedia_eight_port[] = {
488 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
489 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
492 static struct timedia_struct {
496 { 1, timedia_single_port },
497 { 2, timedia_dual_port },
498 { 4, timedia_quad_port },
499 { 8, timedia_eight_port },
503 static int __devinit pci_timedia_init(struct pci_dev *dev)
508 for (i = 0; timedia_data[i].num; i++) {
509 ids = timedia_data[i].ids;
510 for (j = 0; ids[j]; j++)
511 if (dev->subsystem_device == ids[j])
512 return timedia_data[i].num;
518 * Timedia/SUNIX uses a mixture of BARs and offsets
519 * Ugh, this is ugly as all hell --- TYT
522 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
523 struct serial_struct *req, int idx)
525 unsigned int bar = 0, offset = board->first_offset;
532 offset = board->uart_offset;
539 offset = board->uart_offset;
548 return setup_port(dev, req, bar, offset, board->reg_shift);
552 * Some Titan cards are also a little weird
555 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
556 struct serial_struct *req, int idx)
558 unsigned int bar, offset = board->first_offset;
569 offset = (idx - 2) * board->uart_offset;
572 return setup_port(dev, req, bar, offset, board->reg_shift);
575 static int __devinit pci_xircom_init(struct pci_dev *dev)
577 __set_current_state(TASK_UNINTERRUPTIBLE);
578 schedule_timeout(HZ/10);
583 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
584 struct serial_struct *req, int idx)
586 unsigned int bar, offset = board->first_offset, maxnr;
588 bar = FL_GET_BASE(board->flags);
589 if (board->flags & FL_BASE_BARS)
592 offset += idx * board->uart_offset;
594 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
595 (8 << board->reg_shift);
597 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
600 return setup_port(dev, req, bar, offset, board->reg_shift);
603 /* This should be in linux/pci_ids.h */
604 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
605 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
606 #define PCI_DEVICE_ID_OCTPRO 0x0001
607 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
608 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
609 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
610 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
613 * Master list of serial port init/setup/exit quirks.
614 * This does not describe the general nature of the port.
615 * (ie, baud base, number and location of ports, etc)
617 * This list is ordered alphabetically by vendor then device.
618 * Specific entries must come before more generic entries.
620 static struct pci_serial_quirk pci_serial_quirks[] = {
623 * It is not clear whether this applies to all products.
626 .vendor = PCI_VENDOR_ID_AFAVLAB,
627 .device = PCI_ANY_ID,
628 .subvendor = PCI_ANY_ID,
629 .subdevice = PCI_ANY_ID,
630 .setup = afavlab_setup,
636 .vendor = PCI_VENDOR_ID_HP,
637 .device = PCI_DEVICE_ID_HP_DIVA,
638 .subvendor = PCI_ANY_ID,
639 .subdevice = PCI_ANY_ID,
640 .init = pci_hp_diva_init,
641 .setup = pci_hp_diva_setup,
647 .vendor = PCI_VENDOR_ID_INTEL,
648 .device = PCI_DEVICE_ID_INTEL_80960_RP,
650 .subdevice = PCI_ANY_ID,
651 .init = pci_inteli960ni_init,
652 .setup = pci_default_setup,
658 .vendor = PCI_VENDOR_ID_PANACOM,
659 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
660 .subvendor = PCI_ANY_ID,
661 .subdevice = PCI_ANY_ID,
662 .init = pci_plx9050_init,
663 .setup = pci_default_setup,
664 .exit = __devexit_p(pci_plx9050_exit),
667 .vendor = PCI_VENDOR_ID_PANACOM,
668 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
669 .subvendor = PCI_ANY_ID,
670 .subdevice = PCI_ANY_ID,
671 .init = pci_plx9050_init,
672 .setup = pci_default_setup,
673 .exit = __devexit_p(pci_plx9050_exit),
679 .vendor = PCI_VENDOR_ID_PLX,
680 .device = PCI_DEVICE_ID_PLX_9050,
681 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
682 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
683 .init = pci_plx9050_init,
684 .setup = pci_default_setup,
685 .exit = __devexit_p(pci_plx9050_exit),
688 .vendor = PCI_VENDOR_ID_PLX,
689 .device = PCI_DEVICE_ID_PLX_ROMULUS,
690 .subvendor = PCI_VENDOR_ID_PLX,
691 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
692 .init = pci_plx9050_init,
693 .setup = pci_default_setup,
694 .exit = __devexit_p(pci_plx9050_exit),
697 * SBS Technologies, Inc., PMC-OCTALPRO 232
700 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
701 .device = PCI_DEVICE_ID_OCTPRO,
702 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
703 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
706 .exit = __devexit_p(sbs_exit),
709 * SBS Technologies, Inc., PMC-OCTALPRO 422
712 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
713 .device = PCI_DEVICE_ID_OCTPRO,
714 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
715 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
718 .exit = __devexit_p(sbs_exit),
721 * SBS Technologies, Inc., P-Octal 232
724 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
725 .device = PCI_DEVICE_ID_OCTPRO,
726 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
727 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
730 .exit = __devexit_p(sbs_exit),
733 * SBS Technologies, Inc., P-Octal 422
736 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
737 .device = PCI_DEVICE_ID_OCTPRO,
738 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
739 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
742 .exit = __devexit_p(sbs_exit),
747 * It is not clear whether these could be collapsed.
750 .vendor = PCI_VENDOR_ID_SIIG,
751 .device = PCI_DEVICE_ID_SIIG_1S_10x_550,
752 .subvendor = PCI_ANY_ID,
753 .subdevice = PCI_ANY_ID,
754 .init = pci_siig10x_init,
755 .setup = pci_default_setup,
758 .vendor = PCI_VENDOR_ID_SIIG,
759 .device = PCI_DEVICE_ID_SIIG_1S_10x_650,
760 .subvendor = PCI_ANY_ID,
761 .subdevice = PCI_ANY_ID,
762 .init = pci_siig10x_init,
763 .setup = pci_default_setup,
766 .vendor = PCI_VENDOR_ID_SIIG,
767 .device = PCI_DEVICE_ID_SIIG_1S_10x_850,
768 .subvendor = PCI_ANY_ID,
769 .subdevice = PCI_ANY_ID,
770 .init = pci_siig10x_init,
771 .setup = pci_default_setup,
774 .vendor = PCI_VENDOR_ID_SIIG,
775 .device = PCI_DEVICE_ID_SIIG_2S_10x_550,
776 .subvendor = PCI_ANY_ID,
777 .subdevice = PCI_ANY_ID,
778 .init = pci_siig10x_init,
779 .setup = pci_default_setup,
782 .vendor = PCI_VENDOR_ID_SIIG,
783 .device = PCI_DEVICE_ID_SIIG_2S_10x_650,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .init = pci_siig10x_init,
787 .setup = pci_default_setup,
790 .vendor = PCI_VENDOR_ID_SIIG,
791 .device = PCI_DEVICE_ID_SIIG_2S_10x_850,
792 .subvendor = PCI_ANY_ID,
793 .subdevice = PCI_ANY_ID,
794 .init = pci_siig10x_init,
795 .setup = pci_default_setup,
798 .vendor = PCI_VENDOR_ID_SIIG,
799 .device = PCI_DEVICE_ID_SIIG_4S_10x_550,
800 .subvendor = PCI_ANY_ID,
801 .subdevice = PCI_ANY_ID,
802 .init = pci_siig10x_init,
803 .setup = pci_default_setup,
806 .vendor = PCI_VENDOR_ID_SIIG,
807 .device = PCI_DEVICE_ID_SIIG_4S_10x_650,
808 .subvendor = PCI_ANY_ID,
809 .subdevice = PCI_ANY_ID,
810 .init = pci_siig10x_init,
811 .setup = pci_default_setup,
814 .vendor = PCI_VENDOR_ID_SIIG,
815 .device = PCI_DEVICE_ID_SIIG_4S_10x_850,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .init = pci_siig10x_init,
819 .setup = pci_default_setup,
822 .vendor = PCI_VENDOR_ID_SIIG,
823 .device = PCI_DEVICE_ID_SIIG_1S_20x_550,
824 .subvendor = PCI_ANY_ID,
825 .subdevice = PCI_ANY_ID,
826 .init = pci_siig20x_init,
827 .setup = pci_default_setup,
830 .vendor = PCI_VENDOR_ID_SIIG,
831 .device = PCI_DEVICE_ID_SIIG_1S_20x_650,
832 .subvendor = PCI_ANY_ID,
833 .subdevice = PCI_ANY_ID,
834 .init = pci_siig20x_init,
835 .setup = pci_default_setup,
838 .vendor = PCI_VENDOR_ID_SIIG,
839 .device = PCI_DEVICE_ID_SIIG_1S_20x_850,
840 .subvendor = PCI_ANY_ID,
841 .subdevice = PCI_ANY_ID,
842 .init = pci_siig20x_init,
843 .setup = pci_default_setup,
846 .vendor = PCI_VENDOR_ID_SIIG,
847 .device = PCI_DEVICE_ID_SIIG_2S_20x_550,
848 .subvendor = PCI_ANY_ID,
849 .subdevice = PCI_ANY_ID,
850 .init = pci_siig20x_init,
851 .setup = pci_default_setup,
853 { .vendor = PCI_VENDOR_ID_SIIG,
854 .device = PCI_DEVICE_ID_SIIG_2S_20x_650,
855 .subvendor = PCI_ANY_ID,
856 .subdevice = PCI_ANY_ID,
857 .init = pci_siig20x_init,
858 .setup = pci_default_setup,
861 .vendor = PCI_VENDOR_ID_SIIG,
862 .device = PCI_DEVICE_ID_SIIG_2S_20x_850,
863 .subvendor = PCI_ANY_ID,
864 .subdevice = PCI_ANY_ID,
865 .init = pci_siig20x_init,
866 .setup = pci_default_setup,
869 .vendor = PCI_VENDOR_ID_SIIG,
870 .device = PCI_DEVICE_ID_SIIG_4S_20x_550,
871 .subvendor = PCI_ANY_ID,
872 .subdevice = PCI_ANY_ID,
873 .init = pci_siig20x_init,
874 .setup = pci_default_setup,
877 .vendor = PCI_VENDOR_ID_SIIG,
878 .device = PCI_DEVICE_ID_SIIG_4S_20x_650,
879 .subvendor = PCI_ANY_ID,
880 .subdevice = PCI_ANY_ID,
881 .init = pci_siig20x_init,
882 .setup = pci_default_setup,
885 .vendor = PCI_VENDOR_ID_SIIG,
886 .device = PCI_DEVICE_ID_SIIG_4S_20x_850,
887 .subvendor = PCI_ANY_ID,
888 .subdevice = PCI_ANY_ID,
889 .init = pci_siig20x_init,
890 .setup = pci_default_setup,
896 .vendor = PCI_VENDOR_ID_TITAN,
897 .device = PCI_DEVICE_ID_TITAN_400L,
898 .subvendor = PCI_ANY_ID,
899 .subdevice = PCI_ANY_ID,
900 .setup = titan_400l_800l_setup,
903 .vendor = PCI_VENDOR_ID_TITAN,
904 .device = PCI_DEVICE_ID_TITAN_800L,
905 .subvendor = PCI_ANY_ID,
906 .subdevice = PCI_ANY_ID,
907 .setup = titan_400l_800l_setup,
913 .vendor = PCI_VENDOR_ID_TIMEDIA,
914 .device = PCI_DEVICE_ID_TIMEDIA_1889,
915 .subvendor = PCI_VENDOR_ID_TIMEDIA,
916 .subdevice = PCI_ANY_ID,
917 .init = pci_timedia_init,
918 .setup = pci_timedia_setup,
921 .vendor = PCI_VENDOR_ID_TIMEDIA,
922 .device = PCI_ANY_ID,
923 .subvendor = PCI_ANY_ID,
924 .subdevice = PCI_ANY_ID,
925 .setup = pci_timedia_setup,
931 .vendor = PCI_VENDOR_ID_XIRCOM,
932 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
933 .subvendor = PCI_ANY_ID,
934 .subdevice = PCI_ANY_ID,
935 .init = pci_xircom_init,
936 .setup = pci_default_setup,
939 * Default "match everything" terminator entry
942 .vendor = PCI_ANY_ID,
943 .device = PCI_ANY_ID,
944 .subvendor = PCI_ANY_ID,
945 .subdevice = PCI_ANY_ID,
946 .setup = pci_default_setup,
950 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
952 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
955 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
957 struct pci_serial_quirk *quirk;
959 for (quirk = pci_serial_quirks; ; quirk++)
960 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
961 quirk_id_matches(quirk->device, dev->device) &&
962 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
963 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
969 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
971 if (board->flags & FL_NOIRQ)
978 * This is the configuration table for all of the PCI serial boards
979 * which we support. It is directly indexed by the pci_board_num_t enum
980 * value, which is encoded in the pci_device_id PCI probe table's
981 * driver_data member.
983 * The makeup of these names are:
986 * bn = PCI BAR number
987 * bt = Index using PCI BARs
988 * n = number of serial ports
991 * Please note: in theory if n = 1, _bt infix should make no difference.
992 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
994 enum pci_board_num_t {
1058 * Board-specific versions.
1075 * uart_offset - the space between channels
1076 * reg_shift - describes how the UART registers are mapped
1077 * to PCI memory by the card.
1078 * For example IER register on SBS, Inc. PMC-OctPro is located at
1079 * offset 0x10 from the UART base, while UART_IER is defined as 1
1080 * in include/linux/serial_reg.h,
1081 * see first lines of serial_in() and serial_out() in 8250.c
1084 static struct pci_board pci_boards[] __devinitdata = {
1088 .base_baud = 115200,
1091 [pbn_b0_1_115200] = {
1094 .base_baud = 115200,
1097 [pbn_b0_2_115200] = {
1100 .base_baud = 115200,
1103 [pbn_b0_4_115200] = {
1106 .base_baud = 115200,
1109 [pbn_b0_5_115200] = {
1112 .base_baud = 115200,
1116 [pbn_b0_1_921600] = {
1119 .base_baud = 921600,
1122 [pbn_b0_2_921600] = {
1125 .base_baud = 921600,
1128 [pbn_b0_4_921600] = {
1131 .base_baud = 921600,
1135 [pbn_b0_bt_1_115200] = {
1136 .flags = FL_BASE0|FL_BASE_BARS,
1138 .base_baud = 115200,
1141 [pbn_b0_bt_2_115200] = {
1142 .flags = FL_BASE0|FL_BASE_BARS,
1144 .base_baud = 115200,
1147 [pbn_b0_bt_8_115200] = {
1148 .flags = FL_BASE0|FL_BASE_BARS,
1150 .base_baud = 115200,
1154 [pbn_b0_bt_1_460800] = {
1155 .flags = FL_BASE0|FL_BASE_BARS,
1157 .base_baud = 460800,
1160 [pbn_b0_bt_2_460800] = {
1161 .flags = FL_BASE0|FL_BASE_BARS,
1163 .base_baud = 460800,
1166 [pbn_b0_bt_4_460800] = {
1167 .flags = FL_BASE0|FL_BASE_BARS,
1169 .base_baud = 460800,
1173 [pbn_b0_bt_1_921600] = {
1174 .flags = FL_BASE0|FL_BASE_BARS,
1176 .base_baud = 921600,
1179 [pbn_b0_bt_2_921600] = {
1180 .flags = FL_BASE0|FL_BASE_BARS,
1182 .base_baud = 921600,
1185 [pbn_b0_bt_4_921600] = {
1186 .flags = FL_BASE0|FL_BASE_BARS,
1188 .base_baud = 921600,
1191 [pbn_b0_bt_8_921600] = {
1192 .flags = FL_BASE0|FL_BASE_BARS,
1194 .base_baud = 921600,
1198 [pbn_b1_1_115200] = {
1201 .base_baud = 115200,
1204 [pbn_b1_2_115200] = {
1207 .base_baud = 115200,
1210 [pbn_b1_4_115200] = {
1213 .base_baud = 115200,
1216 [pbn_b1_8_115200] = {
1219 .base_baud = 115200,
1223 [pbn_b1_1_921600] = {
1226 .base_baud = 921600,
1229 [pbn_b1_2_921600] = {
1232 .base_baud = 921600,
1235 [pbn_b1_4_921600] = {
1238 .base_baud = 921600,
1241 [pbn_b1_8_921600] = {
1244 .base_baud = 921600,
1248 [pbn_b1_bt_2_921600] = {
1249 .flags = FL_BASE1|FL_BASE_BARS,
1251 .base_baud = 921600,
1255 [pbn_b1_2_1382400] = {
1258 .base_baud = 1382400,
1261 [pbn_b1_4_1382400] = {
1264 .base_baud = 1382400,
1267 [pbn_b1_8_1382400] = {
1270 .base_baud = 1382400,
1274 [pbn_b2_1_115200] = {
1277 .base_baud = 115200,
1280 [pbn_b2_8_115200] = {
1283 .base_baud = 115200,
1287 [pbn_b2_1_460800] = {
1290 .base_baud = 460800,
1293 [pbn_b2_4_460800] = {
1296 .base_baud = 460800,
1299 [pbn_b2_8_460800] = {
1302 .base_baud = 460800,
1305 [pbn_b2_16_460800] = {
1308 .base_baud = 460800,
1312 [pbn_b2_1_921600] = {
1315 .base_baud = 921600,
1318 [pbn_b2_4_921600] = {
1321 .base_baud = 921600,
1324 [pbn_b2_8_921600] = {
1327 .base_baud = 921600,
1331 [pbn_b2_bt_1_115200] = {
1332 .flags = FL_BASE2|FL_BASE_BARS,
1334 .base_baud = 115200,
1337 [pbn_b2_bt_2_115200] = {
1338 .flags = FL_BASE2|FL_BASE_BARS,
1340 .base_baud = 115200,
1343 [pbn_b2_bt_4_115200] = {
1344 .flags = FL_BASE2|FL_BASE_BARS,
1346 .base_baud = 115200,
1350 [pbn_b2_bt_2_921600] = {
1351 .flags = FL_BASE2|FL_BASE_BARS,
1353 .base_baud = 921600,
1356 [pbn_b2_bt_4_921600] = {
1357 .flags = FL_BASE2|FL_BASE_BARS,
1359 .base_baud = 921600,
1363 [pbn_b3_4_115200] = {
1366 .base_baud = 115200,
1369 [pbn_b3_8_115200] = {
1372 .base_baud = 115200,
1377 * Entries following this are board-specific.
1386 .base_baud = 921600,
1387 .uart_offset = 0x400,
1391 .flags = FL_BASE2|FL_BASE_BARS,
1393 .base_baud = 921600,
1394 .uart_offset = 0x400,
1398 .flags = FL_BASE2|FL_BASE_BARS,
1400 .base_baud = 921600,
1401 .uart_offset = 0x400,
1405 /* I think this entry is broken - the first_offset looks wrong --rmk */
1406 [pbn_plx_romulus] = {
1409 .base_baud = 921600,
1410 .uart_offset = 8 << 2,
1412 .first_offset = 0x03,
1416 * This board uses the size of PCI Base region 0 to
1417 * signal now many ports are available
1420 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1422 .base_baud = 115200,
1427 * EKF addition for i960 Boards form EKF with serial port.
1430 [pbn_intel_i960] = {
1433 .base_baud = 921600,
1434 .uart_offset = 8 << 2,
1436 .first_offset = 0x10000,
1439 .flags = FL_BASE0|FL_NOIRQ,
1441 .base_baud = 458333,
1444 .first_offset = 0x20178,
1448 * NEC Vrc-5074 (Nile 4) builtin UART.
1453 .base_baud = 520833,
1454 .uart_offset = 8 << 3,
1456 .first_offset = 0x300,
1460 * Computone - uses IOMEM.
1462 [pbn_computone_4] = {
1465 .base_baud = 921600,
1466 .uart_offset = 0x40,
1468 .first_offset = 0x200,
1470 [pbn_computone_6] = {
1473 .base_baud = 921600,
1474 .uart_offset = 0x40,
1476 .first_offset = 0x200,
1478 [pbn_computone_8] = {
1481 .base_baud = 921600,
1482 .uart_offset = 0x40,
1484 .first_offset = 0x200,
1489 .base_baud = 460800,
1496 * Given a complete unknown PCI device, try to use some heuristics to
1497 * guess what the configuration might be, based on the pitiful PCI
1498 * serial specs. Returns 0 on success, 1 on failure.
1500 static int __devinit
1501 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1503 int num_iomem, num_port, first_port = -1, i;
1506 * If it is not a communications device or the programming
1507 * interface is greater than 6, give up.
1509 * (Should we try to make guesses for multiport serial devices
1512 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1513 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1514 (dev->class & 0xff) > 6)
1517 num_iomem = num_port = 0;
1518 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1519 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1521 if (first_port == -1)
1524 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1529 * If there is 1 or 0 iomem regions, and exactly one port,
1530 * use it. We guess the number of ports based on the IO
1533 if (num_iomem <= 1 && num_port == 1) {
1534 board->flags = first_port;
1535 board->num_ports = pci_resource_len(dev, first_port) / 8;
1540 * Now guess if we've got a board which indexes by BARs.
1541 * Each IO BAR should be 8 bytes, and they should follow
1546 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1547 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1548 pci_resource_len(dev, i) == 8 &&
1549 (first_port == -1 || (first_port + num_port) == i)) {
1551 if (first_port == -1)
1557 board->flags = first_port | FL_BASE_BARS;
1558 board->num_ports = num_port;
1566 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1569 board->num_ports == guessed->num_ports &&
1570 board->base_baud == guessed->base_baud &&
1571 board->uart_offset == guessed->uart_offset &&
1572 board->reg_shift == guessed->reg_shift &&
1573 board->first_offset == guessed->first_offset;
1577 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1578 * to the arrangement of serial ports on a PCI card.
1580 static int __devinit
1581 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1583 struct serial_private *priv;
1584 struct pci_board *board, tmp;
1585 struct pci_serial_quirk *quirk;
1586 struct serial_struct serial_req;
1587 int rc, nr_ports, i;
1589 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1590 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1595 board = &pci_boards[ent->driver_data];
1597 rc = pci_enable_device(dev);
1601 if (ent->driver_data == pbn_default) {
1603 * Use a copy of the pci_board entry for this;
1604 * avoid changing entries in the table.
1606 memcpy(&tmp, board, sizeof(struct pci_board));
1610 * We matched one of our class entries. Try to
1611 * determine the parameters of this board.
1613 rc = serial_pci_guess_board(dev, board);
1618 * We matched an explicit entry. If we are able to
1619 * detect this boards settings with our heuristic,
1620 * then we no longer need this entry.
1622 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1623 rc = serial_pci_guess_board(dev, &tmp);
1624 if (rc == 0 && serial_pci_matches(board, &tmp))
1625 moan_device("Redundant entry in serial pci_table.",
1629 nr_ports = board->num_ports;
1632 * Find an init and setup quirks.
1634 quirk = find_quirk(dev);
1637 * Run the new-style initialization function.
1638 * The initialization function returns:
1640 * 0 - use board->num_ports
1641 * >0 - number of ports
1644 rc = quirk->init(dev);
1651 priv = kmalloc(sizeof(struct serial_private) +
1652 sizeof(unsigned int) * nr_ports,
1659 memset(priv, 0, sizeof(struct serial_private) +
1660 sizeof(unsigned int) * nr_ports);
1662 priv->quirk = quirk;
1663 pci_set_drvdata(dev, priv);
1665 for (i = 0; i < nr_ports; i++) {
1666 memset(&serial_req, 0, sizeof(serial_req));
1667 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1668 UPF_RESOURCES | UPF_SHARE_IRQ;
1669 serial_req.baud_base = board->base_baud;
1670 serial_req.irq = get_pci_irq(dev, board, i);
1671 if (quirk->setup(dev, board, &serial_req, i))
1673 #ifdef SERIAL_DEBUG_PCI
1674 printk("Setup PCI port: port %x, irq %d, type %d\n",
1675 serial_req.port, serial_req.irq, serial_req.io_type);
1678 priv->line[i] = register_serial(&serial_req);
1679 if (priv->line[i] < 0) {
1680 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1693 pci_disable_device(dev);
1697 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1699 struct serial_private *priv = pci_get_drvdata(dev);
1701 pci_set_drvdata(dev, NULL);
1704 struct pci_serial_quirk *quirk;
1707 for (i = 0; i < priv->nr; i++)
1708 unregister_serial(priv->line[i]);
1710 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1711 if (priv->remapped_bar[i])
1712 iounmap(priv->remapped_bar[i]);
1713 priv->remapped_bar[i] = NULL;
1717 * Find the exit quirks.
1719 quirk = find_quirk(dev);
1723 pci_disable_device(dev);
1729 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1731 struct serial_private *priv = pci_get_drvdata(dev);
1736 for (i = 0; i < priv->nr; i++)
1737 serial8250_suspend_port(priv->line[i]);
1742 static int pciserial_resume_one(struct pci_dev *dev)
1744 struct serial_private *priv = pci_get_drvdata(dev);
1750 * Ensure that the board is correctly configured.
1752 if (priv->quirk->init)
1753 priv->quirk->init(dev);
1755 for (i = 0; i < priv->nr; i++)
1756 serial8250_resume_port(priv->line[i]);
1761 static struct pci_device_id serial_pci_tbl[] = {
1762 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1763 PCI_SUBVENDOR_ID_CONNECT_TECH,
1764 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1766 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1767 PCI_SUBVENDOR_ID_CONNECT_TECH,
1768 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1770 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1771 PCI_SUBVENDOR_ID_CONNECT_TECH,
1772 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1774 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1775 PCI_SUBVENDOR_ID_CONNECT_TECH,
1776 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1778 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1779 PCI_SUBVENDOR_ID_CONNECT_TECH,
1780 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1782 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1783 PCI_SUBVENDOR_ID_CONNECT_TECH,
1784 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1786 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1787 PCI_SUBVENDOR_ID_CONNECT_TECH,
1788 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1790 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1791 PCI_SUBVENDOR_ID_CONNECT_TECH,
1792 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1794 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1795 PCI_SUBVENDOR_ID_CONNECT_TECH,
1796 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1798 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1799 PCI_SUBVENDOR_ID_CONNECT_TECH,
1800 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1802 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1803 PCI_SUBVENDOR_ID_CONNECT_TECH,
1804 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1806 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1807 PCI_SUBVENDOR_ID_CONNECT_TECH,
1808 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1810 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1811 PCI_SUBVENDOR_ID_CONNECT_TECH,
1812 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1814 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1815 PCI_SUBVENDOR_ID_CONNECT_TECH,
1816 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1819 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821 pbn_b2_bt_1_115200 },
1822 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1824 pbn_b2_bt_2_115200 },
1825 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827 pbn_b2_bt_4_115200 },
1828 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1830 pbn_b2_bt_2_115200 },
1831 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1833 pbn_b2_bt_4_115200 },
1834 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1838 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1840 pbn_b2_bt_2_115200 },
1841 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1843 pbn_b2_bt_2_921600 },
1845 * VScom SPCOM800, from sl@s.pl
1847 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1850 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1853 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1854 PCI_SUBVENDOR_ID_KEYSPAN,
1855 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1857 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1860 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1864 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1865 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1868 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1869 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1871 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1872 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1873 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1875 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1876 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1877 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1879 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1880 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1881 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1883 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1884 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1885 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1888 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1891 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1892 0x10b5, 0x106a, 0, 0,
1894 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1897 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1900 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1903 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1906 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1907 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1909 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1912 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914 pbn_b0_bt_2_921600 },
1917 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1918 * from skokodyn@yahoo.com
1920 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1921 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1923 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1924 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1926 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1927 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1929 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1930 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1934 * Digitan DS560-558, from jimd@esoft.com
1936 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1941 * Titan Electronic cards
1942 * The 400L and 800L have a custom setup quirk.
1944 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1950 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961 pbn_b1_bt_2_921600 },
1962 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964 pbn_b0_bt_4_921600 },
1965 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 pbn_b0_bt_8_921600 },
1969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980 pbn_b2_bt_2_921600 },
1981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983 pbn_b2_bt_2_921600 },
1984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986 pbn_b2_bt_2_921600 },
1987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_b2_bt_4_921600 },
1990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 pbn_b2_bt_4_921600 },
1993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995 pbn_b2_bt_4_921600 },
1996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 pbn_b0_bt_2_921600 },
2008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010 pbn_b0_bt_2_921600 },
2011 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013 pbn_b0_bt_2_921600 },
2014 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016 pbn_b0_bt_4_921600 },
2017 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019 pbn_b0_bt_4_921600 },
2020 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022 pbn_b0_bt_4_921600 },
2025 * Computone devices submitted by Doug McNash dmcnash@computone.com
2027 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2028 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2029 0, 0, pbn_computone_4 },
2030 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2031 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2032 0, 0, pbn_computone_8 },
2033 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2034 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2035 0, 0, pbn_computone_6 },
2037 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2041 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2042 pbn_b0_bt_1_921600 },
2045 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2047 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049 pbn_b0_bt_8_115200 },
2050 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052 pbn_b0_bt_8_115200 },
2054 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056 pbn_b0_bt_2_115200 },
2057 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059 pbn_b0_bt_2_115200 },
2060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b0_bt_2_115200 },
2063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b0_bt_4_460800 },
2066 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068 pbn_b0_bt_4_460800 },
2069 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 pbn_b0_bt_2_460800 },
2072 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 pbn_b0_bt_2_460800 },
2075 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077 pbn_b0_bt_2_460800 },
2078 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080 pbn_b0_bt_1_115200 },
2081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083 pbn_b0_bt_1_460800 },
2086 * RAStel 2 port modem, gerg@moreton.com.au
2088 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2090 pbn_b2_bt_2_115200 },
2093 * EKF addition for i960 Boards form EKF with serial port
2095 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2096 0xE4BF, PCI_ANY_ID, 0, 0,
2100 * Xircom Cardbus/Ethernet combos
2102 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2108 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113 * Untested PCI modems, sent in from various folks...
2117 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2119 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2120 0x1048, 0x1500, 0, 0,
2123 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2130 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138 * NEC Vrc-5074 (Nile 4) builtin UART.
2140 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2147 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2152 * These entries match devices with class COMMUNICATION_SERIAL,
2153 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2155 { PCI_ANY_ID, PCI_ANY_ID,
2156 PCI_ANY_ID, PCI_ANY_ID,
2157 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2158 0xffff00, pbn_default },
2159 { PCI_ANY_ID, PCI_ANY_ID,
2160 PCI_ANY_ID, PCI_ANY_ID,
2161 PCI_CLASS_COMMUNICATION_MODEM << 8,
2162 0xffff00, pbn_default },
2163 { PCI_ANY_ID, PCI_ANY_ID,
2164 PCI_ANY_ID, PCI_ANY_ID,
2165 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2166 0xffff00, pbn_default },
2170 static struct pci_driver serial_pci_driver = {
2172 .probe = pciserial_init_one,
2173 .remove = __devexit_p(pciserial_remove_one),
2174 .suspend = pciserial_suspend_one,
2175 .resume = pciserial_resume_one,
2176 .id_table = serial_pci_tbl,
2179 static int __init serial8250_pci_init(void)
2181 return pci_module_init(&serial_pci_driver);
2184 static void __exit serial8250_pci_exit(void)
2186 pci_unregister_driver(&serial_pci_driver);
2189 module_init(serial8250_pci_init);
2190 module_exit(serial8250_pci_exit);
2192 MODULE_LICENSE("GPL");
2193 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2194 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);