2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial.h>
26 #include <linux/serial_core.h>
27 #include <linux/8250_pci.h>
29 #include <asm/bitops.h>
30 #include <asm/byteorder.h>
31 #include <asm/serial.h>
37 * Definitions for PCI support.
39 #define FL_BASE_MASK 0x0007
40 #define FL_BASE0 0x0000
41 #define FL_BASE1 0x0001
42 #define FL_BASE2 0x0002
43 #define FL_BASE3 0x0003
44 #define FL_BASE4 0x0004
45 #define FL_GET_BASE(x) (x & FL_BASE_MASK)
47 /* Use successive BARs (PCI base address registers),
48 else use offset into some specified BAR */
49 #define FL_BASE_BARS 0x0008
51 /* do not assign an irq */
52 #define FL_NOIRQ 0x0080
54 /* Use the Base address register size to cap number of ports */
55 #define FL_REGION_SZ_CAP 0x0100
59 unsigned int num_ports;
60 unsigned int base_baud;
61 unsigned int uart_offset;
62 unsigned int reg_shift;
63 unsigned int first_offset;
67 * init function returns:
68 * > 0 - number of ports
69 * = 0 - use board->num_ports
72 struct pci_serial_quirk {
77 int (*init)(struct pci_dev *dev);
78 int (*setup)(struct pci_dev *dev, struct pci_board *board,
79 struct serial_struct *req, int idx);
80 void (*exit)(struct pci_dev *dev);
83 #define PCI_NUM_BAR_RESOURCES 6
85 struct serial_private {
87 void *remapped_bar[PCI_NUM_BAR_RESOURCES];
88 struct pci_serial_quirk *quirk;
92 static void moan_device(const char *str, struct pci_dev *dev)
94 printk(KERN_WARNING "%s: %s\n"
95 KERN_WARNING "Please send the output of lspci -vv, this\n"
96 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
97 KERN_WARNING "manufacturer and name of serial board or\n"
98 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
99 pci_name(dev), str, dev->vendor, dev->device,
100 dev->subsystem_vendor, dev->subsystem_device);
104 setup_port(struct pci_dev *dev, struct serial_struct *req,
105 int bar, int offset, int regshift)
107 struct serial_private *priv = pci_get_drvdata(dev);
108 unsigned long port, len;
110 if (bar >= PCI_NUM_BAR_RESOURCES)
113 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
114 port = pci_resource_start(dev, bar);
115 len = pci_resource_len(dev, bar);
117 if (!priv->remapped_bar[bar])
118 priv->remapped_bar[bar] = ioremap(port, len);
119 if (!priv->remapped_bar[bar])
122 req->io_type = UPIO_MEM;
123 req->iomap_base = port + offset;
124 req->iomem_base = priv->remapped_bar[bar] + offset;
125 req->iomem_reg_shift = regshift;
127 port = pci_resource_start(dev, bar) + offset;
128 req->io_type = UPIO_PORT;
130 if (HIGH_BITS_OFFSET)
131 req->port_high = port >> HIGH_BITS_OFFSET;
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
141 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
142 struct serial_struct *req, int idx)
144 unsigned int bar, offset = board->first_offset;
146 bar = FL_GET_BASE(board->flags);
151 offset += (idx - 4) * board->uart_offset;
154 return setup_port(dev, req, bar, offset, board->reg_shift);
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
164 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
194 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
195 struct serial_struct *req, int idx)
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
200 switch (dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
215 offset += idx * board->uart_offset;
217 return setup_port(dev, req, bar, offset, board->reg_shift);
221 * Added for EKF Intel i960 serial boards
223 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
225 unsigned long oldval;
227 if (!(dev->subsystem_device & 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void*) &oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int __devinit pci_plx9050_init(struct pci_dev *dev)
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
257 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
271 * enable/disable interrupts
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
276 writel(irq_config, (unsigned long)p + 0x4c);
279 * Read the register back to ensure that it took effect.
281 readl((unsigned long)p + 0x4c);
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 p = ioremap(pci_resource_start(dev, 0), 0x80);
302 * Read the register back to ensure that it took effect.
309 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
311 sbs_setup(struct pci_dev *dev, struct pci_board *board,
312 struct serial_struct *req, int idx)
314 unsigned int bar, offset = board->first_offset;
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
327 return setup_port(dev, req, bar, offset, board->reg_shift);
331 * This does initialization for PMC OCTALPRO cards:
332 * maps the device memory, resets the UARTs (needed, bc
333 * if the module is removed and inserted again, the card
334 * is in the sleep mode) and enables global interrupt.
337 /* global control register offset for SBS PMC-OctalPro */
338 #define OCT_REG_CR_OFF 0x500
340 static int __devinit sbs_init(struct pci_dev *dev)
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
348 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
349 writeb(0x10,p + OCT_REG_CR_OFF);
351 writeb(0x0,p + OCT_REG_CR_OFF);
353 /* Set bit-2 (INTENABLE) of Control Register */
354 writeb(0x4, p + OCT_REG_CR_OFF);
361 * Disables the global interrupt of PMC-OctalPro
364 static void __devexit sbs_exit(struct pci_dev *dev)
368 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
370 writeb(0, p + OCT_REG_CR_OFF);
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
393 * Note: some SIIG cards are probed by the parport_serial object.
396 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
397 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
399 static int pci_siig10x_init(struct pci_dev *dev)
403 switch (dev->device & 0xfff8) {
404 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
407 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
410 default: /* 1S1P, 4S */
415 p = ioremap(pci_resource_start(dev, 0), 0x80);
419 writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
420 readw((unsigned long)p + 0x28);
425 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
426 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
428 static int pci_siig20x_init(struct pci_dev *dev)
432 /* Change clock frequency for the first UART. */
433 pci_read_config_byte(dev, 0x6f, &data);
434 pci_write_config_byte(dev, 0x6f, data & 0xef);
436 /* If this card has 2 UART, we have to do the same with second UART. */
437 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
438 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
439 pci_read_config_byte(dev, 0x73, &data);
440 pci_write_config_byte(dev, 0x73, data & 0xef);
445 int pci_siig10x_fn(struct pci_dev *dev, int enable)
449 ret = pci_siig10x_init(dev);
453 int pci_siig20x_fn(struct pci_dev *dev, int enable)
457 ret = pci_siig20x_init(dev);
461 EXPORT_SYMBOL(pci_siig10x_fn);
462 EXPORT_SYMBOL(pci_siig20x_fn);
465 * Timedia has an explosion of boards, and to avoid the PCI table from
466 * growing *huge*, we use this function to collapse some 70 entries
467 * in the PCI table into one, for sanity's and compactness's sake.
469 static unsigned short timedia_single_port[] = {
470 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
473 static unsigned short timedia_dual_port[] = {
474 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
475 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
476 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
477 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
481 static unsigned short timedia_quad_port[] = {
482 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
483 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
484 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
488 static unsigned short timedia_eight_port[] = {
489 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
490 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
493 static struct timedia_struct {
497 { 1, timedia_single_port },
498 { 2, timedia_dual_port },
499 { 4, timedia_quad_port },
500 { 8, timedia_eight_port },
504 static int __devinit pci_timedia_init(struct pci_dev *dev)
509 for (i = 0; timedia_data[i].num; i++) {
510 ids = timedia_data[i].ids;
511 for (j = 0; ids[j]; j++)
512 if (dev->subsystem_device == ids[j])
513 return timedia_data[i].num;
519 * Timedia/SUNIX uses a mixture of BARs and offsets
520 * Ugh, this is ugly as all hell --- TYT
523 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
524 struct serial_struct *req, int idx)
526 unsigned int bar = 0, offset = board->first_offset;
533 offset = board->uart_offset;
540 offset = board->uart_offset;
549 return setup_port(dev, req, bar, offset, board->reg_shift);
553 * Some Titan cards are also a little weird
556 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
557 struct serial_struct *req, int idx)
559 unsigned int bar, offset = board->first_offset;
570 offset = (idx - 2) * board->uart_offset;
573 return setup_port(dev, req, bar, offset, board->reg_shift);
576 static int __devinit pci_xircom_init(struct pci_dev *dev)
578 __set_current_state(TASK_UNINTERRUPTIBLE);
579 schedule_timeout(HZ/10);
584 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
585 struct serial_struct *req, int idx)
587 unsigned int bar, offset = board->first_offset, maxnr;
589 bar = FL_GET_BASE(board->flags);
590 if (board->flags & FL_BASE_BARS)
593 offset += idx * board->uart_offset;
595 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
596 (8 << board->reg_shift);
598 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
601 return setup_port(dev, req, bar, offset, board->reg_shift);
604 /* This should be in linux/pci_ids.h */
605 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
606 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
607 #define PCI_DEVICE_ID_OCTPRO 0x0001
608 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
609 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
610 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
611 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
614 * Master list of serial port init/setup/exit quirks.
615 * This does not describe the general nature of the port.
616 * (ie, baud base, number and location of ports, etc)
618 * This list is ordered alphabetically by vendor then device.
619 * Specific entries must come before more generic entries.
621 static struct pci_serial_quirk pci_serial_quirks[] = {
624 * It is not clear whether this applies to all products.
627 .vendor = PCI_VENDOR_ID_AFAVLAB,
628 .device = PCI_ANY_ID,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 .setup = afavlab_setup,
637 .vendor = PCI_VENDOR_ID_HP,
638 .device = PCI_DEVICE_ID_HP_DIVA,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
641 .init = pci_hp_diva_init,
642 .setup = pci_hp_diva_setup,
648 .vendor = PCI_VENDOR_ID_INTEL,
649 .device = PCI_DEVICE_ID_INTEL_80960_RP,
651 .subdevice = PCI_ANY_ID,
652 .init = pci_inteli960ni_init,
653 .setup = pci_default_setup,
659 .vendor = PCI_VENDOR_ID_PANACOM,
660 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 .init = pci_plx9050_init,
664 .setup = pci_default_setup,
665 .exit = __devexit_p(pci_plx9050_exit),
668 .vendor = PCI_VENDOR_ID_PANACOM,
669 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
680 .vendor = PCI_VENDOR_ID_PLX,
681 .device = PCI_DEVICE_ID_PLX_9050,
682 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
683 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
684 .init = pci_plx9050_init,
685 .setup = pci_default_setup,
686 .exit = __devexit_p(pci_plx9050_exit),
689 .vendor = PCI_VENDOR_ID_PLX,
690 .device = PCI_DEVICE_ID_PLX_ROMULUS,
691 .subvendor = PCI_VENDOR_ID_PLX,
692 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
693 .init = pci_plx9050_init,
694 .setup = pci_default_setup,
695 .exit = __devexit_p(pci_plx9050_exit),
698 * SBS Technologies, Inc., PMC-OCTALPRO 232
701 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
702 .device = PCI_DEVICE_ID_OCTPRO,
703 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
704 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
710 * SBS Technologies, Inc., PMC-OCTALPRO 422
713 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
714 .device = PCI_DEVICE_ID_OCTPRO,
715 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
716 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
722 * SBS Technologies, Inc., P-Octal 232
725 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
726 .device = PCI_DEVICE_ID_OCTPRO,
727 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
728 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
734 * SBS Technologies, Inc., P-Octal 422
737 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
738 .device = PCI_DEVICE_ID_OCTPRO,
739 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
740 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
748 * It is not clear whether these could be collapsed.
751 .vendor = PCI_VENDOR_ID_SIIG,
752 .device = PCI_DEVICE_ID_SIIG_1S_10x_550,
753 .subvendor = PCI_ANY_ID,
754 .subdevice = PCI_ANY_ID,
755 .init = pci_siig10x_init,
756 .setup = pci_default_setup,
759 .vendor = PCI_VENDOR_ID_SIIG,
760 .device = PCI_DEVICE_ID_SIIG_1S_10x_650,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .init = pci_siig10x_init,
764 .setup = pci_default_setup,
767 .vendor = PCI_VENDOR_ID_SIIG,
768 .device = PCI_DEVICE_ID_SIIG_1S_10x_850,
769 .subvendor = PCI_ANY_ID,
770 .subdevice = PCI_ANY_ID,
771 .init = pci_siig10x_init,
772 .setup = pci_default_setup,
775 .vendor = PCI_VENDOR_ID_SIIG,
776 .device = PCI_DEVICE_ID_SIIG_2S_10x_550,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 .init = pci_siig10x_init,
780 .setup = pci_default_setup,
783 .vendor = PCI_VENDOR_ID_SIIG,
784 .device = PCI_DEVICE_ID_SIIG_2S_10x_650,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .init = pci_siig10x_init,
788 .setup = pci_default_setup,
791 .vendor = PCI_VENDOR_ID_SIIG,
792 .device = PCI_DEVICE_ID_SIIG_2S_10x_850,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_siig10x_init,
796 .setup = pci_default_setup,
799 .vendor = PCI_VENDOR_ID_SIIG,
800 .device = PCI_DEVICE_ID_SIIG_4S_10x_550,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .init = pci_siig10x_init,
804 .setup = pci_default_setup,
807 .vendor = PCI_VENDOR_ID_SIIG,
808 .device = PCI_DEVICE_ID_SIIG_4S_10x_650,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .init = pci_siig10x_init,
812 .setup = pci_default_setup,
815 .vendor = PCI_VENDOR_ID_SIIG,
816 .device = PCI_DEVICE_ID_SIIG_4S_10x_850,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .init = pci_siig10x_init,
820 .setup = pci_default_setup,
823 .vendor = PCI_VENDOR_ID_SIIG,
824 .device = PCI_DEVICE_ID_SIIG_1S_20x_550,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .init = pci_siig20x_init,
828 .setup = pci_default_setup,
831 .vendor = PCI_VENDOR_ID_SIIG,
832 .device = PCI_DEVICE_ID_SIIG_1S_20x_650,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
835 .init = pci_siig20x_init,
836 .setup = pci_default_setup,
839 .vendor = PCI_VENDOR_ID_SIIG,
840 .device = PCI_DEVICE_ID_SIIG_1S_20x_850,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .init = pci_siig20x_init,
844 .setup = pci_default_setup,
847 .vendor = PCI_VENDOR_ID_SIIG,
848 .device = PCI_DEVICE_ID_SIIG_2S_20x_550,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .init = pci_siig20x_init,
852 .setup = pci_default_setup,
854 { .vendor = PCI_VENDOR_ID_SIIG,
855 .device = PCI_DEVICE_ID_SIIG_2S_20x_650,
856 .subvendor = PCI_ANY_ID,
857 .subdevice = PCI_ANY_ID,
858 .init = pci_siig20x_init,
859 .setup = pci_default_setup,
862 .vendor = PCI_VENDOR_ID_SIIG,
863 .device = PCI_DEVICE_ID_SIIG_2S_20x_850,
864 .subvendor = PCI_ANY_ID,
865 .subdevice = PCI_ANY_ID,
866 .init = pci_siig20x_init,
867 .setup = pci_default_setup,
870 .vendor = PCI_VENDOR_ID_SIIG,
871 .device = PCI_DEVICE_ID_SIIG_4S_20x_550,
872 .subvendor = PCI_ANY_ID,
873 .subdevice = PCI_ANY_ID,
874 .init = pci_siig20x_init,
875 .setup = pci_default_setup,
878 .vendor = PCI_VENDOR_ID_SIIG,
879 .device = PCI_DEVICE_ID_SIIG_4S_20x_650,
880 .subvendor = PCI_ANY_ID,
881 .subdevice = PCI_ANY_ID,
882 .init = pci_siig20x_init,
883 .setup = pci_default_setup,
886 .vendor = PCI_VENDOR_ID_SIIG,
887 .device = PCI_DEVICE_ID_SIIG_4S_20x_850,
888 .subvendor = PCI_ANY_ID,
889 .subdevice = PCI_ANY_ID,
890 .init = pci_siig20x_init,
891 .setup = pci_default_setup,
897 .vendor = PCI_VENDOR_ID_TITAN,
898 .device = PCI_DEVICE_ID_TITAN_400L,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .setup = titan_400l_800l_setup,
904 .vendor = PCI_VENDOR_ID_TITAN,
905 .device = PCI_DEVICE_ID_TITAN_800L,
906 .subvendor = PCI_ANY_ID,
907 .subdevice = PCI_ANY_ID,
908 .setup = titan_400l_800l_setup,
914 .vendor = PCI_VENDOR_ID_TIMEDIA,
915 .device = PCI_DEVICE_ID_TIMEDIA_1889,
916 .subvendor = PCI_VENDOR_ID_TIMEDIA,
917 .subdevice = PCI_ANY_ID,
918 .init = pci_timedia_init,
919 .setup = pci_timedia_setup,
922 .vendor = PCI_VENDOR_ID_TIMEDIA,
923 .device = PCI_ANY_ID,
924 .subvendor = PCI_ANY_ID,
925 .subdevice = PCI_ANY_ID,
926 .setup = pci_timedia_setup,
932 .vendor = PCI_VENDOR_ID_XIRCOM,
933 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .init = pci_xircom_init,
937 .setup = pci_default_setup,
940 * Default "match everything" terminator entry
943 .vendor = PCI_ANY_ID,
944 .device = PCI_ANY_ID,
945 .subvendor = PCI_ANY_ID,
946 .subdevice = PCI_ANY_ID,
947 .setup = pci_default_setup,
951 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
953 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
956 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
958 struct pci_serial_quirk *quirk;
960 for (quirk = pci_serial_quirks; ; quirk++)
961 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
962 quirk_id_matches(quirk->device, dev->device) &&
963 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
964 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
970 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
972 if (board->flags & FL_NOIRQ)
979 * This is the configuration table for all of the PCI serial boards
980 * which we support. It is directly indexed by the pci_board_num_t enum
981 * value, which is encoded in the pci_device_id PCI probe table's
982 * driver_data member.
984 * The makeup of these names are:
987 * bn = PCI BAR number
988 * bt = Index using PCI BARs
989 * n = number of serial ports
992 * Please note: in theory if n = 1, _bt infix should make no difference.
993 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
995 enum pci_board_num_t {
1059 * Board-specific versions.
1076 * uart_offset - the space between channels
1077 * reg_shift - describes how the UART registers are mapped
1078 * to PCI memory by the card.
1079 * For example IER register on SBS, Inc. PMC-OctPro is located at
1080 * offset 0x10 from the UART base, while UART_IER is defined as 1
1081 * in include/linux/serial_reg.h,
1082 * see first lines of serial_in() and serial_out() in 8250.c
1085 static struct pci_board pci_boards[] __devinitdata = {
1089 .base_baud = 115200,
1092 [pbn_b0_1_115200] = {
1095 .base_baud = 115200,
1098 [pbn_b0_2_115200] = {
1101 .base_baud = 115200,
1104 [pbn_b0_4_115200] = {
1107 .base_baud = 115200,
1110 [pbn_b0_5_115200] = {
1113 .base_baud = 115200,
1117 [pbn_b0_1_921600] = {
1120 .base_baud = 921600,
1123 [pbn_b0_2_921600] = {
1126 .base_baud = 921600,
1129 [pbn_b0_4_921600] = {
1132 .base_baud = 921600,
1136 [pbn_b0_bt_1_115200] = {
1137 .flags = FL_BASE0|FL_BASE_BARS,
1139 .base_baud = 115200,
1142 [pbn_b0_bt_2_115200] = {
1143 .flags = FL_BASE0|FL_BASE_BARS,
1145 .base_baud = 115200,
1148 [pbn_b0_bt_8_115200] = {
1149 .flags = FL_BASE0|FL_BASE_BARS,
1151 .base_baud = 115200,
1155 [pbn_b0_bt_1_460800] = {
1156 .flags = FL_BASE0|FL_BASE_BARS,
1158 .base_baud = 460800,
1161 [pbn_b0_bt_2_460800] = {
1162 .flags = FL_BASE0|FL_BASE_BARS,
1164 .base_baud = 460800,
1167 [pbn_b0_bt_4_460800] = {
1168 .flags = FL_BASE0|FL_BASE_BARS,
1170 .base_baud = 460800,
1174 [pbn_b0_bt_1_921600] = {
1175 .flags = FL_BASE0|FL_BASE_BARS,
1177 .base_baud = 921600,
1180 [pbn_b0_bt_2_921600] = {
1181 .flags = FL_BASE0|FL_BASE_BARS,
1183 .base_baud = 921600,
1186 [pbn_b0_bt_4_921600] = {
1187 .flags = FL_BASE0|FL_BASE_BARS,
1189 .base_baud = 921600,
1192 [pbn_b0_bt_8_921600] = {
1193 .flags = FL_BASE0|FL_BASE_BARS,
1195 .base_baud = 921600,
1199 [pbn_b1_1_115200] = {
1202 .base_baud = 115200,
1205 [pbn_b1_2_115200] = {
1208 .base_baud = 115200,
1211 [pbn_b1_4_115200] = {
1214 .base_baud = 115200,
1217 [pbn_b1_8_115200] = {
1220 .base_baud = 115200,
1224 [pbn_b1_1_921600] = {
1227 .base_baud = 921600,
1230 [pbn_b1_2_921600] = {
1233 .base_baud = 921600,
1236 [pbn_b1_4_921600] = {
1239 .base_baud = 921600,
1242 [pbn_b1_8_921600] = {
1245 .base_baud = 921600,
1249 [pbn_b1_bt_2_921600] = {
1250 .flags = FL_BASE1|FL_BASE_BARS,
1252 .base_baud = 921600,
1256 [pbn_b1_2_1382400] = {
1259 .base_baud = 1382400,
1262 [pbn_b1_4_1382400] = {
1265 .base_baud = 1382400,
1268 [pbn_b1_8_1382400] = {
1271 .base_baud = 1382400,
1275 [pbn_b2_1_115200] = {
1278 .base_baud = 115200,
1281 [pbn_b2_8_115200] = {
1284 .base_baud = 115200,
1288 [pbn_b2_1_460800] = {
1291 .base_baud = 460800,
1294 [pbn_b2_4_460800] = {
1297 .base_baud = 460800,
1300 [pbn_b2_8_460800] = {
1303 .base_baud = 460800,
1306 [pbn_b2_16_460800] = {
1309 .base_baud = 460800,
1313 [pbn_b2_1_921600] = {
1316 .base_baud = 921600,
1319 [pbn_b2_4_921600] = {
1322 .base_baud = 921600,
1325 [pbn_b2_8_921600] = {
1328 .base_baud = 921600,
1332 [pbn_b2_bt_1_115200] = {
1333 .flags = FL_BASE2|FL_BASE_BARS,
1335 .base_baud = 115200,
1338 [pbn_b2_bt_2_115200] = {
1339 .flags = FL_BASE2|FL_BASE_BARS,
1341 .base_baud = 115200,
1344 [pbn_b2_bt_4_115200] = {
1345 .flags = FL_BASE2|FL_BASE_BARS,
1347 .base_baud = 115200,
1351 [pbn_b2_bt_2_921600] = {
1352 .flags = FL_BASE2|FL_BASE_BARS,
1354 .base_baud = 921600,
1357 [pbn_b2_bt_4_921600] = {
1358 .flags = FL_BASE2|FL_BASE_BARS,
1360 .base_baud = 921600,
1364 [pbn_b3_4_115200] = {
1367 .base_baud = 115200,
1370 [pbn_b3_8_115200] = {
1373 .base_baud = 115200,
1378 * Entries following this are board-specific.
1387 .base_baud = 921600,
1388 .uart_offset = 0x400,
1392 .flags = FL_BASE2|FL_BASE_BARS,
1394 .base_baud = 921600,
1395 .uart_offset = 0x400,
1399 .flags = FL_BASE2|FL_BASE_BARS,
1401 .base_baud = 921600,
1402 .uart_offset = 0x400,
1406 /* I think this entry is broken - the first_offset looks wrong --rmk */
1407 [pbn_plx_romulus] = {
1410 .base_baud = 921600,
1411 .uart_offset = 8 << 2,
1413 .first_offset = 0x03,
1417 * This board uses the size of PCI Base region 0 to
1418 * signal now many ports are available
1421 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1423 .base_baud = 115200,
1428 * EKF addition for i960 Boards form EKF with serial port.
1431 [pbn_intel_i960] = {
1434 .base_baud = 921600,
1435 .uart_offset = 8 << 2,
1437 .first_offset = 0x10000,
1440 .flags = FL_BASE0|FL_NOIRQ,
1442 .base_baud = 458333,
1445 .first_offset = 0x20178,
1449 * NEC Vrc-5074 (Nile 4) builtin UART.
1454 .base_baud = 520833,
1455 .uart_offset = 8 << 3,
1457 .first_offset = 0x300,
1461 * Computone - uses IOMEM.
1463 [pbn_computone_4] = {
1466 .base_baud = 921600,
1467 .uart_offset = 0x40,
1469 .first_offset = 0x200,
1471 [pbn_computone_6] = {
1474 .base_baud = 921600,
1475 .uart_offset = 0x40,
1477 .first_offset = 0x200,
1479 [pbn_computone_8] = {
1482 .base_baud = 921600,
1483 .uart_offset = 0x40,
1485 .first_offset = 0x200,
1490 .base_baud = 460800,
1497 * Given a complete unknown PCI device, try to use some heuristics to
1498 * guess what the configuration might be, based on the pitiful PCI
1499 * serial specs. Returns 0 on success, 1 on failure.
1501 static int __devinit
1502 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1504 int num_iomem, num_port, first_port = -1, i;
1507 * If it is not a communications device or the programming
1508 * interface is greater than 6, give up.
1510 * (Should we try to make guesses for multiport serial devices
1513 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1514 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1515 (dev->class & 0xff) > 6)
1518 num_iomem = num_port = 0;
1519 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1520 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1522 if (first_port == -1)
1525 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1530 * If there is 1 or 0 iomem regions, and exactly one port,
1531 * use it. We guess the number of ports based on the IO
1534 if (num_iomem <= 1 && num_port == 1) {
1535 board->flags = first_port;
1536 board->num_ports = pci_resource_len(dev, first_port) / 8;
1541 * Now guess if we've got a board which indexes by BARs.
1542 * Each IO BAR should be 8 bytes, and they should follow
1547 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1548 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1549 pci_resource_len(dev, i) == 8 &&
1550 (first_port == -1 || (first_port + num_port) == i)) {
1552 if (first_port == -1)
1558 board->flags = first_port | FL_BASE_BARS;
1559 board->num_ports = num_port;
1567 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1570 board->num_ports == guessed->num_ports &&
1571 board->base_baud == guessed->base_baud &&
1572 board->uart_offset == guessed->uart_offset &&
1573 board->reg_shift == guessed->reg_shift &&
1574 board->first_offset == guessed->first_offset;
1578 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1579 * to the arrangement of serial ports on a PCI card.
1581 static int __devinit
1582 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1584 struct serial_private *priv;
1585 struct pci_board *board, tmp;
1586 struct pci_serial_quirk *quirk;
1587 struct serial_struct serial_req;
1588 int base_baud, rc, nr_ports, i;
1590 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1591 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1596 board = &pci_boards[ent->driver_data];
1598 rc = pci_enable_device(dev);
1602 if (ent->driver_data == pbn_default) {
1604 * Use a copy of the pci_board entry for this;
1605 * avoid changing entries in the table.
1607 memcpy(&tmp, board, sizeof(struct pci_board));
1611 * We matched one of our class entries. Try to
1612 * determine the parameters of this board.
1614 rc = serial_pci_guess_board(dev, board);
1619 * We matched an explicit entry. If we are able to
1620 * detect this boards settings with our heuristic,
1621 * then we no longer need this entry.
1623 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1624 rc = serial_pci_guess_board(dev, &tmp);
1625 if (rc == 0 && serial_pci_matches(board, &tmp))
1626 moan_device("Redundant entry in serial pci_table.",
1630 nr_ports = board->num_ports;
1633 * Find an init and setup quirks.
1635 quirk = find_quirk(dev);
1638 * Run the new-style initialization function.
1639 * The initialization function returns:
1641 * 0 - use board->num_ports
1642 * >0 - number of ports
1645 rc = quirk->init(dev);
1652 priv = kmalloc(sizeof(struct serial_private) +
1653 sizeof(unsigned int) * nr_ports,
1660 memset(priv, 0, sizeof(struct serial_private) +
1661 sizeof(unsigned int) * nr_ports);
1663 priv->quirk = quirk;
1664 pci_set_drvdata(dev, priv);
1666 base_baud = board->base_baud;
1668 moan_device("Board entry does not specify baud rate.", dev);
1669 base_baud = BASE_BAUD;
1671 for (i = 0; i < nr_ports; i++) {
1672 memset(&serial_req, 0, sizeof(serial_req));
1673 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1674 UPF_RESOURCES | UPF_SHARE_IRQ;
1675 serial_req.baud_base = base_baud;
1676 serial_req.irq = get_pci_irq(dev, board, i);
1677 if (quirk->setup(dev, board, &serial_req, i))
1679 #ifdef SERIAL_DEBUG_PCI
1680 printk("Setup PCI port: port %x, irq %d, type %d\n",
1681 serial_req.port, serial_req.irq, serial_req.io_type);
1684 priv->line[i] = register_serial(&serial_req);
1685 if (priv->line[i] < 0) {
1686 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1699 pci_disable_device(dev);
1703 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1705 struct serial_private *priv = pci_get_drvdata(dev);
1707 pci_set_drvdata(dev, NULL);
1710 struct pci_serial_quirk *quirk;
1713 for (i = 0; i < priv->nr; i++)
1714 unregister_serial(priv->line[i]);
1716 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1717 if (priv->remapped_bar[i])
1718 iounmap(priv->remapped_bar[i]);
1719 priv->remapped_bar[i] = NULL;
1723 * Find the exit quirks.
1725 quirk = find_quirk(dev);
1729 pci_disable_device(dev);
1735 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1737 struct serial_private *priv = pci_get_drvdata(dev);
1742 for (i = 0; i < priv->nr; i++)
1743 serial8250_suspend_port(priv->line[i]);
1748 static int pciserial_resume_one(struct pci_dev *dev)
1750 struct serial_private *priv = pci_get_drvdata(dev);
1756 * Ensure that the board is correctly configured.
1758 if (priv->quirk->init)
1759 priv->quirk->init(dev);
1761 for (i = 0; i < priv->nr; i++)
1762 serial8250_resume_port(priv->line[i]);
1767 static struct pci_device_id serial_pci_tbl[] = {
1768 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1769 PCI_SUBVENDOR_ID_CONNECT_TECH,
1770 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1772 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1773 PCI_SUBVENDOR_ID_CONNECT_TECH,
1774 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1776 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1777 PCI_SUBVENDOR_ID_CONNECT_TECH,
1778 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1780 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1781 PCI_SUBVENDOR_ID_CONNECT_TECH,
1782 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1784 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1785 PCI_SUBVENDOR_ID_CONNECT_TECH,
1786 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1788 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1789 PCI_SUBVENDOR_ID_CONNECT_TECH,
1790 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1792 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1793 PCI_SUBVENDOR_ID_CONNECT_TECH,
1794 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1796 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1797 PCI_SUBVENDOR_ID_CONNECT_TECH,
1798 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1800 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1801 PCI_SUBVENDOR_ID_CONNECT_TECH,
1802 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1804 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1805 PCI_SUBVENDOR_ID_CONNECT_TECH,
1806 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1808 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1809 PCI_SUBVENDOR_ID_CONNECT_TECH,
1810 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1812 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1813 PCI_SUBVENDOR_ID_CONNECT_TECH,
1814 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1816 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1817 PCI_SUBVENDOR_ID_CONNECT_TECH,
1818 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1820 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1821 PCI_SUBVENDOR_ID_CONNECT_TECH,
1822 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1825 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827 pbn_b2_bt_1_115200 },
1828 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1830 pbn_b2_bt_2_115200 },
1831 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1833 pbn_b2_bt_4_115200 },
1834 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1836 pbn_b2_bt_2_115200 },
1837 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1839 pbn_b2_bt_4_115200 },
1840 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1844 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1846 pbn_b2_bt_2_115200 },
1847 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1849 pbn_b2_bt_2_921600 },
1851 * VScom SPCOM800, from sl@s.pl
1853 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1859 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1860 PCI_SUBVENDOR_ID_KEYSPAN,
1861 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1863 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1866 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1869 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1870 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1871 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1873 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1874 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1875 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1877 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1878 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1879 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1881 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1882 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1883 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1885 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1886 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1887 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1889 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1890 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1891 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1894 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1897 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1898 0x10b5, 0x106a, 0, 0,
1900 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1903 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1906 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1909 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1912 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1913 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1915 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1918 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920 pbn_b0_bt_2_921600 },
1923 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1924 * from skokodyn@yahoo.com
1926 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1927 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1929 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1930 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1932 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1933 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1935 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1936 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1940 * Digitan DS560-558, from jimd@esoft.com
1942 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947 * Titan Electronic cards
1948 * The 400L and 800L have a custom setup quirk.
1950 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 pbn_b1_bt_2_921600 },
1968 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970 pbn_b0_bt_4_921600 },
1971 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973 pbn_b0_bt_8_921600 },
1975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986 pbn_b2_bt_2_921600 },
1987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_b2_bt_2_921600 },
1990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 pbn_b2_bt_2_921600 },
1993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995 pbn_b2_bt_4_921600 },
1996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998 pbn_b2_bt_4_921600 },
1999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001 pbn_b2_bt_4_921600 },
2002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2011 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013 pbn_b0_bt_2_921600 },
2014 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016 pbn_b0_bt_2_921600 },
2017 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019 pbn_b0_bt_2_921600 },
2020 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022 pbn_b0_bt_4_921600 },
2023 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025 pbn_b0_bt_4_921600 },
2026 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028 pbn_b0_bt_4_921600 },
2031 * Computone devices submitted by Doug McNash dmcnash@computone.com
2033 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2034 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2035 0, 0, pbn_computone_4 },
2036 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2037 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2038 0, 0, pbn_computone_8 },
2039 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2040 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2041 0, 0, pbn_computone_6 },
2043 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2047 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2048 pbn_b0_bt_1_921600 },
2051 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2053 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055 pbn_b0_bt_8_115200 },
2056 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058 pbn_b0_bt_8_115200 },
2060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b0_bt_2_115200 },
2063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b0_bt_2_115200 },
2066 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068 pbn_b0_bt_2_115200 },
2069 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 pbn_b0_bt_4_460800 },
2072 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 pbn_b0_bt_4_460800 },
2075 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077 pbn_b0_bt_2_460800 },
2078 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080 pbn_b0_bt_2_460800 },
2081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083 pbn_b0_bt_2_460800 },
2084 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b0_bt_1_115200 },
2087 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089 pbn_b0_bt_1_460800 },
2092 * RAStel 2 port modem, gerg@moreton.com.au
2094 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096 pbn_b2_bt_2_115200 },
2099 * EKF addition for i960 Boards form EKF with serial port
2101 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2102 0xE4BF, PCI_ANY_ID, 0, 0,
2106 * Xircom Cardbus/Ethernet combos
2108 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2114 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2119 * Untested PCI modems, sent in from various folks...
2123 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2125 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2126 0x1048, 0x1500, 0, 0,
2129 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2136 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144 * NEC Vrc-5074 (Nile 4) builtin UART.
2146 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2150 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158 * These entries match devices with class COMMUNICATION_SERIAL,
2159 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2161 { PCI_ANY_ID, PCI_ANY_ID,
2162 PCI_ANY_ID, PCI_ANY_ID,
2163 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2164 0xffff00, pbn_default },
2165 { PCI_ANY_ID, PCI_ANY_ID,
2166 PCI_ANY_ID, PCI_ANY_ID,
2167 PCI_CLASS_COMMUNICATION_MODEM << 8,
2168 0xffff00, pbn_default },
2169 { PCI_ANY_ID, PCI_ANY_ID,
2170 PCI_ANY_ID, PCI_ANY_ID,
2171 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2172 0xffff00, pbn_default },
2176 static struct pci_driver serial_pci_driver = {
2178 .probe = pciserial_init_one,
2179 .remove = __devexit_p(pciserial_remove_one),
2180 .suspend = pciserial_suspend_one,
2181 .resume = pciserial_resume_one,
2182 .id_table = serial_pci_tbl,
2185 static int __init serial8250_pci_init(void)
2187 return pci_module_init(&serial_pci_driver);
2190 static void __exit serial8250_pci_exit(void)
2192 pci_unregister_driver(&serial_pci_driver);
2195 module_init(serial8250_pci_init);
2196 module_exit(serial8250_pci_exit);
2198 MODULE_LICENSE("GPL");
2199 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2200 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);