4 * Copyright (C) 1992, 1994 by Theodore Ts'o.
5 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
7 * Redistribution of this file is permitted under the terms of the GNU
10 * These are the UART port assignments, expressed as offsets from the base
11 * register. These assignments should hold for any serial port based on
12 * a 8250, 16450, or 16550(A).
15 #ifndef _M32R_SIO_REG_H
16 #define _M32R_SIO_REG_H
18 #include <linux/config.h>
20 #ifdef CONFIG_SERIAL_M32R_PLDSIO
28 // #define SIORBAUR 0x018
32 #define UART_RX ((unsigned long) PLD_ESIO0RXB)
33 /* In: Receive buffer (DLAB=0) */
34 #define UART_TX ((unsigned long) PLD_ESIO0TXB)
35 /* Out: Transmit buffer (DLAB=0) */
36 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
37 #define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
39 * Out: Fifo custom trigger levels
42 #define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
43 #define UART_IER ((unsigned long) PLD_ESIO0INTCR)
44 /* Out: Interrupt Enable Register */
45 #define UART_FCTR 0 /* (LCR=BF) Feature Control Register
48 #define UART_IIR 0 /* In: Interrupt ID Register */
49 #define UART_FCR 0 /* Out: FIFO Control Register */
50 #define UART_EFR 0 /* I/O: Extended Features Register */
51 /* (DLAB=1, 16C660 only) */
53 #define UART_LCR 0 /* Out: Line Control Register */
54 #define UART_MCR 0 /* Out: Modem Control Register */
55 #define UART_LSR ((unsigned long) PLD_ESIO0STS)
56 /* In: Line Status Register */
57 #define UART_MSR 0 /* In: Modem Status Register */
58 #define UART_SCR 0 /* I/O: Scratch Register */
59 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
60 * FCTR bit 6 selects SCR or EMSR
63 #else /* not CONFIG_SERIAL_M32R_PLDSIO */
71 #define SIORBAUR 0x018
75 #define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
76 #define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
77 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
78 #define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
80 * Out: Fifo custom trigger levels
83 #define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
84 #define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
85 #define UART_FCTR 0 /* (LCR=BF) Feature Control Register
88 #define UART_IIR 0 /* In: Interrupt ID Register */
89 #define UART_FCR 0 /* Out: FIFO Control Register */
90 #define UART_EFR 0 /* I/O: Extended Features Register */
91 /* (DLAB=1, 16C660 only) */
93 #define UART_LCR 0 /* Out: Line Control Register */
94 #define UART_MCR 0 /* Out: Modem Control Register */
95 #define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
96 #define UART_MSR 0 /* In: Modem Status Register */
97 #define UART_SCR 0 /* I/O: Scratch Register */
98 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
99 * FCTR bit 6 selects SCR or EMSR
102 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
104 #define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
107 * These are the definitions for the FIFO Control Register
110 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
111 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
112 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
113 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
114 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
115 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
116 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
117 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
118 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
119 /* 16650 redefinitions */
120 #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
121 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
122 #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
123 #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
124 #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
125 #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
126 #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
127 #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
128 /* TI 16750 definitions */
129 #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */
132 * These are the definitions for the Line Control Register
134 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
135 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
137 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
138 #define UART_LCR_SBC 0x40 /* Set break control */
139 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
140 #define UART_LCR_EPAR 0x10 /* Even parity select */
141 #define UART_LCR_PARITY 0x08 /* Parity Enable */
142 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
143 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
144 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
145 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
146 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
149 * These are the definitions for the Line Status Register
151 #define UART_LSR_TEMT 0x02 /* Transmitter empty */
152 #define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
153 #define UART_LSR_BI 0x00 /* Break interrupt indicator */
154 #define UART_LSR_FE 0x80 /* Frame error indicator */
155 #define UART_LSR_PE 0x40 /* Parity error indicator */
156 #define UART_LSR_OE 0x20 /* Overrun error indicator */
157 #define UART_LSR_DR 0x04 /* Receiver data ready */
160 * These are the definitions for the Interrupt Identification Register
162 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
163 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
165 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
166 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
167 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
168 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
171 * These are the definitions for the Interrupt Enable Register
173 #define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
174 #define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
175 #define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
176 #define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
178 * Sleep mode for ST16650 and TI16750.
179 * Note that for 16650, EFR-bit 4 must be selected as well.
181 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
184 * These are the definitions for the Modem Control Register
186 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
187 #define UART_MCR_OUT2 0x08 /* Out2 complement */
188 #define UART_MCR_OUT1 0x04 /* Out1 complement */
189 #define UART_MCR_RTS 0x02 /* RTS complement */
190 #define UART_MCR_DTR 0x01 /* DTR complement */
193 * These are the definitions for the Modem Status Register
195 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
196 #define UART_MSR_RI 0x40 /* Ring Indicator */
197 #define UART_MSR_DSR 0x20 /* Data Set Ready */
198 #define UART_MSR_CTS 0x10 /* Clear to Send */
199 #define UART_MSR_DDCD 0x08 /* Delta DCD */
200 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
201 #define UART_MSR_DDSR 0x02 /* Delta DSR */
202 #define UART_MSR_DCTS 0x01 /* Delta CTS */
203 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
206 * These are the definitions for the Extended Features Register
207 * (StarTech 16C660 only, when DLAB=1)
209 #define UART_EFR_CTS 0x80 /* CTS flow control */
210 #define UART_EFR_RTS 0x40 /* RTS flow control */
211 #define UART_EFR_SCD 0x20 /* Special character detect */
212 #define UART_EFR_ECB 0x10 /* Enhanced control bit */
214 * the low four bits control software flow control
218 * These register definitions are for the 16C950
220 #define UART_ASR 0x01 /* Additional Status Register */
221 #define UART_RFL 0x03 /* Receiver FIFO level */
222 #define UART_TFL 0x04 /* Transmitter FIFO level */
223 #define UART_ICR 0x05 /* Index Control Register */
225 /* The 16950 ICR registers */
226 #define UART_ACR 0x00 /* Additional Control Register */
227 #define UART_CPR 0x01 /* Clock Prescalar Register */
228 #define UART_TCR 0x02 /* Times Clock Register */
229 #define UART_CKS 0x03 /* Clock Select Register */
230 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
231 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
232 #define UART_FCL 0x06 /* Flow Control Level Lower */
233 #define UART_FCH 0x07 /* Flow Control Level Higher */
234 #define UART_ID1 0x08 /* ID #1 */
235 #define UART_ID2 0x09 /* ID #2 */
236 #define UART_ID3 0x0A /* ID #3 */
237 #define UART_REV 0x0B /* Revision */
238 #define UART_CSR 0x0C /* Channel Software Reset */
239 #define UART_NMR 0x0D /* Nine-bit Mode Register */
240 #define UART_CTR 0xFF
243 * The 16C950 Additional Control Reigster
245 #define UART_ACR_RXDIS 0x01 /* Receiver disable */
246 #define UART_ACR_TXDIS 0x02 /* Receiver disable */
247 #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
248 #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
249 #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
250 #define UART_ACR_ASREN 0x80 /* Additional status enable */
253 * These are the definitions for the Feature Control Register
254 * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable
255 * Register, UART register #1)
257 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
258 #define UART_FCTR_RTS_4DELAY 0x01
259 #define UART_FCTR_RTS_6DELAY 0x02
260 #define UART_FCTR_RTS_8DELAY 0x03
261 #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
262 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
263 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
264 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
265 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
266 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
267 #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
268 #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
269 #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
272 * These are the definitions for the Enhanced Mode Select Register
273 * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the
274 * Scratch register, UART register #7)
276 #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
277 #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
280 * These are the definitions for the Programmable Trigger
281 * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX
282 * register, UART register #0)
284 #define UART_TRG_1 0x01
285 #define UART_TRG_4 0x04
286 #define UART_TRG_8 0x08
287 #define UART_TRG_16 0x10
288 #define UART_TRG_32 0x20
289 #define UART_TRG_64 0x40
290 #define UART_TRG_96 0x60
291 #define UART_TRG_120 0x78
292 #define UART_TRG_128 0x80
295 * These definitions are for the RSA-DV II/S card, from
297 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
300 #define UART_RSA_BASE (-8)
302 #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
304 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
305 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
306 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
307 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
309 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
311 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
312 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
313 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
314 #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
315 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
317 #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
319 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
320 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
321 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
322 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
323 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
324 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
325 #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
326 #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
328 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
330 #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
332 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
334 #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
337 * The RSA DSV/II board has two fixed clock frequencies. One is the
338 * standard rate, and the other is 8 times faster.
340 #define SERIAL_RSA_BAUD_BASE (921600)
341 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
343 #endif /* _M32R_SIO_REG_H */