2 * drivers/serial/mpsc/mpsc.c
4 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
5 * GT64260, MV64340, MV64360, GT96100, ... ).
7 * Author: Mark A. Greer <mgreer@mvista.com>
9 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
10 * have been created by Chris Zankel (formerly of MontaVista) but there
11 * is no proper Copyright so I'm not sure. Parts were, apparently, also
12 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
15 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
16 * the terms of the GNU General Public License version 2. This program
17 * is licensed "as is" without any warranty of any kind, whether express
21 * The MPSC interface is much like a typical network controller's interface.
22 * That is, you set up separate rings of descriptors for transmitting and
23 * receiving data. There is also a pool of buffers with (one buffer per
24 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
27 * The MPSC requires two other controllers to be able to work. The Baud Rate
28 * Generator (BRG) provides a clock at programmable frequencies which determines
29 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
30 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
31 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
32 * transmit and receive "engines" going (i.e., indicate data has been
33 * transmitted or received).
37 * 1) Some chips have an erratum where several regs cannot be
38 * read. To work around that, we keep a local copy of those regs in
39 * 'mpsc_port_info_t' and use the *_M macros when accessing those regs.
41 * 2) Some chips have an erratum where the chip will hang when the SDMA ctlr
42 * accesses system mem in a cache coherent region. This *should* be a
43 * show-stopper when coherency is turned on but it seems to work okay as
44 * long as there are no snoop hits. Therefore, there are explicit cache
45 * management macros in addition to the dma_* calls--the dma_* calls don't
46 * do cache mgmt on coherent systems--to manage the cache ensuring there
49 * 3) AFAICT, hardware flow control isn't supported by the controller --MAG.
55 * Define how this driver is known to the outside (we've been assigned a
56 * range on the "Low-density serial ports" major).
58 #define MPSC_MAJOR 204
59 #define MPSC_MINOR_START 5 /* XXXX */
60 #define MPSC_DRIVER_NAME "MPSC"
61 #define MPSC_DEVFS_NAME "ttym/"
62 #define MPSC_DEV_NAME "ttyM"
63 #define MPSC_VERSION "1.00"
65 static mpsc_port_info_t mpsc_ports[MPSC_NUM_CTLRS];
71 #define DBG(x...) printk(x)
77 ******************************************************************************
79 * Baud Rate Generator Routines (BRG)
81 ******************************************************************************
84 mpsc_brg_init(mpsc_port_info_t *pi, u32 clk_src)
86 if (pi->brg_can_tune) {
87 MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 25, 0);
90 MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 4, 18, clk_src);
91 MPSC_MOD_FIELD(pi, brg, BRG_BTR, 16, 0, 0);
96 mpsc_brg_enable(mpsc_port_info_t *pi)
98 MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 1);
103 mpsc_brg_disable(mpsc_port_info_t *pi)
105 MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 0);
110 mpsc_set_baudrate(mpsc_port_info_t *pi, u32 baud)
113 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
114 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
115 * However, the input clock is divided by 16 in the MPSC b/c of how
116 * 'MPSC_MMCRH' was set up so we have to divide 'clk' used in our
117 * calculation by 16 to account for that. So the real calculation
118 * that accounts for the way the mpsc is set up is:
119 * CDV = (clk / (baud*32)) - 1 ==> CDV = (clk / (baud << 5)) -1.
121 u32 cdv = (pi->port.uartclk/(baud << 5)) - 1;
123 mpsc_brg_disable(pi);
124 MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 16, 0, cdv);
131 ******************************************************************************
133 * Serial DMA Routines (SDMA)
135 ******************************************************************************
139 mpsc_sdma_burstsize(mpsc_port_info_t *pi, u32 burst_size)
143 DBG("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
144 pi->port.line, burst_size);
146 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
148 if (burst_size < 2) v = 0x0; /* 1 64-bit word */
149 else if (burst_size < 4) v = 0x1; /* 2 64-bit words */
150 else if (burst_size < 8) v = 0x2; /* 4 64-bit words */
151 else v = 0x3; /* 8 64-bit words */
153 MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 2, 12, v);
158 mpsc_sdma_init(mpsc_port_info_t *pi, u32 burst_size)
160 DBG("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, burst_size);
162 MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 10, 0, 0x03f);
163 mpsc_sdma_burstsize(pi, burst_size);
168 mpsc_sdma_intr_mask(mpsc_port_info_t *pi, u32 mask)
172 DBG("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
174 old = v = MPSC_READ_M(pi, sdma_intr, SDMA_INTR_MASK);
176 if (pi->port.line) mask <<= 8;
178 MPSC_WRITE_M(pi, sdma_intr, SDMA_INTR_MASK, v);
180 if (pi->port.line) old >>= 8;
185 mpsc_sdma_intr_unmask(mpsc_port_info_t *pi, u32 mask)
189 DBG("mpsc_sdma_intr_unmask[%d]: clk_src: 0x%x\n", pi->port.line, mask);
191 v = MPSC_READ_M(pi, sdma_intr, SDMA_INTR_MASK);
193 if (pi->port.line) mask <<= 8;
195 MPSC_WRITE_M(pi, sdma_intr, SDMA_INTR_MASK, v);
200 mpsc_sdma_intr_ack(mpsc_port_info_t *pi)
202 DBG("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
203 MPSC_WRITE(pi, sdma_intr, SDMA_INTR_CAUSE, 0);
208 mpsc_sdma_set_rx_ring(mpsc_port_info_t *pi, mpsc_rx_desc_t *rxre_p)
210 DBG("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
211 pi->port.line, (uint)rxre_p);
213 MPSC_WRITE(pi, sdma, SDMA_SCRDP, (u32)rxre_p);
218 mpsc_sdma_set_tx_ring(mpsc_port_info_t *pi, volatile mpsc_tx_desc_t *txre_p)
220 MPSC_WRITE(pi, sdma, SDMA_SFTDP, (int)txre_p);
221 MPSC_WRITE(pi, sdma, SDMA_SCTDP, (int)txre_p);
226 mpsc_sdma_cmd(mpsc_port_info_t *pi, u32 val)
230 v = MPSC_READ(pi, sdma, SDMA_SDCM);
235 MPSC_WRITE(pi, sdma, SDMA_SDCM, v);
240 mpsc_sdma_start_tx(mpsc_port_info_t *pi, volatile mpsc_tx_desc_t *txre_p)
242 mpsc_sdma_set_tx_ring(pi, txre_p);
243 mpsc_sdma_cmd(pi, SDMA_SDCM_TXD);
248 mpsc_sdma_stop(mpsc_port_info_t *pi)
250 DBG("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
252 /* Abort any SDMA transfers */
253 mpsc_sdma_cmd(pi, 0);
254 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
256 /* Clear the SDMA current and first TX and RX pointers */
257 mpsc_sdma_set_tx_ring(pi, 0);
258 mpsc_sdma_set_rx_ring(pi, 0);
259 /* udelay(100); XXXX was in original gt64260 driver */
261 /* Disable interrupts */
262 mpsc_sdma_intr_mask(pi, 0xf);
263 mpsc_sdma_intr_ack(pi);
270 ******************************************************************************
272 * Multi-Protocol Serial Controller Routines (MPSC)
274 ******************************************************************************
278 mpsc_hw_init(mpsc_port_info_t *pi)
280 DBG("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
282 /* Set up clock routing */
283 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_MRR, 3, 0, 0);
284 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_MRR, 3, 6, 0);
285 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_RCRR, 4, 0, 0);
286 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_RCRR, 4, 8, 1);
287 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_TCRR, 4, 0, 0);
288 MPSC_MOD_FIELD_M(pi, mpsc_routing, MPSC_TCRR, 4, 8, 1);
290 /* Put MPSC in UART mode & enabel Tx/Rx egines */
291 MPSC_WRITE(pi, mpsc, MPSC_MMCRL, 0x000004c4);
293 /* No preamble, 16x divider, low-latency, */
294 MPSC_WRITE(pi, mpsc, MPSC_MMCRH, 0x04400400);
296 MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0);
297 MPSC_WRITE_M(pi, mpsc, MPSC_CHR_2, 0);
298 MPSC_WRITE(pi, mpsc, MPSC_CHR_3, pi->mpsc_max_idle);
299 MPSC_WRITE(pi, mpsc, MPSC_CHR_4, 0);
300 MPSC_WRITE(pi, mpsc, MPSC_CHR_5, 0);
301 MPSC_WRITE(pi, mpsc, MPSC_CHR_6, 0);
302 MPSC_WRITE(pi, mpsc, MPSC_CHR_7, 0);
303 MPSC_WRITE(pi, mpsc, MPSC_CHR_8, 0);
304 MPSC_WRITE(pi, mpsc, MPSC_CHR_9, 0);
305 MPSC_WRITE(pi, mpsc, MPSC_CHR_10, 0);
311 mpsc_enter_hunt(mpsc_port_info_t *pi)
315 DBG("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
317 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 1, 31, 1);
319 if (pi->mirror_regs) {
324 v = MPSC_READ_M(pi, mpsc, MPSC_CHR_2);
325 } while (v & MPSC_CHR_2_EH);
331 mpsc_freeze(mpsc_port_info_t *pi)
333 DBG("mpsc_freeze[%d]: Freezing\n", pi->port.line);
335 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 9, 1);
340 mpsc_unfreeze(mpsc_port_info_t *pi)
342 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 9, 0);
344 DBG("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
349 mpsc_set_char_length(mpsc_port_info_t *pi, u32 len)
351 DBG("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line, len);
353 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 2, 12, len);
358 mpsc_set_stop_bit_length(mpsc_port_info_t *pi, u32 len)
360 DBG("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",pi->port.line,len);
362 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 14, len);
367 mpsc_set_parity(mpsc_port_info_t *pi, u32 p)
369 DBG("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
371 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 2, 2, p); /* TPM */
372 MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 2, 18, p); /* RPM */
377 ******************************************************************************
379 * Driver Init Routines
381 ******************************************************************************
385 mpsc_init_hw(mpsc_port_info_t *pi)
387 DBG("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
389 mpsc_brg_init(pi, pi->brg_clk_src);
391 mpsc_sdma_init(pi, dma_get_cache_alignment());/* burst a cacheline */
399 mpsc_alloc_ring_mem(mpsc_port_info_t *pi)
402 static void mpsc_free_ring_mem(mpsc_port_info_t *pi);
404 DBG("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n", pi->port.line);
406 pi->desc_region_size = MPSC_TXR_SIZE + MPSC_RXR_SIZE +
407 (2 * MPSC_DESC_ALIGN);
408 pi->buf_region_size = MPSC_TXB_SIZE + MPSC_RXB_SIZE +
409 (2 * MPSC_BUF_ALIGN);
411 if (!pi->desc_region) {
412 if (!dma_supported(pi->port.dev, 0xffffffff)) {
413 printk(KERN_ERR "MPSC: inadequate DMA support\n");
416 else if ((pi->desc_region = dma_alloc_coherent(pi->port.dev,
417 pi->desc_region_size, &pi->desc_region_p,
418 GFP_KERNEL)) == NULL) {
420 printk(KERN_ERR "MPSC: can't alloc Desc region\n");
423 else if ((pi->buf_region = kmalloc(pi->buf_region_size,
424 GFP_KERNEL)) == NULL) {
426 printk(KERN_ERR "MPSC: can't alloc bufs\n");
427 mpsc_free_ring_mem(pi);
436 mpsc_free_ring_mem(mpsc_port_info_t *pi)
438 DBG("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
440 if (pi->desc_region) {
441 MPSC_CACHE_INVALIDATE(pi, pi->desc_region,
442 pi->desc_region + pi->desc_region_size);
443 dma_free_coherent(pi->port.dev, pi->desc_region_size,
444 pi->desc_region, pi->desc_region_p);
445 pi->desc_region = NULL;
446 pi->desc_region_p = (dma_addr_t)NULL;
449 if (pi->buf_region) {
450 MPSC_CACHE_INVALIDATE(pi, pi->buf_region,
451 pi->buf_region + pi->buf_region_size);
452 kfree(pi->buf_region);
453 pi->buf_region = NULL;
460 mpsc_init_rings(mpsc_port_info_t *pi)
462 mpsc_rx_desc_t *rxre, *rxre_p;
463 mpsc_tx_desc_t *txre, *txre_p;
464 u32 bp_p, save_first, i;
467 DBG("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
469 BUG_ON((pi->desc_region == NULL) || (pi->buf_region == NULL));
471 memset(pi->desc_region, 0, pi->desc_region_size);
472 memset(pi->buf_region, 0, pi->buf_region_size);
474 pi->rxr = (mpsc_rx_desc_t *)ALIGN((u32)pi->desc_region,
475 (u32)MPSC_DESC_ALIGN);
476 pi->rxr_p = (mpsc_rx_desc_t *)ALIGN((u32)pi->desc_region_p,
477 (u32)MPSC_DESC_ALIGN);
478 pi->rxb = (u8 *)ALIGN((u32)pi->buf_region, (u32)MPSC_BUF_ALIGN);
479 pi->rxb_p = __pa(pi->rxb);
483 save_first = (u32)rxre_p;
486 for (i=0; i<MPSC_RXR_ENTRIES; i++,rxre++,rxre_p++) {
487 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
488 rxre->bytecnt = cpu_to_be16(0);
489 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
490 SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F |
491 SDMA_DESC_CMDSTAT_L);
492 rxre->link = cpu_to_be32(rxre_p + 1);
493 rxre->buf_ptr = cpu_to_be32(bp_p);
494 MPSC_CACHE_FLUSH(pi, rxre, rxre + 1);
495 dma_map_single(pi->port.dev, bp, MPSC_RXBE_SIZE,
497 MPSC_CACHE_INVALIDATE(pi, bp, bp + MPSC_RXBE_SIZE);
498 bp += MPSC_RXBE_SIZE;
499 bp_p += MPSC_RXBE_SIZE;
501 (--rxre)->link = cpu_to_be32(save_first); /* Wrap last back to first */
502 MPSC_CACHE_FLUSH(pi, rxre, rxre + 1);
504 pi->txr = (mpsc_tx_desc_t *)ALIGN((u32)&pi->rxr[MPSC_RXR_ENTRIES],
505 (u32)MPSC_DESC_ALIGN);
506 pi->txr_p = (mpsc_tx_desc_t *)ALIGN((u32)&pi->rxr_p[MPSC_RXR_ENTRIES],
507 (u32)MPSC_DESC_ALIGN);
508 pi->txb = (u8 *)ALIGN((u32)(pi->rxb + MPSC_RXB_SIZE),
509 (u32)MPSC_BUF_ALIGN);
510 pi->txb_p = __pa(pi->txb);
514 save_first = (u32)txre_p;
517 for (i=0; i<MPSC_TXR_ENTRIES; i++,txre++,txre_p++) {
518 txre->link = cpu_to_be32(txre_p + 1);
519 txre->buf_ptr = cpu_to_be32(bp_p);
520 MPSC_CACHE_FLUSH(pi, txre, txre + 1);
521 dma_map_single(pi->port.dev, bp, MPSC_TXBE_SIZE, DMA_TO_DEVICE);
522 bp += MPSC_TXBE_SIZE;
523 bp_p += MPSC_TXBE_SIZE;
525 (--txre)->link = cpu_to_be32(save_first); /* Wrap last back to first */
526 MPSC_CACHE_FLUSH(pi, txre, txre + 1);
532 mpsc_uninit_rings(mpsc_port_info_t *pi)
536 DBG("mpsc_uninit_rings[%d]: Uninitializing rings\n", pi->port.line);
538 BUG_ON((pi->desc_region == NULL) || (pi->buf_region == NULL));
541 for (i=0; i<MPSC_RXR_ENTRIES; i++) {
542 dma_unmap_single(pi->port.dev, bp_p, MPSC_RXBE_SIZE,
544 bp_p += MPSC_RXBE_SIZE;
553 for (i=0; i<MPSC_TXR_ENTRIES; i++) {
554 dma_unmap_single(pi->port.dev, bp_p, MPSC_TXBE_SIZE,
556 bp_p += MPSC_TXBE_SIZE;
568 mpsc_make_ready(mpsc_port_info_t *pi)
572 DBG("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
576 if ((rc = mpsc_alloc_ring_mem(pi)))
586 ******************************************************************************
588 * Interrupt Handling Routines
590 ******************************************************************************
594 mpsc_rx_intr(mpsc_port_info_t *pi, struct pt_regs *regs)
596 volatile mpsc_rx_desc_t *rxre = &pi->rxr[pi->rxr_posn];
597 struct tty_struct *tty = pi->port.info->tty;
598 u32 cmdstat, bytes_in;
601 static void mpsc_start_rx(mpsc_port_info_t *pi);
603 DBG("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
606 * Loop through Rx descriptors handling ones that have been completed.
608 MPSC_CACHE_INVALIDATE(pi, rxre, rxre + 1);
610 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
611 bytes_in = be16_to_cpu(rxre->bytecnt);
613 if (unlikely((tty->flip.count + bytes_in) >= TTY_FLIPBUF_SIZE)){
614 tty->flip.work.func((void *)tty);
616 if ((tty->flip.count + bytes_in) >= TTY_FLIPBUF_SIZE) {
617 /* Take what we can, throw away the rest */
618 bytes_in = TTY_FLIPBUF_SIZE - tty->flip.count;
619 cmdstat &= ~SDMA_DESC_CMDSTAT_PE;
623 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
624 bp_p = pi->txb_p + (pi->rxr_posn * MPSC_RXBE_SIZE);
626 dma_sync_single_for_cpu(pi->port.dev, bp_p, MPSC_RXBE_SIZE,
628 MPSC_CACHE_INVALIDATE(pi, bp, bp + MPSC_RXBE_SIZE);
631 * Other than for parity error, the manual provides little
632 * info on what data will be in a frame flagged by any of
633 * these errors. For parity error, it is the last byte in
634 * the buffer that had the error. As for the rest, I guess
635 * we'll assume there is no data in the buffer.
636 * If there is...it gets lost.
638 if (cmdstat & (SDMA_DESC_CMDSTAT_BR | SDMA_DESC_CMDSTAT_FR |
639 SDMA_DESC_CMDSTAT_OR)) {
641 pi->port.icount.rx++;
643 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
644 pi->port.icount.brk++;
646 if (uart_handle_break(&pi->port))
649 else if (cmdstat & SDMA_DESC_CMDSTAT_FR) /* Framing */
650 pi->port.icount.frame++;
651 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
652 pi->port.icount.overrun++;
654 cmdstat &= pi->port.read_status_mask;
656 if (!(cmdstat & pi->port.ignore_status_mask)) {
657 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
658 *tty->flip.flag_buf_ptr = TTY_BREAK;
659 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
660 *tty->flip.flag_buf_ptr = TTY_FRAME;
661 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
662 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
664 tty->flip.flag_buf_ptr++;
665 *tty->flip.char_buf_ptr = '\0';
666 tty->flip.char_buf_ptr++;
671 if (uart_handle_sysrq_char(&pi->port, *bp, regs)) {
676 memcpy(tty->flip.char_buf_ptr, bp, bytes_in);
677 memset(tty->flip.flag_buf_ptr, TTY_NORMAL, bytes_in);
679 tty->flip.char_buf_ptr += bytes_in;
680 tty->flip.flag_buf_ptr += bytes_in;
681 tty->flip.count += bytes_in;
682 pi->port.icount.rx += bytes_in;
684 cmdstat &= SDMA_DESC_CMDSTAT_PE;
686 if (cmdstat) { /* Parity */
687 pi->port.icount.parity++;
689 if (!(cmdstat & pi->port.read_status_mask))
690 *(tty->flip.flag_buf_ptr-1) = TTY_FRAME;
695 dma_sync_single_for_device(pi->port.dev, bp_p,
696 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
697 rxre->bytecnt = cpu_to_be16(0);
698 wmb(); /* ensure other writes done before cmdstat update */
699 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
700 SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F |
701 SDMA_DESC_CMDSTAT_L);
702 MPSC_CACHE_FLUSH(pi, rxre, rxre + 1);
704 /* Advance to next descriptor */
705 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
706 rxre = &pi->rxr[pi->rxr_posn];
707 MPSC_CACHE_INVALIDATE(pi, rxre, rxre + 1);
710 /* Restart rx engine, if its stopped */
711 if ((MPSC_READ(pi, sdma, SDMA_SDCM) & SDMA_SDCM_ERD) == 0) {
715 tty_flip_buffer_push(tty);
720 mpsc_send_tx_data(mpsc_port_info_t *pi, volatile mpsc_tx_desc_t *txre,
721 volatile mpsc_tx_desc_t *txre_p, void *bp, u32 count, u32 intr)
723 dma_sync_single_for_device(pi->port.dev, be32_to_cpu(txre->buf_ptr),
724 MPSC_TXBE_SIZE, DMA_TO_DEVICE);
725 MPSC_CACHE_FLUSH(pi, bp, bp + MPSC_TXBE_SIZE);
727 txre->bytecnt = cpu_to_be16(count);
728 txre->shadow = txre->bytecnt;
729 wmb(); /* ensure cmdstat is last field updated */
730 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
731 SDMA_DESC_CMDSTAT_L | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
732 MPSC_CACHE_FLUSH(pi, txre, txre + 1);
734 /* Start Tx engine, if its stopped */
735 if ((MPSC_READ(pi, sdma, SDMA_SDCM) & SDMA_SDCM_TXD) == 0) {
736 mpsc_sdma_start_tx(pi, txre_p);
743 mpsc_tx_intr(mpsc_port_info_t *pi)
745 volatile mpsc_tx_desc_t *txre = &pi->txr[pi->txr_posn];
746 volatile mpsc_tx_desc_t *txre_p = &pi->txr_p[pi->txr_posn];
747 struct circ_buf *xmit = &pi->port.info->xmit;
751 MPSC_CACHE_INVALIDATE(pi, txre, txre + 1);
753 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
754 bp = &pi->txb[pi->txr_posn * MPSC_TXBE_SIZE];
756 dma_sync_single_for_cpu(pi->port.dev,be32_to_cpu(txre->buf_ptr),
757 MPSC_TXBE_SIZE, DMA_TO_DEVICE);
759 if (pi->port.x_char) {
761 * Ideally, we should use the TCS field in CHR_1 to
762 * put the x_char out immediately but errata prevents
763 * us from being able to read CHR_2 to know that its
764 * safe to write to CHR_1. Instead, just put it
765 * in-band with all the other Tx data.
767 *bp = pi->port.x_char;
771 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
772 i = MIN(MPSC_TXBE_SIZE, uart_circ_chars_pending(xmit));
773 i = MIN(i, CIRC_CNT_TO_END(xmit->head, xmit->tail,
775 memcpy(bp, &xmit->buf[xmit->tail], i);
776 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
778 else { /* No more data to transmit or tx engine is stopped */
779 MPSC_CACHE_INVALIDATE(pi, txre, txre + 1);
783 mpsc_send_tx_data(pi, txre, txre_p, bp, i, 1);
784 pi->port.icount.tx += i;
786 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
787 uart_write_wakeup(&pi->port);
789 /* Advance to next descriptor */
790 pi->txr_posn = (pi->txr_posn + 1) & (MPSC_TXR_ENTRIES - 1);
791 txre = &pi->txr[pi->txr_posn];
792 txre_p = &pi->txr_p[pi->txr_posn];
793 MPSC_CACHE_INVALIDATE(pi, txre, txre + 1);
800 * This is the driver's interrupt handler. To avoid a race, we first clear
801 * the interrupt, then handle any completed Rx/Tx descriptors. When done
802 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
805 mpsc_sdma_intr(int irq, void *dev_id, struct pt_regs *regs)
807 mpsc_port_info_t *pi = dev_id;
810 DBG("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n", pi->port.line);
812 spin_lock_irqsave(&pi->port.lock, iflags);
813 mpsc_sdma_intr_ack(pi);
814 mpsc_rx_intr(pi, regs);
816 spin_unlock_irqrestore(&pi->port.lock, iflags);
818 DBG("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
823 ******************************************************************************
825 * serial_core.c Interface routines
827 ******************************************************************************
831 _mpsc_tx_empty(mpsc_port_info_t *pi)
833 return (((MPSC_READ(pi, sdma, SDMA_SDCM) & SDMA_SDCM_TXD) == 0) ?
838 mpsc_tx_empty(struct uart_port *port)
840 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
844 spin_lock_irqsave(&pi->port.lock, iflags);
845 rc = _mpsc_tx_empty(pi);
846 spin_unlock_irqrestore(&pi->port.lock, iflags);
852 mpsc_set_mctrl(struct uart_port *port, uint mctrl)
854 /* Have no way to set modem control lines AFAICT */
859 mpsc_get_mctrl(struct uart_port *port)
861 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
865 spin_lock_irqsave(&pi->port.lock, iflags);
866 status = MPSC_READ_M(pi, mpsc, MPSC_CHR_10);
867 spin_unlock_irqrestore(&pi->port.lock, iflags);
875 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
879 mpsc_stop_tx(struct uart_port *port, uint tty_start)
881 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
883 DBG("mpsc_stop_tx[%d]: tty_start: %d\n", port->line, tty_start);
890 mpsc_start_tx(struct uart_port *port, uint tty_start)
892 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
895 mpsc_tx_intr(pi); /* Load Tx data into Tx ring bufs & go */
897 DBG("mpsc_start_tx[%d]: tty_start: %d\n", port->line, tty_start);
902 mpsc_start_rx(mpsc_port_info_t *pi)
904 DBG("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
909 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
915 mpsc_stop_rx(struct uart_port *port)
917 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
919 DBG("mpsc_stop_rx[%d]: Stopping...\n", port->line);
921 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
926 mpsc_enable_ms(struct uart_port *port)
928 return; /* Not supported */
932 mpsc_break_ctl(struct uart_port *port, int ctl)
934 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
937 spin_lock_irqsave(&pi->port.lock, flags);
939 /* Send as many BRK chars as we can */
940 MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0x00ff0000);
943 /* Stop sending BRK chars */
944 MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0);
946 spin_unlock_irqrestore(&pi->port.lock, flags);
952 mpsc_startup(struct uart_port *port)
954 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
957 DBG("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
958 port->line, pi->port.irq);
960 if ((rc = mpsc_make_ready(pi)) == 0) {
961 /* Setup IRQ handler */
962 mpsc_sdma_intr_ack(pi);
963 mpsc_sdma_intr_unmask(pi, 0xf);
965 if (request_irq(pi->port.irq, mpsc_sdma_intr, 0, "MPSC/SDMA",
967 printk(KERN_ERR "MPSC: Can't get SDMA IRQ");
968 printk("MPSC: Can't get SDMA IRQ %d\n", pi->port.irq);
971 mpsc_sdma_set_rx_ring(pi, &pi->rxr_p[pi->rxr_posn]);
979 mpsc_shutdown(struct uart_port *port)
981 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
982 static void mpsc_release_port(struct uart_port *port);
984 DBG("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
987 free_irq(pi->port.irq, pi);
992 mpsc_set_termios(struct uart_port *port, struct termios *termios,
995 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
998 u32 chr_bits, stop_bits, par;
1000 pi->c_iflag = termios->c_iflag;
1001 pi->c_cflag = termios->c_cflag;
1003 switch (termios->c_cflag & CSIZE) {
1005 chr_bits = MPSC_MPCR_CL_5;
1008 chr_bits = MPSC_MPCR_CL_6;
1011 chr_bits = MPSC_MPCR_CL_7;
1015 chr_bits = MPSC_MPCR_CL_8;
1019 if (termios->c_cflag & CSTOPB)
1020 stop_bits = MPSC_MPCR_SBL_2;
1022 stop_bits = MPSC_MPCR_SBL_1;
1024 if (termios->c_cflag & PARENB) {
1025 if (termios->c_cflag & PARODD)
1026 par = MPSC_CHR_2_PAR_ODD;
1028 par = MPSC_CHR_2_PAR_EVEN;
1030 if (termios->c_cflag & CMSPAR) {
1031 if (termios->c_cflag & PARODD)
1032 par = MPSC_CHR_2_PAR_MARK;
1034 par = MPSC_CHR_2_PAR_SPACE;
1039 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1040 quot = uart_get_divisor(port, baud);
1042 spin_lock_irqsave(&pi->port.lock, flags);
1044 uart_update_timeout(port, termios->c_cflag, baud);
1046 mpsc_set_char_length(pi, chr_bits);
1047 mpsc_set_stop_bit_length(pi, stop_bits);
1048 mpsc_set_parity(pi, par);
1049 mpsc_set_baudrate(pi, baud);
1051 /* Characters/events to read */
1053 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1055 if (termios->c_iflag & INPCK)
1056 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1057 SDMA_DESC_CMDSTAT_FR;
1059 if (termios->c_iflag & (BRKINT | PARMRK))
1060 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1062 /* Characters/events to ignore */
1063 pi->port.ignore_status_mask = 0;
1065 if (termios->c_iflag & IGNPAR)
1066 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
1067 SDMA_DESC_CMDSTAT_FR;
1069 if (termios->c_iflag & IGNBRK) {
1070 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1072 if (termios->c_iflag & IGNPAR)
1073 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1076 /* Ignore all chars if CREAD not set */
1077 if (!(termios->c_cflag & CREAD))
1080 spin_unlock_irqrestore(&pi->port.lock, flags);
1085 mpsc_type(struct uart_port *port)
1087 DBG("mpsc_type[%d]: port type: %s\n", port->line, MPSC_DRIVER_NAME);
1088 return MPSC_DRIVER_NAME;
1092 mpsc_request_port(struct uart_port *port)
1094 /* Should make chip/platform specific call */
1099 mpsc_release_port(struct uart_port *port)
1101 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
1103 mpsc_uninit_rings(pi);
1104 mpsc_free_ring_mem(pi);
1111 mpsc_config_port(struct uart_port *port, int flags)
1117 mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1119 mpsc_port_info_t *pi = (mpsc_port_info_t *)port;
1122 DBG("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1124 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1126 if (pi->port.irq != ser->irq)
1128 if (ser->io_type != SERIAL_IO_MEM)
1130 if (pi->port.uartclk / 16 != ser->baud_base) /* XXXX Not sure */
1132 if ((void *)pi->port.mapbase != ser->iomem_base)
1134 if (pi->port.iobase != ser->port)
1142 static struct uart_ops mpsc_pops = {
1143 .tx_empty = mpsc_tx_empty,
1144 .set_mctrl = mpsc_set_mctrl,
1145 .get_mctrl = mpsc_get_mctrl,
1146 .stop_tx = mpsc_stop_tx,
1147 .start_tx = mpsc_start_tx,
1148 .stop_rx = mpsc_stop_rx,
1149 .enable_ms = mpsc_enable_ms,
1150 .break_ctl = mpsc_break_ctl,
1151 .startup = mpsc_startup,
1152 .shutdown = mpsc_shutdown,
1153 .set_termios = mpsc_set_termios,
1155 .release_port = mpsc_release_port,
1156 .request_port = mpsc_request_port,
1157 .config_port = mpsc_config_port,
1158 .verify_port = mpsc_verify_port,
1162 ******************************************************************************
1164 * Console Interface Routines
1166 ******************************************************************************
1169 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1171 mpsc_console_write(struct console *co, const char *s, uint count)
1173 mpsc_port_info_t *pi = &mpsc_ports[co->index];
1174 volatile mpsc_tx_desc_t *txre = &pi->txr[pi->txr_posn];
1175 volatile mpsc_tx_desc_t *txre_p = &pi->txr_p[pi->txr_posn];
1176 u8 *bp, *dp, add_cr = 0;
1180 * Step thru tx ring one entry at a time, filling up its buf, sending
1181 * the data out and moving to the next ring entry until its all out.
1183 MPSC_CACHE_INVALIDATE(pi, txre, txre + 1);
1186 while (_mpsc_tx_empty(pi) != TIOCSER_TEMT);
1188 BUG_ON(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O);
1190 bp = dp = &pi->txb[pi->txr_posn * MPSC_TXBE_SIZE];
1192 dma_sync_single_for_cpu(pi->port.dev,be32_to_cpu(txre->buf_ptr),
1193 MPSC_TXBE_SIZE, DMA_TO_DEVICE);
1195 for (i=0; i<MPSC_TXBE_SIZE; i++) {
1206 if (*(s++) == '\n') { /* add '\r' after '\n' */
1215 mpsc_send_tx_data(pi, txre, txre_p, bp, i, 0);
1217 /* Advance to next descriptor */
1218 pi->txr_posn = (pi->txr_posn + 1) & (MPSC_TXR_ENTRIES - 1);
1219 txre = &pi->txr[pi->txr_posn];
1220 txre_p = &pi->txr_p[pi->txr_posn];
1221 MPSC_CACHE_INVALIDATE(pi, txre, txre + 1);
1224 while (_mpsc_tx_empty(pi) != TIOCSER_TEMT);
1229 mpsc_console_setup(struct console *co, char *options)
1231 mpsc_port_info_t *pi;
1232 int baud, bits, parity, flow;
1234 DBG("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1236 if (co->index >= MPSC_NUM_CTLRS)
1239 pi = &mpsc_ports[co->index];
1241 baud = pi->default_baud;
1242 bits = pi->default_bits;
1243 parity = pi->default_parity;
1244 flow = pi->default_flow;
1249 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1252 uart_parse_options(options, &baud, &parity, &bits, &flow);
1254 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1257 extern struct uart_driver mpsc_reg;
1258 static struct console mpsc_console = {
1259 .name = MPSC_DEV_NAME,
1260 .write = mpsc_console_write,
1261 .device = uart_console_device,
1262 .setup = mpsc_console_setup,
1263 .flags = CON_PRINTBUFFER,
1269 mpsc_console_init(void)
1271 DBG("mpsc_console_init: Enter\n");
1272 register_console(&mpsc_console);
1275 console_initcall(mpsc_console_init);
1278 mpsc_late_console_init(void)
1280 DBG("mpsc_late_console_init: Enter\n");
1282 if (!(mpsc_console.flags & CON_ENABLED))
1283 register_console(&mpsc_console);
1286 late_initcall(mpsc_late_console_init);
1288 #define MPSC_CONSOLE &mpsc_console
1290 #define MPSC_CONSOLE NULL
1294 ******************************************************************************
1296 * Driver Interface Routines
1298 ******************************************************************************
1302 mpsc_map_regs(mpsc_port_info_t *pi)
1304 pi->mpsc_base = (u32)ioremap(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
1305 pi->mpsc_routing_base = (u32)ioremap(pi->mpsc_routing_base_p,
1306 MPSC_ROUTING_REG_BLOCK_SIZE);
1307 pi->sdma_base = (u32)ioremap(pi->sdma_base_p, SDMA_REG_BLOCK_SIZE);
1308 pi->sdma_intr_base = (u32)ioremap(pi->sdma_intr_base_p,
1309 SDMA_INTR_REG_BLOCK_SIZE);
1310 pi->brg_base = (u32)ioremap(pi->brg_base_p, BRG_REG_BLOCK_SIZE);
1316 mpsc_unmap_regs(mpsc_port_info_t *pi)
1318 iounmap((void *)pi->mpsc_base);
1319 iounmap((void *)pi->mpsc_routing_base);
1320 iounmap((void *)pi->sdma_base);
1321 iounmap((void *)pi->sdma_intr_base);
1322 iounmap((void *)pi->brg_base);
1325 pi->mpsc_routing_base = 0;
1327 pi->sdma_intr_base = 0;
1333 /* Called from platform specific device probe routine */
1335 mpsc_device_probe(int index)
1337 mpsc_port_info_t *pi = NULL;
1339 if ((index >= 0) && (index < MPSC_NUM_CTLRS))
1340 pi = &mpsc_ports[index];
1345 /* Called from platform specific device remove routine */
1347 mpsc_device_remove(int index)
1349 mpsc_port_info_t *pi = NULL;
1351 if ((index >= 0) && (index < MPSC_NUM_CTLRS))
1352 pi = &mpsc_ports[index];
1357 static struct uart_driver mpsc_reg = {
1358 .owner = THIS_MODULE,
1359 .driver_name = MPSC_DRIVER_NAME,
1360 .devfs_name = MPSC_DEVFS_NAME,
1361 .dev_name = MPSC_DEV_NAME,
1362 .major = MPSC_MAJOR,
1363 .minor = MPSC_MINOR_START,
1364 .nr = MPSC_NUM_CTLRS,
1365 .cons = MPSC_CONSOLE,
1371 mpsc_port_info_t *pi;
1374 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n");
1376 if ((rc = mpsc_platform_register_driver()) >= 0) {
1377 if ((rc = uart_register_driver(&mpsc_reg)) < 0) {
1378 mpsc_platform_unregister_driver();
1381 for (i=0; i<MPSC_NUM_CTLRS; i++) {
1382 pi = &mpsc_ports[i];
1385 pi->port.type = PORT_MPSC;
1386 pi->port.fifosize = MPSC_TXBE_SIZE;
1387 pi->port.membase = (char *)pi->mpsc_base;
1388 pi->port.mapbase = (ulong)pi->mpsc_base;
1389 pi->port.ops = &mpsc_pops;
1393 if ((rc = mpsc_make_ready(pi)) >= 0) {
1394 uart_add_one_port(&mpsc_reg, &pi->port);
1396 else { /* on failure, undo everything */
1397 for (j=0; j<i; j++) {
1398 mpsc_unmap_regs(&mpsc_ports[j]);
1399 uart_remove_one_port(&mpsc_reg,
1400 &mpsc_ports[j].port);
1403 uart_unregister_driver(&mpsc_reg);
1404 mpsc_platform_unregister_driver();
1419 DBG("mpsc_exit: Exiting\n");
1421 for (i=0; i<MPSC_NUM_CTLRS; i++) {
1422 mpsc_unmap_regs(&mpsc_ports[i]);
1423 uart_remove_one_port(&mpsc_reg, &mpsc_ports[i].port);
1426 uart_unregister_driver(&mpsc_reg);
1427 mpsc_platform_unregister_driver();
1433 register_serial(struct serial_struct *req)
1435 return uart_register_port(&mpsc_reg, &mpsc_ports[req->line].port);
1439 unregister_serial(int line)
1441 uart_unregister_port(&mpsc_reg, line);
1445 module_init(mpsc_init);
1446 module_exit(mpsc_exit);
1448 EXPORT_SYMBOL(register_serial);
1449 EXPORT_SYMBOL(unregister_serial);
1451 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1452 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $");
1453 MODULE_VERSION(MPSC_VERSION);
1454 MODULE_LICENSE("GPL");
1455 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);