2 * drivers/serial/mpsc/mpsc_defs.h
4 * Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
5 * Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
7 * Author: Mark A. Greer <mgreer@mvista.com>
9 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #ifndef __MPSC_DEFS_H__
15 #define __MPSC_DEFS_H__
17 #define MPSC_NUM_CTLRS 2
21 *****************************************************************************
23 * Multi-Protocol Serial Controller Interface Registers
25 *****************************************************************************
28 /* Main Configuratino Register Offsets */
29 #define MPSC_MMCRL 0x0000
30 #define MPSC_MMCRH 0x0004
31 #define MPSC_MPCR 0x0008
32 #define MPSC_CHR_1 0x000c
33 #define MPSC_CHR_2 0x0010
34 #define MPSC_CHR_3 0x0014
35 #define MPSC_CHR_4 0x0018
36 #define MPSC_CHR_5 0x001c
37 #define MPSC_CHR_6 0x0020
38 #define MPSC_CHR_7 0x0024
39 #define MPSC_CHR_8 0x0028
40 #define MPSC_CHR_9 0x002c
41 #define MPSC_CHR_10 0x0030
42 #define MPSC_CHR_11 0x0034
43 #define MPSC_REG_BLOCK_SIZE 0x0038
46 #define MPSC_MPCR_CL_5 0
47 #define MPSC_MPCR_CL_6 1
48 #define MPSC_MPCR_CL_7 2
49 #define MPSC_MPCR_CL_8 3
50 #define MPSC_MPCR_SBL_1 0
51 #define MPSC_MPCR_SBL_2 3
53 #define MPSC_CHR_2_TEV (1<<1)
54 #define MPSC_CHR_2_TA (1<<7)
55 #define MPSC_CHR_2_TTCS (1<<9)
56 #define MPSC_CHR_2_REV (1<<17)
57 #define MPSC_CHR_2_RA (1<<23)
58 #define MPSC_CHR_2_CRD (1<<25)
59 #define MPSC_CHR_2_EH (1<<31)
60 #define MPSC_CHR_2_PAR_ODD 0
61 #define MPSC_CHR_2_PAR_SPACE 1
62 #define MPSC_CHR_2_PAR_EVEN 2
63 #define MPSC_CHR_2_PAR_MARK 3
65 /* MPSC Signal Routing */
66 #define MPSC_MRR 0x0000
67 #define MPSC_RCRR 0x0004
68 #define MPSC_TCRR 0x0008
69 #define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
72 *****************************************************************************
74 * Serial DMA Controller Interface Registers
76 *****************************************************************************
79 #define SDMA_SDC 0x0000
80 #define SDMA_SDCM 0x0008
81 #define SDMA_RX_DESC 0x0800
82 #define SDMA_RX_BUF_PTR 0x0808
83 #define SDMA_SCRDP 0x0810
84 #define SDMA_TX_DESC 0x0c00
85 #define SDMA_SCTDP 0x0c10
86 #define SDMA_SFTDP 0x0c14
87 #define SDMA_REG_BLOCK_SIZE 0x0c18
89 #define SDMA_DESC_CMDSTAT_PE (1<<0)
90 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
91 #define SDMA_DESC_CMDSTAT_FR (1<<3)
92 #define SDMA_DESC_CMDSTAT_OR (1<<6)
93 #define SDMA_DESC_CMDSTAT_BR (1<<9)
94 #define SDMA_DESC_CMDSTAT_MI (1<<10)
95 #define SDMA_DESC_CMDSTAT_A (1<<11)
96 #define SDMA_DESC_CMDSTAT_AM (1<<12)
97 #define SDMA_DESC_CMDSTAT_CT (1<<13)
98 #define SDMA_DESC_CMDSTAT_C (1<<14)
99 #define SDMA_DESC_CMDSTAT_ES (1<<15)
100 #define SDMA_DESC_CMDSTAT_L (1<<16)
101 #define SDMA_DESC_CMDSTAT_F (1<<17)
102 #define SDMA_DESC_CMDSTAT_P (1<<18)
103 #define SDMA_DESC_CMDSTAT_EI (1<<23)
104 #define SDMA_DESC_CMDSTAT_O (1<<31)
106 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
107 SDMA_DESC_CMDSTAT_EI)
109 #define SDMA_SDC_RFT (1<<0)
110 #define SDMA_SDC_SFM (1<<1)
111 #define SDMA_SDC_BLMR (1<<6)
112 #define SDMA_SDC_BLMT (1<<7)
113 #define SDMA_SDC_POVR (1<<8)
114 #define SDMA_SDC_RIFB (1<<9)
116 #define SDMA_SDCM_ERD (1<<7)
117 #define SDMA_SDCM_AR (1<<15)
118 #define SDMA_SDCM_STD (1<<16)
119 #define SDMA_SDCM_TXD (1<<23)
120 #define SDMA_SDCM_AT (1<<31)
122 #define SDMA_0_CAUSE_RXBUF (1<<0)
123 #define SDMA_0_CAUSE_RXERR (1<<1)
124 #define SDMA_0_CAUSE_TXBUF (1<<2)
125 #define SDMA_0_CAUSE_TXEND (1<<3)
126 #define SDMA_1_CAUSE_RXBUF (1<<8)
127 #define SDMA_1_CAUSE_RXERR (1<<9)
128 #define SDMA_1_CAUSE_TXBUF (1<<10)
129 #define SDMA_1_CAUSE_TXEND (1<<11)
131 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
132 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
133 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
134 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
136 /* SDMA Interrupt registers */
137 #define SDMA_INTR_CAUSE 0x0000
138 #define SDMA_INTR_MASK 0x0080
139 #define SDMA_INTR_REG_BLOCK_SIZE 0x0084
142 *****************************************************************************
144 * Baud Rate Generator Interface Registers
146 *****************************************************************************
149 #define BRG_BCR 0x0000
150 #define BRG_BTR 0x0004
151 #define BRG_REG_BLOCK_SIZE 0x0008
153 #endif /*__MPSC_DEFS_H__ */