2 * linux/drivers/serial/s3c2410.c
4 * Driver for onboard UARTs on the Samsung S3C24XX
6 * Based on drivers/char/serial.c and drivers/char/21285.c
8 * Ben Dooks, (c) 2003 Simtec Electronics
12 * 22-Jul-2004 BJD Finished off device rewrite
14 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
15 * problems with baud rate and loss of IR settings. Update
16 * to add configuration via platform_device structure
18 * 28-Sep-2004 BJD Re-write for the following items
19 * - S3C2410 and S3C2440 serial support
20 * - Power Management support
21 * - Fix console via IrDA devices
22 * - SysReq (Herbert Pötzl)
23 * - Break character handling (Herbert Pötzl)
24 * - spin-lock initialisation (Dimitry Andric)
25 * - added clock control
26 * - updated init code to use platform_device info
29 /* Hote on 2410 error handling
31 * The s3c2410 manual has a love/hate affair with the contents of the
32 * UERSTAT register in the UART blocks, and keeps marking some of the
33 * error bits as reserved. Having checked with the s3c2410x01,
34 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
35 * feature from the latter versions of the manual.
37 * If it becomes aparrent that latter versions of the 2410 remove these
38 * bits, then action will have to be taken to differentiate the versions
39 * and change the policy on BREAK
44 #include <linux/config.h>
46 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50 #include <linux/module.h>
51 #include <linux/ioport.h>
52 #include <linux/device.h>
53 #include <linux/init.h>
54 #include <linux/sysrq.h>
55 #include <linux/console.h>
56 #include <linux/tty.h>
57 #include <linux/tty_flip.h>
58 #include <linux/serial_core.h>
59 #include <linux/serial.h>
60 #include <linux/delay.h>
65 #include <asm/hardware.h>
66 #include <asm/hardware/clock.h>
68 #include <asm/arch/regs-serial.h>
69 #include <asm/arch/regs-gpio.h>
71 #include <asm/mach-types.h>
75 struct s3c24xx_uart_info {
78 unsigned int fifosize;
79 unsigned long rx_fifomask;
80 unsigned long rx_fifoshift;
81 unsigned long rx_fifofull;
82 unsigned long tx_fifomask;
83 unsigned long tx_fifoshift;
84 unsigned long tx_fifofull;
86 /* clock source control */
88 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
89 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
92 struct s3c24xx_uart_port {
93 unsigned char rx_claimed;
94 unsigned char tx_claimed;
96 struct s3c24xx_uart_info *info;
97 struct s3c24xx_uart_clksrc *clksrc;
100 struct uart_port port;
104 /* configuration defines */
108 /* send debug to the low-level output routines */
110 extern void printascii(const char *);
113 s3c24xx_serial_dbg(const char *fmt, ...)
119 vsprintf(buff, fmt, va);
125 #define dbg(x...) s3c24xx_serial_dbg(x)
128 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
131 #define dbg(x...) do {} while(0)
134 /* UART name and device definitions */
136 #define S3C24XX_SERIAL_NAME "ttySAC"
137 #define S3C24XX_SERIAL_DEVFS "tts/"
138 #define S3C24XX_SERIAL_MAJOR 204
139 #define S3C24XX_SERIAL_MINOR 64
142 /* conversion functions */
144 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
145 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
147 /* we can support 3 uarts, but not always use them */
151 /* port irq numbers */
153 #define TX_IRQ(port) ((port)->irq + 1)
154 #define RX_IRQ(port) ((port)->irq)
156 /* register access controls */
158 #define portaddr(port, reg) ((port)->membase + (reg))
160 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
161 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
163 #define wr_regb(port, reg, val) \
164 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
166 #define wr_regl(port, reg, val) \
167 do { __raw_writel(val, portaddr(port, reg)); } while(0)
169 /* macros to change one thing to another */
171 #define tx_enabled(port) ((port)->unused[0])
172 #define rx_enabled(port) ((port)->unused[1])
174 /* flag to ignore all characters comming in */
175 #define RXSTAT_DUMMY_READ (0x10000000)
177 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
179 return container_of(port, struct s3c24xx_uart_port, port);
182 /* translate a port to the device name */
184 static inline char *s3c24xx_serial_portname(struct uart_port *port)
186 return to_platform_device(port->dev)->name;
189 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
191 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
194 static void s3c24xx_serial_rx_enable(struct uart_port *port)
197 unsigned int ucon, ufcon;
200 spin_lock_irqsave(&port->lock, flags);
202 while (--count && !s3c24xx_serial_txempty_nofifo(port))
205 ufcon = rd_regl(port, S3C2410_UFCON);
206 ufcon |= S3C2410_UFCON_RESETRX;
207 wr_regl(port, S3C2410_UFCON, ufcon);
209 ucon = rd_regl(port, S3C2410_UCON);
210 ucon |= S3C2410_UCON_RXIRQMODE;
211 wr_regl(port, S3C2410_UCON, ucon);
213 rx_enabled(port) = 1;
214 spin_unlock_irqrestore(&port->lock, flags);
217 static void s3c24xx_serial_rx_disable(struct uart_port *port)
222 spin_lock_irqsave(&port->lock, flags);
224 ucon = rd_regl(port, S3C2410_UCON);
225 ucon &= ~S3C2410_UCON_RXIRQMODE;
226 wr_regl(port, S3C2410_UCON, ucon);
228 rx_enabled(port) = 0;
229 spin_unlock_irqrestore(&port->lock, flags);
233 s3c24xx_serial_stop_tx(struct uart_port *port, unsigned int tty_stop)
235 if (tx_enabled(port)) {
236 disable_irq(TX_IRQ(port));
237 tx_enabled(port) = 0;
238 if (port->flags & UPF_CONS_FLOW)
239 s3c24xx_serial_rx_enable(port);
244 s3c24xx_serial_start_tx(struct uart_port *port, unsigned int tty_start)
246 if (!tx_enabled(port)) {
247 if (port->flags & UPF_CONS_FLOW)
248 s3c24xx_serial_rx_disable(port);
250 enable_irq(TX_IRQ(port));
251 tx_enabled(port) = 1;
256 static void s3c24xx_serial_stop_rx(struct uart_port *port)
258 if (rx_enabled(port)) {
259 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
260 disable_irq(RX_IRQ(port));
261 rx_enabled(port) = 0;
265 static void s3c24xx_serial_enable_ms(struct uart_port *port)
269 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
271 return to_ourport(port)->info;
274 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
276 if (port->dev == NULL)
279 return (struct s3c2410_uartcfg *)port->dev->platform_data;
282 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
283 unsigned long ufstat)
285 struct s3c24xx_uart_info *info = ourport->info;
287 if (ufstat & info->rx_fifofull)
288 return info->fifosize;
290 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
294 /* ? - where has parity gone?? */
295 #define S3C2410_UERSTAT_PARITY (0x1000)
298 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
300 struct s3c24xx_uart_port *ourport = dev_id;
301 struct uart_port *port = &ourport->port;
302 struct tty_struct *tty = port->info->tty;
303 unsigned int ufcon, ch, flag, ufstat, uerstat;
306 while (max_count-- > 0) {
307 ufcon = rd_regl(port, S3C2410_UFCON);
308 ufstat = rd_regl(port, S3C2410_UFSTAT);
310 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
313 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
314 if (tty->low_latency)
315 tty_flip_buffer_push(tty);
318 * If this failed then we will throw away the
319 * bytes but must do so to clear interrupts
323 uerstat = rd_regl(port, S3C2410_UERSTAT);
324 ch = rd_regb(port, S3C2410_URXH);
326 if (port->flags & UPF_CONS_FLOW) {
327 int txe = s3c24xx_serial_txempty_nofifo(port);
329 if (rx_enabled(port)) {
331 rx_enabled(port) = 0;
336 ufcon |= S3C2410_UFCON_RESETRX;
337 wr_regl(port, S3C2410_UFCON, ufcon);
338 rx_enabled(port) = 1;
345 /* insert the character into the buffer */
350 if (uerstat & S3C2410_UERSTAT_ANY) {
351 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
354 /* check for break */
355 if (uerstat & S3C2410_UERSTAT_BREAK) {
358 if (uart_handle_break(port))
362 if (uerstat & S3C2410_UERSTAT_FRAME)
363 port->icount.frame++;
364 if (uerstat & S3C2410_UERSTAT_OVERRUN)
365 port->icount.overrun++;
367 uerstat &= port->read_status_mask;
369 if (uerstat & S3C2410_UERSTAT_BREAK)
371 else if (uerstat & S3C2410_UERSTAT_PARITY)
373 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
377 if (uart_handle_sysrq_char(port, ch, regs))
380 if ((uerstat & port->ignore_status_mask) == 0) {
381 tty_insert_flip_char(tty, ch, flag);
384 if ((uerstat & S3C2410_UERSTAT_OVERRUN) &&
385 tty->flip.count < TTY_FLIPBUF_SIZE) {
387 * Overrun is special, since it's reported
388 * immediately, and doesn't affect the current
392 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
398 tty_flip_buffer_push(tty);
404 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
406 struct s3c24xx_uart_port *ourport = id;
407 struct uart_port *port = &ourport->port;
408 struct circ_buf *xmit = &port->info->xmit;
412 wr_regb(port, S3C2410_UTXH, port->x_char);
418 /* if there isnt anything more to transmit, or the uart is now
419 * stopped, disable the uart and exit
422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
423 s3c24xx_serial_stop_tx(port, 0);
427 /* try and drain the buffer... */
429 while (!uart_circ_empty(xmit) && count-- > 0) {
430 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
433 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(port);
441 if (uart_circ_empty(xmit))
442 s3c24xx_serial_stop_tx(port, 0);
448 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
451 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
452 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
454 if (ufcon & S3C2410_UFCON_FIFOMODE) {
455 if ((ufstat & info->tx_fifomask) != 0 ||
456 (ufstat & info->tx_fifofull))
462 return s3c24xx_serial_txempty_nofifo(port);
465 /* no modem control lines */
466 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
468 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
470 if (umstat & S3C2410_UMSTAT_CTS)
471 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
473 return TIOCM_CAR | TIOCM_DSR;
476 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
478 /* todo - possibly remove AFC and do manual CTS */
481 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
486 spin_lock_irqsave(&port->lock, flags);
488 ucon = rd_regl(port, S3C2410_UCON);
491 ucon |= S3C2410_UCON_SBREAK;
493 ucon &= ~S3C2410_UCON_SBREAK;
495 wr_regl(port, S3C2410_UCON, ucon);
497 spin_unlock_irqrestore(&port->lock, flags);
500 static void s3c24xx_serial_shutdown(struct uart_port *port)
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
504 if (ourport->tx_claimed) {
505 free_irq(TX_IRQ(port), ourport);
506 tx_enabled(port) = 0;
507 ourport->tx_claimed = 0;
510 if (ourport->rx_claimed) {
511 free_irq(RX_IRQ(port), ourport);
512 ourport->rx_claimed = 0;
513 rx_enabled(port) = 0;
518 static int s3c24xx_serial_startup(struct uart_port *port)
520 struct s3c24xx_uart_port *ourport = to_ourport(port);
524 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
525 port->mapbase, port->membase);
527 local_irq_save(flags);
529 rx_enabled(port) = 1;
531 ret = request_irq(RX_IRQ(port),
532 s3c24xx_serial_rx_chars, 0,
533 s3c24xx_serial_portname(port), ourport);
536 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
540 ourport->rx_claimed = 1;
542 dbg("requesting tx irq...\n");
544 tx_enabled(port) = 1;
546 ret = request_irq(TX_IRQ(port),
547 s3c24xx_serial_tx_chars, 0,
548 s3c24xx_serial_portname(port), ourport);
551 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
555 ourport->tx_claimed = 1;
557 dbg("s3c24xx_serial_startup ok\n");
559 /* the port reset code should have done the correct
560 * register setup for the port controls */
562 local_irq_restore(flags);
566 s3c24xx_serial_shutdown(port);
567 local_irq_restore(flags);
571 /* power power management control */
573 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
576 struct s3c24xx_uart_port *ourport = to_ourport(port);
580 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
581 clk_disable(ourport->baudclk);
583 clk_disable(ourport->clk);
587 clk_enable(ourport->clk);
589 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
590 clk_enable(ourport->baudclk);
594 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
598 /* baud rate calculation
600 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
601 * of different sources, including the peripheral clock ("pclk") and an
602 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
603 * with a programmable extra divisor.
605 * The following code goes through the clock sources, and calculates the
606 * baud clocks (and the resultant actual baud rates) and then tries to
607 * pick the closest one and select that.
610 * 1) there is no current code to properly select/deselect FCLK on
611 * the s3c2440, so only specify FCLK or non-FCLK in the clock
612 * sources for the UART
619 static struct s3c24xx_uart_clksrc tmp_clksrc = {
627 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
629 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
631 return (info->get_clksrc)(port, c);
635 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
637 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
639 return (info->set_clksrc)(port, c);
643 struct s3c24xx_uart_clksrc *clksrc;
649 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
650 struct uart_port *port,
651 struct s3c24xx_uart_clksrc *clksrc,
656 calc->src = clk_get(port->dev, clksrc->name);
657 if (calc->src == NULL || IS_ERR(calc->src))
660 rate = clk_get_rate(calc->src);
662 calc->clksrc = clksrc;
663 calc->quot = (rate + (8 * baud)) / (16 * baud);
664 calc->calc = (rate / (calc->quot * 16));
670 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
671 struct s3c24xx_uart_clksrc **clksrc,
675 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
676 struct s3c24xx_uart_clksrc *clkp;
677 struct baud_calc res[MAX_CLKS];
678 struct baud_calc *resptr, *best, *sptr;
684 if (cfg->clocks_size < 2) {
685 if (cfg->clocks_size == 0)
688 s3c24xx_serial_calcbaud(res, port, clkp, baud);
694 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
695 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
700 /* ok, we now need to select the best clock we found */
703 unsigned int deviation = (1<<30)|((1<<30)-1);
706 for (sptr = res; sptr < resptr; sptr++) {
708 "found clk %p (%s) quot %d, calc %d\n",
709 sptr->clksrc, sptr->clksrc->name,
710 sptr->quot, sptr->calc);
712 calc_deviation = baud - sptr->calc;
713 if (calc_deviation < 0)
714 calc_deviation = -calc_deviation;
716 if (calc_deviation < deviation) {
718 deviation = calc_deviation;
722 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
725 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
726 best->clksrc, best->clksrc->name, best->quot, best->calc);
728 /* store results to pass back */
730 *clksrc = best->clksrc;
736 static void s3c24xx_serial_set_termios(struct uart_port *port,
737 struct termios *termios,
740 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
741 struct s3c24xx_uart_port *ourport = to_ourport(port);
742 struct s3c24xx_uart_clksrc *clksrc;
745 unsigned int baud, quot;
750 * We don't support modem control lines.
752 termios->c_cflag &= ~(HUPCL | CMSPAR);
753 termios->c_cflag |= CLOCAL;
756 * Ask the core to calculate the divisor for us.
759 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
761 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
762 quot = port->custom_divisor;
764 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
766 /* check to see if we need to change clock source */
768 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
769 s3c24xx_serial_setsource(port, clksrc);
771 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
772 clk_disable(ourport->baudclk);
773 clk_unuse(ourport->baudclk);
774 ourport->baudclk = NULL;
780 ourport->clksrc = clksrc;
781 ourport->baudclk = clk;
784 switch (termios->c_cflag & CSIZE) {
786 dbg("config: 5bits/char\n");
787 ulcon = S3C2410_LCON_CS5;
790 dbg("config: 6bits/char\n");
791 ulcon = S3C2410_LCON_CS6;
794 dbg("config: 7bits/char\n");
795 ulcon = S3C2410_LCON_CS7;
799 dbg("config: 8bits/char\n");
800 ulcon = S3C2410_LCON_CS8;
804 /* preserve original lcon IR settings */
805 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
807 if (termios->c_cflag & CSTOPB)
808 ulcon |= S3C2410_LCON_STOPB;
810 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
812 if (termios->c_cflag & PARENB) {
813 if (termios->c_cflag & PARODD)
814 ulcon |= S3C2410_LCON_PODD;
816 ulcon |= S3C2410_LCON_PEVEN;
818 ulcon |= S3C2410_LCON_PNONE;
821 spin_lock_irqsave(&port->lock, flags);
823 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
825 wr_regl(port, S3C2410_ULCON, ulcon);
826 wr_regl(port, S3C2410_UBRDIV, quot);
827 wr_regl(port, S3C2410_UMCON, umcon);
829 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
830 rd_regl(port, S3C2410_ULCON),
831 rd_regl(port, S3C2410_UCON),
832 rd_regl(port, S3C2410_UFCON));
835 * Update the per-port timeout.
837 uart_update_timeout(port, termios->c_cflag, baud);
840 * Which character status flags are we interested in?
842 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
843 if (termios->c_iflag & INPCK)
844 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
847 * Which character status flags should we ignore?
849 port->ignore_status_mask = 0;
850 if (termios->c_iflag & IGNPAR)
851 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
852 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
853 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
856 * Ignore all characters if CREAD is not set.
858 if ((termios->c_cflag & CREAD) == 0)
859 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
861 spin_unlock_irqrestore(&port->lock, flags);
864 static const char *s3c24xx_serial_type(struct uart_port *port)
866 switch (port->type) {
876 #define MAP_SIZE (0x100)
878 static void s3c24xx_serial_release_port(struct uart_port *port)
880 release_mem_region(port->mapbase, MAP_SIZE);
883 static int s3c24xx_serial_request_port(struct uart_port *port)
885 char *name = s3c24xx_serial_portname(port);
886 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
889 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
891 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
893 if (flags & UART_CONFIG_TYPE &&
894 s3c24xx_serial_request_port(port) == 0)
895 port->type = info->type;
899 * verify the new serial_struct (for TIOCSSERIAL).
902 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
904 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
906 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
913 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
915 static struct console s3c24xx_serial_console;
917 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
919 #define S3C24XX_SERIAL_CONSOLE NULL
922 static struct uart_ops s3c24xx_serial_ops = {
923 .pm = s3c24xx_serial_pm,
924 .tx_empty = s3c24xx_serial_tx_empty,
925 .get_mctrl = s3c24xx_serial_get_mctrl,
926 .set_mctrl = s3c24xx_serial_set_mctrl,
927 .stop_tx = s3c24xx_serial_stop_tx,
928 .start_tx = s3c24xx_serial_start_tx,
929 .stop_rx = s3c24xx_serial_stop_rx,
930 .enable_ms = s3c24xx_serial_enable_ms,
931 .break_ctl = s3c24xx_serial_break_ctl,
932 .startup = s3c24xx_serial_startup,
933 .shutdown = s3c24xx_serial_shutdown,
934 .set_termios = s3c24xx_serial_set_termios,
935 .type = s3c24xx_serial_type,
936 .release_port = s3c24xx_serial_release_port,
937 .request_port = s3c24xx_serial_request_port,
938 .config_port = s3c24xx_serial_config_port,
939 .verify_port = s3c24xx_serial_verify_port,
943 static struct uart_driver s3c24xx_uart_drv = {
944 .owner = THIS_MODULE,
945 .dev_name = "s3c2410_serial",
947 .cons = S3C24XX_SERIAL_CONSOLE,
948 .driver_name = S3C24XX_SERIAL_NAME,
949 .devfs_name = S3C24XX_SERIAL_DEVFS,
950 .major = S3C24XX_SERIAL_MAJOR,
951 .minor = S3C24XX_SERIAL_MINOR,
954 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
957 .lock = SPIN_LOCK_UNLOCKED,
961 .irq = IRQ_S3CUART_RX0,
964 .ops = &s3c24xx_serial_ops,
965 .flags = UPF_BOOT_AUTOCONF,
971 .lock = SPIN_LOCK_UNLOCKED,
975 .irq = IRQ_S3CUART_RX1,
978 .ops = &s3c24xx_serial_ops,
979 .flags = UPF_BOOT_AUTOCONF,
987 .lock = SPIN_LOCK_UNLOCKED,
991 .irq = IRQ_S3CUART_RX2,
994 .ops = &s3c24xx_serial_ops,
995 .flags = UPF_BOOT_AUTOCONF,
1003 static int s3c24xx_serial_resetport(struct uart_port *port,
1004 struct s3c2410_uartcfg *cfg)
1006 /* ensure registers are setup */
1008 dbg("s3c24xx_serial_resetport: port=%p (%08lx), cfg=%p\n",
1009 port, port->mapbase, cfg);
1011 wr_regl(port, S3C2410_UCON, cfg->ucon);
1012 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1014 /* reset both fifos */
1016 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1017 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1022 /* s3c24xx_serial_init_port
1024 * initialise a single serial port from the platform device given
1027 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1028 struct s3c24xx_uart_info *info,
1029 struct platform_device *platdev)
1031 struct uart_port *port = &ourport->port;
1032 struct s3c2410_uartcfg *cfg;
1033 struct resource *res;
1035 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1037 if (platdev == NULL)
1040 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1042 if (port->mapbase != 0)
1045 if (cfg->hwport > 3)
1048 /* setup info for port */
1049 port->dev = &platdev->dev;
1050 ourport->info = info;
1052 /* copy the info in from provided structure */
1053 ourport->port.fifosize = info->fifosize;
1055 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1059 if (cfg->uart_flags & UPF_CONS_FLOW) {
1060 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1061 port->flags |= UPF_CONS_FLOW;
1064 /* sort our the physical and virtual addresses for each UART */
1066 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1068 printk(KERN_ERR "failed to find memory resource for uart\n");
1072 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1074 port->mapbase = res->start;
1075 port->membase = (void __iomem *)(res->start - S3C2410_PA_UART);
1076 port->membase += S3C2410_VA_UART;
1077 port->irq = platform_get_irq(platdev, 0);
1079 ourport->clk = clk_get(&platdev->dev, "uart");
1081 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1082 clk_use(ourport->clk);
1084 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1085 port->mapbase, port->membase, port->irq, port->uartclk);
1087 /* reset the fifos (and setup the uart) */
1088 s3c24xx_serial_resetport(port, cfg);
1092 /* Device driver serial port probe */
1094 static int probe_index = 0;
1096 int s3c24xx_serial_probe(struct device *_dev,
1097 struct s3c24xx_uart_info *info)
1099 struct s3c24xx_uart_port *ourport;
1100 struct platform_device *dev = to_platform_device(_dev);
1103 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1105 ourport = &s3c24xx_serial_ports[probe_index];
1108 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1110 ret = s3c24xx_serial_init_port(ourport, info, dev);
1114 dbg("%s: adding port\n", __FUNCTION__);
1115 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1116 dev_set_drvdata(_dev, &ourport->port);
1124 int s3c24xx_serial_remove(struct device *_dev)
1126 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1129 uart_remove_one_port(&s3c24xx_uart_drv, port);
1134 /* UART power management code */
1138 int s3c24xx_serial_suspend(struct device *dev, u32 state, u32 level)
1140 struct uart_port *port = s3c24xx_dev_to_port(dev);
1142 if (port && level == SUSPEND_DISABLE)
1143 uart_suspend_port(&s3c24xx_uart_drv, port);
1148 int s3c24xx_serial_resume(struct device *dev, u32 level)
1150 struct uart_port *port = s3c24xx_dev_to_port(dev);
1151 struct s3c24xx_uart_port *ourport = to_ourport(port);
1153 if (port && level == RESUME_ENABLE) {
1154 clk_enable(ourport->clk);
1155 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1156 clk_disable(ourport->clk);
1158 uart_resume_port(&s3c24xx_uart_drv, port);
1165 #define s3c24xx_serial_suspend NULL
1166 #define s3c24xx_serial_resume NULL
1169 int s3c24xx_serial_init(struct device_driver *drv,
1170 struct s3c24xx_uart_info *info)
1172 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1173 return driver_register(drv);
1177 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1181 /* cpu specific variations on the serial port support */
1183 #ifdef CONFIG_CPU_S3C2410
1185 static int s3c2410_serial_setsource(struct uart_port *port,
1186 struct s3c24xx_uart_clksrc *clk)
1188 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1190 if (strcmp(clk->name, "uclk") == 0)
1191 ucon |= S3C2410_UCON_UCLK;
1193 ucon &= ~S3C2410_UCON_UCLK;
1195 wr_regl(port, S3C2410_UCON, ucon);
1199 static int s3c2410_serial_getsource(struct uart_port *port,
1200 struct s3c24xx_uart_clksrc *clk)
1202 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1205 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1210 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1211 .name = "Samsung S3C2410 UART",
1212 .type = PORT_S3C2410,
1214 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1215 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1216 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1217 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1218 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1219 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1220 .get_clksrc = s3c2410_serial_getsource,
1221 .set_clksrc = s3c2410_serial_setsource,
1224 /* device management */
1226 static int s3c2410_serial_probe(struct device *dev)
1228 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1231 static struct device_driver s3c2410_serial_drv = {
1232 .name = "s3c2410-uart",
1233 .bus = &platform_bus_type,
1234 .probe = s3c2410_serial_probe,
1235 .remove = s3c24xx_serial_remove,
1236 .suspend = s3c24xx_serial_suspend,
1237 .resume = s3c24xx_serial_resume,
1240 static inline int s3c2410_serial_init(void)
1242 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1245 static inline void s3c2410_serial_exit(void)
1247 driver_unregister(&s3c2410_serial_drv);
1250 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1253 static inline int s3c2410_serial_init(void)
1258 static inline void s3c2410_serial_exit(void)
1262 #define s3c2410_uart_inf_at NULL
1264 #endif /* CONFIG_CPU_S3C2410 */
1266 #ifdef CONFIG_CPU_S3C2440
1268 static int s3c2440_serial_setsource(struct uart_port *port,
1269 struct s3c24xx_uart_clksrc *clk)
1271 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1273 // todo - proper fclk<>nonfclk switch //
1275 ucon &= ~S3C2440_UCON_CLKMASK;
1277 if (strcmp(clk->name, "uclk") == 0)
1278 ucon |= S3C2440_UCON_UCLK;
1279 else if (strcmp(clk->name, "pclk") == 0)
1280 ucon |= S3C2440_UCON_PCLK;
1281 else if (strcmp(clk->name, "fclk") == 0)
1282 ucon |= S3C2440_UCON_FCLK;
1284 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1288 wr_regl(port, S3C2410_UCON, ucon);
1293 static int s3c2440_serial_getsource(struct uart_port *port,
1294 struct s3c24xx_uart_clksrc *clk)
1296 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1298 switch (ucon & S3C2440_UCON_CLKMASK) {
1299 case S3C2440_UCON_UCLK:
1304 case S3C2440_UCON_PCLK:
1305 case S3C2440_UCON_PCLK2:
1310 case S3C2440_UCON_FCLK:
1311 clk->divisor = 7; /* todo - work out divisor */
1320 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1321 .name = "Samsung S3C2440 UART",
1322 .type = PORT_S3C2440,
1324 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1325 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1326 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1327 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1328 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1329 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1330 .get_clksrc = s3c2440_serial_getsource,
1331 .set_clksrc = s3c2440_serial_setsource
1334 /* device management */
1336 static int s3c2440_serial_probe(struct device *dev)
1338 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1339 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1342 static struct device_driver s3c2440_serial_drv = {
1343 .name = "s3c2440-uart",
1344 .bus = &platform_bus_type,
1345 .probe = s3c2440_serial_probe,
1346 .remove = s3c24xx_serial_remove,
1347 .suspend = s3c24xx_serial_suspend,
1348 .resume = s3c24xx_serial_resume,
1352 static inline int s3c2440_serial_init(void)
1354 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1357 static inline void s3c2440_serial_exit(void)
1359 driver_unregister(&s3c2440_serial_drv);
1362 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1365 static inline int s3c2440_serial_init(void)
1370 static inline void s3c2440_serial_exit(void)
1374 #define s3c2440_uart_inf_at NULL
1375 #endif /* CONFIG_CPU_S3C2440 */
1377 /* module initialisation code */
1379 static int __init s3c24xx_serial_modinit(void)
1383 ret = uart_register_driver(&s3c24xx_uart_drv);
1385 printk(KERN_ERR "failed to register UART driver\n");
1389 s3c2410_serial_init();
1390 s3c2440_serial_init();
1395 static void __exit s3c24xx_serial_modexit(void)
1397 s3c2410_serial_exit();
1398 s3c2440_serial_exit();
1400 uart_unregister_driver(&s3c24xx_uart_drv);
1404 module_init(s3c24xx_serial_modinit);
1405 module_exit(s3c24xx_serial_modexit);
1409 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1411 static struct uart_port *cons_uart;
1414 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1416 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1417 unsigned long ufstat, utrstat;
1419 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1420 /* fifo mode - check ammount of data in fifo registers... */
1422 ufstat = rd_regl(port, S3C2410_UFSTAT);
1423 return (ufstat & info->tx_fifofull) ? 0 : 1;
1426 /* in non-fifo mode, we go and use the tx buffer empty */
1428 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1429 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1433 s3c24xx_serial_console_write(struct console *co, const char *s,
1437 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1439 for (i = 0; i < count; i++) {
1440 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1443 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1446 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1449 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1455 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1456 int *parity, int *bits)
1458 struct s3c24xx_uart_clksrc clksrc;
1462 unsigned int ubrdiv;
1465 ulcon = rd_regl(port, S3C2410_ULCON);
1466 ucon = rd_regl(port, S3C2410_UCON);
1467 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1469 dbg("s3c24xx_serial_get_options: port=%p\n"
1470 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1471 port, ulcon, ucon, ubrdiv);
1473 if ((ucon & 0xf) != 0) {
1474 /* consider the serial port configured if the tx/rx mode set */
1476 switch (ulcon & S3C2410_LCON_CSMASK) {
1477 case S3C2410_LCON_CS5:
1480 case S3C2410_LCON_CS6:
1483 case S3C2410_LCON_CS7:
1487 case S3C2410_LCON_CS8:
1492 switch (ulcon & S3C2410_LCON_PMASK) {
1493 case S3C2410_LCON_PEVEN:
1497 case S3C2410_LCON_PODD:
1501 case S3C2410_LCON_PNONE:
1506 /* now calculate the baud rate */
1508 s3c24xx_serial_getsource(port, &clksrc);
1510 clk = clk_get(port->dev, clksrc.name);
1511 if (!IS_ERR(clk) && clk != NULL)
1512 rate = clk_get_rate(clk);
1517 *baud = rate / ( 16 * (ubrdiv + 1));
1518 dbg("calculated baud %d\n", *baud);
1523 /* s3c24xx_serial_init_ports
1525 * initialise the serial ports from the machine provided initialisation
1529 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1531 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1532 struct platform_device **platdev_ptr;
1535 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1537 platdev_ptr = s3c24xx_uart_devs;
1539 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1540 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1547 s3c24xx_serial_console_setup(struct console *co, char *options)
1549 struct uart_port *port;
1555 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1556 co, co->index, options);
1558 /* is this a valid port */
1560 if (co->index == -1 || co->index >= NR_PORTS)
1563 port = &s3c24xx_serial_ports[co->index].port;
1565 /* is the port configured? */
1567 if (port->mapbase == 0x0) {
1569 port = &s3c24xx_serial_ports[co->index].port;
1574 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1577 * Check whether an invalid uart number has been specified, and
1578 * if so, search for the first available port that does have
1582 uart_parse_options(options, &baud, &parity, &bits, &flow);
1584 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1586 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1588 return uart_set_options(port, co, baud, parity, bits, flow);
1591 /* s3c24xx_serial_initconsole
1593 * initialise the console from one of the uart drivers
1596 static struct console s3c24xx_serial_console =
1598 .name = S3C24XX_SERIAL_NAME,
1599 .device = uart_console_device,
1600 .flags = CON_PRINTBUFFER,
1602 .write = s3c24xx_serial_console_write,
1603 .setup = s3c24xx_serial_console_setup
1607 static int s3c24xx_serial_initconsole(void)
1609 struct s3c24xx_uart_info *info;
1610 struct platform_device *dev = s3c24xx_uart_devs[0];
1612 dbg("s3c24xx_serial_initconsole\n");
1614 /* select driver based on the cpu */
1617 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1621 if (strcmp(dev->name, "s3c2410-uart") == 0) {
1622 info = s3c2410_uart_inf_at;
1623 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1624 info = s3c2440_uart_inf_at;
1626 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1631 printk(KERN_ERR "s3c24xx: no driver for console\n");
1635 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1636 s3c24xx_serial_init_ports(info);
1638 register_console(&s3c24xx_serial_console);
1642 console_initcall(s3c24xx_serial_initconsole);
1644 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1646 MODULE_LICENSE("GPL");
1647 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1648 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");