2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002, 2003 Paul Mundt
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/signal.h>
26 #include <linux/sched.h>
27 #include <linux/timer.h>
28 #include <linux/interrupt.h>
29 #include <linux/tty.h>
30 #include <linux/tty_flip.h>
31 #include <linux/serial.h>
32 #include <linux/major.h>
33 #include <linux/string.h>
34 #include <linux/sysrq.h>
35 #include <linux/fcntl.h>
36 #include <linux/ptrace.h>
37 #include <linux/ioport.h>
39 #include <linux/slab.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
44 #ifdef CONFIG_CPU_FREQ
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
49 #include <asm/system.h>
52 #include <asm/uaccess.h>
53 #include <asm/bitops.h>
55 #include <linux/generic_serial.h>
57 #ifdef CONFIG_SH_STANDARD_BIOS
58 #include <asm/sh_bios.h>
61 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
70 static int kgdb_get_char(struct sci_port *port);
71 static void kgdb_put_char(struct sci_port *port, char c);
72 static void kgdb_handle_error(struct sci_port *port);
73 static struct sci_port *kgdb_sci_port;
74 #endif /* CONFIG_SH_KGDB */
76 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
77 static struct sci_port *serial_console_port = 0;
78 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
80 /* Function prototypes */
81 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop);
82 static void sci_start_tx(struct uart_port *port, unsigned int tty_start);
83 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
84 static void sci_stop_rx(struct uart_port *port);
85 static int sci_request_irq(struct sci_port *port);
86 static void sci_free_irq(struct sci_port *port);
88 static struct sci_port sci_ports[SCI_NPORTS];
89 static struct uart_driver sci_uart_driver;
91 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
93 static void handle_error(struct sci_port *port)
94 { /* Clear error flags */
95 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
98 static int get_char(struct sci_port *port)
101 unsigned short status;
104 local_irq_save(flags);
106 status = sci_in(port, SCxSR);
107 if (status & SCxSR_ERRORS(port)) {
111 } while (!(status & SCxSR_RDxF(port)));
112 c = sci_in(port, SCxRDR);
113 sci_in(port, SCxSR); /* Dummy read */
114 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
115 local_irq_restore(flags);
120 /* Taken from sh-stub.c of GDB 4.18 */
121 static const char hexchars[] = "0123456789abcdef";
123 static __inline__ char highhex(int x)
125 return hexchars[(x >> 4) & 0xf];
128 static __inline__ char lowhex(int x)
130 return hexchars[x & 0xf];
133 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
136 * Send the packet in buffer. The host gets one chance to read it.
137 * This routine does not wait for a positive acknowledge.
140 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
141 static void put_char(struct uart_port *port, char c)
144 unsigned short status;
146 local_irq_save(flags);
149 status = sci_in(port, SCxSR);
150 } while (!(status & SCxSR_TDxE(port)));
152 sci_out(port, SCxTDR, c);
153 sci_in(port, SCxSR); /* Dummy read */
154 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
156 local_irq_restore(flags);
159 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
161 struct uart_port *port = &sci_port->port;
162 const unsigned char *p = buffer;
165 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
169 #ifdef CONFIG_SH_STANDARD_BIOS
170 /* This call only does a trap the first time it is
171 * called, and so is safe to do here unconditionally
173 usegdb |= sh_bios_in_gdb_mode();
175 #ifdef CONFIG_SH_KGDB
176 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
180 /* $<packet info>#<checksum>. */
184 put_char(port, 'O'); /* 'O'utput to console */
187 for (i=0; i<count; i++) { /* Don't use run length encoding */
198 put_char(port, highhex(checksum));
199 put_char(port, lowhex(checksum));
200 } while (get_char(port) != '+');
202 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
203 for (i=0; i<count; i++) {
205 put_char(port, '\r');
206 put_char(port, *p++);
209 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
212 #ifdef CONFIG_SH_KGDB
214 /* Is the SCI ready, ie is there a char waiting? */
215 static int kgdb_is_char_ready(struct sci_port *port)
217 unsigned short status = sci_in(port, SCxSR);
219 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
220 kgdb_handle_error(port);
222 return (status & SCxSR_RDxF(port));
226 static void kgdb_put_char(struct sci_port *port, char c)
228 unsigned short status;
231 status = sci_in(port, SCxSR);
232 while (!(status & SCxSR_TDxE(port)));
234 sci_out(port, SCxTDR, c);
235 sci_in(port, SCxSR); /* Dummy read */
236 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
239 /* Get a char if there is one, else ret -1 */
240 static int kgdb_get_char(struct sci_port *port)
244 if (kgdb_is_char_ready(port) == 0)
247 c = sci_in(port, SCxRDR);
248 sci_in(port, SCxSR); /* Dummy read */
249 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
255 /* Called from kgdbstub.c to get a character, i.e. is blocking */
256 static int kgdb_sci_getchar(void)
260 /* Keep trying to read a character, this could be neater */
261 while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
266 /* Called from kgdbstub.c to put a character, just a wrapper */
267 static void kgdb_sci_putchar(int c)
270 kgdb_put_char(kgdb_sci_port, c);
273 /* Clear any errors on the SCI */
274 static void kgdb_handle_error(struct sci_port *port)
276 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */
279 /* Breakpoint if there's a break sent on the serial port */
280 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
282 struct sci_port *port = ptr;
283 unsigned short status = sci_in(port, SCxSR);
285 if (status & SCxSR_BRK(port)) {
287 /* Break into the debugger if a break is detected */
291 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
295 #endif /* CONFIG_SH_KGDB */
297 #if defined(__H8300S__)
298 enum { sci_disable, sci_enable };
300 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
302 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
303 int ch = (port->mapbase - SMR0) >> 3;
304 unsigned char mask = 1 << (ch+1);
306 if (ctrl == sci_disable) {
314 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
315 #if defined(__H8300H__) || defined(__H8300S__)
316 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
318 int ch = (port->mapbase - SMR0) >> 3;
321 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
322 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
324 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
327 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
333 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
334 #if defined(CONFIG_CPU_SH3)
335 /* For SH7707, SH7709, SH7709A, SH7729 */
336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338 unsigned int fcr_val = 0;
343 /* We need to set SCPCR to enable RTS/CTS */
344 data = ctrl_inw(SCPCR);
345 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
346 ctrl_outw(data&0x0fcf, SCPCR);
349 fcr_val |= SCFCR_MCE;
353 /* We need to set SCPCR to enable RTS/CTS */
354 data = ctrl_inw(SCPCR);
355 /* Clear out SCP7MD1,0, SCP4MD1,0,
356 Set SCP6MD1,0 = {01} (output) */
357 ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
359 data = ctrl_inb(SCPDR);
360 /* Set /RTS2 (bit6) = 0 */
361 ctrl_outb(data&0xbf, SCPDR);
363 sci_out(port, SCFCR, fcr_val);
366 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
368 unsigned int fcr_val = 0;
371 fcr_val |= SCFCR_MCE;
373 sci_out(port, SCFCR, fcr_val);
379 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
381 unsigned int fcr_val = 0;
383 if (cflag & CRTSCTS) {
384 fcr_val |= SCFCR_MCE;
386 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
388 sci_out(port, SCFCR, fcr_val);
392 #endif /* SCIF_ONLY || SCI_AND_SCIF */
394 /* ********************************************************************** *
395 * the interrupt related routines *
396 * ********************************************************************** */
398 static void sci_transmit_chars(struct uart_port *port)
400 struct circ_buf *xmit = &port->info->xmit;
401 unsigned int stopped = uart_tx_stopped(port);
403 unsigned short status;
407 status = sci_in(port, SCxSR);
408 if (!(status & SCxSR_TDxE(port))) {
409 local_irq_save(flags);
410 ctrl = sci_in(port, SCSCR);
411 if (uart_circ_empty(xmit)) {
412 ctrl &= ~SCI_CTRL_FLAGS_TIE;
414 ctrl |= SCI_CTRL_FLAGS_TIE;
416 sci_out(port, SCSCR, ctrl);
417 local_irq_restore(flags);
421 #if !defined(SCI_ONLY)
422 if (port->type == PORT_SCIF) {
423 txroom = 16 - (sci_in(port, SCFDR)>>8);
425 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
428 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
439 } else if (!uart_circ_empty(xmit) && !stopped) {
440 c = xmit->buf[xmit->tail];
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
446 sci_out(port, SCxTDR, c);
449 } while (--count > 0);
451 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
453 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
454 uart_write_wakeup(port);
455 if (uart_circ_empty(xmit)) {
456 sci_stop_tx(port, 0);
458 local_irq_save(flags);
459 ctrl = sci_in(port, SCSCR);
461 #if !defined(SCI_ONLY)
462 if (port->type == PORT_SCIF) {
463 sci_in(port, SCxSR); /* Dummy read */
464 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
468 ctrl |= SCI_CTRL_FLAGS_TIE;
469 sci_out(port, SCSCR, ctrl);
470 local_irq_restore(flags);
474 /* On SH3, SCIF may read end-of-break as a space->mark char */
475 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
477 static inline void sci_receive_chars(struct uart_port *port,
478 struct pt_regs *regs)
480 struct tty_struct *tty = port->info->tty;
481 int i, count, copied = 0;
482 unsigned short status;
484 status = sci_in(port, SCxSR);
485 if (!(status & SCxSR_RDxF(port)))
489 #if !defined(SCI_ONLY)
490 if (port->type == PORT_SCIF) {
491 count = sci_in(port, SCFDR)&0x001f;
493 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
496 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
499 /* Don't copy more bytes than there is room for in the buffer */
500 if (tty->flip.count + count > TTY_FLIPBUF_SIZE)
501 count = TTY_FLIPBUF_SIZE - tty->flip.count;
503 /* If for any reason we can't copy more data, we're done! */
507 if (port->type == PORT_SCI) {
508 char c = sci_in(port, SCxRDR);
509 if(((struct sci_port *)port)->break_flag
510 || uart_handle_sysrq_char(port, c, regs)) {
513 tty->flip.char_buf_ptr[0] = c;
514 tty->flip.flag_buf_ptr[0] = TTY_NORMAL;
517 for (i=0; i<count; i++) {
518 char c = sci_in(port, SCxRDR);
519 status = sci_in(port, SCxSR);
520 #if defined(CONFIG_CPU_SH3)
521 /* Skip "chars" during break */
522 if (((struct sci_port *)port)->break_flag) {
524 (status & SCxSR_FER(port))) {
528 /* Nonzero => end-of-break */
529 pr_debug("scif: debounce<%02x>\n", c);
530 ((struct sci_port *)port)->break_flag = 0;
536 #endif /* CONFIG_CPU_SH3 */
537 if (uart_handle_sysrq_char(port, c, regs)) {
542 /* Store data and status */
543 tty->flip.char_buf_ptr[i] = c;
544 if (status&SCxSR_FER(port)) {
545 tty->flip.flag_buf_ptr[i] = TTY_FRAME;
546 pr_debug("sci: frame error\n");
547 } else if (status&SCxSR_PER(port)) {
548 tty->flip.flag_buf_ptr[i] = TTY_PARITY;
549 pr_debug("sci: parity error\n");
551 tty->flip.flag_buf_ptr[i] = TTY_NORMAL;
556 sci_in(port, SCxSR); /* dummy read */
557 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
559 /* Update the kernel buffer end */
560 tty->flip.count += count;
561 tty->flip.char_buf_ptr += count;
562 tty->flip.flag_buf_ptr += count;
564 port->icount.rx += count;
568 /* Tell the rest of the system the news. New characters! */
569 tty_flip_buffer_push(tty);
571 sci_in(port, SCxSR); /* dummy read */
572 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
576 #define SCI_BREAK_JIFFIES (HZ/20)
577 /* The sci generates interrupts during the break,
578 * 1 per millisecond or so during the break period, for 9600 baud.
579 * So dont bother disabling interrupts.
580 * But dont want more than 1 break event.
581 * Use a kernel timer to periodically poll the rx line until
582 * the break is finished.
584 static void sci_schedule_break_timer(struct sci_port *port)
586 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
587 add_timer(&port->break_timer);
589 /* Ensure that two consecutive samples find the break over. */
590 static void sci_break_timer(unsigned long data)
592 struct sci_port * port = (struct sci_port *)data;
593 if(sci_rxd_in(&port->port) == 0) {
594 port->break_flag = 1;
595 sci_schedule_break_timer(port);
596 } else if(port->break_flag == 1){
598 port->break_flag = 2;
599 sci_schedule_break_timer(port);
600 } else port->break_flag = 0;
603 static inline int sci_handle_errors(struct uart_port *port)
606 unsigned short status = sci_in(port, SCxSR);
607 struct tty_struct *tty = port->info->tty;
609 if (status&SCxSR_ORER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
612 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
613 pr_debug("sci: overrun error\n");
616 if (status&SCxSR_FER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
617 if (sci_rxd_in(port) == 0) {
618 /* Notify of BREAK */
619 struct sci_port * sci_port = (struct sci_port *)port;
620 if(!sci_port->break_flag) {
621 sci_port->break_flag = 1;
622 sci_schedule_break_timer((struct sci_port *)port);
623 /* Do sysrq handling. */
624 if(uart_handle_break(port)) {
627 pr_debug("sci: BREAK detected\n");
629 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
635 *tty->flip.flag_buf_ptr++ = TTY_FRAME;
636 pr_debug("sci: frame error\n");
640 if (status&SCxSR_PER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
643 *tty->flip.flag_buf_ptr++ = TTY_PARITY;
644 pr_debug("sci: parity error\n");
648 tty->flip.count += copied;
649 tty_flip_buffer_push(tty);
655 static inline int sci_handle_breaks(struct uart_port *port)
658 unsigned short status = sci_in(port, SCxSR);
659 struct tty_struct *tty = port->info->tty;
660 struct sci_port *s = &sci_ports[port->line];
662 if (!s->break_flag && status & SCxSR_BRK(port) &&
663 tty->flip.count < TTY_FLIPBUF_SIZE) {
664 #if defined(CONFIG_CPU_SH3)
668 /* Notify of BREAK */
670 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
671 pr_debug("sci: BREAK detected\n");
674 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_ST40STB1) || \
675 defined(CONFIG_CPU_SUBTYPE_SH7760)
676 /* XXX: Handle SCIF overrun error */
677 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
678 sci_out(port, SCLSR, 0);
679 if(tty->flip.count<TTY_FLIPBUF_SIZE) {
681 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
682 pr_debug("sci: overrun error\n");
688 tty->flip.count += copied;
689 tty_flip_buffer_push(tty);
695 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
697 struct uart_port *port = ptr;
699 /* I think sci_receive_chars has to be called irrespective
700 * of whether the I_IXOFF is set, otherwise, how is the interrupt
703 sci_receive_chars(port, regs);
708 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
710 struct uart_port *port = ptr;
712 sci_transmit_chars(port);
717 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
719 struct uart_port *port = ptr;
722 if (port->type == PORT_SCI) {
723 if (sci_handle_errors(port)) {
724 /* discard character in rx buffer */
726 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
729 sci_rx_interrupt(irq, ptr, regs);
732 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
734 /* Kick the transmission */
735 sci_tx_interrupt(irq, ptr, regs);
740 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
742 struct uart_port *port = ptr;
745 sci_handle_breaks(port);
746 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
751 #ifdef CONFIG_CPU_FREQ
753 * Here we define a transistion notifier so that we can update all of our
754 * ports' baud rate when the peripheral clock changes.
756 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
758 struct cpufreq_freqs *freqs = p;
761 if ((phase == CPUFREQ_POSTCHANGE) ||
762 (phase == CPUFREQ_RESUMECHANGE)){
763 for (i = 0; i < SCI_NPORTS; i++) {
764 struct uart_port *port = &sci_ports[i];
767 * Update the uartclk per-port if frequency has
768 * changed, since it will no longer necessarily be
769 * consistent with the old frequency.
771 * Really we want to be able to do something like
772 * uart_change_speed() or something along those lines
773 * here to implicitly reset the per-port baud rate..
775 * Clean this up later..
777 port->uartclk = current_cpu_data.module_clock * 16;
780 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
781 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
787 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
788 #endif /* CONFIG_CPU_FREQ */
790 static int sci_request_irq(struct sci_port *port)
793 irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
794 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
797 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
798 "SCI Transmit Data Empty", "SCI Break" };
800 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
803 if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
805 printk(KERN_ERR "sci: Cannot allocate irq.\n");
813 static void sci_free_irq(struct sci_port *port)
817 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
821 free_irq(port->irqs[i], port);
825 static unsigned int sci_tx_empty(struct uart_port *port)
831 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
833 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
834 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
835 /* If you have signals for DTR and DCD, please implement here. */
838 static unsigned int sci_get_mctrl(struct uart_port *port)
840 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
843 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
846 static void sci_start_tx(struct uart_port *port, unsigned int tty_start)
848 struct sci_port *s = &sci_ports[port->line];
850 disable_irq(s->irqs[SCIx_TXI_IRQ]);
851 sci_transmit_chars(port);
852 enable_irq(s->irqs[SCIx_TXI_IRQ]);
855 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop)
860 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
861 local_irq_save(flags);
862 ctrl = sci_in(port, SCSCR);
863 ctrl &= ~SCI_CTRL_FLAGS_TIE;
864 sci_out(port, SCSCR, ctrl);
865 local_irq_restore(flags);
868 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
873 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
874 local_irq_save(flags);
875 ctrl = sci_in(port, SCSCR);
876 ctrl |= SCI_CTRL_FLAGS_RIE;
877 sci_out(port, SCSCR, ctrl);
878 local_irq_restore(flags);
881 static void sci_stop_rx(struct uart_port *port)
886 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
887 local_irq_save(flags);
888 ctrl = sci_in(port, SCSCR);
889 ctrl &= ~SCI_CTRL_FLAGS_RIE;
890 sci_out(port, SCSCR, ctrl);
891 local_irq_restore(flags);
894 static void sci_enable_ms(struct uart_port *port)
896 /* Nothing here yet .. */
899 static void sci_break_ctl(struct uart_port *port, int break_state)
901 /* Nothing here yet .. */
904 static int sci_startup(struct uart_port *port)
906 struct sci_port *s = &sci_ports[port->line];
908 #if defined(__H8300S__)
909 h8300_sci_enable(port, sci_enable);
913 sci_start_tx(port, 1);
914 sci_start_rx(port, 1);
919 static void sci_shutdown(struct uart_port *port)
921 struct sci_port *s = &sci_ports[port->line];
924 sci_stop_tx(port, 1);
927 #if defined(__H8300S__)
928 h8300_sci_enable(port, sci_disable);
932 static void sci_set_termios(struct uart_port *port, struct termios *termios,
935 struct sci_port *s = &sci_ports[port->line];
936 unsigned int status, baud, smr_val;
940 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
942 spin_lock_irqsave(&port->lock, flags);
945 status = sci_in(port, SCxSR);
946 } while (!(status & SCxSR_TEND(port)));
948 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
950 #if !defined(SCI_ONLY)
951 if (port->type == PORT_SCIF) {
952 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
956 smr_val = sci_in(port, SCSMR) & 3;
957 if ((termios->c_cflag & CSIZE) == CS7)
959 if (termios->c_cflag & PARENB)
961 if (termios->c_cflag & PARODD)
963 if (termios->c_cflag & CSTOPB)
966 uart_update_timeout(port, termios->c_cflag, baud);
968 sci_out(port, SCSMR, smr_val);
971 case 0: t = -1; break;
972 case 2400: t = BPS_2400; break;
973 case 4800: t = BPS_4800; break;
974 case 9600: t = BPS_9600; break;
975 case 19200: t = BPS_19200; break;
976 case 38400: t = BPS_38400; break;
977 case 57600: t = BPS_57600; break;
978 case 115200: t = BPS_115200; break;
979 default: t = BPS_115200; break;
984 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
987 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
989 sci_out(port, SCBRR, t);
990 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
993 s->init_pins(port, termios->c_cflag);
994 sci_out(port, SCSCR, SCSCR_INIT(port));
996 if ((termios->c_cflag & CREAD) != 0)
997 sci_start_rx(port,0);
999 spin_unlock_irqrestore(&port->lock, flags);
1002 static const char *sci_type(struct uart_port *port)
1004 switch (port->type) {
1005 case PORT_SCI: return "sci";
1006 case PORT_SCIF: return "scif";
1007 case PORT_IRDA: return "irda";
1013 static void sci_release_port(struct uart_port *port)
1015 /* Nothing here yet .. */
1018 static int sci_request_port(struct uart_port *port)
1020 /* Nothing here yet .. */
1024 static void sci_config_port(struct uart_port *port, int flags)
1026 struct sci_port *s = &sci_ports[port->line];
1028 port->type = s->type;
1031 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1033 struct sci_port *s = &sci_ports[port->line];
1035 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1037 if (ser->baud_base < 2400)
1038 /* No paper tape reader for Mitch.. */
1044 static struct uart_ops sci_uart_ops = {
1045 .tx_empty = sci_tx_empty,
1046 .set_mctrl = sci_set_mctrl,
1047 .get_mctrl = sci_get_mctrl,
1048 .start_tx = sci_start_tx,
1049 .stop_tx = sci_stop_tx,
1050 .stop_rx = sci_stop_rx,
1051 .enable_ms = sci_enable_ms,
1052 .break_ctl = sci_break_ctl,
1053 .startup = sci_startup,
1054 .shutdown = sci_shutdown,
1055 .set_termios = sci_set_termios,
1057 .release_port = sci_release_port,
1058 .request_port = sci_request_port,
1059 .config_port = sci_config_port,
1060 .verify_port = sci_verify_port,
1063 static struct sci_port sci_ports[SCI_NPORTS] = {
1064 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1067 .membase = (void *)0xfffffe80,
1068 .mapbase = 0xfffffe80,
1069 .iotype = SERIAL_IO_MEM,
1071 .ops = &sci_uart_ops,
1072 .flags = ASYNC_BOOT_AUTOCONF,
1077 .init_pins = sci_init_pins_sci,
1079 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1082 .membase = (void *)0xfffffe80,
1083 .mapbase = 0xfffffe80,
1084 .iotype = SERIAL_IO_MEM,
1086 .ops = &sci_uart_ops,
1087 .flags = ASYNC_BOOT_AUTOCONF,
1092 .init_pins = sci_init_pins_sci,
1096 .membase = (void *)0xa4000150,
1097 .mapbase = 0xa4000150,
1098 .iotype = SERIAL_IO_MEM,
1100 .ops = &sci_uart_ops,
1101 .flags = ASYNC_BOOT_AUTOCONF,
1105 .irqs = SH3_SCIF_IRQS,
1106 .init_pins = sci_init_pins_scif,
1110 .membase = (void *)0xa4000140,
1111 .mapbase = 0xa4000140,
1112 .iotype = SERIAL_IO_MEM,
1114 .ops = &sci_uart_ops,
1115 .flags = ASYNC_BOOT_AUTOCONF,
1119 .irqs = SH3_IRDA_IRQS,
1120 .init_pins = sci_init_pins_irda,
1122 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1125 .membase = (void *)0xffe00000,
1126 .mapbase = 0xffe00000,
1127 .iotype = SERIAL_IO_MEM,
1129 .ops = &sci_uart_ops,
1130 .flags = ASYNC_BOOT_AUTOCONF,
1135 .init_pins = sci_init_pins_sci,
1139 .membase = (void *)0xffe80000,
1140 .mapbase = 0xffe80000,
1141 .iotype = SERIAL_IO_MEM,
1143 .ops = &sci_uart_ops,
1144 .flags = ASYNC_BOOT_AUTOCONF,
1148 .irqs = SH4_SCIF_IRQS,
1149 .init_pins = sci_init_pins_scif,
1151 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1154 .membase = (void *)0xfe600000,
1155 .mapbase = 0xfe600000,
1156 .iotype = SERIAL_IO_MEM,
1158 .ops = &sci_uart_ops,
1159 .flags = ASYNC_BOOT_AUTOCONF,
1163 .irqs = SH7760_SCIF0_IRQS,
1164 .init_pins = sci_init_pins_scif,
1168 .membase = (void *)0xfe610000,
1169 .mapbase = 0xfe610000,
1170 .iotype = SERIAL_IO_MEM,
1172 .ops = &sci_uart_ops,
1173 .flags = ASYNC_BOOT_AUTOCONF,
1177 .irqs = SH7760_SCIF1_IRQS,
1178 .init_pins = sci_init_pins_scif,
1182 .membase = (void *)0xfe620000,
1183 .mapbase = 0xfe620000,
1184 .iotype = SERIAL_IO_MEM,
1186 .ops = &sci_uart_ops,
1187 .flags = ASYNC_BOOT_AUTOCONF,
1191 .irqs = SH7760_SCIF2_IRQS,
1192 .init_pins = sci_init_pins_scif,
1194 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1197 .membase = (void *)0xffe00000,
1198 .mapbase = 0xffe00000,
1199 .iotype = SERIAL_IO_MEM,
1201 .ops = &sci_uart_ops,
1202 .flags = ASYNC_BOOT_AUTOCONF,
1206 .irqs = STB1_SCIF1_IRQS,
1207 .init_pins = sci_init_pins_scif,
1211 .membase = (void *)0xffe80000,
1212 .mapbase = 0xffe80000,
1213 .iotype = SERIAL_IO_MEM,
1215 .ops = &sci_uart_ops,
1216 .flags = ASYNC_BOOT_AUTOCONF,
1220 .irqs = SH4_SCIF_IRQS,
1221 .init_pins = sci_init_pins_scif,
1223 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1226 .membase = (void *)0x00ffffb0,
1227 .mapbase = 0x00ffffb0,
1228 .iotype = SERIAL_IO_MEM,
1230 .ops = &sci_uart_ops,
1231 .flags = ASYNC_BOOT_AUTOCONF,
1235 .irqs = H8300H_SCI_IRQS0,
1236 .init_pins = sci_init_pins_sci,
1240 .membase = (void *)0x00ffffb8,
1241 .mapbase = 0x00ffffb8,
1242 .iotype = SERIAL_IO_MEM,
1244 .ops = &sci_uart_ops,
1245 .flags = ASYNC_BOOT_AUTOCONF,
1249 .irqs = H8300H_SCI_IRQS1,
1250 .init_pins = sci_init_pins_sci,
1254 .membase = (void *)0x00ffffc0,
1255 .mapbase = 0x00ffffc0,
1256 .iotype = SERIAL_IO_MEM,
1258 .ops = &sci_uart_ops,
1259 .flags = ASYNC_BOOT_AUTOCONF,
1263 .irqs = H8300H_SCI_IRQS2,
1264 .init_pins = sci_init_pins_sci,
1266 #elif defined(CONFIG_H8S2678)
1269 .membase = (void *)0x00ffff78,
1270 .mapbase = 0x00ffff78,
1271 .iotype = SERIAL_IO_MEM,
1273 .ops = &sci_uart_ops,
1274 .flags = ASYNC_BOOT_AUTOCONF,
1278 .irqs = H8S_SCI_IRQS0,
1279 .init_pins = sci_init_pins_sci,
1283 .membase = (void *)0x00ffff80,
1284 .mapbase = 0x00ffff80,
1285 .iotype = SERIAL_IO_MEM,
1287 .ops = &sci_uart_ops,
1288 .flags = ASYNC_BOOT_AUTOCONF,
1292 .irqs = H8S_SCI_IRQS1,
1293 .init_pins = sci_init_pins_sci,
1297 .membase = (void *)0x00ffff88,
1298 .mapbase = 0x00ffff88,
1299 .iotype = SERIAL_IO_MEM,
1301 .ops = &sci_uart_ops,
1302 .flags = ASYNC_BOOT_AUTOCONF,
1306 .irqs = H8S_SCI_IRQS2,
1307 .init_pins = sci_init_pins_sci,
1310 #error "CPU subtype not defined"
1314 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1316 * Print a string to the serial port trying not to disturb
1317 * any possible real use of the port...
1319 static void serial_console_write(struct console *co, const char *s,
1322 put_string(serial_console_port, s, count);
1325 static int __init serial_console_setup(struct console *co, char *options)
1327 struct uart_port *port;
1334 if (co->index >= SCI_NPORTS)
1337 serial_console_port = &sci_ports[co->index];
1338 port = &serial_console_port->port;
1339 port->type = serial_console_port->type;
1342 * We need to set the initial uartclk here, since otherwise it will
1343 * only ever be setup at sci_init() time.
1345 #if !defined(__H8300H__) && !defined(__H8300S__)
1346 port->uartclk = current_cpu_data.module_clock * 16;
1348 port->uartclk = CONFIG_CPU_CLOCK;
1350 #if defined(__H8300S__)
1351 h8300_sci_enable(port, sci_enable);
1354 uart_parse_options(options, &baud, &parity, &bits, &flow);
1356 ret = uart_set_options(port, co, baud, parity, bits, flow);
1357 #if defined(__H8300H__) || defined(__H8300S__)
1358 /* disable rx interrupt */
1365 static struct console serial_console = {
1367 .device = uart_console_device,
1368 .write = serial_console_write,
1369 .setup = serial_console_setup,
1370 .flags = CON_PRINTBUFFER,
1372 .data = &sci_uart_driver,
1375 static int __init sci_console_init(void)
1377 #ifdef CONFIG_SH_EARLY_PRINTK
1378 extern void sh_console_unregister(void);
1381 * Now that the real console is available, unregister the one we
1382 * used while first booting.
1384 sh_console_unregister();
1387 register_console(&serial_console);
1392 console_initcall(sci_console_init);
1393 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1395 #ifdef CONFIG_SH_KGDB
1397 * FIXME: Most of this can go away.. at the moment, we rely on
1398 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1399 * most of that can easily be done here instead.
1401 * For the time being, just accept the values that were parsed earlier..
1403 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1404 int *parity, int *bits)
1407 *parity = tolower(kgdb_parity);
1408 *bits = kgdb_bits - '0';
1412 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1413 * care of the early-on initialization for kgdb, regardless of whether we
1414 * actually use kgdb as a console or not.
1416 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1418 int __init kgdb_console_setup(struct console *co, char *options)
1420 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1426 if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
1427 co->index = kgdb_portnum;
1430 uart_parse_options(options, &baud, &parity, &bits, &flow);
1432 kgdb_console_get_options(port, &baud, &parity, &bits);
1434 kgdb_getchar = kgdb_sci_getchar;
1435 kgdb_putchar = kgdb_sci_putchar;
1437 return uart_set_options(port, co, baud, parity, bits, flow);
1439 #endif /* CONFIG_SH_KGDB */
1441 #ifdef CONFIG_SH_KGDB_CONSOLE
1442 static struct console kgdb_console = {
1444 .write = kgdb_console_write,
1445 .setup = kgdb_console_setup,
1446 .flags = CON_PRINTBUFFER | CON_ENABLED,
1448 .data = &sci_uart_driver,
1451 /* Register the KGDB console so we get messages (d'oh!) */
1452 static int __init kgdb_console_init(void)
1454 register_console(&kgdb_console);
1459 console_initcall(kgdb_console_init);
1460 #endif /* CONFIG_SH_KGDB_CONSOLE */
1462 #if defined(CONFIG_SH_KGDB_CONSOLE)
1463 #define SCI_CONSOLE &kgdb_console
1464 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1465 #define SCI_CONSOLE &serial_console
1467 #define SCI_CONSOLE 0
1470 static char banner[] __initdata =
1471 KERN_INFO "SuperH SCI(F) driver initialized\n";
1473 static struct uart_driver sci_uart_driver = {
1474 .owner = THIS_MODULE,
1475 .driver_name = "sci",
1476 #ifdef CONFIG_DEVFS_FS
1477 .devfs_name = "ttsc/",
1479 .dev_name = "ttySC",
1481 .minor = SCI_MINOR_START,
1483 .cons = SCI_CONSOLE,
1486 static int __init sci_init(void)
1490 printk("%s", banner);
1492 ret = uart_register_driver(&sci_uart_driver);
1494 for (chan = 0; chan < SCI_NPORTS; chan++) {
1495 struct sci_port *sciport = &sci_ports[chan];
1497 #if !defined(__H8300H__) && !defined(__H8300S__)
1498 sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1500 sciport->port.uartclk = CONFIG_CPU_CLOCK;
1502 uart_add_one_port(&sci_uart_driver, &sciport->port);
1503 sciport->break_timer.data = (unsigned long)sciport;
1504 sciport->break_timer.function = sci_break_timer;
1505 init_timer(&sciport->break_timer);
1509 #ifdef CONFIG_CPU_FREQ
1510 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1511 printk("sci: CPU frequency notifier registered\n");
1514 #ifdef CONFIG_SH_STANDARD_BIOS
1515 sh_bios_gdb_detach();
1521 static void __exit sci_exit(void)
1525 for (chan = 0; chan < SCI_NPORTS; chan++)
1526 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1528 uart_unregister_driver(&sci_uart_driver);
1531 module_init(sci_init);
1532 module_exit(sci_exit);