1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
40 #include <asm/oplib.h>
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #include <linux/serial_core.h>
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
67 * This assumes you have a 29.4912 MHz clock for your UART.
69 #define SAB_BASE_BAUD ( 29491200 / 16 )
71 static char *sab82532_version[16] = {
72 "V1.0", "V2.0", "V3.2", "V(0x03)",
73 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
74 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
75 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
78 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
79 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
81 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
82 #define SAB82532_XMIT_FIFO_SIZE 32
84 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
86 int timeout = up->tec_timeout;
88 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
92 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
94 int timeout = up->cec_timeout;
96 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
100 static void receive_chars(struct uart_sunsab_port *up,
101 union sab82532_irq_status *stat,
102 struct pt_regs *regs)
104 struct tty_struct *tty = NULL;
105 unsigned char buf[32];
106 int saw_console_brk = 0;
111 if (up->port.info != NULL) /* Unopened serial console */
112 tty = up->port.info->tty;
114 /* Read number of BYTES (Character + Status) available. */
115 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
116 count = SAB82532_RECV_FIFO_SIZE;
120 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
121 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
125 /* Issue a FIFO read command in case we where idle. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
128 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
132 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
136 for (i = 0; i < count; i++)
137 buf[i] = readb(&up->regs->r.rfifo[i]);
139 /* Issue Receive Message Complete command. */
142 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
145 for (i = 0; i < count; i++) {
146 unsigned char ch = buf[i];
149 uart_handle_sysrq_char(&up->port, ch, regs);
153 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
154 tty->flip.work.func((void *)tty);
155 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
156 return; // if TTY_DONT_FLIP is set
159 *tty->flip.char_buf_ptr = ch;
160 *tty->flip.flag_buf_ptr = TTY_NORMAL;
161 up->port.icount.rx++;
163 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
165 SAB82532_ISR0_RFO)) ||
166 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
168 * For statistics only
170 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
171 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
173 up->port.icount.brk++;
174 if (up->port.line == up->port.cons->index)
177 * We do the SysRQ and SAK checking
178 * here because otherwise the break
179 * may get masked by ignore_status_mask
180 * or read_status_mask.
182 if (uart_handle_break(&up->port))
184 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
185 up->port.icount.parity++;
186 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
187 up->port.icount.frame++;
188 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
189 up->port.icount.overrun++;
192 * Mask off conditions which should be ingored.
194 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
195 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
197 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
198 *tty->flip.flag_buf_ptr = TTY_BREAK;
199 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
200 *tty->flip.flag_buf_ptr = TTY_PARITY;
201 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
202 *tty->flip.flag_buf_ptr = TTY_FRAME;
205 if (uart_handle_sysrq_char(&up->port, ch, regs))
208 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
209 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
210 tty->flip.flag_buf_ptr++;
211 tty->flip.char_buf_ptr++;
214 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
215 tty->flip.count < TTY_FLIPBUF_SIZE) {
217 * Overrun is special, since it's reported
218 * immediately, and doesn't affect the current
221 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
222 tty->flip.flag_buf_ptr++;
223 tty->flip.char_buf_ptr++;
229 tty_flip_buffer_push(tty);
235 static void sunsab_stop_tx(struct uart_port *, unsigned int);
237 static void transmit_chars(struct uart_sunsab_port *up,
238 union sab82532_irq_status *stat)
240 struct circ_buf *xmit = &up->port.info->xmit;
243 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
244 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
245 writeb(up->interrupt_mask1, &up->regs->w.imr1);
246 set_bit(SAB82532_ALLS, &up->irqflags);
249 #if 0 /* bde@nwlink.com says this check causes problems */
250 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
254 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
257 set_bit(SAB82532_XPR, &up->irqflags);
259 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
260 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
261 writeb(up->interrupt_mask1, &up->regs->w.imr1);
262 uart_write_wakeup(&up->port);
266 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
267 writeb(up->interrupt_mask1, &up->regs->w.imr1);
268 clear_bit(SAB82532_ALLS, &up->irqflags);
270 /* Stuff 32 bytes into Transmit FIFO. */
271 clear_bit(SAB82532_XPR, &up->irqflags);
272 for (i = 0; i < up->port.fifosize; i++) {
273 writeb(xmit->buf[xmit->tail],
274 &up->regs->w.xfifo[i]);
275 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
276 up->port.icount.tx++;
277 if (uart_circ_empty(xmit))
281 /* Issue a Transmit Frame command. */
283 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
285 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
286 uart_write_wakeup(&up->port);
288 if (uart_circ_empty(xmit))
289 sunsab_stop_tx(&up->port, 0);
292 static void check_status(struct uart_sunsab_port *up,
293 union sab82532_irq_status *stat)
295 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
296 uart_handle_dcd_change(&up->port,
297 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
299 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
300 uart_handle_cts_change(&up->port,
301 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
303 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
304 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
305 up->port.icount.dsr++;
308 wake_up_interruptible(&up->port.info->delta_msr_wait);
311 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
313 struct uart_sunsab_port *up = dev_id;
314 union sab82532_irq_status status;
317 spin_lock_irqsave(&up->port.lock, flags);
320 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
321 status.sreg.isr0 = readb(&up->regs->r.isr0);
322 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
323 status.sreg.isr1 = readb(&up->regs->r.isr1);
326 if (status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
327 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF))
328 receive_chars(up, &status, regs);
329 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
330 (status.sreg.isr1 & SAB82532_ISR1_CSC))
331 check_status(up, &status);
332 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
333 transmit_chars(up, &status);
336 spin_unlock(&up->port.lock);
340 spin_lock(&up->port.lock);
343 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
344 status.sreg.isr0 = readb(&up->regs->r.isr0);
345 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
346 status.sreg.isr1 = readb(&up->regs->r.isr1);
349 if (status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
350 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF))
351 receive_chars(up, &status, regs);
352 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
353 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
354 check_status(up, &status);
355 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
356 transmit_chars(up, &status);
359 spin_unlock_irqrestore(&up->port.lock, flags);
364 /* port->lock is not held. */
365 static unsigned int sunsab_tx_empty(struct uart_port *port)
367 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
370 /* Do not need a lock for a state test like this. */
371 if (test_bit(SAB82532_ALLS, &up->irqflags))
379 /* port->lock held by caller. */
380 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
382 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
384 if (mctrl & TIOCM_RTS) {
385 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS,
387 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
390 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
392 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
395 if (mctrl & TIOCM_DTR) {
396 writeb(readb(&up->regs->rw.pvr) & ~(up->pvr_dtr_bit), &up->regs->rw.pvr);
398 writeb(readb(&up->regs->rw.pvr) | up->pvr_dtr_bit, &up->regs->rw.pvr);
402 /* port->lock is not held. */
403 static unsigned int sunsab_get_mctrl(struct uart_port *port)
405 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
412 spin_lock_irqsave(&up->port.lock, flags);
414 val = readb(&up->regs->r.pvr);
415 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
417 val = readb(&up->regs->r.vstr);
418 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
420 val = readb(&up->regs->r.star);
421 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
423 spin_unlock_irqrestore(&up->port.lock, flags);
428 /* port->lock held by caller. */
429 static void sunsab_stop_tx(struct uart_port *port, unsigned int tty_stop)
431 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
434 writeb(up->interrupt_mask1, &up->regs->w.imr1);
437 /* port->lock held by caller. */
438 static void sunsab_start_tx(struct uart_port *port, unsigned int tty_start)
440 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
441 struct circ_buf *xmit = &up->port.info->xmit;
444 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
445 writeb(up->interrupt_mask1, &up->regs->w.imr1);
447 if (!test_bit(SAB82532_XPR, &up->irqflags))
450 clear_bit(SAB82532_ALLS, &up->irqflags);
451 clear_bit(SAB82532_XPR, &up->irqflags);
453 for (i = 0; i < up->port.fifosize; i++) {
454 writeb(xmit->buf[xmit->tail],
455 &up->regs->w.xfifo[i]);
456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
457 up->port.icount.tx++;
458 if (uart_circ_empty(xmit))
462 /* Issue a Transmit Frame command. */
464 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
467 /* port->lock is not held. */
468 static void sunsab_send_xchar(struct uart_port *port, char ch)
470 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
473 spin_lock_irqsave(&up->port.lock, flags);
476 writeb(ch, &up->regs->w.tic);
478 spin_unlock_irqrestore(&up->port.lock, flags);
481 /* port->lock held by caller. */
482 static void sunsab_stop_rx(struct uart_port *port)
484 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
486 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
487 writeb(up->interrupt_mask1, &up->regs->w.imr0);
490 /* port->lock held by caller. */
491 static void sunsab_enable_ms(struct uart_port *port)
493 /* For now we always receive these interrupts. */
496 /* port->lock is not held. */
497 static void sunsab_break_ctl(struct uart_port *port, int break_state)
499 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
503 spin_lock_irqsave(&up->port.lock, flags);
505 val = readb(&up->regs->rw.dafo);
507 val |= SAB82532_DAFO_XBRK;
509 val &= ~SAB82532_DAFO_XBRK;
510 writeb(val, &up->regs->rw.dafo);
512 spin_unlock_irqrestore(&up->port.lock, flags);
515 /* port->lock is not held. */
516 static int sunsab_startup(struct uart_port *port)
518 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
522 spin_lock_irqsave(&up->port.lock, flags);
525 * Wait for any commands or immediate characters
531 * Clear the FIFO buffers.
533 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
535 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
538 * Clear the interrupt registers.
540 (void) readb(&up->regs->r.isr0);
541 (void) readb(&up->regs->r.isr1);
544 * Now, initialize the UART
546 writeb(0, &up->regs->w.ccr0); /* power-down */
547 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
548 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
549 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
550 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
551 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
552 writeb(0, &up->regs->w.ccr3);
553 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
554 writeb(SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
555 SAB82532_MODE_RAC, &up->regs->w.mode);
556 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
558 tmp = readb(&up->regs->rw.ccr0);
559 tmp |= SAB82532_CCR0_PU; /* power-up */
560 writeb(tmp, &up->regs->rw.ccr0);
563 * Finally, enable interrupts
565 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
567 writeb(up->interrupt_mask0, &up->regs->w.imr0);
568 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
569 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
570 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
572 writeb(up->interrupt_mask1, &up->regs->w.imr1);
573 set_bit(SAB82532_ALLS, &up->irqflags);
574 set_bit(SAB82532_XPR, &up->irqflags);
576 spin_unlock_irqrestore(&up->port.lock, flags);
581 /* port->lock is not held. */
582 static void sunsab_shutdown(struct uart_port *port)
584 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
588 spin_lock_irqsave(&up->port.lock, flags);
590 /* Disable Interrupts */
591 up->interrupt_mask0 = 0xff;
592 writeb(up->interrupt_mask0, &up->regs->w.imr0);
593 up->interrupt_mask1 = 0xff;
594 writeb(up->interrupt_mask1, &up->regs->w.imr1);
596 /* Disable break condition */
597 tmp = readb(&up->regs->rw.dafo);
598 tmp &= ~SAB82532_DAFO_XBRK;
599 writeb(tmp, &up->regs->rw.dafo);
601 /* Disable Receiver */
602 tmp = readb(&up->regs->rw.mode);
603 tmp &= ~SAB82532_MODE_RAC;
604 writeb(tmp, &up->regs->rw.mode);
609 * If the chip is powered down here the system hangs/crashes during
610 * reboot or shutdown. This needs to be investigated further,
611 * similar behaviour occurs in 2.4 when the driver is configured
612 * as a module only. One hint may be that data is sometimes
613 * transmitted at 9600 baud during shutdown (regardless of the
614 * speed the chip was configured for when the port was open).
618 tmp = readb(&up->regs->rw.ccr0);
619 tmp &= ~SAB82532_CCR0_PU;
620 writeb(tmp, &up->regs->rw.ccr0);
623 spin_unlock_irqrestore(&up->port.lock, flags);
627 * This is used to figure out the divisor speeds.
629 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
631 * with 0 <= N < 64 and 0 <= M < 16
634 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
645 * We scale numbers by 10 so that we get better accuracy
646 * without having to use floating point. Here we increment m
647 * until n is within the valid range.
649 n = (SAB_BASE_BAUD * 10) / baud;
657 * We try very hard to avoid speeds with M == 0 since they may
658 * not work correctly for XTAL frequences above 10 MHz.
660 if ((m == 0) && ((n & 1) == 0)) {
668 /* Internal routine, port->lock is held and local interrupts are disabled. */
669 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
670 unsigned int iflag, int baud)
676 /* Byte size and parity */
677 switch (cflag & CSIZE) {
678 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
679 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
680 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
681 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
682 /* Never happens, but GCC is too dumb to figure it out */
683 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
686 if (cflag & CSTOPB) {
687 dafo |= SAB82532_DAFO_STOP;
691 if (cflag & PARENB) {
692 dafo |= SAB82532_DAFO_PARE;
696 if (cflag & PARODD) {
697 dafo |= SAB82532_DAFO_PAR_ODD;
699 dafo |= SAB82532_DAFO_PAR_EVEN;
702 calc_ebrg(baud, &n, &m);
706 up->tec_timeout = (10 * 1000000) / baud;
707 up->cec_timeout = up->tec_timeout >> 2;
709 /* CTS flow control flags */
710 /* We encode read_status_mask and ignore_status_mask like so:
712 * ---------------------
713 * | ... | ISR1 | ISR0 |
714 * ---------------------
718 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
719 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
721 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
723 SAB82532_ISR1_XPR) << 8;
725 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
727 if (iflag & (BRKINT | PARMRK))
728 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
731 * Characteres to ignore
733 up->port.ignore_status_mask = 0;
735 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
737 if (iflag & IGNBRK) {
738 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
740 * If we're ignoring parity and break indicators,
741 * ignore overruns too (for real raw support).
744 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
748 * ignore all characters if CREAD is not set
750 if ((cflag & CREAD) == 0)
751 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
754 /* Now bang the new settings into the chip. */
757 writeb(dafo, &up->regs->w.dafo);
758 writeb(ebrg & 0xff, &up->regs->w.bgr);
759 writeb((readb(&up->regs->rw.ccr2) & ~0xc0) | ((ebrg >> 2) & 0xc0),
762 if (cflag & CRTSCTS) {
763 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_RTS,
765 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
767 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FCTS,
769 up->interrupt_mask1 &= ~SAB82532_IMR1_CSC;
770 writeb(up->interrupt_mask1, &up->regs->w.imr1);
772 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
774 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS,
776 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FCTS,
778 up->interrupt_mask1 |= SAB82532_IMR1_CSC;
779 writeb(up->interrupt_mask1, &up->regs->w.imr1);
781 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RAC, &up->regs->rw.mode);
785 /* port->lock is not held. */
786 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
789 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
791 int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
793 spin_lock_irqsave(&up->port.lock, flags);
794 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud);
795 spin_unlock_irqrestore(&up->port.lock, flags);
798 static const char *sunsab_type(struct uart_port *port)
800 struct uart_sunsab_port *up = (void *)port;
803 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
807 static void sunsab_release_port(struct uart_port *port)
811 static int sunsab_request_port(struct uart_port *port)
816 static void sunsab_config_port(struct uart_port *port, int flags)
820 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
825 static struct uart_ops sunsab_pops = {
826 .tx_empty = sunsab_tx_empty,
827 .set_mctrl = sunsab_set_mctrl,
828 .get_mctrl = sunsab_get_mctrl,
829 .stop_tx = sunsab_stop_tx,
830 .start_tx = sunsab_start_tx,
831 .send_xchar = sunsab_send_xchar,
832 .stop_rx = sunsab_stop_rx,
833 .enable_ms = sunsab_enable_ms,
834 .break_ctl = sunsab_break_ctl,
835 .startup = sunsab_startup,
836 .shutdown = sunsab_shutdown,
837 .set_termios = sunsab_set_termios,
839 .release_port = sunsab_release_port,
840 .request_port = sunsab_request_port,
841 .config_port = sunsab_config_port,
842 .verify_port = sunsab_verify_port,
845 static struct uart_driver sunsab_reg = {
846 .owner = THIS_MODULE,
847 .driver_name = "serial",
848 .devfs_name = "tts/",
853 static struct uart_sunsab_port *sunsab_ports;
854 static int num_channels;
856 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
858 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
862 spin_lock_irqsave(&up->port.lock, flags);
865 writeb(c, &up->regs->w.tic);
867 spin_unlock_irqrestore(&up->port.lock, flags);
870 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
872 struct uart_sunsab_port *up = &sunsab_ports[con->index];
875 for (i = 0; i < n; i++) {
877 sunsab_console_putchar(up, '\r');
878 sunsab_console_putchar(up, *s++);
883 static int sunsab_console_setup(struct console *con, char *options)
885 struct uart_sunsab_port *up = &sunsab_ports[con->index];
889 printk("Console: ttyS%d (SAB82532)\n",
890 (sunsab_reg.minor - 64) + con->index);
892 sunserial_console_termios(con);
894 /* Firmware console speed is limited to 150-->38400 baud so
895 * this hackish cflag thing is OK.
897 switch (con->cflag & CBAUD) {
898 case B150: baud = 150; break;
899 case B300: baud = 300; break;
900 case B600: baud = 600; break;
901 case B1200: baud = 1200; break;
902 case B2400: baud = 2400; break;
903 case B4800: baud = 4800; break;
904 default: case B9600: baud = 9600; break;
905 case B19200: baud = 19200; break;
906 case B38400: baud = 38400; break;
912 spin_lock_init(&up->port.lock);
915 * Initialize the hardware
917 sunsab_startup(&up->port);
919 spin_lock_irqsave(&up->port.lock, flags);
922 * Finally, enable interrupts
924 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
925 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
926 writeb(up->interrupt_mask0, &up->regs->w.imr0);
927 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
928 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
929 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
931 writeb(up->interrupt_mask1, &up->regs->w.imr1);
933 sunsab_convert_to_sab(up, con->cflag, 0, baud);
935 spin_unlock_irqrestore(&up->port.lock, flags);
940 static struct console sunsab_console = {
942 .write = sunsab_console_write,
943 .device = uart_console_device,
944 .setup = sunsab_console_setup,
945 .flags = CON_PRINTBUFFER,
949 #define SUNSAB_CONSOLE (&sunsab_console)
951 static void __init sunsab_console_init(void)
955 if (con_is_present())
958 for (i = 0; i < num_channels; i++) {
959 int this_minor = sunsab_reg.minor + i;
961 if ((this_minor - 64) == (serial_console - 1))
964 if (i == num_channels)
967 sunsab_console.index = i;
968 register_console(&sunsab_console);
971 #define SUNSAB_CONSOLE (NULL)
972 #define sunsab_console_init() do { } while (0)
975 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
977 struct linux_ebus *ebus;
978 struct linux_ebus_device *edev = NULL;
980 for_each_ebus(ebus) {
981 for_each_ebusdev(edev, ebus) {
982 if (!strcmp(edev->prom_name, "se")) {
985 } else if (!strcmp(edev->prom_name, "serial")) {
989 /* On RIO this can be an SE, check it. We could
990 * just check ebus->is_rio, but this is more portable.
992 clen = prom_getproperty(edev->prom_node, "compatible",
993 compat, sizeof(compat));
995 if (strncmp(compat, "sab82532", 8) == 0) {
1005 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1012 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1014 int *instance_p = arg;
1015 struct uart_sunsab_port *up;
1016 unsigned long regs, offset;
1019 /* Note: ports are located in reverse order */
1020 regs = edev->resource[0].start;
1021 offset = sizeof(union sab82532_async_regs);
1022 for (i = 0; i < 2; i++) {
1023 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1025 memset(up, 0, sizeof(*up));
1026 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1027 up->port.irq = edev->irqs[0];
1028 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1029 up->port.mapbase = (unsigned long)up->regs;
1030 up->port.iotype = SERIAL_IO_MEM;
1032 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1034 offset -= sizeof(union sab82532_async_regs);
1040 static int __init probe_for_sabs(void)
1044 /* Find device instances. */
1045 for_each_sab_edev(&sab_count_callback, &this_sab);
1049 /* Allocate tables. */
1050 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1055 num_channels = this_sab * 2;
1058 for_each_sab_edev(&sab_attach_callback, &this_sab);
1062 static void __init sunsab_init_hw(void)
1066 for (i = 0; i < num_channels; i++) {
1067 struct uart_sunsab_port *up = &sunsab_ports[i];
1070 up->port.ops = &sunsab_pops;
1071 up->port.type = PORT_SUNSAB;
1072 up->port.uartclk = SAB_BASE_BAUD;
1074 up->type = readb(&up->regs->r.vstr) & 0x0f;
1075 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1076 writeb(0xff, &up->regs->w.pim);
1077 if (up->port.line == 0) {
1078 up->pvr_dsr_bit = (1 << 0);
1079 up->pvr_dtr_bit = (1 << 1);
1081 up->pvr_dsr_bit = (1 << 3);
1082 up->pvr_dtr_bit = (1 << 2);
1084 writeb((1 << 1) | (1 << 2) | (1 << 4), &up->regs->w.pvr);
1085 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
1086 &up->regs->rw.mode);
1087 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
1088 &up->regs->rw.mode);
1090 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1091 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1093 if (!(up->port.line & 0x01)) {
1094 if (request_irq(up->port.irq, sunsab_interrupt,
1095 SA_SHIRQ, "serial(sab82532)", up)) {
1096 printk("sunsab%d: can't get IRQ %x\n",
1104 static int __init sunsab_init(void)
1106 int ret = probe_for_sabs();
1114 sunsab_reg.minor = sunserial_current_minor;
1115 sunsab_reg.nr = num_channels;
1116 sunsab_reg.cons = SUNSAB_CONSOLE;
1118 ret = uart_register_driver(&sunsab_reg);
1122 for (i = 0; i < num_channels; i++) {
1123 struct uart_sunsab_port *up = &sunsab_ports[i];
1125 if (!(up->port.line & 0x01))
1126 free_irq(up->port.irq, up);
1129 kfree(sunsab_ports);
1130 sunsab_ports = NULL;
1135 sunserial_current_minor += num_channels;
1137 for (i = 0; i < num_channels; i++) {
1138 struct uart_sunsab_port *up = &sunsab_ports[i];
1140 uart_add_one_port(&sunsab_reg, &up->port);
1143 sunsab_console_init();
1148 static void __exit sunsab_exit(void)
1152 for (i = 0; i < num_channels; i++) {
1153 struct uart_sunsab_port *up = &sunsab_ports[i];
1155 uart_remove_one_port(&sunsab_reg, &up->port);
1157 if (!(up->port.line & 0x01))
1158 free_irq(up->port.irq, up);
1162 sunserial_current_minor -= num_channels;
1163 uart_unregister_driver(&sunsab_reg);
1165 kfree(sunsab_ports);
1166 sunsab_ports = NULL;
1169 module_init(sunsab_init);
1170 module_exit(sunsab_exit);
1172 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1173 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1174 MODULE_LICENSE("GPL");