2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 // #define VERBOSE DBG_VERBOSE
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/types.h>
35 #include <linux/version.h>
36 #include <linux/errno.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/init.h>
41 #include <linux/timer.h>
42 #include <linux/list.h>
43 #include <linux/interrupt.h>
44 #include <linux/proc_fs.h>
46 #include <linux/device.h>
47 #include <linux/dma-mapping.h>
49 #include <asm/byteorder.h>
53 #include <asm/system.h>
54 #include <asm/mach-types.h>
55 #include <asm/unaligned.h>
56 #include <asm/hardware.h>
57 #include <asm/arch/pxa-regs.h>
59 #include <linux/usb_ch9.h>
60 #include <linux/usb_gadget.h>
62 #include <asm/arch/udc.h>
66 * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
67 * series processors. The UDC for the IXP 4xx series is very similar.
68 * There are fifteen endpoints, in addition to ep0.
70 * Such controller drivers work with a gadget driver. The gadget driver
71 * returns descriptors, implements configuration and data protocols used
72 * by the host to interact with this device, and allocates endpoints to
73 * the different protocol interfaces. The controller driver virtualizes
74 * usb hardware so that the gadget drivers will be more portable.
76 * This UDC hardware wants to implement a bit too much USB protocol, so
77 * it constrains the sorts of USB configuration change events that work.
78 * The errata for these chips are misleading; some "fixed" bugs from
79 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
82 #define DRIVER_VERSION "14-Dec-2003"
83 #define DRIVER_DESC "PXA 2xx USB Device Controller driver"
86 static const char driver_name [] = "pxa2xx_udc";
88 static const char ep0name [] = "ep0";
92 // #define USE_OUT_DMA
93 // #define DISABLE_TEST_MODE
99 #ifdef CONFIG_ARCH_IXP4XX
102 /* cpu-specific register addresses are compiled in to this code */
103 #ifdef CONFIG_ARCH_PXA
104 #error "Can't configure both IXP and PXA"
109 #include "pxa2xx_udc.h"
112 #ifdef CONFIG_EMBEDDED
113 /* few strings, and little code to use them */
119 static int use_dma = 1;
120 module_param(use_dma, bool, 0);
121 MODULE_PARM_DESC (use_dma, "true to use dma");
123 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
124 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
127 #define DMASTR " (dma support)"
129 #define DMASTR " (dma in)"
133 #define DMASTR " (pio only)"
137 #ifdef CONFIG_USB_PXA2XX_SMALL
138 #define SIZE_STR " (small)"
143 #ifdef DISABLE_TEST_MODE
144 /* (mode == 0) == no undocumented chip tweaks
145 * (mode & 1) == double buffer bulk IN
146 * (mode & 2) == double buffer bulk OUT
147 * ... so mode = 3 (or 7, 15, etc) does it for both
149 static ushort fifo_mode = 0;
150 module_param(fifo_mode, ushort, 0);
151 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
154 /* ---------------------------------------------------------------------------
155 * endpoint related parts of the api to the usb controller hardware,
156 * used by gadget driver; and the inner talker-to-hardware core.
157 * ---------------------------------------------------------------------------
160 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
161 static void nuke (struct pxa2xx_ep *, int status);
163 static void pio_irq_enable(int bEndpointAddress)
165 bEndpointAddress &= 0xf;
166 if (bEndpointAddress < 8)
167 UICR0 &= ~(1 << bEndpointAddress);
169 bEndpointAddress -= 8;
170 UICR1 &= ~(1 << bEndpointAddress);
174 static void pio_irq_disable(int bEndpointAddress)
176 bEndpointAddress &= 0xf;
177 if (bEndpointAddress < 8)
178 UICR0 |= 1 << bEndpointAddress;
180 bEndpointAddress -= 8;
181 UICR1 |= 1 << bEndpointAddress;
185 /* The UDCCR reg contains mask and interrupt status bits,
186 * so using '|=' isn't safe as it may ack an interrupt.
188 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
190 static inline void udc_set_mask_UDCCR(int mask)
192 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
195 static inline void udc_clear_mask_UDCCR(int mask)
197 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
200 static inline void udc_ack_int_UDCCR(int mask)
202 /* udccr contains the bits we dont want to change */
203 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
205 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
209 * endpoint enable/disable
211 * we need to verify the descriptors used to enable endpoints. since pxa2xx
212 * endpoint configurations are fixed, and are pretty much always enabled,
213 * there's not a lot to manage here.
215 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
216 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
217 * for a single interface (with only the default altsetting) and for gadget
218 * drivers that don't halt endpoints (not reset by set_interface). that also
219 * means that if you use ISO, you must violate the USB spec rule that all
220 * iso endpoints must be in non-default altsettings.
222 static int pxa2xx_ep_enable (struct usb_ep *_ep,
223 const struct usb_endpoint_descriptor *desc)
225 struct pxa2xx_ep *ep;
226 struct pxa2xx_udc *dev;
228 ep = container_of (_ep, struct pxa2xx_ep, ep);
229 if (!_ep || !desc || ep->desc || _ep->name == ep0name
230 || desc->bDescriptorType != USB_DT_ENDPOINT
231 || ep->bEndpointAddress != desc->bEndpointAddress
232 || ep->fifo_size < le16_to_cpu
233 (desc->wMaxPacketSize)) {
234 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
238 /* xfer types must match, except that interrupt ~= bulk */
239 if (ep->bmAttributes != desc->bmAttributes
240 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
241 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
242 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
246 /* hardware _could_ do smaller, but driver doesn't */
247 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
248 && le16_to_cpu (desc->wMaxPacketSize)
250 || !desc->wMaxPacketSize) {
251 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
256 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
257 DMSG("%s, bogus device state\n", __FUNCTION__);
264 ep->pio_irqs = ep->dma_irqs = 0;
265 ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
267 /* flush fifo (mostly for OUT buffers) */
268 pxa2xx_ep_fifo_flush (_ep);
270 /* ... reset halt state too, if we could ... */
273 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
274 * bind it to the endpoint. otherwise use PIO.
276 switch (ep->bmAttributes) {
277 case USB_ENDPOINT_XFER_ISOC:
278 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
281 case USB_ENDPOINT_XFER_BULK:
282 if (!use_dma || !ep->reg_drcmr)
284 ep->dma = pxa_request_dma ((char *)_ep->name,
285 (le16_to_cpu (desc->wMaxPacketSize) > 64)
286 ? DMA_PRIO_MEDIUM /* some iso */
288 dma_nodesc_handler, ep);
290 *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
291 DMSG("%s using dma%d\n", _ep->name, ep->dma);
296 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
300 static int pxa2xx_ep_disable (struct usb_ep *_ep)
302 struct pxa2xx_ep *ep;
304 ep = container_of (_ep, struct pxa2xx_ep, ep);
305 if (!_ep || !ep->desc) {
306 DMSG("%s, %s not enabled\n", __FUNCTION__,
307 _ep ? ep->ep.name : NULL);
310 nuke (ep, -ESHUTDOWN);
315 pxa_free_dma (ep->dma);
320 /* flush fifo (mostly for IN buffers) */
321 pxa2xx_ep_fifo_flush (_ep);
326 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
330 /*-------------------------------------------------------------------------*/
332 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
333 * must still pass correctly initialized endpoints, since other controller
334 * drivers may care about how it's currently set up (dma issues etc).
338 * pxa2xx_ep_alloc_request - allocate a request data structure
340 static struct usb_request *
341 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
343 struct pxa2xx_request *req;
345 req = kmalloc (sizeof *req, gfp_flags);
349 memset (req, 0, sizeof *req);
350 INIT_LIST_HEAD (&req->queue);
356 * pxa2xx_ep_free_request - deallocate a request data structure
359 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
361 struct pxa2xx_request *req;
363 req = container_of (_req, struct pxa2xx_request, req);
364 WARN_ON (!list_empty (&req->queue));
369 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
370 * no device-affinity and the heap works perfectly well for i/o buffers.
371 * It wastes much less memory than dma_alloc_coherent() would, and even
372 * prevents cacheline (32 bytes wide) sharing problems.
375 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
376 dma_addr_t *dma, int gfp_flags)
380 retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
382 *dma = virt_to_bus (retval);
387 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
393 /*-------------------------------------------------------------------------*/
396 * done - retire a request; caller blocked irqs
398 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
400 unsigned stopped = ep->stopped;
402 list_del_init(&req->queue);
404 if (likely (req->req.status == -EINPROGRESS))
405 req->req.status = status;
407 status = req->req.status;
409 if (status && status != -ESHUTDOWN)
410 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
411 ep->ep.name, &req->req, status,
412 req->req.actual, req->req.length);
414 /* don't modify queue heads during completion callback */
416 req->req.complete(&ep->ep, &req->req);
417 ep->stopped = stopped;
421 static inline void ep0_idle (struct pxa2xx_udc *dev)
423 dev->ep0state = EP0_IDLE;
428 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
431 unsigned length, count;
433 buf = req->req.buf + req->req.actual;
436 /* how big will this packet be? */
437 length = min(req->req.length - req->req.actual, max);
438 req->req.actual += length;
441 while (likely(count--))
448 * write to an IN endpoint fifo, as many packets as possible.
449 * irqs will use this to write the rest later.
450 * caller guarantees at least one packet buffer is ready (or a zlp).
453 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
457 max = le16_to_cpu(ep->desc->wMaxPacketSize);
460 int is_last, is_short;
462 count = write_packet(ep->reg_uddr, req, max);
464 /* last packet is usually short (or a zlp) */
465 if (unlikely (count != max))
466 is_last = is_short = 1;
468 if (likely(req->req.length != req->req.actual)
473 /* interrupt/iso maxpacket may not fill the fifo */
474 is_short = unlikely (max < ep->fifo_size);
477 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
479 is_last ? "/L" : "", is_short ? "/S" : "",
480 req->req.length - req->req.actual, req);
482 /* let loose that packet. maybe try writing another one,
483 * double buffering might work. TSP, TPC, and TFS
484 * bit values are the same for all normal IN endpoints.
486 *ep->reg_udccs = UDCCS_BI_TPC;
488 *ep->reg_udccs = UDCCS_BI_TSP;
490 /* requests complete when all IN data is in the FIFO */
493 if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
494 pio_irq_disable (ep->bEndpointAddress);
496 /* unaligned data and zlps couldn't use dma */
497 if (unlikely(!list_empty(&ep->queue))) {
498 req = list_entry(ep->queue.next,
499 struct pxa2xx_request, queue);
508 // TODO experiment: how robust can fifo mode tweaking be?
509 // double buffering is off in the default fifo mode, which
510 // prevents TFS from being set here.
512 } while (*ep->reg_udccs & UDCCS_BI_TFS);
516 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
517 * ep0 data stage. these chips want very simple state transitions.
520 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
522 UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
524 dev->req_pending = 0;
525 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
526 __FUNCTION__, tag, UDCCS0, flags);
530 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
535 count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
536 ep->dev->stats.write.bytes += count;
538 /* last packet "must be" short (or a zlp) */
539 is_short = (count != EP0_FIFO_SIZE);
541 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
542 req->req.length - req->req.actual, req);
544 if (unlikely (is_short)) {
545 if (ep->dev->req_pending)
546 ep0start(ep->dev, UDCCS0_IPR, "short IN");
550 count = req->req.length;
554 /* This seems to get rid of lost status irqs in some cases:
555 * host responds quickly, or next request involves config
556 * change automagic, or should have been hidden, or ...
558 * FIXME get rid of all udelays possible...
560 if (count >= EP0_FIFO_SIZE) {
563 if ((UDCCS0 & UDCCS0_OPR) != 0) {
564 /* clear OPR, generate ack */
573 } else if (ep->dev->req_pending)
574 ep0start(ep->dev, 0, "IN");
580 * read_fifo - unload packet(s) from the fifo we use for usb OUT
581 * transfers and put them into the request. caller should have made
582 * sure there's at least one packet ready.
584 * returns true if the request completed because of short packet or the
585 * request buffer having filled (and maybe overran till end-of-packet).
588 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
593 unsigned bufferspace, count, is_short;
595 /* make sure there's a packet in the FIFO.
596 * UDCCS_{BO,IO}_RPC are all the same bit value.
597 * UDCCS_{BO,IO}_RNE are all the same bit value.
599 udccs = *ep->reg_udccs;
600 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
602 buf = req->req.buf + req->req.actual;
604 bufferspace = req->req.length - req->req.actual;
606 /* read all bytes from this packet */
607 if (likely (udccs & UDCCS_BO_RNE)) {
608 count = 1 + (0x0ff & *ep->reg_ubcr);
609 req->req.actual += min (count, bufferspace);
612 is_short = (count < ep->ep.maxpacket);
613 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
614 ep->ep.name, udccs, count,
615 is_short ? "/S" : "",
616 req, req->req.actual, req->req.length);
617 while (likely (count-- != 0)) {
618 u8 byte = (u8) *ep->reg_uddr;
620 if (unlikely (bufferspace == 0)) {
621 /* this happens when the driver's buffer
622 * is smaller than what the host sent.
623 * discard the extra data.
625 if (req->req.status != -EOVERFLOW)
626 DMSG("%s overflow %d\n",
628 req->req.status = -EOVERFLOW;
634 *ep->reg_udccs = UDCCS_BO_RPC;
635 /* RPC/RSP/RNE could now reflect the other packet buffer */
637 /* iso is one request per packet */
638 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
639 if (udccs & UDCCS_IO_ROF)
640 req->req.status = -EHOSTUNREACH;
641 /* more like "is_done" */
646 if (is_short || req->req.actual == req->req.length) {
648 if (list_empty(&ep->queue))
649 pio_irq_disable (ep->bEndpointAddress);
653 /* finished that packet. the next one may be waiting... */
659 * special ep0 version of the above. no UBCR0 or double buffering; status
660 * handshaking is magic. most device protocols don't need control-OUT.
661 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
662 * protocols do use them.
665 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
668 unsigned bufferspace;
670 buf = req->req.buf + req->req.actual;
671 bufferspace = req->req.length - req->req.actual;
673 while (UDCCS0 & UDCCS0_RNE) {
676 if (unlikely (bufferspace == 0)) {
677 /* this happens when the driver's buffer
678 * is smaller than what the host sent.
679 * discard the extra data.
681 if (req->req.status != -EOVERFLOW)
682 DMSG("%s overflow\n", ep->ep.name);
683 req->req.status = -EOVERFLOW;
691 UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
694 if (req->req.actual >= req->req.length)
697 /* finished that packet. the next one may be waiting... */
703 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
706 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
708 u32 dcmd = req->req.length;
709 u32 buf = req->req.dma;
710 u32 fifo = io_v2p ((u32)ep->reg_uddr);
712 /* caller guarantees there's a packet or more remaining
713 * - IN may end with a short packet (TSP set separately),
714 * - OUT is always full length
716 buf += req->req.actual;
717 dcmd -= req->req.actual;
720 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
721 DCSR(ep->dma) = DCSR_NODESC;
723 DSADR(ep->dma) = buf;
724 DTADR(ep->dma) = fifo;
725 if (dcmd > MAX_IN_DMA)
728 ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
729 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
730 | DCMD_FLOWTRG | DCMD_INCSRCADDR;
733 DSADR(ep->dma) = fifo;
734 DTADR(ep->dma) = buf;
735 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
736 dcmd = ep->ep.maxpacket;
737 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
738 | DCMD_FLOWSRC | DCMD_INCTRGADDR;
741 DCMD(ep->dma) = dcmd;
742 DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
744 ? DCSR_STOPIRQEN /* use dma_nodesc_handler() */
745 : 0); /* use handle_ep() */
748 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
750 int is_in = ep->bEndpointAddress & USB_DIR_IN;
753 /* unaligned tx buffers and zlps only work with PIO */
754 if ((req->req.dma & 0x0f) != 0
755 || unlikely((req->req.length - req->req.actual)
757 pio_irq_enable(ep->bEndpointAddress);
758 if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
759 (void) write_fifo(ep, req);
761 start_dma_nodesc(ep, req, USB_DIR_IN);
764 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
765 DMSG("%s short dma read...\n", ep->ep.name);
766 /* we're always set up for pio out */
769 *ep->reg_udccs = UDCCS_BO_DME
770 | (*ep->reg_udccs & UDCCS_BO_FST);
771 start_dma_nodesc(ep, req, USB_DIR_OUT);
776 static void cancel_dma(struct pxa2xx_ep *ep)
778 struct pxa2xx_request *req;
781 if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
785 while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
788 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
789 tmp = DCMD(ep->dma) & DCMD_LENGTH;
790 req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
792 /* the last tx packet may be incomplete, so flush the fifo.
793 * FIXME correct req.actual if we can
795 if (ep->bEndpointAddress & USB_DIR_IN)
796 *ep->reg_udccs = UDCCS_BI_FTF;
799 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
800 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
802 struct pxa2xx_ep *ep = _ep;
803 struct pxa2xx_request *req;
808 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
811 ep->dev->stats.irqs++;
812 HEX_DISPLAY(ep->dev->stats.irqs);
817 if ((tmp & DCSR_STOPSTATE) == 0
818 || (DDADR(ep->dma) & DDADR_STOP) != 0) {
819 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
820 ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
823 DCSR(ep->dma) = 0; /* clear DCSR_STOPSTATE */
825 /* update transfer status */
826 completed = tmp & DCSR_BUSERR;
827 if (ep->bEndpointAddress & USB_DIR_IN)
828 tmp = DSADR(ep->dma);
830 tmp = DTADR(ep->dma);
831 req->req.actual = tmp - req->req.dma;
833 /* FIXME seems we sometimes see partial transfers... */
835 if (unlikely(completed != 0))
836 req->req.status = -EIO;
837 else if (req->req.actual) {
838 /* these registers have zeroes in low bits; they miscount
839 * some (end-of-transfer) short packets: tx 14 as tx 12
842 req->req.actual = min(req->req.actual + 3,
845 tmp = (req->req.length - req->req.actual);
846 completed = (tmp == 0);
847 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
849 /* maybe validate final short packet ... */
850 if ((req->req.actual % ep->ep.maxpacket) != 0)
851 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
853 /* ... or zlp, using pio fallback */
854 else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
856 DMSG("%s zlp terminate ...\n", ep->ep.name);
862 if (likely(completed)) {
865 /* maybe re-activate after completion */
866 if (ep->stopped || list_empty(&ep->queue))
868 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
877 /*-------------------------------------------------------------------------*/
880 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
882 struct pxa2xx_request *req;
883 struct pxa2xx_ep *ep;
884 struct pxa2xx_udc *dev;
887 req = container_of(_req, struct pxa2xx_request, req);
888 if (unlikely (!_req || !_req->complete || !_req->buf
889 || !list_empty(&req->queue))) {
890 DMSG("%s, bad params\n", __FUNCTION__);
894 ep = container_of(_ep, struct pxa2xx_ep, ep);
895 if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
896 DMSG("%s, bad ep\n", __FUNCTION__);
901 if (unlikely (!dev->driver
902 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
903 DMSG("%s, bogus device state\n", __FUNCTION__);
907 /* iso is always one packet per request, that's the only way
908 * we can report per-packet status. that also helps with dma.
910 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
911 && req->req.length > le16_to_cpu
912 (ep->desc->wMaxPacketSize)))
916 // FIXME caller may already have done the dma mapping
918 _req->dma = dma_map_single(dev->dev,
919 _req->buf, _req->length,
920 ((ep->bEndpointAddress & USB_DIR_IN) != 0)
926 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
927 _ep->name, _req, _req->length, _req->buf);
929 local_irq_save(flags);
931 _req->status = -EINPROGRESS;
934 /* kickstart this i/o queue? */
935 if (list_empty(&ep->queue) && !ep->stopped) {
936 if (ep->desc == 0 /* ep0 */) {
937 unsigned length = _req->length;
939 switch (dev->ep0state) {
940 case EP0_IN_DATA_PHASE:
941 dev->stats.write.ops++;
942 if (write_ep0_fifo(ep, req))
946 case EP0_OUT_DATA_PHASE:
947 dev->stats.read.ops++;
949 if (dev->req_config) {
950 DBG(DBG_VERBOSE, "ep0 config ack%s\n",
951 dev->has_cfr ? "" : " raced");
953 UDCCFR = UDCCFR_AREN|UDCCFR_ACM;
955 dev->ep0state = EP0_END_XFER;
958 if (dev->req_pending)
959 ep0start(dev, UDCCS0_IPR, "OUT");
960 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
961 && read_ep0_fifo(ep, req))) {
969 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
970 local_irq_restore (flags);
974 /* either start dma or prime pio pump */
975 } else if (ep->dma >= 0) {
978 /* can the FIFO can satisfy the request immediately? */
979 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
980 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
981 && write_fifo(ep, req)) {
983 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
984 && read_fifo(ep, req)) {
988 if (likely (req && ep->desc) && ep->dma < 0)
989 pio_irq_enable(ep->bEndpointAddress);
992 /* pio or dma irq handler advances the queue. */
993 if (likely (req != 0))
994 list_add_tail(&req->queue, &ep->queue);
995 local_irq_restore(flags);
1002 * nuke - dequeue ALL requests
1004 static void nuke(struct pxa2xx_ep *ep, int status)
1006 struct pxa2xx_request *req;
1008 /* called with irqs blocked */
1010 if (ep->dma >= 0 && !ep->stopped)
1013 while (!list_empty(&ep->queue)) {
1014 req = list_entry(ep->queue.next,
1015 struct pxa2xx_request,
1017 done(ep, req, status);
1020 pio_irq_disable (ep->bEndpointAddress);
1024 /* dequeue JUST ONE request */
1025 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1027 struct pxa2xx_ep *ep;
1028 struct pxa2xx_request *req;
1029 unsigned long flags;
1031 ep = container_of(_ep, struct pxa2xx_ep, ep);
1032 if (!_ep || ep->ep.name == ep0name)
1035 local_irq_save(flags);
1037 /* make sure it's actually queued on this endpoint */
1038 list_for_each_entry (req, &ep->queue, queue) {
1039 if (&req->req == _req)
1042 if (&req->req != _req) {
1043 local_irq_restore(flags);
1048 if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1050 done(ep, req, -ECONNRESET);
1052 if (!list_empty(&ep->queue)) {
1053 req = list_entry(ep->queue.next,
1054 struct pxa2xx_request, queue);
1059 done(ep, req, -ECONNRESET);
1061 local_irq_restore(flags);
1065 /*-------------------------------------------------------------------------*/
1067 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1069 struct pxa2xx_ep *ep;
1070 unsigned long flags;
1072 ep = container_of(_ep, struct pxa2xx_ep, ep);
1074 || (!ep->desc && ep->ep.name != ep0name))
1075 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1076 DMSG("%s, bad ep\n", __FUNCTION__);
1080 /* this path (reset toggle+halt) is needed to implement
1081 * SET_INTERFACE on normal hardware. but it can't be
1082 * done from software on the PXA UDC, and the hardware
1083 * forgets to do it as part of SET_INTERFACE automagic.
1085 DMSG("only host can clear %s halt\n", _ep->name);
1089 local_irq_save(flags);
1091 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1092 && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1093 || !list_empty(&ep->queue))) {
1094 local_irq_restore(flags);
1098 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1099 *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1101 /* ep0 needs special care */
1103 start_watchdog(ep->dev);
1104 ep->dev->req_pending = 0;
1105 ep->dev->ep0state = EP0_STALL;
1108 /* and bulk/intr endpoints like dropping stalls too */
1111 for (i = 0; i < 1000; i += 20) {
1112 if (*ep->reg_udccs & UDCCS_BI_SST)
1117 local_irq_restore(flags);
1119 DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1123 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1125 struct pxa2xx_ep *ep;
1127 ep = container_of(_ep, struct pxa2xx_ep, ep);
1129 DMSG("%s, bad ep\n", __FUNCTION__);
1132 /* pxa can't report unclaimed bytes from IN fifos */
1133 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1135 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1136 || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1139 return (*ep->reg_ubcr & 0xfff) + 1;
1142 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1144 struct pxa2xx_ep *ep;
1146 ep = container_of(_ep, struct pxa2xx_ep, ep);
1147 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1148 DMSG("%s, bad ep\n", __FUNCTION__);
1152 /* toggle and halt bits stay unchanged */
1154 /* for OUT, just read and discard the FIFO contents. */
1155 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1156 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1157 (void) *ep->reg_uddr;
1161 /* most IN status is the same, but ISO can't stall */
1162 *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1163 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1168 static struct usb_ep_ops pxa2xx_ep_ops = {
1169 .enable = pxa2xx_ep_enable,
1170 .disable = pxa2xx_ep_disable,
1172 .alloc_request = pxa2xx_ep_alloc_request,
1173 .free_request = pxa2xx_ep_free_request,
1175 .alloc_buffer = pxa2xx_ep_alloc_buffer,
1176 .free_buffer = pxa2xx_ep_free_buffer,
1178 .queue = pxa2xx_ep_queue,
1179 .dequeue = pxa2xx_ep_dequeue,
1181 .set_halt = pxa2xx_ep_set_halt,
1182 .fifo_status = pxa2xx_ep_fifo_status,
1183 .fifo_flush = pxa2xx_ep_fifo_flush,
1187 /* ---------------------------------------------------------------------------
1188 * device-scoped parts of the api to the usb controller hardware
1189 * ---------------------------------------------------------------------------
1192 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1194 return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1197 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1199 /* host may not have enabled remote wakeup */
1200 if ((UDCCS0 & UDCCS0_DRWF) == 0)
1201 return -EHOSTUNREACH;
1202 udc_set_mask_UDCCR(UDCCR_RSM);
1206 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1207 .get_frame = pxa2xx_udc_get_frame,
1208 .wakeup = pxa2xx_udc_wakeup,
1209 // current versions must always be self-powered
1213 /*-------------------------------------------------------------------------*/
1215 #ifdef UDC_PROC_FILE
1217 static const char proc_node_name [] = "driver/udc";
1220 udc_proc_read(char *page, char **start, off_t off, int count,
1221 int *eof, void *_dev)
1224 struct pxa2xx_udc *dev = _dev;
1226 unsigned size = count;
1227 unsigned long flags;
1234 local_irq_save(flags);
1236 /* basic device status */
1237 t = scnprintf(next, size, DRIVER_DESC "\n"
1238 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1239 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1240 dev->driver ? dev->driver->driver.name : "(none)",
1241 is_usb_connected() ? "full speed" : "disconnected");
1245 /* registers for device and ep0 */
1246 t = scnprintf(next, size,
1247 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1248 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1253 t = scnprintf(next, size,
1254 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1255 (tmp & UDCCR_REM) ? " rem" : "",
1256 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1257 (tmp & UDCCR_SRM) ? " srm" : "",
1258 (tmp & UDCCR_SUSIR) ? " susir" : "",
1259 (tmp & UDCCR_RESIR) ? " resir" : "",
1260 (tmp & UDCCR_RSM) ? " rsm" : "",
1261 (tmp & UDCCR_UDA) ? " uda" : "",
1262 (tmp & UDCCR_UDE) ? " ude" : "");
1267 t = scnprintf(next, size,
1268 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1269 (tmp & UDCCS0_SA) ? " sa" : "",
1270 (tmp & UDCCS0_RNE) ? " rne" : "",
1271 (tmp & UDCCS0_FST) ? " fst" : "",
1272 (tmp & UDCCS0_SST) ? " sst" : "",
1273 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1274 (tmp & UDCCS0_FTF) ? " ftf" : "",
1275 (tmp & UDCCS0_IPR) ? " ipr" : "",
1276 (tmp & UDCCS0_OPR) ? " opr" : "");
1282 t = scnprintf(next, size,
1283 "udccfr %02X =%s%s\n", tmp,
1284 (tmp & UDCCFR_AREN) ? " aren" : "",
1285 (tmp & UDCCFR_ACM) ? " acm" : "");
1290 if (!is_usb_connected() || !dev->driver)
1293 t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1294 dev->stats.write.bytes, dev->stats.write.ops,
1295 dev->stats.read.bytes, dev->stats.read.ops,
1300 /* dump endpoint queues */
1301 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1302 struct pxa2xx_ep *ep = &dev->ep [i];
1303 struct pxa2xx_request *req;
1307 const struct usb_endpoint_descriptor *d;
1312 tmp = *dev->ep [i].reg_udccs;
1313 t = scnprintf(next, size,
1314 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1315 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1316 (ep->dma >= 0) ? "dma" : "pio", tmp,
1317 ep->pio_irqs, ep->dma_irqs);
1318 /* TODO translate all five groups of udccs bits! */
1320 } else /* ep0 should only have one transfer queued */
1321 t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1323 if (t <= 0 || t > size)
1328 if (list_empty(&ep->queue)) {
1329 t = scnprintf(next, size, "\t(nothing queued)\n");
1330 if (t <= 0 || t > size)
1336 list_for_each_entry(req, &ep->queue, queue) {
1338 if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1339 t = scnprintf(next, size,
1340 "\treq %p len %d/%d "
1341 "buf %p (dma%d dcmd %08x)\n",
1342 &req->req, req->req.actual,
1343 req->req.length, req->req.buf,
1344 ep->dma, DCMD(ep->dma)
1345 // low 13 bits == bytes-to-go
1349 t = scnprintf(next, size,
1350 "\treq %p len %d/%d buf %p\n",
1351 &req->req, req->req.actual,
1352 req->req.length, req->req.buf);
1353 if (t <= 0 || t > size)
1361 local_irq_restore(flags);
1363 return count - size;
1366 #define create_proc_files() \
1367 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1368 #define remove_proc_files() \
1369 remove_proc_entry(proc_node_name, NULL)
1371 #else /* !UDC_PROC_FILE */
1372 #define create_proc_files() do {} while (0)
1373 #define remove_proc_files() do {} while (0)
1375 #endif /* UDC_PROC_FILE */
1377 /* "function" sysfs attribute */
1379 show_function (struct device *_dev, char *buf)
1381 struct pxa2xx_udc *dev = dev_get_drvdata (_dev);
1384 || !dev->driver->function
1385 || strlen (dev->driver->function) > PAGE_SIZE)
1387 return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1389 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1391 /*-------------------------------------------------------------------------*/
1394 * udc_disable - disable USB device controller
1396 static void udc_disable(struct pxa2xx_udc *dev)
1398 /* block all irqs */
1399 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1400 UICR0 = UICR1 = 0xff;
1403 /* if hardware supports it, disconnect from usb */
1404 make_usb_disappear();
1406 udc_clear_mask_UDCCR(UDCCR_UDE);
1408 #ifdef CONFIG_ARCH_PXA
1409 /* Disable clock for USB device */
1410 pxa_set_cken(CKEN11_USB, 0);
1414 dev->gadget.speed = USB_SPEED_UNKNOWN;
1420 * udc_reinit - initialize software state
1422 static void udc_reinit(struct pxa2xx_udc *dev)
1426 /* device/ep0 records init */
1427 INIT_LIST_HEAD (&dev->gadget.ep_list);
1428 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1429 dev->ep0state = EP0_IDLE;
1431 /* basic endpoint records init */
1432 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1433 struct pxa2xx_ep *ep = &dev->ep[i];
1436 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1440 INIT_LIST_HEAD (&ep->queue);
1441 ep->pio_irqs = ep->dma_irqs = 0;
1444 /* the rest was statically initialized, and is read-only */
1447 /* until it's enabled, this UDC should be completely invisible
1450 static void udc_enable (struct pxa2xx_udc *dev)
1452 udc_clear_mask_UDCCR(UDCCR_UDE);
1454 #ifdef CONFIG_ARCH_PXA
1455 /* Enable clock for USB device */
1456 pxa_set_cken(CKEN11_USB, 1);
1459 /* try to clear these bits before we enable the udc */
1460 udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1463 dev->gadget.speed = USB_SPEED_UNKNOWN;
1464 dev->stats.irqs = 0;
1467 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1469 * - if RESET is already in progress, ack interrupt
1470 * - unmask reset interrupt
1472 udc_set_mask_UDCCR(UDCCR_UDE);
1473 if (!(UDCCR & UDCCR_UDA))
1474 udc_ack_int_UDCCR(UDCCR_RSTIR);
1476 if (dev->has_cfr /* UDC_RES2 is defined */) {
1477 /* pxa255 (a0+) can avoid a set_config race that could
1478 * prevent gadget drivers from configuring correctly
1480 UDCCFR = UDCCFR_ACM;
1482 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1483 * which could result in missing packets and interrupts.
1484 * supposedly one bit per endpoint, controlling whether it
1485 * double buffers or not; ACM/AREN bits fit into the holes.
1486 * zero bits (like USIR0_IRx) disable double buffering.
1492 #ifdef DISABLE_TEST_MODE
1493 /* "test mode" seems to have become the default in later chip
1494 * revs, preventing double buffering (and invalidating docs).
1495 * this EXPERIMENT enables it for bulk endpoints by tweaking
1496 * undefined/reserved register bits (that other drivers clear).
1497 * Belcarra code comments noted this usage.
1499 if (fifo_mode & 1) { /* IN endpoints */
1500 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1501 UDC_RES2 |= USIR1_IR11;
1503 if (fifo_mode & 2) { /* OUT endpoints */
1504 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1505 UDC_RES2 |= USIR1_IR12;
1509 /* caller must be able to sleep in order to cope
1510 * with startup transients.
1514 /* enable suspend/resume and reset irqs */
1515 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1517 /* enable ep0 irqs */
1518 UICR0 &= ~UICR0_IM0;
1520 /* if hardware supports it, connect to usb and wait for host */
1525 /* when a driver is successfully registered, it will receive
1526 * control requests including set_configuration(), which enables
1527 * non-control requests. then usb traffic follows until a
1528 * disconnect is reported. then a host may connect again, or
1529 * the driver might get unbound.
1531 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1533 struct pxa2xx_udc *dev = the_controller;
1537 || driver->speed != USB_SPEED_FULL
1540 || !driver->disconnect
1548 /* first hook up the driver ... */
1549 dev->driver = driver;
1550 dev->gadget.dev.driver = &driver->driver;
1552 device_add (&dev->gadget.dev);
1553 retval = driver->bind(&dev->gadget);
1555 DMSG("bind to driver %s --> error %d\n",
1556 driver->driver.name, retval);
1557 device_del (&dev->gadget.dev);
1560 dev->gadget.dev.driver = 0;
1563 device_create_file(dev->dev, &dev_attr_function);
1565 /* ... then enable host detection and ep0; and we're ready
1566 * for set_configuration as well as eventual disconnect.
1567 * NOTE: this shouldn't power up until later.
1569 DMSG("registered gadget driver '%s'\n", driver->driver.name);
1574 EXPORT_SYMBOL(usb_gadget_register_driver);
1577 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1581 /* don't disconnect drivers more than once */
1582 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1584 dev->gadget.speed = USB_SPEED_UNKNOWN;
1586 /* prevent new request submissions, kill any outstanding requests */
1587 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1588 struct pxa2xx_ep *ep = &dev->ep[i];
1591 nuke(ep, -ESHUTDOWN);
1593 del_timer_sync(&dev->timer);
1595 /* report disconnect; the driver is already quiesced */
1598 driver->disconnect(&dev->gadget);
1600 /* re-init driver-visible data structures */
1604 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1606 struct pxa2xx_udc *dev = the_controller;
1610 if (!driver || driver != dev->driver)
1613 local_irq_disable();
1615 stop_activity(dev, driver);
1618 driver->unbind(&dev->gadget);
1621 device_del (&dev->gadget.dev);
1622 device_remove_file(dev->dev, &dev_attr_function);
1624 DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1628 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1631 /*-------------------------------------------------------------------------*/
1633 #ifdef CONFIG_ARCH_LUBBOCK
1635 /* Lubbock can report connect or disconnect irqs. Likely more hardware
1636 * could support it as a timer callback.
1638 * FIXME for better power management, keep the hardware powered down
1639 * until a host is powering the link. means scheduling work later
1640 * in some task that can udc_enable().
1643 #define enable_disconnect_irq() \
1644 if (machine_is_lubbock()) { enable_irq(LUBBOCK_USB_DISC_IRQ); }
1645 #define disable_disconnect_irq() \
1646 if (machine_is_lubbock()) { disable_irq(LUBBOCK_USB_DISC_IRQ); }
1649 usb_connection_irq(int irq, void *_dev, struct pt_regs *r)
1651 struct pxa2xx_udc *dev = _dev;
1654 HEX_DISPLAY(dev->stats.irqs);
1656 if (!is_usb_connected()) {
1658 disable_disconnect_irq();
1659 /* report disconnect just once */
1660 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1661 DMSG("disconnect %s\n",
1662 dev->driver ? dev->driver->driver.name : 0);
1663 stop_activity(dev, dev->driver);
1665 // udc_disable (dev);
1667 // maybe "ACTION=disconnect /sbin/hotplug gadget".
1669 } else if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
1672 DMSG("?? connect irq ??\n");
1674 // if there's no driver bound, ignore; else
1675 // udc_enable (dev);
1676 // UDC irqs drive the rest.
1677 // maybe "ACTION=connect /sbin/hotplug gadget".
1684 #ifndef enable_disconnect_irq
1685 #warning USB disconnect() is not yet reported.
1686 #define enable_disconnect_irq() do {} while (0)
1687 #define disable_disconnect_irq() do {} while (0)
1691 /*-------------------------------------------------------------------------*/
1693 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1697 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1698 * fifos, and pending transactions mustn't be continued in any case.
1700 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1701 nuke(&dev->ep[i], -ECONNABORTED);
1704 static void udc_watchdog(unsigned long _dev)
1706 struct pxa2xx_udc *dev = (void *)_dev;
1708 local_irq_disable();
1709 if (dev->ep0state == EP0_STALL
1710 && (UDCCS0 & UDCCS0_FST) == 0
1711 && (UDCCS0 & UDCCS0_SST) == 0) {
1712 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1713 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1714 start_watchdog(dev);
1719 static void handle_ep0 (struct pxa2xx_udc *dev)
1721 u32 udccs0 = UDCCS0;
1722 struct pxa2xx_ep *ep = &dev->ep [0];
1723 struct pxa2xx_request *req;
1725 struct usb_ctrlrequest r;
1730 if (list_empty(&ep->queue))
1733 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1735 /* clear stall status */
1736 if (udccs0 & UDCCS0_SST) {
1738 UDCCS0 = UDCCS0_SST;
1739 del_timer(&dev->timer);
1743 /* previous request unfinished? non-error iff back-to-back ... */
1744 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1746 del_timer(&dev->timer);
1750 switch (dev->ep0state) {
1752 /* late-breaking status? */
1755 /* start control request? */
1756 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1757 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1762 /* read SETUP packet */
1763 for (i = 0; i < 8; i++) {
1764 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1766 DMSG("SETUP %d!\n", i);
1769 u.raw [i] = (u8) UDDR0;
1771 if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1775 le16_to_cpus (&u.r.wValue);
1776 le16_to_cpus (&u.r.wIndex);
1777 le16_to_cpus (&u.r.wLength);
1780 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1781 u.r.bRequestType, u.r.bRequest,
1782 u.r.wValue, u.r.wIndex, u.r.wLength);
1784 /* cope with automagic for some standard requests. */
1785 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1786 == USB_TYPE_STANDARD;
1787 dev->req_config = 0;
1788 dev->req_pending = 1;
1789 switch (u.r.bRequest) {
1790 /* hardware restricts gadget drivers here! */
1791 case USB_REQ_SET_CONFIGURATION:
1792 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1793 /* reflect hardware's automagic
1794 * up to the gadget driver.
1797 dev->req_config = 1;
1798 clear_ep_state(dev);
1799 /* if !has_cfr, there's no synch
1800 * else use AREN (later) not SA|OPR
1801 * USIR0_IR0 acts edge sensitive
1805 /* ... and here, even more ... */
1806 case USB_REQ_SET_INTERFACE:
1807 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1808 /* udc hardware is broken by design:
1809 * - altsetting may only be zero;
1810 * - hw resets all interfaces' eps;
1811 * - ep reset doesn't include halt(?).
1813 DMSG("broken set_interface (%d/%d)\n",
1814 u.r.wIndex, u.r.wValue);
1818 /* hardware was supposed to hide this */
1819 case USB_REQ_SET_ADDRESS:
1820 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1821 ep0start(dev, 0, "address");
1827 if (u.r.bRequestType & USB_DIR_IN)
1828 dev->ep0state = EP0_IN_DATA_PHASE;
1830 dev->ep0state = EP0_OUT_DATA_PHASE;
1832 i = dev->driver->setup(&dev->gadget, &u.r);
1834 /* hardware automagic preventing STALL... */
1835 if (dev->req_config) {
1836 /* hardware sometimes neglects to tell
1837 * tell us about config change events,
1838 * so later ones may fail...
1840 WARN("config change %02x fail %d?\n",
1843 /* TODO experiment: if has_cfr,
1844 * hardware didn't ACK; maybe we
1845 * could actually STALL!
1848 DBG(DBG_VERBOSE, "protocol STALL, "
1849 "%02x err %d\n", UDCCS0, i);
1851 /* the watchdog timer helps deal with cases
1852 * where udc seems to clear FST wrongly, and
1853 * then NAKs instead of STALLing.
1855 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1856 start_watchdog(dev);
1857 dev->ep0state = EP0_STALL;
1860 /* deferred i/o == no response yet */
1861 } else if (dev->req_pending) {
1862 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1863 || dev->req_std || u.r.wLength))
1864 ep0start(dev, 0, "defer");
1866 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1869 /* expect at least one data or status stage irq */
1872 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1873 == (UDCCS0_OPR|UDCCS0_SA))) {
1876 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1877 * still observed on a pxa255 a0.
1879 DBG(DBG_VERBOSE, "e131\n");
1882 /* read SETUP data, but don't trust it too much */
1883 for (i = 0; i < 8; i++)
1884 u.raw [i] = (u8) UDDR0;
1885 if ((u.r.bRequestType & USB_RECIP_MASK)
1888 if (u.word [0] == 0 && u.word [1] == 0)
1892 /* some random early IRQ:
1895 * - OPR got set, without SA (likely status stage)
1897 UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1900 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1901 if (udccs0 & UDCCS0_OPR) {
1902 UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1903 DBG(DBG_VERBOSE, "ep0in premature status\n");
1907 } else /* irq was IPR clearing */ {
1909 /* this IN packet might finish the request */
1910 (void) write_ep0_fifo(ep, req);
1911 } /* else IN token before response was written */
1914 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1915 if (udccs0 & UDCCS0_OPR) {
1917 /* this OUT packet might finish the request */
1918 if (read_ep0_fifo(ep, req))
1920 /* else more OUT packets expected */
1921 } /* else OUT token before read was issued */
1922 } else /* irq was IPR clearing */ {
1923 DBG(DBG_VERBOSE, "ep0out premature status\n");
1932 /* ack control-IN status (maybe in-zlp was skipped)
1933 * also appears after some config change events.
1935 if (udccs0 & UDCCS0_OPR)
1936 UDCCS0 = UDCCS0_OPR;
1940 UDCCS0 = UDCCS0_FST;
1946 static void handle_ep(struct pxa2xx_ep *ep)
1948 struct pxa2xx_request *req;
1949 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1955 if (likely (!list_empty(&ep->queue)))
1956 req = list_entry(ep->queue.next,
1957 struct pxa2xx_request, queue);
1961 // TODO check FST handling
1963 udccs = *ep->reg_udccs;
1964 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1966 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1967 tmp |= UDCCS_BI_SST;
1970 *ep->reg_udccs = tmp;
1971 if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1972 completed = write_fifo(ep, req);
1974 } else { /* irq from RPC (or for ISO, ROF) */
1975 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1976 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1978 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1981 *ep->reg_udccs = tmp;
1983 /* fifos can hold packets, ready for reading... */
1986 // TODO didn't yet debug out-dma. this approach assumes
1987 // the worst about short packets and RPC; it might be better.
1989 if (likely(ep->dma >= 0)) {
1990 if (!(udccs & UDCCS_BO_RSP)) {
1991 *ep->reg_udccs = UDCCS_BO_RPC;
1997 completed = read_fifo(ep, req);
1999 pio_irq_disable (ep->bEndpointAddress);
2002 } while (completed);
2006 * pxa2xx_udc_irq - interrupt handler
2008 * avoid delays in ep0 processing. the control handshaking isn't always
2009 * under software control (pxa250c0 and the pxa255 are better), and delays
2010 * could cause usb protocol errors.
2013 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2015 struct pxa2xx_udc *dev = _dev;
2019 HEX_DISPLAY(dev->stats.irqs);
2025 /* SUSpend Interrupt Request */
2026 if (unlikely(udccr & UDCCR_SUSIR)) {
2027 udc_ack_int_UDCCR(UDCCR_SUSIR);
2029 DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2030 ? "" : "+disconnect");
2032 if (!is_usb_connected())
2033 stop_activity(dev, dev->driver);
2034 else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2036 && dev->driver->suspend)
2037 dev->driver->suspend(&dev->gadget);
2041 /* RESume Interrupt Request */
2042 if (unlikely(udccr & UDCCR_RESIR)) {
2043 udc_ack_int_UDCCR(UDCCR_RESIR);
2045 DBG(DBG_VERBOSE, "USB resume\n");
2047 if (dev->gadget.speed != USB_SPEED_UNKNOWN
2049 && dev->driver->resume
2050 && is_usb_connected())
2051 dev->driver->resume(&dev->gadget);
2054 /* ReSeT Interrupt Request - USB reset */
2055 if (unlikely(udccr & UDCCR_RSTIR)) {
2056 udc_ack_int_UDCCR(UDCCR_RSTIR);
2059 if ((UDCCR & UDCCR_UDA) == 0) {
2060 DBG(DBG_VERBOSE, "USB reset start\n");
2061 if (dev->gadget.speed != USB_SPEED_UNKNOWN)
2062 disable_disconnect_irq();
2064 /* reset driver and endpoints,
2065 * in case that's not yet done
2067 stop_activity (dev, dev->driver);
2070 INFO("USB reset\n");
2071 dev->gadget.speed = USB_SPEED_FULL;
2073 memset(&dev->stats, 0, sizeof dev->stats);
2074 /* driver and endpoints are still reset */
2075 enable_disconnect_irq();
2079 u32 usir0 = USIR0 & ~UICR0;
2080 u32 usir1 = USIR1 & ~UICR1;
2083 if (unlikely (!usir0 && !usir1))
2086 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2088 /* control traffic */
2089 if (usir0 & USIR0_IR0) {
2090 dev->ep[0].pio_irqs++;
2095 /* endpoint data transfers */
2096 for (i = 0; i < 8; i++) {
2099 if (i && (usir0 & tmp)) {
2100 handle_ep(&dev->ep[i]);
2105 handle_ep(&dev->ep[i+8]);
2112 /* we could also ask for 1 msec SOF (SIR) interrupts */
2118 /*-------------------------------------------------------------------------*/
2120 static void nop_release (struct device *dev)
2122 DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2125 /* this uses load-time allocation and initialization (instead of
2126 * doing it at run-time) to save code, eliminate fault paths, and
2127 * be more obviously correct.
2129 static struct pxa2xx_udc memory = {
2131 .ops = &pxa2xx_udc_ops,
2132 .ep0 = &memory.ep[0].ep,
2133 .name = driver_name,
2136 .release = nop_release,
2140 /* control endpoint */
2144 .ops = &pxa2xx_ep_ops,
2145 .maxpacket = EP0_FIFO_SIZE,
2148 .reg_udccs = &UDCCS0,
2152 /* first group of endpoints */
2155 .name = "ep1in-bulk",
2156 .ops = &pxa2xx_ep_ops,
2157 .maxpacket = BULK_FIFO_SIZE,
2160 .fifo_size = BULK_FIFO_SIZE,
2161 .bEndpointAddress = USB_DIR_IN | 1,
2162 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2163 .reg_udccs = &UDCCS1,
2169 .name = "ep2out-bulk",
2170 .ops = &pxa2xx_ep_ops,
2171 .maxpacket = BULK_FIFO_SIZE,
2174 .fifo_size = BULK_FIFO_SIZE,
2175 .bEndpointAddress = 2,
2176 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2177 .reg_udccs = &UDCCS2,
2182 #ifndef CONFIG_USB_PXA2XX_SMALL
2185 .name = "ep3in-iso",
2186 .ops = &pxa2xx_ep_ops,
2187 .maxpacket = ISO_FIFO_SIZE,
2190 .fifo_size = ISO_FIFO_SIZE,
2191 .bEndpointAddress = USB_DIR_IN | 3,
2192 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2193 .reg_udccs = &UDCCS3,
2199 .name = "ep4out-iso",
2200 .ops = &pxa2xx_ep_ops,
2201 .maxpacket = ISO_FIFO_SIZE,
2204 .fifo_size = ISO_FIFO_SIZE,
2205 .bEndpointAddress = 4,
2206 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2207 .reg_udccs = &UDCCS4,
2214 .name = "ep5in-int",
2215 .ops = &pxa2xx_ep_ops,
2216 .maxpacket = INT_FIFO_SIZE,
2219 .fifo_size = INT_FIFO_SIZE,
2220 .bEndpointAddress = USB_DIR_IN | 5,
2221 .bmAttributes = USB_ENDPOINT_XFER_INT,
2222 .reg_udccs = &UDCCS5,
2226 /* second group of endpoints */
2229 .name = "ep6in-bulk",
2230 .ops = &pxa2xx_ep_ops,
2231 .maxpacket = BULK_FIFO_SIZE,
2234 .fifo_size = BULK_FIFO_SIZE,
2235 .bEndpointAddress = USB_DIR_IN | 6,
2236 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2237 .reg_udccs = &UDCCS6,
2243 .name = "ep7out-bulk",
2244 .ops = &pxa2xx_ep_ops,
2245 .maxpacket = BULK_FIFO_SIZE,
2248 .fifo_size = BULK_FIFO_SIZE,
2249 .bEndpointAddress = 7,
2250 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2251 .reg_udccs = &UDCCS7,
2258 .name = "ep8in-iso",
2259 .ops = &pxa2xx_ep_ops,
2260 .maxpacket = ISO_FIFO_SIZE,
2263 .fifo_size = ISO_FIFO_SIZE,
2264 .bEndpointAddress = USB_DIR_IN | 8,
2265 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2266 .reg_udccs = &UDCCS8,
2272 .name = "ep9out-iso",
2273 .ops = &pxa2xx_ep_ops,
2274 .maxpacket = ISO_FIFO_SIZE,
2277 .fifo_size = ISO_FIFO_SIZE,
2278 .bEndpointAddress = 9,
2279 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2280 .reg_udccs = &UDCCS9,
2287 .name = "ep10in-int",
2288 .ops = &pxa2xx_ep_ops,
2289 .maxpacket = INT_FIFO_SIZE,
2292 .fifo_size = INT_FIFO_SIZE,
2293 .bEndpointAddress = USB_DIR_IN | 10,
2294 .bmAttributes = USB_ENDPOINT_XFER_INT,
2295 .reg_udccs = &UDCCS10,
2296 .reg_uddr = &UDDR10,
2299 /* third group of endpoints */
2302 .name = "ep11in-bulk",
2303 .ops = &pxa2xx_ep_ops,
2304 .maxpacket = BULK_FIFO_SIZE,
2307 .fifo_size = BULK_FIFO_SIZE,
2308 .bEndpointAddress = USB_DIR_IN | 11,
2309 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2310 .reg_udccs = &UDCCS11,
2311 .reg_uddr = &UDDR11,
2316 .name = "ep12out-bulk",
2317 .ops = &pxa2xx_ep_ops,
2318 .maxpacket = BULK_FIFO_SIZE,
2321 .fifo_size = BULK_FIFO_SIZE,
2322 .bEndpointAddress = 12,
2323 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2324 .reg_udccs = &UDCCS12,
2325 .reg_ubcr = &UBCR12,
2326 .reg_uddr = &UDDR12,
2331 .name = "ep13in-iso",
2332 .ops = &pxa2xx_ep_ops,
2333 .maxpacket = ISO_FIFO_SIZE,
2336 .fifo_size = ISO_FIFO_SIZE,
2337 .bEndpointAddress = USB_DIR_IN | 13,
2338 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2339 .reg_udccs = &UDCCS13,
2340 .reg_uddr = &UDDR13,
2345 .name = "ep14out-iso",
2346 .ops = &pxa2xx_ep_ops,
2347 .maxpacket = ISO_FIFO_SIZE,
2350 .fifo_size = ISO_FIFO_SIZE,
2351 .bEndpointAddress = 14,
2352 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2353 .reg_udccs = &UDCCS14,
2354 .reg_ubcr = &UBCR14,
2355 .reg_uddr = &UDDR14,
2360 .name = "ep15in-int",
2361 .ops = &pxa2xx_ep_ops,
2362 .maxpacket = INT_FIFO_SIZE,
2365 .fifo_size = INT_FIFO_SIZE,
2366 .bEndpointAddress = USB_DIR_IN | 15,
2367 .bmAttributes = USB_ENDPOINT_XFER_INT,
2368 .reg_udccs = &UDCCS15,
2369 .reg_uddr = &UDDR15,
2371 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2374 #define CP15R0_VENDOR_MASK 0xffffe000
2376 #if defined(CONFIG_ARCH_PXA)
2377 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2379 #elif defined(CONFIG_ARCH_IXP4XX)
2380 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2384 #define CP15R0_PROD_MASK 0x000003f0
2385 #define PXA25x 0x00000100 /* and PXA26x */
2386 #define PXA210 0x00000120
2388 #define CP15R0_REV_MASK 0x0000000f
2390 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2392 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2393 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2394 #define PXA250_B2 0x00000104
2395 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2396 #define PXA250_B0 0x00000102
2397 #define PXA250_A1 0x00000101
2398 #define PXA250_A0 0x00000100
2400 #define PXA210_C0 0x00000125
2401 #define PXA210_B2 0x00000124
2402 #define PXA210_B1 0x00000123
2403 #define PXA210_B0 0x00000122
2404 #define IXP425_A0 0x000001c1
2407 * probe - binds to the platform device
2409 static int __init pxa2xx_udc_probe(struct device *_dev)
2411 struct pxa2xx_udc *dev = &memory;
2412 int retval, out_dma = 1;
2415 /* insist on Intel/ARM/XScale */
2416 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2417 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2418 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2422 /* trigger chiprev-specific logic */
2423 switch (chiprev & CP15R0_PRODREV_MASK) {
2424 #if defined(CONFIG_ARCH_PXA)
2430 /* A0/A1 "not released"; ep 13, 15 unusable */
2432 case PXA250_B2: case PXA210_B2:
2433 case PXA250_B1: case PXA210_B1:
2434 case PXA250_B0: case PXA210_B0:
2437 case PXA250_C0: case PXA210_C0:
2439 #elif defined(CONFIG_ARCH_IXP4XX)
2446 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2447 driver_name, chiprev);
2448 /* iop3xx, ixp4xx, ... */
2452 pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2453 dev->has_cfr ? "" : " (!cfr)",
2454 out_dma ? "" : " (broken dma-out)",
2462 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2464 DMSG("disabled OUT dma\n");
2465 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2466 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2467 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2471 /* other non-static parts of init */
2473 dev->mach = _dev->platform_data;
2475 init_timer(&dev->timer);
2476 dev->timer.function = udc_watchdog;
2477 dev->timer.data = (unsigned long) dev;
2479 device_initialize(&dev->gadget.dev);
2480 dev->gadget.dev.parent = _dev;
2481 dev->gadget.dev.dma_mask = _dev->dma_mask;
2483 the_controller = dev;
2484 dev_set_drvdata(_dev, dev);
2489 /* irq setup after old hardware state is cleaned up */
2490 retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2491 SA_INTERRUPT, driver_name, dev);
2493 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2494 driver_name, IRQ_USB, retval);
2499 #ifdef CONFIG_ARCH_LUBBOCK
2500 if (machine_is_lubbock()) {
2501 disable_irq(LUBBOCK_USB_DISC_IRQ);
2502 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2504 SA_INTERRUPT /* OOPSING | SA_SAMPLE_RANDOM */,
2507 enable_irq(LUBBOCK_USB_DISC_IRQ);
2508 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2509 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2515 create_proc_files();
2519 static int __exit pxa2xx_udc_remove(struct device *_dev)
2521 struct pxa2xx_udc *dev = _dev->driver_data;
2524 remove_proc_files();
2525 usb_gadget_unregister_driver(dev->driver);
2528 free_irq(IRQ_USB, dev);
2531 if (machine_is_lubbock() && dev->got_disc) {
2532 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2535 dev_set_drvdata(_dev, 0);
2540 /*-------------------------------------------------------------------------*/
2542 static struct device_driver udc_driver = {
2543 .name = "pxa2xx-udc",
2544 .bus = &platform_bus_type,
2545 .probe = pxa2xx_udc_probe,
2546 .remove = __exit_p(pxa2xx_udc_remove),
2548 // FIXME power management support
2549 // .suspend = ... disable UDC
2550 // .resume = ... re-enable UDC
2553 static int __init udc_init(void)
2555 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2556 return driver_register(&udc_driver);
2558 module_init(udc_init);
2560 static void __exit udc_exit(void)
2562 driver_unregister(&udc_driver);
2564 module_exit(udc_exit);
2566 MODULE_DESCRIPTION(DRIVER_DESC);
2567 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2568 MODULE_LICENSE("GPL");