2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 // #define VERBOSE DBG_VERBOSE
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/types.h>
35 #include <linux/version.h>
36 #include <linux/errno.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/init.h>
41 #include <linux/timer.h>
42 #include <linux/list.h>
43 #include <linux/interrupt.h>
44 #include <linux/proc_fs.h>
46 #include <linux/device.h>
47 #include <linux/dma-mapping.h>
49 #include <asm/byteorder.h>
53 #include <asm/system.h>
54 #include <asm/unaligned.h>
55 #include <asm/hardware.h>
57 #include <linux/usb_ch9.h>
58 #include <linux/usb_gadget.h>
60 #include <asm/arch/udc.h>
64 * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
65 * series processors. The UDC for the IXP 4xx series is very similar.
66 * There are fifteen endpoints, in addition to ep0.
68 * Such controller drivers work with a gadget driver. The gadget driver
69 * returns descriptors, implements configuration and data protocols used
70 * by the host to interact with this device, and allocates endpoints to
71 * the different protocol interfaces. The controller driver virtualizes
72 * usb hardware so that the gadget drivers will be more portable.
74 * This UDC hardware wants to implement a bit too much USB protocol, so
75 * it constrains the sorts of USB configuration change events that work.
76 * The errata for these chips are misleading; some "fixed" bugs from
77 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
80 #define DRIVER_VERSION "14-Dec-2003"
81 #define DRIVER_DESC "PXA 2xx USB Device Controller driver"
84 static const char driver_name [] = "pxa2xx_udc";
86 static const char ep0name [] = "ep0";
90 // #define USE_OUT_DMA
91 // #define DISABLE_TEST_MODE
97 #ifdef CONFIG_ARCH_IXP4XX
100 /* cpu-specific register addresses are compiled in to this code */
101 #ifdef CONFIG_ARCH_PXA
102 #error "Can't configure both IXP and PXA"
107 #include "pxa2xx_udc.h"
110 #ifdef CONFIG_EMBEDDED
111 /* few strings, and little code to use them */
117 static int use_dma = 1;
118 MODULE_PARM (use_dma, "i");
119 MODULE_PARM_DESC (use_dma, "true to use dma");
121 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
122 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
125 #define DMASTR " (dma support)"
127 #define DMASTR " (dma in)"
131 #define DMASTR " (pio only)"
135 #ifdef CONFIG_USB_PXA2XX_SMALL
136 #define SIZE_STR " (small)"
141 #ifdef DISABLE_TEST_MODE
142 /* (mode == 0) == no undocumented chip tweaks
143 * (mode & 1) == double buffer bulk IN
144 * (mode & 2) == double buffer bulk OUT
145 * ... so mode = 3 (or 7, 15, etc) does it for both
147 static ushort fifo_mode = 0;
148 MODULE_PARM (fifo_mode, "h");
149 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
152 /* ---------------------------------------------------------------------------
153 * endpoint related parts of the api to the usb controller hardware,
154 * used by gadget driver; and the inner talker-to-hardware core.
155 * ---------------------------------------------------------------------------
158 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
159 static void nuke (struct pxa2xx_ep *, int status);
161 static void pio_irq_enable(int bEndpointAddress)
163 bEndpointAddress &= 0xf;
164 if (bEndpointAddress < 8)
165 UICR0 &= ~(1 << bEndpointAddress);
167 bEndpointAddress -= 8;
168 UICR1 &= ~(1 << bEndpointAddress);
172 static void pio_irq_disable(int bEndpointAddress)
174 bEndpointAddress &= 0xf;
175 if (bEndpointAddress < 8)
176 UICR0 |= 1 << bEndpointAddress;
178 bEndpointAddress -= 8;
179 UICR1 |= 1 << bEndpointAddress;
183 /* The UDCCR reg contains mask and interrupt status bits,
184 * so using '|=' isn't safe as it may ack an interrupt.
186 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
188 static inline void udc_set_mask_UDCCR(int mask)
190 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
193 static inline void udc_clear_mask_UDCCR(int mask)
195 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
198 static inline void udc_ack_int_UDCCR(int mask)
200 /* udccr contains the bits we dont want to change */
201 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
203 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
207 * endpoint enable/disable
209 * we need to verify the descriptors used to enable endpoints. since pxa2xx
210 * endpoint configurations are fixed, and are pretty much always enabled,
211 * there's not a lot to manage here.
213 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
214 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
215 * for a single interface (with only the default altsetting) and for gadget
216 * drivers that don't halt endpoints (not reset by set_interface). that also
217 * means that if you use ISO, you must violate the USB spec rule that all
218 * iso endpoints must be in non-default altsettings.
220 static int pxa2xx_ep_enable (struct usb_ep *_ep,
221 const struct usb_endpoint_descriptor *desc)
223 struct pxa2xx_ep *ep;
224 struct pxa2xx_udc *dev;
226 ep = container_of (_ep, struct pxa2xx_ep, ep);
227 if (!_ep || !desc || ep->desc || _ep->name == ep0name
228 || desc->bDescriptorType != USB_DT_ENDPOINT
229 || ep->bEndpointAddress != desc->bEndpointAddress
230 || ep->fifo_size < le16_to_cpu
231 (desc->wMaxPacketSize)) {
232 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
236 /* xfer types must match, except that interrupt ~= bulk */
237 if (ep->bmAttributes != desc->bmAttributes
238 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
239 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
240 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
244 /* hardware _could_ do smaller, but driver doesn't */
245 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
246 && le16_to_cpu (desc->wMaxPacketSize)
248 || !desc->wMaxPacketSize) {
249 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
254 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
255 DMSG("%s, bogus device state\n", __FUNCTION__);
262 ep->pio_irqs = ep->dma_irqs = 0;
263 ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
265 /* flush fifo (mostly for OUT buffers) */
266 pxa2xx_ep_fifo_flush (_ep);
268 /* ... reset halt state too, if we could ... */
271 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
272 * bind it to the endpoint. otherwise use PIO.
274 switch (ep->bmAttributes) {
275 case USB_ENDPOINT_XFER_ISOC:
276 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
279 case USB_ENDPOINT_XFER_BULK:
280 if (!use_dma || !ep->reg_drcmr)
282 ep->dma = pxa_request_dma ((char *)_ep->name,
283 (le16_to_cpu (desc->wMaxPacketSize) > 64)
284 ? DMA_PRIO_MEDIUM /* some iso */
286 dma_nodesc_handler, ep);
288 *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
289 DMSG("%s using dma%d\n", _ep->name, ep->dma);
294 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
298 static int pxa2xx_ep_disable (struct usb_ep *_ep)
300 struct pxa2xx_ep *ep;
302 ep = container_of (_ep, struct pxa2xx_ep, ep);
303 if (!_ep || !ep->desc) {
304 DMSG("%s, %s not enabled\n", __FUNCTION__,
305 _ep ? ep->ep.name : NULL);
308 nuke (ep, -ESHUTDOWN);
313 pxa_free_dma (ep->dma);
318 /* flush fifo (mostly for IN buffers) */
319 pxa2xx_ep_fifo_flush (_ep);
324 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
328 /*-------------------------------------------------------------------------*/
330 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
331 * must still pass correctly initialized endpoints, since other controller
332 * drivers may care about how it's currently set up (dma issues etc).
336 * pxa2xx_ep_alloc_request - allocate a request data structure
338 static struct usb_request *
339 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
341 struct pxa2xx_request *req;
343 req = kmalloc (sizeof *req, gfp_flags);
347 memset (req, 0, sizeof *req);
348 INIT_LIST_HEAD (&req->queue);
354 * pxa2xx_ep_free_request - deallocate a request data structure
357 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
359 struct pxa2xx_request *req;
361 req = container_of (_req, struct pxa2xx_request, req);
362 WARN_ON (!list_empty (&req->queue));
367 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
368 * no device-affinity and the heap works perfectly well for i/o buffers.
369 * It wastes much less memory than dma_alloc_coherent() would, and even
370 * prevents cacheline (32 bytes wide) sharing problems.
373 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
374 dma_addr_t *dma, int gfp_flags)
378 retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
380 *dma = virt_to_bus (retval);
385 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
391 /*-------------------------------------------------------------------------*/
394 * done - retire a request; caller blocked irqs
396 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
398 unsigned stopped = ep->stopped;
400 list_del_init(&req->queue);
402 if (likely (req->req.status == -EINPROGRESS))
403 req->req.status = status;
405 status = req->req.status;
407 if (status && status != -ESHUTDOWN)
408 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
409 ep->ep.name, &req->req, status,
410 req->req.actual, req->req.length);
412 /* don't modify queue heads during completion callback */
414 req->req.complete(&ep->ep, &req->req);
415 ep->stopped = stopped;
419 static inline void ep0_idle (struct pxa2xx_udc *dev)
421 dev->ep0state = EP0_IDLE;
426 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
429 unsigned length, count;
431 buf = req->req.buf + req->req.actual;
434 /* how big will this packet be? */
435 length = min(req->req.length - req->req.actual, max);
436 req->req.actual += length;
439 while (likely(count--))
446 * write to an IN endpoint fifo, as many packets as possible.
447 * irqs will use this to write the rest later.
448 * caller guarantees at least one packet buffer is ready (or a zlp).
451 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
455 max = le16_to_cpu(ep->desc->wMaxPacketSize);
458 int is_last, is_short;
460 count = write_packet(ep->reg_uddr, req, max);
462 /* last packet is usually short (or a zlp) */
463 if (unlikely (count != max))
464 is_last = is_short = 1;
466 if (likely(req->req.length != req->req.actual)
471 /* interrupt/iso maxpacket may not fill the fifo */
472 is_short = unlikely (max < ep->fifo_size);
475 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
477 is_last ? "/L" : "", is_short ? "/S" : "",
478 req->req.length - req->req.actual, req);
480 /* let loose that packet. maybe try writing another one,
481 * double buffering might work. TSP, TPC, and TFS
482 * bit values are the same for all normal IN endpoints.
484 *ep->reg_udccs = UDCCS_BI_TPC;
486 *ep->reg_udccs = UDCCS_BI_TSP;
488 /* requests complete when all IN data is in the FIFO */
491 if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
492 pio_irq_disable (ep->bEndpointAddress);
494 /* unaligned data and zlps couldn't use dma */
495 if (unlikely(!list_empty(&ep->queue))) {
496 req = list_entry(ep->queue.next,
497 struct pxa2xx_request, queue);
506 // TODO experiment: how robust can fifo mode tweaking be?
507 // double buffering is off in the default fifo mode, which
508 // prevents TFS from being set here.
510 } while (*ep->reg_udccs & UDCCS_BI_TFS);
514 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
515 * ep0 data stage. these chips want very simple state transitions.
518 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
520 UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
522 dev->req_pending = 0;
523 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
524 __FUNCTION__, tag, UDCCS0, flags);
528 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
533 count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
534 ep->dev->stats.write.bytes += count;
536 /* last packet "must be" short (or a zlp) */
537 is_short = (count != EP0_FIFO_SIZE);
539 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
540 req->req.length - req->req.actual, req);
542 if (unlikely (is_short)) {
543 if (ep->dev->req_pending)
544 ep0start(ep->dev, UDCCS0_IPR, "short IN");
548 count = req->req.length;
552 /* This seems to get rid of lost status irqs in some cases:
553 * host responds quickly, or next request involves config
554 * change automagic, or should have been hidden, or ...
556 * FIXME get rid of all udelays possible...
558 if (count >= EP0_FIFO_SIZE) {
561 if ((UDCCS0 & UDCCS0_OPR) != 0) {
562 /* clear OPR, generate ack */
571 } else if (ep->dev->req_pending)
572 ep0start(ep->dev, 0, "IN");
578 * read_fifo - unload packet(s) from the fifo we use for usb OUT
579 * transfers and put them into the request. caller should have made
580 * sure there's at least one packet ready.
582 * returns true if the request completed because of short packet or the
583 * request buffer having filled (and maybe overran till end-of-packet).
586 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
591 unsigned bufferspace, count, is_short;
593 /* make sure there's a packet in the FIFO.
594 * UDCCS_{BO,IO}_RPC are all the same bit value.
595 * UDCCS_{BO,IO}_RNE are all the same bit value.
597 udccs = *ep->reg_udccs;
598 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
600 buf = req->req.buf + req->req.actual;
602 bufferspace = req->req.length - req->req.actual;
604 /* read all bytes from this packet */
605 if (likely (udccs & UDCCS_BO_RNE)) {
606 count = 1 + (0x0ff & *ep->reg_ubcr);
607 req->req.actual += min (count, bufferspace);
610 is_short = (count < ep->ep.maxpacket);
611 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
612 ep->ep.name, udccs, count,
613 is_short ? "/S" : "",
614 req, req->req.actual, req->req.length);
615 while (likely (count-- != 0)) {
616 u8 byte = (u8) *ep->reg_uddr;
618 if (unlikely (bufferspace == 0)) {
619 /* this happens when the driver's buffer
620 * is smaller than what the host sent.
621 * discard the extra data.
623 if (req->req.status != -EOVERFLOW)
624 DMSG("%s overflow %d\n",
626 req->req.status = -EOVERFLOW;
632 *ep->reg_udccs = UDCCS_BO_RPC;
633 /* RPC/RSP/RNE could now reflect the other packet buffer */
635 /* iso is one request per packet */
636 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
637 if (udccs & UDCCS_IO_ROF)
638 req->req.status = -EHOSTUNREACH;
639 /* more like "is_done" */
644 if (is_short || req->req.actual == req->req.length) {
646 if (list_empty(&ep->queue))
647 pio_irq_disable (ep->bEndpointAddress);
651 /* finished that packet. the next one may be waiting... */
657 * special ep0 version of the above. no UBCR0 or double buffering; status
658 * handshaking is magic. most device protocols don't need control-OUT.
659 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
660 * protocols do use them.
663 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
666 unsigned bufferspace;
668 buf = req->req.buf + req->req.actual;
669 bufferspace = req->req.length - req->req.actual;
671 while (UDCCS0 & UDCCS0_RNE) {
674 if (unlikely (bufferspace == 0)) {
675 /* this happens when the driver's buffer
676 * is smaller than what the host sent.
677 * discard the extra data.
679 if (req->req.status != -EOVERFLOW)
680 DMSG("%s overflow\n", ep->ep.name);
681 req->req.status = -EOVERFLOW;
689 UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
692 if (req->req.actual >= req->req.length)
695 /* finished that packet. the next one may be waiting... */
701 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
704 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
706 u32 dcmd = req->req.length;
707 u32 buf = req->req.dma;
708 u32 fifo = io_v2p ((u32)ep->reg_uddr);
710 /* caller guarantees there's a packet or more remaining
711 * - IN may end with a short packet (TSP set separately),
712 * - OUT is always full length
714 buf += req->req.actual;
715 dcmd -= req->req.actual;
718 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
719 DCSR(ep->dma) = DCSR_NODESC;
721 DSADR(ep->dma) = buf;
722 DTADR(ep->dma) = fifo;
723 if (dcmd > MAX_IN_DMA)
726 ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
727 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
728 | DCMD_FLOWTRG | DCMD_INCSRCADDR;
731 DSADR(ep->dma) = fifo;
732 DTADR(ep->dma) = buf;
733 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
734 dcmd = ep->ep.maxpacket;
735 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
736 | DCMD_FLOWSRC | DCMD_INCTRGADDR;
739 DCMD(ep->dma) = dcmd;
740 DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
742 ? DCSR_STOPIRQEN /* use dma_nodesc_handler() */
743 : 0); /* use handle_ep() */
746 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
748 int is_in = ep->bEndpointAddress & USB_DIR_IN;
751 /* unaligned tx buffers and zlps only work with PIO */
752 if ((req->req.dma & 0x0f) != 0
753 || unlikely((req->req.length - req->req.actual)
755 pio_irq_enable(ep->bEndpointAddress);
756 if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
757 (void) write_fifo(ep, req);
759 start_dma_nodesc(ep, req, USB_DIR_IN);
762 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
763 DMSG("%s short dma read...\n", ep->ep.name);
764 /* we're always set up for pio out */
767 *ep->reg_udccs = UDCCS_BO_DME
768 | (*ep->reg_udccs & UDCCS_BO_FST);
769 start_dma_nodesc(ep, req, USB_DIR_OUT);
774 static void cancel_dma(struct pxa2xx_ep *ep)
776 struct pxa2xx_request *req;
779 if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
783 while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
786 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
787 tmp = DCMD(ep->dma) & DCMD_LENGTH;
788 req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
790 /* the last tx packet may be incomplete, so flush the fifo.
791 * FIXME correct req.actual if we can
793 if (ep->bEndpointAddress & USB_DIR_IN)
794 *ep->reg_udccs = UDCCS_BI_FTF;
797 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
798 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
800 struct pxa2xx_ep *ep = _ep;
801 struct pxa2xx_request *req;
806 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
809 ep->dev->stats.irqs++;
810 HEX_DISPLAY(ep->dev->stats.irqs);
815 if ((tmp & DCSR_STOPSTATE) == 0
816 || (DDADR(ep->dma) & DDADR_STOP) != 0) {
817 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
818 ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
821 DCSR(ep->dma) = 0; /* clear DCSR_STOPSTATE */
823 /* update transfer status */
824 completed = tmp & DCSR_BUSERR;
825 if (ep->bEndpointAddress & USB_DIR_IN)
826 tmp = DSADR(ep->dma);
828 tmp = DTADR(ep->dma);
829 req->req.actual = tmp - req->req.dma;
831 /* FIXME seems we sometimes see partial transfers... */
833 if (unlikely(completed != 0))
834 req->req.status = -EIO;
835 else if (req->req.actual) {
836 /* these registers have zeroes in low bits; they miscount
837 * some (end-of-transfer) short packets: tx 14 as tx 12
840 req->req.actual = min(req->req.actual + 3,
843 tmp = (req->req.length - req->req.actual);
844 completed = (tmp == 0);
845 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
847 /* maybe validate final short packet ... */
848 if ((req->req.actual % ep->ep.maxpacket) != 0)
849 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
851 /* ... or zlp, using pio fallback */
852 else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
854 DMSG("%s zlp terminate ...\n", ep->ep.name);
860 if (likely(completed)) {
863 /* maybe re-activate after completion */
864 if (ep->stopped || list_empty(&ep->queue))
866 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
875 /*-------------------------------------------------------------------------*/
878 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
880 struct pxa2xx_request *req;
881 struct pxa2xx_ep *ep;
882 struct pxa2xx_udc *dev;
885 req = container_of(_req, struct pxa2xx_request, req);
886 if (unlikely (!_req || !_req->complete || !_req->buf
887 || !list_empty(&req->queue))) {
888 DMSG("%s, bad params\n", __FUNCTION__);
892 ep = container_of(_ep, struct pxa2xx_ep, ep);
893 if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
894 DMSG("%s, bad ep\n", __FUNCTION__);
899 if (unlikely (!dev->driver
900 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
901 DMSG("%s, bogus device state\n", __FUNCTION__);
905 /* iso is always one packet per request, that's the only way
906 * we can report per-packet status. that also helps with dma.
908 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
909 && req->req.length > le16_to_cpu
910 (ep->desc->wMaxPacketSize)))
914 // FIXME caller may already have done the dma mapping
916 _req->dma = dma_map_single(dev->dev,
917 _req->buf, _req->length,
918 ((ep->bEndpointAddress & USB_DIR_IN) != 0)
924 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
925 _ep->name, _req, _req->length, _req->buf);
927 local_irq_save(flags);
929 _req->status = -EINPROGRESS;
932 /* kickstart this i/o queue? */
933 if (list_empty(&ep->queue) && !ep->stopped) {
934 if (ep->desc == 0 /* ep0 */) {
935 unsigned length = _req->length;
937 switch (dev->ep0state) {
938 case EP0_IN_DATA_PHASE:
939 dev->stats.write.ops++;
940 if (write_ep0_fifo(ep, req))
944 case EP0_OUT_DATA_PHASE:
945 dev->stats.read.ops++;
947 if (dev->req_config) {
948 DBG(DBG_VERBOSE, "ep0 config ack%s\n",
949 dev->has_cfr ? "" : " raced");
951 UDCCFR = UDCCFR_AREN|UDCCFR_ACM;
953 dev->ep0state = EP0_END_XFER;
956 if (dev->req_pending)
957 ep0start(dev, UDCCS0_IPR, "OUT");
958 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
959 && read_ep0_fifo(ep, req))) {
967 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
968 local_irq_restore (flags);
972 /* either start dma or prime pio pump */
973 } else if (ep->dma >= 0) {
976 /* can the FIFO can satisfy the request immediately? */
977 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
978 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
979 && write_fifo(ep, req)) {
981 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
982 && read_fifo(ep, req)) {
986 if (likely (req && ep->desc) && ep->dma < 0)
987 pio_irq_enable(ep->bEndpointAddress);
990 /* pio or dma irq handler advances the queue. */
991 if (likely (req != 0))
992 list_add_tail(&req->queue, &ep->queue);
993 local_irq_restore(flags);
1000 * nuke - dequeue ALL requests
1002 static void nuke(struct pxa2xx_ep *ep, int status)
1004 struct pxa2xx_request *req;
1006 /* called with irqs blocked */
1008 if (ep->dma >= 0 && !ep->stopped)
1011 while (!list_empty(&ep->queue)) {
1012 req = list_entry(ep->queue.next,
1013 struct pxa2xx_request,
1015 done(ep, req, status);
1018 pio_irq_disable (ep->bEndpointAddress);
1022 /* dequeue JUST ONE request */
1023 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1025 struct pxa2xx_ep *ep;
1026 struct pxa2xx_request *req;
1027 unsigned long flags;
1029 ep = container_of(_ep, struct pxa2xx_ep, ep);
1030 if (!_ep || ep->ep.name == ep0name)
1033 local_irq_save(flags);
1035 /* make sure it's actually queued on this endpoint */
1036 list_for_each_entry (req, &ep->queue, queue) {
1037 if (&req->req == _req)
1040 if (&req->req != _req) {
1041 local_irq_restore(flags);
1046 if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1048 done(ep, req, -ECONNRESET);
1050 if (!list_empty(&ep->queue)) {
1051 req = list_entry(ep->queue.next,
1052 struct pxa2xx_request, queue);
1057 done(ep, req, -ECONNRESET);
1059 local_irq_restore(flags);
1063 /*-------------------------------------------------------------------------*/
1065 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1067 struct pxa2xx_ep *ep;
1068 unsigned long flags;
1070 ep = container_of(_ep, struct pxa2xx_ep, ep);
1072 || (!ep->desc && ep->ep.name != ep0name))
1073 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1074 DMSG("%s, bad ep\n", __FUNCTION__);
1078 /* this path (reset toggle+halt) is needed to implement
1079 * SET_INTERFACE on normal hardware. but it can't be
1080 * done from software on the PXA UDC, and the hardware
1081 * forgets to do it as part of SET_INTERFACE automagic.
1083 DMSG("only host can clear %s halt\n", _ep->name);
1087 local_irq_save(flags);
1089 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1090 && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1091 || !list_empty(&ep->queue))) {
1092 local_irq_restore(flags);
1096 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1097 *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1099 /* ep0 needs special care */
1101 start_watchdog(ep->dev);
1102 ep->dev->req_pending = 0;
1103 ep->dev->ep0state = EP0_STALL;
1106 /* and bulk/intr endpoints like dropping stalls too */
1109 for (i = 0; i < 1000; i += 20) {
1110 if (*ep->reg_udccs & UDCCS_BI_SST)
1115 local_irq_restore(flags);
1117 DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1121 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1123 struct pxa2xx_ep *ep;
1125 ep = container_of(_ep, struct pxa2xx_ep, ep);
1127 DMSG("%s, bad ep\n", __FUNCTION__);
1130 /* pxa can't report unclaimed bytes from IN fifos */
1131 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1133 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1134 || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1137 return (*ep->reg_ubcr & 0xfff) + 1;
1140 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1142 struct pxa2xx_ep *ep;
1144 ep = container_of(_ep, struct pxa2xx_ep, ep);
1145 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1146 DMSG("%s, bad ep\n", __FUNCTION__);
1150 /* toggle and halt bits stay unchanged */
1152 /* for OUT, just read and discard the FIFO contents. */
1153 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1154 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1155 (void) *ep->reg_uddr;
1159 /* most IN status is the same, but ISO can't stall */
1160 *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1161 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1166 static struct usb_ep_ops pxa2xx_ep_ops = {
1167 .enable = pxa2xx_ep_enable,
1168 .disable = pxa2xx_ep_disable,
1170 .alloc_request = pxa2xx_ep_alloc_request,
1171 .free_request = pxa2xx_ep_free_request,
1173 .alloc_buffer = pxa2xx_ep_alloc_buffer,
1174 .free_buffer = pxa2xx_ep_free_buffer,
1176 .queue = pxa2xx_ep_queue,
1177 .dequeue = pxa2xx_ep_dequeue,
1179 .set_halt = pxa2xx_ep_set_halt,
1180 .fifo_status = pxa2xx_ep_fifo_status,
1181 .fifo_flush = pxa2xx_ep_fifo_flush,
1185 /* ---------------------------------------------------------------------------
1186 * device-scoped parts of the api to the usb controller hardware
1187 * ---------------------------------------------------------------------------
1190 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1192 return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1195 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1197 /* host may not have enabled remote wakeup */
1198 if ((UDCCS0 & UDCCS0_DRWF) == 0)
1199 return -EHOSTUNREACH;
1200 udc_set_mask_UDCCR(UDCCR_RSM);
1204 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1205 .get_frame = pxa2xx_udc_get_frame,
1206 .wakeup = pxa2xx_udc_wakeup,
1207 // current versions must always be self-powered
1211 /*-------------------------------------------------------------------------*/
1213 #ifdef UDC_PROC_FILE
1215 static const char proc_node_name [] = "driver/udc";
1218 udc_proc_read(char *page, char **start, off_t off, int count,
1219 int *eof, void *_dev)
1222 struct pxa2xx_udc *dev = _dev;
1224 unsigned size = count;
1225 unsigned long flags;
1232 local_irq_save(flags);
1234 /* basic device status */
1235 t = scnprintf(next, size, DRIVER_DESC "\n"
1236 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1237 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1238 dev->driver ? dev->driver->driver.name : "(none)",
1239 is_usb_connected() ? "full speed" : "disconnected");
1243 /* registers for device and ep0 */
1244 t = scnprintf(next, size,
1245 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1246 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1251 t = scnprintf(next, size,
1252 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1253 (tmp & UDCCR_REM) ? " rem" : "",
1254 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1255 (tmp & UDCCR_SRM) ? " srm" : "",
1256 (tmp & UDCCR_SUSIR) ? " susir" : "",
1257 (tmp & UDCCR_RESIR) ? " resir" : "",
1258 (tmp & UDCCR_RSM) ? " rsm" : "",
1259 (tmp & UDCCR_UDA) ? " uda" : "",
1260 (tmp & UDCCR_UDE) ? " ude" : "");
1265 t = scnprintf(next, size,
1266 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1267 (tmp & UDCCS0_SA) ? " sa" : "",
1268 (tmp & UDCCS0_RNE) ? " rne" : "",
1269 (tmp & UDCCS0_FST) ? " fst" : "",
1270 (tmp & UDCCS0_SST) ? " sst" : "",
1271 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1272 (tmp & UDCCS0_FTF) ? " ftf" : "",
1273 (tmp & UDCCS0_IPR) ? " ipr" : "",
1274 (tmp & UDCCS0_OPR) ? " opr" : "");
1280 t = scnprintf(next, size,
1281 "udccfr %02X =%s%s\n", tmp,
1282 (tmp & UDCCFR_AREN) ? " aren" : "",
1283 (tmp & UDCCFR_ACM) ? " acm" : "");
1288 if (!is_usb_connected() || !dev->driver)
1291 t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1292 dev->stats.write.bytes, dev->stats.write.ops,
1293 dev->stats.read.bytes, dev->stats.read.ops,
1298 /* dump endpoint queues */
1299 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1300 struct pxa2xx_ep *ep = &dev->ep [i];
1301 struct pxa2xx_request *req;
1305 const struct usb_endpoint_descriptor *d;
1310 tmp = *dev->ep [i].reg_udccs;
1311 t = scnprintf(next, size,
1312 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1313 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1314 (ep->dma >= 0) ? "dma" : "pio", tmp,
1315 ep->pio_irqs, ep->dma_irqs);
1316 /* TODO translate all five groups of udccs bits! */
1318 } else /* ep0 should only have one transfer queued */
1319 t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1321 if (t <= 0 || t > size)
1326 if (list_empty(&ep->queue)) {
1327 t = scnprintf(next, size, "\t(nothing queued)\n");
1328 if (t <= 0 || t > size)
1334 list_for_each_entry(req, &ep->queue, queue) {
1336 if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1337 t = scnprintf(next, size,
1338 "\treq %p len %d/%d "
1339 "buf %p (dma%d dcmd %08x)\n",
1340 &req->req, req->req.actual,
1341 req->req.length, req->req.buf,
1342 ep->dma, DCMD(ep->dma)
1343 // low 13 bits == bytes-to-go
1347 t = scnprintf(next, size,
1348 "\treq %p len %d/%d buf %p\n",
1349 &req->req, req->req.actual,
1350 req->req.length, req->req.buf);
1351 if (t <= 0 || t > size)
1359 local_irq_restore(flags);
1361 return count - size;
1364 #define create_proc_files() \
1365 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1366 #define remove_proc_files() \
1367 remove_proc_entry(proc_node_name, NULL)
1369 #else /* !UDC_PROC_FILE */
1370 #define create_proc_files() do {} while (0)
1371 #define remove_proc_files() do {} while (0)
1373 #endif /* UDC_PROC_FILE */
1375 /* "function" sysfs attribute */
1377 show_function (struct device *_dev, char *buf)
1379 struct pxa2xx_udc *dev = dev_get_drvdata (_dev);
1382 || !dev->driver->function
1383 || strlen (dev->driver->function) > PAGE_SIZE)
1385 return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1387 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1389 /*-------------------------------------------------------------------------*/
1392 * udc_disable - disable USB device controller
1394 static void udc_disable(struct pxa2xx_udc *dev)
1396 /* block all irqs */
1397 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1398 UICR0 = UICR1 = 0xff;
1401 /* if hardware supports it, disconnect from usb */
1402 make_usb_disappear();
1404 udc_clear_mask_UDCCR(UDCCR_UDE);
1406 #ifdef CONFIG_ARCH_PXA
1407 /* Disable clock for USB device */
1408 CKEN &= ~CKEN11_USB;
1412 dev->gadget.speed = USB_SPEED_UNKNOWN;
1418 * udc_reinit - initialize software state
1420 static void udc_reinit(struct pxa2xx_udc *dev)
1424 /* device/ep0 records init */
1425 INIT_LIST_HEAD (&dev->gadget.ep_list);
1426 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1427 dev->ep0state = EP0_IDLE;
1429 /* basic endpoint records init */
1430 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1431 struct pxa2xx_ep *ep = &dev->ep[i];
1434 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1438 INIT_LIST_HEAD (&ep->queue);
1439 ep->pio_irqs = ep->dma_irqs = 0;
1442 /* the rest was statically initialized, and is read-only */
1445 /* until it's enabled, this UDC should be completely invisible
1448 static void udc_enable (struct pxa2xx_udc *dev)
1450 udc_clear_mask_UDCCR(UDCCR_UDE);
1452 #ifdef CONFIG_ARCH_PXA
1453 /* Enable clock for USB device */
1457 /* try to clear these bits before we enable the udc */
1458 udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1461 dev->gadget.speed = USB_SPEED_UNKNOWN;
1462 dev->stats.irqs = 0;
1465 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1467 * - if RESET is already in progress, ack interrupt
1468 * - unmask reset interrupt
1470 udc_set_mask_UDCCR(UDCCR_UDE);
1471 if (!(UDCCR & UDCCR_UDA))
1472 udc_ack_int_UDCCR(UDCCR_RSTIR);
1474 if (dev->has_cfr /* UDC_RES2 is defined */) {
1475 /* pxa255 (a0+) can avoid a set_config race that could
1476 * prevent gadget drivers from configuring correctly
1478 UDCCFR = UDCCFR_ACM;
1480 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1481 * which could result in missing packets and interrupts.
1482 * supposedly one bit per endpoint, controlling whether it
1483 * double buffers or not; ACM/AREN bits fit into the holes.
1484 * zero bits (like USIR0_IRx) disable double buffering.
1490 #ifdef DISABLE_TEST_MODE
1491 /* "test mode" seems to have become the default in later chip
1492 * revs, preventing double buffering (and invalidating docs).
1493 * this EXPERIMENT enables it for bulk endpoints by tweaking
1494 * undefined/reserved register bits (that other drivers clear).
1495 * Belcarra code comments noted this usage.
1497 if (fifo_mode & 1) { /* IN endpoints */
1498 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1499 UDC_RES2 |= USIR1_IR11;
1501 if (fifo_mode & 2) { /* OUT endpoints */
1502 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1503 UDC_RES2 |= USIR1_IR12;
1507 /* caller must be able to sleep in order to cope
1508 * with startup transients.
1510 schedule_timeout(HZ/10);
1512 /* enable suspend/resume and reset irqs */
1513 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1515 /* enable ep0 irqs */
1516 UICR0 &= ~UICR0_IM0;
1518 /* if hardware supports it, connect to usb and wait for host */
1523 /* when a driver is successfully registered, it will receive
1524 * control requests including set_configuration(), which enables
1525 * non-control requests. then usb traffic follows until a
1526 * disconnect is reported. then a host may connect again, or
1527 * the driver might get unbound.
1529 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1531 struct pxa2xx_udc *dev = the_controller;
1535 || driver->speed != USB_SPEED_FULL
1538 || !driver->disconnect
1546 /* first hook up the driver ... */
1547 dev->driver = driver;
1548 dev->gadget.dev.driver = &driver->driver;
1550 device_add (&dev->gadget.dev);
1551 retval = driver->bind(&dev->gadget);
1553 DMSG("bind to driver %s --> error %d\n",
1554 driver->driver.name, retval);
1555 device_del (&dev->gadget.dev);
1558 dev->gadget.dev.driver = 0;
1561 device_create_file(dev->dev, &dev_attr_function);
1563 /* ... then enable host detection and ep0; and we're ready
1564 * for set_configuration as well as eventual disconnect.
1565 * NOTE: this shouldn't power up until later.
1567 DMSG("registered gadget driver '%s'\n", driver->driver.name);
1572 EXPORT_SYMBOL(usb_gadget_register_driver);
1575 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1579 /* don't disconnect drivers more than once */
1580 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1582 dev->gadget.speed = USB_SPEED_UNKNOWN;
1584 /* prevent new request submissions, kill any outstanding requests */
1585 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1586 struct pxa2xx_ep *ep = &dev->ep[i];
1589 nuke(ep, -ESHUTDOWN);
1591 del_timer_sync(&dev->timer);
1593 /* report disconnect; the driver is already quiesced */
1596 driver->disconnect(&dev->gadget);
1598 /* re-init driver-visible data structures */
1602 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1604 struct pxa2xx_udc *dev = the_controller;
1608 if (!driver || driver != dev->driver)
1611 local_irq_disable();
1613 stop_activity(dev, driver);
1616 driver->unbind(&dev->gadget);
1619 device_del (&dev->gadget.dev);
1620 device_remove_file(dev->dev, &dev_attr_function);
1622 DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1626 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1629 /*-------------------------------------------------------------------------*/
1631 #ifdef CONFIG_ARCH_LUBBOCK
1633 /* Lubbock can report connect or disconnect irqs. Likely more hardware
1634 * could support it as a timer callback.
1636 * FIXME for better power management, keep the hardware powered down
1637 * until a host is powering the link. means scheduling work later
1638 * in some task that can udc_enable().
1641 #define enable_disconnect_irq() \
1642 if (machine_is_lubbock()) { enable_irq(LUBBOCK_USB_DISC_IRQ); }
1643 #define disable_disconnect_irq() \
1644 if (machine_is_lubbock()) { disable_irq(LUBBOCK_USB_DISC_IRQ); }
1647 usb_connection_irq(int irq, void *_dev, struct pt_regs *r)
1649 struct pxa2xx_udc *dev = _dev;
1652 HEX_DISPLAY(dev->stats.irqs);
1654 if (!is_usb_connected()) {
1656 disable_disconnect_irq();
1657 /* report disconnect just once */
1658 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1659 DMSG("disconnect %s\n",
1660 dev->driver ? dev->driver->driver.name : 0);
1661 stop_activity(dev, dev->driver);
1663 // udc_disable (dev);
1665 // maybe "ACTION=disconnect /sbin/hotplug gadget".
1667 } else if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
1670 DMSG("?? connect irq ??\n");
1672 // if there's no driver bound, ignore; else
1673 // udc_enable (dev);
1674 // UDC irqs drive the rest.
1675 // maybe "ACTION=connect /sbin/hotplug gadget".
1682 #ifndef enable_disconnect_irq
1683 #warning USB disconnect() is not yet reported.
1684 #define enable_disconnect_irq() do {} while (0)
1685 #define disable_disconnect_irq() do {} while (0)
1689 /*-------------------------------------------------------------------------*/
1691 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1695 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1696 * fifos, and pending transactions mustn't be continued in any case.
1698 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1699 nuke(&dev->ep[i], -ECONNABORTED);
1702 static void udc_watchdog(unsigned long _dev)
1704 struct pxa2xx_udc *dev = (void *)_dev;
1706 local_irq_disable();
1707 if (dev->ep0state == EP0_STALL
1708 && (UDCCS0 & UDCCS0_FST) == 0
1709 && (UDCCS0 & UDCCS0_SST) == 0) {
1710 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1711 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1712 start_watchdog(dev);
1717 static void handle_ep0 (struct pxa2xx_udc *dev)
1719 u32 udccs0 = UDCCS0;
1720 struct pxa2xx_ep *ep = &dev->ep [0];
1721 struct pxa2xx_request *req;
1723 struct usb_ctrlrequest r;
1728 if (list_empty(&ep->queue))
1731 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1733 /* clear stall status */
1734 if (udccs0 & UDCCS0_SST) {
1736 UDCCS0 = UDCCS0_SST;
1737 del_timer(&dev->timer);
1741 /* previous request unfinished? non-error iff back-to-back ... */
1742 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1744 del_timer(&dev->timer);
1748 switch (dev->ep0state) {
1750 /* late-breaking status? */
1753 /* start control request? */
1754 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1755 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1760 /* read SETUP packet */
1761 for (i = 0; i < 8; i++) {
1762 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1764 DMSG("SETUP %d!\n", i);
1767 u.raw [i] = (u8) UDDR0;
1769 if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1773 le16_to_cpus (&u.r.wValue);
1774 le16_to_cpus (&u.r.wIndex);
1775 le16_to_cpus (&u.r.wLength);
1778 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1779 u.r.bRequestType, u.r.bRequest,
1780 u.r.wValue, u.r.wIndex, u.r.wLength);
1782 /* cope with automagic for some standard requests. */
1783 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1784 == USB_TYPE_STANDARD;
1785 dev->req_config = 0;
1786 dev->req_pending = 1;
1787 switch (u.r.bRequest) {
1788 /* hardware restricts gadget drivers here! */
1789 case USB_REQ_SET_CONFIGURATION:
1790 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1791 /* reflect hardware's automagic
1792 * up to the gadget driver.
1795 dev->req_config = 1;
1796 clear_ep_state(dev);
1797 /* if !has_cfr, there's no synch
1798 * else use AREN (later) not SA|OPR
1799 * USIR0_IR0 acts edge sensitive
1803 /* ... and here, even more ... */
1804 case USB_REQ_SET_INTERFACE:
1805 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1806 /* udc hardware is broken by design:
1807 * - altsetting may only be zero;
1808 * - hw resets all interfaces' eps;
1809 * - ep reset doesn't include halt(?).
1811 DMSG("broken set_interface (%d/%d)\n",
1812 u.r.wIndex, u.r.wValue);
1816 /* hardware was supposed to hide this */
1817 case USB_REQ_SET_ADDRESS:
1818 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1819 ep0start(dev, 0, "address");
1825 if (u.r.bRequestType & USB_DIR_IN)
1826 dev->ep0state = EP0_IN_DATA_PHASE;
1828 dev->ep0state = EP0_OUT_DATA_PHASE;
1830 i = dev->driver->setup(&dev->gadget, &u.r);
1832 /* hardware automagic preventing STALL... */
1833 if (dev->req_config) {
1834 /* hardware sometimes neglects to tell
1835 * tell us about config change events,
1836 * so later ones may fail...
1838 WARN("config change %02x fail %d?\n",
1841 /* TODO experiment: if has_cfr,
1842 * hardware didn't ACK; maybe we
1843 * could actually STALL!
1846 DBG(DBG_VERBOSE, "protocol STALL, "
1847 "%02x err %d\n", UDCCS0, i);
1849 /* the watchdog timer helps deal with cases
1850 * where udc seems to clear FST wrongly, and
1851 * then NAKs instead of STALLing.
1853 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1854 start_watchdog(dev);
1855 dev->ep0state = EP0_STALL;
1858 /* deferred i/o == no response yet */
1859 } else if (dev->req_pending) {
1860 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1861 || dev->req_std || u.r.wLength))
1862 ep0start(dev, 0, "defer");
1864 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1867 /* expect at least one data or status stage irq */
1870 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1871 == (UDCCS0_OPR|UDCCS0_SA))) {
1874 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1875 * still observed on a pxa255 a0.
1877 DBG(DBG_VERBOSE, "e131\n");
1880 /* read SETUP data, but don't trust it too much */
1881 for (i = 0; i < 8; i++)
1882 u.raw [i] = (u8) UDDR0;
1883 if ((u.r.bRequestType & USB_RECIP_MASK)
1886 if (u.word [0] == 0 && u.word [1] == 0)
1890 /* some random early IRQ:
1893 * - OPR got set, without SA (likely status stage)
1895 UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1898 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1899 if (udccs0 & UDCCS0_OPR) {
1900 UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1901 DBG(DBG_VERBOSE, "ep0in premature status\n");
1905 } else /* irq was IPR clearing */ {
1907 /* this IN packet might finish the request */
1908 (void) write_ep0_fifo(ep, req);
1909 } /* else IN token before response was written */
1912 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1913 if (udccs0 & UDCCS0_OPR) {
1915 /* this OUT packet might finish the request */
1916 if (read_ep0_fifo(ep, req))
1918 /* else more OUT packets expected */
1919 } /* else OUT token before read was issued */
1920 } else /* irq was IPR clearing */ {
1921 DBG(DBG_VERBOSE, "ep0out premature status\n");
1930 /* ack control-IN status (maybe in-zlp was skipped)
1931 * also appears after some config change events.
1933 if (udccs0 & UDCCS0_OPR)
1934 UDCCS0 = UDCCS0_OPR;
1938 UDCCS0 = UDCCS0_FST;
1944 static void handle_ep(struct pxa2xx_ep *ep)
1946 struct pxa2xx_request *req;
1947 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1953 if (likely (!list_empty(&ep->queue)))
1954 req = list_entry(ep->queue.next,
1955 struct pxa2xx_request, queue);
1959 // TODO check FST handling
1961 udccs = *ep->reg_udccs;
1962 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1964 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1965 tmp |= UDCCS_BI_SST;
1968 *ep->reg_udccs = tmp;
1969 if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1970 completed = write_fifo(ep, req);
1972 } else { /* irq from RPC (or for ISO, ROF) */
1973 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1974 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1976 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1979 *ep->reg_udccs = tmp;
1981 /* fifos can hold packets, ready for reading... */
1984 // TODO didn't yet debug out-dma. this approach assumes
1985 // the worst about short packets and RPC; it might be better.
1987 if (likely(ep->dma >= 0)) {
1988 if (!(udccs & UDCCS_BO_RSP)) {
1989 *ep->reg_udccs = UDCCS_BO_RPC;
1995 completed = read_fifo(ep, req);
1997 pio_irq_disable (ep->bEndpointAddress);
2000 } while (completed);
2004 * pxa2xx_udc_irq - interrupt handler
2006 * avoid delays in ep0 processing. the control handshaking isn't always
2007 * under software control (pxa250c0 and the pxa255 are better), and delays
2008 * could cause usb protocol errors.
2011 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2013 struct pxa2xx_udc *dev = _dev;
2017 HEX_DISPLAY(dev->stats.irqs);
2023 /* SUSpend Interrupt Request */
2024 if (unlikely(udccr & UDCCR_SUSIR)) {
2025 udc_ack_int_UDCCR(UDCCR_SUSIR);
2027 DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2028 ? "" : "+disconnect");
2030 if (!is_usb_connected())
2031 stop_activity(dev, dev->driver);
2032 else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2034 && dev->driver->suspend)
2035 dev->driver->suspend(&dev->gadget);
2039 /* RESume Interrupt Request */
2040 if (unlikely(udccr & UDCCR_RESIR)) {
2041 udc_ack_int_UDCCR(UDCCR_RESIR);
2043 DBG(DBG_VERBOSE, "USB resume\n");
2045 if (dev->gadget.speed != USB_SPEED_UNKNOWN
2047 && dev->driver->resume
2048 && is_usb_connected())
2049 dev->driver->resume(&dev->gadget);
2052 /* ReSeT Interrupt Request - USB reset */
2053 if (unlikely(udccr & UDCCR_RSTIR)) {
2054 udc_ack_int_UDCCR(UDCCR_RSTIR);
2057 if ((UDCCR & UDCCR_UDA) == 0) {
2058 DBG(DBG_VERBOSE, "USB reset start\n");
2059 if (dev->gadget.speed != USB_SPEED_UNKNOWN)
2060 disable_disconnect_irq();
2062 /* reset driver and endpoints,
2063 * in case that's not yet done
2065 stop_activity (dev, dev->driver);
2068 INFO("USB reset\n");
2069 dev->gadget.speed = USB_SPEED_FULL;
2071 memset(&dev->stats, 0, sizeof dev->stats);
2072 /* driver and endpoints are still reset */
2073 enable_disconnect_irq();
2077 u32 usir0 = USIR0 & ~UICR0;
2078 u32 usir1 = USIR1 & ~UICR1;
2081 if (unlikely (!usir0 && !usir1))
2084 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2086 /* control traffic */
2087 if (usir0 & USIR0_IR0) {
2088 dev->ep[0].pio_irqs++;
2093 /* endpoint data transfers */
2094 for (i = 0; i < 8; i++) {
2097 if (i && (usir0 & tmp)) {
2098 handle_ep(&dev->ep[i]);
2103 handle_ep(&dev->ep[i+8]);
2110 /* we could also ask for 1 msec SOF (SIR) interrupts */
2116 /*-------------------------------------------------------------------------*/
2118 static void nop_release (struct device *dev)
2120 DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2123 /* this uses load-time allocation and initialization (instead of
2124 * doing it at run-time) to save code, eliminate fault paths, and
2125 * be more obviously correct.
2127 static struct pxa2xx_udc memory = {
2129 .ops = &pxa2xx_udc_ops,
2130 .ep0 = &memory.ep[0].ep,
2131 .name = driver_name,
2134 .release = nop_release,
2138 /* control endpoint */
2142 .ops = &pxa2xx_ep_ops,
2143 .maxpacket = EP0_FIFO_SIZE,
2146 .reg_udccs = &UDCCS0,
2150 /* first group of endpoints */
2153 .name = "ep1in-bulk",
2154 .ops = &pxa2xx_ep_ops,
2155 .maxpacket = BULK_FIFO_SIZE,
2158 .fifo_size = BULK_FIFO_SIZE,
2159 .bEndpointAddress = USB_DIR_IN | 1,
2160 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2161 .reg_udccs = &UDCCS1,
2167 .name = "ep2out-bulk",
2168 .ops = &pxa2xx_ep_ops,
2169 .maxpacket = BULK_FIFO_SIZE,
2172 .fifo_size = BULK_FIFO_SIZE,
2173 .bEndpointAddress = 2,
2174 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2175 .reg_udccs = &UDCCS2,
2180 #ifndef CONFIG_USB_PXA2XX_SMALL
2183 .name = "ep3in-iso",
2184 .ops = &pxa2xx_ep_ops,
2185 .maxpacket = ISO_FIFO_SIZE,
2188 .fifo_size = ISO_FIFO_SIZE,
2189 .bEndpointAddress = USB_DIR_IN | 3,
2190 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2191 .reg_udccs = &UDCCS3,
2197 .name = "ep4out-iso",
2198 .ops = &pxa2xx_ep_ops,
2199 .maxpacket = ISO_FIFO_SIZE,
2202 .fifo_size = ISO_FIFO_SIZE,
2203 .bEndpointAddress = 4,
2204 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2205 .reg_udccs = &UDCCS4,
2212 .name = "ep5in-int",
2213 .ops = &pxa2xx_ep_ops,
2214 .maxpacket = INT_FIFO_SIZE,
2217 .fifo_size = INT_FIFO_SIZE,
2218 .bEndpointAddress = USB_DIR_IN | 5,
2219 .bmAttributes = USB_ENDPOINT_XFER_INT,
2220 .reg_udccs = &UDCCS5,
2224 /* second group of endpoints */
2227 .name = "ep6in-bulk",
2228 .ops = &pxa2xx_ep_ops,
2229 .maxpacket = BULK_FIFO_SIZE,
2232 .fifo_size = BULK_FIFO_SIZE,
2233 .bEndpointAddress = USB_DIR_IN | 6,
2234 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2235 .reg_udccs = &UDCCS6,
2241 .name = "ep7out-bulk",
2242 .ops = &pxa2xx_ep_ops,
2243 .maxpacket = BULK_FIFO_SIZE,
2246 .fifo_size = BULK_FIFO_SIZE,
2247 .bEndpointAddress = 7,
2248 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2249 .reg_udccs = &UDCCS7,
2256 .name = "ep8in-iso",
2257 .ops = &pxa2xx_ep_ops,
2258 .maxpacket = ISO_FIFO_SIZE,
2261 .fifo_size = ISO_FIFO_SIZE,
2262 .bEndpointAddress = USB_DIR_IN | 8,
2263 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2264 .reg_udccs = &UDCCS8,
2270 .name = "ep9out-iso",
2271 .ops = &pxa2xx_ep_ops,
2272 .maxpacket = ISO_FIFO_SIZE,
2275 .fifo_size = ISO_FIFO_SIZE,
2276 .bEndpointAddress = 9,
2277 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2278 .reg_udccs = &UDCCS9,
2285 .name = "ep10in-int",
2286 .ops = &pxa2xx_ep_ops,
2287 .maxpacket = INT_FIFO_SIZE,
2290 .fifo_size = INT_FIFO_SIZE,
2291 .bEndpointAddress = USB_DIR_IN | 10,
2292 .bmAttributes = USB_ENDPOINT_XFER_INT,
2293 .reg_udccs = &UDCCS10,
2294 .reg_uddr = &UDDR10,
2297 /* third group of endpoints */
2300 .name = "ep11in-bulk",
2301 .ops = &pxa2xx_ep_ops,
2302 .maxpacket = BULK_FIFO_SIZE,
2305 .fifo_size = BULK_FIFO_SIZE,
2306 .bEndpointAddress = USB_DIR_IN | 11,
2307 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2308 .reg_udccs = &UDCCS11,
2309 .reg_uddr = &UDDR11,
2314 .name = "ep12out-bulk",
2315 .ops = &pxa2xx_ep_ops,
2316 .maxpacket = BULK_FIFO_SIZE,
2319 .fifo_size = BULK_FIFO_SIZE,
2320 .bEndpointAddress = 12,
2321 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2322 .reg_udccs = &UDCCS12,
2323 .reg_ubcr = &UBCR12,
2324 .reg_uddr = &UDDR12,
2329 .name = "ep13in-iso",
2330 .ops = &pxa2xx_ep_ops,
2331 .maxpacket = ISO_FIFO_SIZE,
2334 .fifo_size = ISO_FIFO_SIZE,
2335 .bEndpointAddress = USB_DIR_IN | 13,
2336 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2337 .reg_udccs = &UDCCS13,
2338 .reg_uddr = &UDDR13,
2343 .name = "ep14out-iso",
2344 .ops = &pxa2xx_ep_ops,
2345 .maxpacket = ISO_FIFO_SIZE,
2348 .fifo_size = ISO_FIFO_SIZE,
2349 .bEndpointAddress = 14,
2350 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2351 .reg_udccs = &UDCCS14,
2352 .reg_ubcr = &UBCR14,
2353 .reg_uddr = &UDDR14,
2358 .name = "ep15in-int",
2359 .ops = &pxa2xx_ep_ops,
2360 .maxpacket = INT_FIFO_SIZE,
2363 .fifo_size = INT_FIFO_SIZE,
2364 .bEndpointAddress = USB_DIR_IN | 15,
2365 .bmAttributes = USB_ENDPOINT_XFER_INT,
2366 .reg_udccs = &UDCCS15,
2367 .reg_uddr = &UDDR15,
2369 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2372 #define CP15R0_VENDOR_MASK 0xffffe000
2374 #if defined(CONFIG_ARCH_PXA)
2375 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2377 #elif defined(CONFIG_ARCH_IXP4XX)
2378 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2382 #define CP15R0_PROD_MASK 0x000003f0
2383 #define PXA25x 0x00000100 /* and PXA26x */
2384 #define PXA210 0x00000120
2386 #define CP15R0_REV_MASK 0x0000000f
2388 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2390 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2391 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2392 #define PXA250_B2 0x00000104
2393 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2394 #define PXA250_B0 0x00000102
2395 #define PXA250_A1 0x00000101
2396 #define PXA250_A0 0x00000100
2398 #define PXA210_C0 0x00000125
2399 #define PXA210_B2 0x00000124
2400 #define PXA210_B1 0x00000123
2401 #define PXA210_B0 0x00000122
2402 #define IXP425_A0 0x000001c1
2405 * probe - binds to the platform device
2407 static int __init pxa2xx_udc_probe(struct device *_dev)
2409 struct pxa2xx_udc *dev = &memory;
2410 int retval, out_dma = 1;
2413 /* insist on Intel/ARM/XScale */
2414 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2415 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2416 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2420 /* trigger chiprev-specific logic */
2421 switch (chiprev & CP15R0_PRODREV_MASK) {
2422 #if defined(CONFIG_ARCH_PXA)
2428 /* A0/A1 "not released"; ep 13, 15 unusable */
2430 case PXA250_B2: case PXA210_B2:
2431 case PXA250_B1: case PXA210_B1:
2432 case PXA250_B0: case PXA210_B0:
2435 case PXA250_C0: case PXA210_C0:
2437 #elif defined(CONFIG_ARCH_IXP4XX)
2444 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2445 driver_name, chiprev);
2446 /* iop3xx, ixp4xx, ... */
2450 pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2451 dev->has_cfr ? "" : " (!cfr)",
2452 out_dma ? "" : " (broken dma-out)",
2460 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2462 DMSG("disabled OUT dma\n");
2463 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2464 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2465 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2469 /* other non-static parts of init */
2471 dev->mach = _dev->platform_data;
2473 init_timer(&dev->timer);
2474 dev->timer.function = udc_watchdog;
2475 dev->timer.data = (unsigned long) dev;
2477 device_initialize(&dev->gadget.dev);
2478 dev->gadget.dev.parent = _dev;
2479 dev->gadget.dev.dma_mask = _dev->dma_mask;
2481 the_controller = dev;
2482 dev_set_drvdata(_dev, dev);
2487 /* irq setup after old hardware state is cleaned up */
2488 retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2489 SA_INTERRUPT, driver_name, dev);
2491 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2492 driver_name, IRQ_USB, retval);
2497 #ifdef CONFIG_ARCH_LUBBOCK
2498 if (machine_is_lubbock()) {
2499 disable_irq(LUBBOCK_USB_DISC_IRQ);
2500 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2502 SA_INTERRUPT /* OOPSING | SA_SAMPLE_RANDOM */,
2505 enable_irq(LUBBOCK_USB_DISC_IRQ);
2506 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2507 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2513 create_proc_files();
2517 static int __exit pxa2xx_udc_remove(struct device *_dev)
2519 struct pxa2xx_udc *dev = _dev->driver_data;
2522 remove_proc_files();
2523 usb_gadget_unregister_driver(dev->driver);
2526 free_irq(IRQ_USB, dev);
2529 if (machine_is_lubbock() && dev->got_disc) {
2530 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2533 dev_set_drvdata(_dev, 0);
2538 /*-------------------------------------------------------------------------*/
2540 static struct device_driver udc_driver = {
2541 .name = (char *) driver_name,
2542 .bus = &platform_bus_type,
2543 .probe = pxa2xx_udc_probe,
2544 .remove = __exit_p(pxa2xx_udc_remove),
2546 // FIXME power management support
2547 // .suspend = ... disable UDC
2548 // .resume = ... re-enable UDC
2551 static int __init udc_init(void)
2553 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2554 return driver_register(&udc_driver);
2556 module_init(udc_init);
2558 static void __exit udc_exit(void)
2560 driver_unregister(&udc_driver);
2562 module_exit(udc_exit);
2564 MODULE_DESCRIPTION(DRIVER_DESC);
2565 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2566 MODULE_LICENSE("GPL");