2 * Copyright (c) 2000-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/config.h>
21 #ifdef CONFIG_USB_DEBUG
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/smp_lock.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/reboot.h>
42 #include <linux/usb.h>
43 #include <linux/moduleparam.h>
44 #include <linux/dma-mapping.h>
46 #include "../core/hcd.h"
48 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
55 /*-------------------------------------------------------------------------*/
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
72 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
73 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
74 * <sojkam@centrum.cz>, updates by DB).
76 * 2002-11-29 Correct handling for hw async_next register.
77 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
78 * only scheduling is different, no arbitrary limitations.
79 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
80 * clean up HC run state handshaking.
81 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
82 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
83 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
84 * 2002-05-07 Some error path cleanups to report better errors; wmb();
85 * use non-CVS version id; better iso bandwidth claim.
86 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
87 * errors in submit path. Bugfixes to interrupt scheduling/processing.
88 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
89 * more checking to generic hcd framework (db). Make it work with
90 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
91 * 2002-01-14 Minor cleanup; version synch.
92 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
93 * 2002-01-04 Control/Bulk queuing behaves.
95 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
96 * 2001-June Works with usb-storage and NEC EHCI on 2.4
99 #define DRIVER_VERSION "2003-Dec-29"
100 #define DRIVER_AUTHOR "David Brownell"
101 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
103 static const char hcd_name [] = "ehci_hcd";
106 #undef EHCI_VERBOSE_DEBUG
107 #undef EHCI_URB_TRACE
113 /* magic numbers that can affect system performance */
114 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
115 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
116 #define EHCI_TUNE_RL_TT 0
117 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
118 #define EHCI_TUNE_MULT_TT 1
119 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
121 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
122 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
123 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
124 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
126 /* Initial IRQ latency: lower than default */
127 static int log2_irq_thresh = 0; // 0 to 6
128 module_param (log2_irq_thresh, int, S_IRUGO);
129 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
131 #define INTR_MASK (STS_IAA | STS_FATAL | STS_ERR | STS_INT)
133 /*-------------------------------------------------------------------------*/
136 #include "ehci-dbg.c"
138 /*-------------------------------------------------------------------------*/
141 * handshake - spin reading hc until handshake completes or fails
142 * @ptr: address of hc register to be read
143 * @mask: bits to look at in result of read
144 * @done: value of those bits when handshake succeeds
145 * @usec: timeout in microseconds
147 * Returns negative errno, or zero on success
149 * Success happens when the "mask" bits have the specified value (hardware
150 * handshake done). There are two failure modes: "usec" have passed (major
151 * hardware flakeout), or the register reads as all-ones (hardware removed).
153 * That last failure should_only happen in cases like physical cardbus eject
154 * before driver shutdown. But it also seems to be caused by bugs in cardbus
155 * bridge shutdown: shutting down the bridge before the devices using it.
157 static int handshake (u32 *ptr, u32 mask, u32 done, int usec)
162 result = readl (ptr);
163 if (result == ~(u32)0) /* card removed */
175 * hc states include: unknown, halted, ready, running
176 * transitional states are messy just now
177 * trying to avoid "running" unless urbs are active
178 * a "ready" hc can be finishing prefetched work
181 /* force HC to halt state from unknown (EHCI spec section 2.3) */
182 static int ehci_halt (struct ehci_hcd *ehci)
184 u32 temp = readl (&ehci->regs->status);
186 if ((temp & STS_HALT) != 0)
189 temp = readl (&ehci->regs->command);
191 writel (temp, &ehci->regs->command);
192 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
195 /* reset a non-running (STS_HALT == 1) controller */
196 static int ehci_reset (struct ehci_hcd *ehci)
198 u32 command = readl (&ehci->regs->command);
200 command |= CMD_RESET;
201 dbg_cmd (ehci, "reset", command);
202 writel (command, &ehci->regs->command);
203 ehci->hcd.state = USB_STATE_HALT;
204 return handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
207 /* idle the controller (from running) */
208 static void ehci_ready (struct ehci_hcd *ehci)
213 if (!HCD_IS_RUNNING (ehci->hcd.state))
217 /* wait for any schedule enables/disables to take effect */
219 if (ehci->async->qh_next.qh)
221 if (ehci->next_uframe != -1)
223 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
224 temp, 16 * 125) != 0) {
225 ehci->hcd.state = USB_STATE_HALT;
229 /* then disable anything that's still active */
230 temp = readl (&ehci->regs->command);
231 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
232 writel (temp, &ehci->regs->command);
234 /* hardware can take 16 microframes to turn off ... */
235 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
237 ehci->hcd.state = USB_STATE_HALT;
242 /*-------------------------------------------------------------------------*/
244 #include "ehci-hub.c"
245 #include "ehci-mem.c"
247 #include "ehci-sched.c"
249 /*-------------------------------------------------------------------------*/
251 static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
253 static void ehci_watchdog (unsigned long param)
255 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
258 spin_lock_irqsave (&ehci->lock, flags);
260 /* lost IAA irqs wedge things badly; seen with a vt8235 */
262 u32 status = readl (&ehci->regs->status);
264 if (status & STS_IAA) {
265 ehci_vdbg (ehci, "lost IAA\n");
266 COUNT (ehci->stats.lost_iaa);
267 writel (STS_IAA, &ehci->regs->status);
268 ehci->reclaim_ready = 1;
272 /* stop async processing after it's idled a bit */
273 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
274 start_unlink_async (ehci, ehci->async);
276 /* ehci could run by timer, without IRQs ... */
277 ehci_work (ehci, NULL);
279 spin_unlock_irqrestore (&ehci->lock, flags);
284 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
285 * off the controller (maybe it can boot from highspeed USB disks).
287 static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
289 if (cap & (1 << 16)) {
292 /* request handoff to OS */
294 pci_write_config_dword (to_pci_dev(ehci->hcd.self.controller), where, cap);
296 /* and wait a while for it to happen */
300 pci_read_config_dword (to_pci_dev(ehci->hcd.self.controller), where, &cap);
301 } while ((cap & (1 << 16)) && msec);
302 if (cap & (1 << 16)) {
303 ehci_err (ehci, "BIOS handoff failed (%d, %04x)\n",
307 ehci_dbg (ehci, "BIOS handoff succeeded\n");
315 ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
317 struct ehci_hcd *ehci;
319 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
321 /* make BIOS/etc use companion controller during reboot */
322 writel (0, &ehci->regs->configured_flag);
327 /* called by khubd or root hub init threads */
329 static int ehci_hc_reset (struct usb_hcd *hcd)
331 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
333 unsigned count = 256/4;
335 spin_lock_init (&ehci->lock);
337 ehci->caps = (struct ehci_caps *) hcd->regs;
338 ehci->regs = (struct ehci_regs *) (hcd->regs +
339 HC_LENGTH (readl (&ehci->caps->hc_capbase)));
340 dbg_hcs_params (ehci, "reset");
341 dbg_hcc_params (ehci, "reset");
344 /* EHCI 0.96 and later may have "extended capabilities" */
345 if (hcd->self.controller->bus == &pci_bus_type)
346 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
349 while (temp && count--) {
352 pci_read_config_dword (to_pci_dev(ehci->hcd.self.controller),
354 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
355 switch (cap & 0xff) {
356 case 1: /* BIOS/SMM/... handoff */
357 if (bios_handoff (ehci, temp, cap) != 0)
360 case 0x0a: /* appendix C */
361 ehci_dbg (ehci, "debug registers, BAR %d offset %d\n",
362 (cap >> 29) & 0x07, (cap >> 16) & 0x0fff);
364 case 0: /* illegal reserved capability */
365 ehci_warn (ehci, "illegal capability!\n");
368 default: /* unknown */
371 temp = (cap >> 8) & 0xff;
374 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
379 /* cache this readonly data; minimize PCI reads */
380 ehci->hcs_params = readl (&ehci->caps->hcs_params);
382 /* force HC to halt state */
383 return ehci_halt (ehci);
386 static int ehci_start (struct usb_hcd *hcd)
388 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
390 struct usb_device *udev;
396 init_timer (&ehci->watchdog);
397 ehci->watchdog.function = ehci_watchdog;
398 ehci->watchdog.data = (unsigned long) ehci;
401 * hw default: 1K periodic list heads, one per frame.
402 * periodic_size can shrink by USBCMD update if hcc_params allows.
404 ehci->periodic_size = DEFAULT_I_TDPS;
405 if ((retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
408 /* controllers may cache some of the periodic schedule ... */
409 hcc_params = readl (&ehci->caps->hcc_params);
410 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
412 else // N microframes cached
413 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
416 ehci->next_uframe = -1;
418 /* controller state: unknown --> reset */
420 /* EHCI spec section 4.1 */
421 if ((retval = ehci_reset (ehci)) != 0) {
422 ehci_mem_cleanup (ehci);
425 writel (INTR_MASK, &ehci->regs->intr_enable);
426 writel (ehci->periodic_dma, &ehci->regs->frame_list);
429 if (hcd->self.controller->bus == &pci_bus_type) {
430 struct pci_dev *pdev;
432 pdev = to_pci_dev(hcd->self.controller);
434 /* Serial Bus Release Number is at PCI 0x60 offset */
435 pci_read_config_byte(pdev, 0x60, &sbrn);
437 /* help hc dma work well with cachelines */
440 /* chip-specific init */
441 switch (pdev->vendor) {
442 case PCI_VENDOR_ID_ARC:
443 if (pdev->device == PCI_DEVICE_ID_ARC_EHCI)
444 ehci->is_arc_rh_tt = 1;
452 * dedicate a qh for the async ring head, since we couldn't unlink
453 * a 'real' qh without stopping the async schedule [4.8]. use it
454 * as the 'reclamation list head' too.
455 * its dummy is used in hw_alt_next of many tds, to prevent the qh
456 * from automatically advancing to the next td after short reads.
458 ehci->async->qh_next.qh = 0;
459 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
460 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
461 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
462 ehci->async->hw_qtd_next = EHCI_LIST_END;
463 ehci->async->qh_state = QH_STATE_LINKED;
464 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
465 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
468 * hcc_params controls whether ehci->regs->segment must (!!!)
469 * be used; it constrains QH/ITD/SITD and QTD locations.
470 * pci_pool consistent memory always uses segment zero.
471 * streaming mappings for I/O buffers, like pci_map_single(),
472 * can return segments above 4GB, if the device allows.
474 * NOTE: the dma mask is visible through dma_supported(), so
475 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
476 * Scsi_Host.highmem_io, and so forth. It's readonly to all
477 * host side drivers though.
479 if (HCC_64BIT_ADDR (hcc_params)) {
480 writel (0, &ehci->regs->segment);
482 // this is deeply broken on almost all architectures
483 if (!pci_set_dma_mask (to_pci_dev(ehci->hcd.self.controller), 0xffffffffffffffffULL))
484 ehci_info (ehci, "enabled 64bit PCI DMA\n");
488 /* clear interrupt enables, set irq latency */
489 temp = readl (&ehci->regs->command) & 0x0fff;
490 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
492 temp |= 1 << (16 + log2_irq_thresh);
493 // if hc can park (ehci >= 0.96), default is 3 packets per async QH
494 if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
495 /* periodic schedule size can be smaller than default */
497 temp |= (EHCI_TUNE_FLS << 2);
498 switch (EHCI_TUNE_FLS) {
499 case 0: ehci->periodic_size = 1024; break;
500 case 1: ehci->periodic_size = 512; break;
501 case 2: ehci->periodic_size = 256; break;
505 temp &= ~(CMD_IAAD | CMD_ASE | CMD_PSE),
506 // Philips, Intel, and maybe others need CMD_RUN before the
507 // root hub will detect new devices (why?); NEC doesn't
509 writel (temp, &ehci->regs->command);
510 dbg_cmd (ehci, "init", temp);
512 /* set async sleep time = 10 us ... ? */
514 /* wire up the root hub */
515 bus = hcd_to_bus (hcd);
516 bus->root_hub = udev = usb_alloc_dev (NULL, bus, 0);
519 ehci_mem_cleanup (ehci);
524 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
525 * are explicitly handed to companion controller(s), so no TT is
526 * involved with the root hub.
528 ehci->reboot_notifier.notifier_call = ehci_reboot;
529 register_reboot_notifier (&ehci->reboot_notifier);
531 ehci->hcd.state = USB_STATE_RUNNING;
532 writel (FLAG_CF, &ehci->regs->configured_flag);
533 readl (&ehci->regs->command); /* unblock posted write */
535 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
537 "USB %x.%x enabled, EHCI %x.%02x, driver %s\n",
538 ((sbrn & 0xf0)>>4), (sbrn & 0x0f),
539 temp >> 8, temp & 0xff, DRIVER_VERSION);
542 * From here on, khubd concurrently accesses the root
543 * hub; drivers will be talking to enumerated devices.
545 * Before this point the HC was idle/ready. After, khubd
546 * and device drivers may start it running.
548 udev->speed = USB_SPEED_HIGH;
549 if (hcd_register_root (hcd) != 0) {
550 if (hcd->state == USB_STATE_RUNNING)
559 create_debug_files (ehci);
564 /* always called by thread; normally rmmod */
566 static void ehci_stop (struct usb_hcd *hcd)
568 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
570 ehci_dbg (ehci, "stop\n");
572 /* no more interrupts ... */
573 if (hcd->state == USB_STATE_RUNNING)
575 if (in_interrupt ()) { /* must not happen!! */
576 ehci_err (ehci, "stopped in_interrupt!\n");
579 del_timer_sync (&ehci->watchdog);
582 /* let companion controllers work when we aren't */
583 writel (0, &ehci->regs->configured_flag);
584 unregister_reboot_notifier (&ehci->reboot_notifier);
586 remove_debug_files (ehci);
588 /* root hub is shut down separately (first, when possible) */
589 spin_lock_irq (&ehci->lock);
591 ehci_work (ehci, NULL);
592 spin_unlock_irq (&ehci->lock);
593 ehci_mem_cleanup (ehci);
596 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
597 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
598 ehci->stats.lost_iaa);
599 ehci_dbg (ehci, "complete %ld unlink %ld\n",
600 ehci->stats.complete, ehci->stats.unlink);
603 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
606 static int ehci_get_frame (struct usb_hcd *hcd)
608 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
609 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
612 /*-------------------------------------------------------------------------*/
616 /* suspend/resume, section 4.3 */
618 static int ehci_suspend (struct usb_hcd *hcd, u32 state)
620 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
624 ehci_dbg (ehci, "suspend to %d\n", state);
626 ports = HCS_N_PORTS (ehci->hcs_params);
628 // FIXME: This assumes what's probably a D3 level suspend...
630 // FIXME: usb wakeup events on this bus should resume the machine.
631 // pci config register PORTWAKECAP controls which ports can do it;
632 // bios may have initted the register...
634 /* suspend each port, then stop the hc */
635 for (i = 0; i < ports; i++) {
636 int temp = readl (&ehci->regs->port_status [i]);
638 if ((temp & PORT_PE) == 0
639 || (temp & PORT_OWNER) != 0)
641 ehci_dbg (ehci, "suspend port %d", i);
642 temp |= PORT_SUSPEND;
643 writel (temp, &ehci->regs->port_status [i]);
646 if (hcd->state == USB_STATE_RUNNING)
648 writel (readl (&ehci->regs->command) & ~CMD_RUN, &ehci->regs->command);
650 // save pci FLADJ value
652 /* who tells PCI to reduce power consumption? */
657 static int ehci_resume (struct usb_hcd *hcd)
659 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
663 ehci_dbg (ehci, "resume\n");
665 ports = HCS_N_PORTS (ehci->hcs_params);
667 // FIXME: if controller didn't retain state,
668 // return and let generic code clean it up
669 // test configured_flag ?
671 /* resume HC and each port */
672 // restore pci FLADJ value
673 // khubd and drivers will set HC running, if needed;
674 hcd->state = USB_STATE_RUNNING;
675 // FIXME Philips/Intel/... etc don't really have a "READY"
676 // state ... turn on CMD_RUN too
677 for (i = 0; i < ports; i++) {
678 int temp = readl (&ehci->regs->port_status [i]);
680 if ((temp & PORT_PE) == 0
681 || (temp & PORT_SUSPEND) != 0)
683 ehci_dbg (ehci, "resume port %d", i);
685 writel (temp, &ehci->regs->port_status [i]);
686 readl (&ehci->regs->command); /* unblock posted writes */
689 temp &= ~PORT_RESUME;
690 writel (temp, &ehci->regs->port_status [i]);
692 readl (&ehci->regs->command); /* unblock posted writes */
698 /*-------------------------------------------------------------------------*/
701 * ehci_work is called from some interrupts, timers, and so on.
702 * it calls driver completion functions, after dropping ehci->lock.
704 static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
706 timer_action_done (ehci, TIMER_IO_WATCHDOG);
707 if (ehci->reclaim_ready)
708 end_unlink_async (ehci, regs);
709 scan_async (ehci, regs);
710 if (ehci->next_uframe != -1)
711 scan_periodic (ehci, regs);
713 /* the IO watchdog guards against hardware or driver bugs that
714 * misplace IRQs, and should let us run completely without IRQs.
715 * such lossage has been observed on both VT6202 and VT8235.
717 if ((ehci->async->qh_next.ptr != 0) || (ehci->periodic_sched != 0))
718 timer_action (ehci, TIMER_IO_WATCHDOG);
721 /*-------------------------------------------------------------------------*/
723 static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
725 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
729 spin_lock (&ehci->lock);
731 status = readl (&ehci->regs->status);
735 spin_unlock (&ehci->lock);
739 /* e.g. cardbus physical eject */
740 if (status == ~(u32) 0) {
741 ehci_dbg (ehci, "device removed\n");
746 if (!status) /* irq sharing? */
749 /* clear (just) interrupts */
750 writel (status, &ehci->regs->status);
751 readl (&ehci->regs->command); /* unblock posted write */
754 #ifdef EHCI_VERBOSE_DEBUG
755 /* unrequested/ignored: Port Change Detect, Frame List Rollover */
756 dbg_status (ehci, "irq", status);
759 /* INT, ERR, and IAA interrupt rates can be throttled */
761 /* normal [4.15.1.2] or error [4.15.1.1] completion */
762 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
763 if (likely ((status & STS_ERR) == 0))
764 COUNT (ehci->stats.normal);
766 COUNT (ehci->stats.error);
770 /* complete the unlinking of some qh [4.15.2.3] */
771 if (status & STS_IAA) {
772 COUNT (ehci->stats.reclaim);
773 ehci->reclaim_ready = 1;
777 /* PCI errors [4.15.2.4] */
778 if (unlikely ((status & STS_FATAL) != 0)) {
779 ehci_err (ehci, "fatal error\n");
782 /* generic layer kills/unlinks all urbs, then
783 * uses ehci_stop to clean up the rest
789 ehci_work (ehci, regs);
791 spin_unlock (&ehci->lock);
795 /*-------------------------------------------------------------------------*/
798 * non-error returns are a promise to giveback() the urb later
799 * we drop ownership so next owner (or urb unlink) can get it
801 * urb + dev is in hcd.self.controller.urb_list
802 * we're queueing TDs onto software and hardware lists
804 * hcd-specific init for hcpriv hasn't been done yet
806 * NOTE: control, bulk, and interrupt share the same code to append TDs
807 * to a (possibly active) QH, and the same QH scanning code.
809 static int ehci_urb_enqueue (
814 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
815 struct list_head qtd_list;
817 urb->transfer_flags &= ~EHCI_STATE_UNLINK;
818 INIT_LIST_HEAD (&qtd_list);
820 switch (usb_pipetype (urb->pipe)) {
821 // case PIPE_CONTROL:
824 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
826 return submit_async (ehci, urb, &qtd_list, mem_flags);
829 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
831 return intr_submit (ehci, urb, &qtd_list, mem_flags);
833 case PIPE_ISOCHRONOUS:
834 if (urb->dev->speed == USB_SPEED_HIGH)
835 return itd_submit (ehci, urb, mem_flags);
837 return sitd_submit (ehci, urb, mem_flags);
841 /* remove from hardware lists
842 * completions normally happen asynchronously
845 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
847 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
851 spin_lock_irqsave (&ehci->lock, flags);
852 switch (usb_pipetype (urb->pipe)) {
853 // case PIPE_CONTROL:
856 qh = (struct ehci_qh *) urb->hcpriv;
860 /* if we need to use IAA and it's busy, defer */
861 if (qh->qh_state == QH_STATE_LINKED
863 && HCD_IS_RUNNING (ehci->hcd.state)
865 struct ehci_qh *last;
867 for (last = ehci->reclaim;
869 last = last->reclaim)
871 qh->qh_state = QH_STATE_UNLINK_WAIT;
874 /* bypass IAA if the hc can't care */
875 } else if (!HCD_IS_RUNNING (ehci->hcd.state) && ehci->reclaim)
876 end_unlink_async (ehci, NULL);
878 /* something else might have unlinked the qh by now */
879 if (qh->qh_state == QH_STATE_LINKED)
880 start_unlink_async (ehci, qh);
884 qh = (struct ehci_qh *) urb->hcpriv;
887 if (qh->qh_state == QH_STATE_LINKED) {
888 /* messy, can spin or block a microframe ... */
889 intr_deschedule (ehci, qh, 1);
890 /* qh_state == IDLE */
892 qh_completions (ehci, qh, NULL);
894 /* reschedule QH iff another request is queued */
895 if (!list_empty (&qh->qtd_list)
896 && HCD_IS_RUNNING (ehci->hcd.state)) {
899 status = qh_schedule (ehci, qh);
900 spin_unlock_irqrestore (&ehci->lock, flags);
903 // shouldn't happen often, but ...
904 // FIXME kill those tds' urbs
905 err ("can't reschedule qh %p, err %d",
912 case PIPE_ISOCHRONOUS:
915 // wait till next completion, do it then.
916 // completion irqs can wait up to 1024 msec,
917 urb->transfer_flags |= EHCI_STATE_UNLINK;
920 spin_unlock_irqrestore (&ehci->lock, flags);
924 /*-------------------------------------------------------------------------*/
926 // bulk qh holds the data toggle
929 ehci_endpoint_disable (struct usb_hcd *hcd, struct hcd_dev *dev, int ep)
931 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
936 /* ASSERT: any requests/urbs are being unlinked */
937 /* ASSERT: nobody can be submitting urbs for this any more */
939 epnum = ep & USB_ENDPOINT_NUMBER_MASK;
940 if (epnum != 0 && (ep & USB_DIR_IN))
944 spin_lock_irqsave (&ehci->lock, flags);
945 qh = (struct ehci_qh *) dev->ep [epnum];
949 /* endpoints can be iso streams. for now, we don't
950 * accelerate iso completions ... so spin a while.
952 if (qh->hw_info1 == 0) {
953 ehci_vdbg (ehci, "iso delay\n");
957 if (!HCD_IS_RUNNING (ehci->hcd.state))
958 qh->qh_state = QH_STATE_IDLE;
959 switch (qh->qh_state) {
960 case QH_STATE_UNLINK: /* wait for hw to finish? */
962 spin_unlock_irqrestore (&ehci->lock, flags);
963 set_current_state (TASK_UNINTERRUPTIBLE);
964 schedule_timeout (1);
966 case QH_STATE_IDLE: /* fully unlinked */
967 if (list_empty (&qh->qtd_list)) {
971 /* else FALL THROUGH */
973 /* caller was supposed to have unlinked any requests;
974 * that's not our job. just leak this memory.
976 ehci_err (ehci, "qh %p (#%d) state %d%s\n",
977 qh, epnum, qh->qh_state,
978 list_empty (&qh->qtd_list) ? "" : "(has tds)");
983 spin_unlock_irqrestore (&ehci->lock, flags);
987 /*-------------------------------------------------------------------------*/
989 static const struct hc_driver ehci_driver = {
990 .description = hcd_name,
993 * generic hardware linkage
996 .flags = HCD_MEMORY | HCD_USB2,
999 * basic lifecycle operations
1001 .reset = ehci_hc_reset,
1002 .start = ehci_start,
1004 .suspend = ehci_suspend,
1005 .resume = ehci_resume,
1010 * memory lifecycle (except per-request)
1012 .hcd_alloc = ehci_hcd_alloc,
1013 .hcd_free = ehci_hcd_free,
1016 * managing i/o requests and associated device resources
1018 .urb_enqueue = ehci_urb_enqueue,
1019 .urb_dequeue = ehci_urb_dequeue,
1020 .endpoint_disable = ehci_endpoint_disable,
1023 * scheduling support
1025 .get_frame_number = ehci_get_frame,
1030 .hub_status_data = ehci_hub_status_data,
1031 .hub_control = ehci_hub_control,
1034 /*-------------------------------------------------------------------------*/
1036 /* EHCI 1.0 doesn't require PCI */
1040 /* PCI driver selection metadata; PCI hotplugging uses this */
1041 static const struct pci_device_id pci_ids [] = { {
1042 /* handle any USB 2.0 EHCI controller */
1043 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
1044 .driver_data = (unsigned long) &ehci_driver,
1046 { /* end: all zeroes */ }
1048 MODULE_DEVICE_TABLE (pci, pci_ids);
1050 /* pci driver glue; this is a "new style" PCI driver module */
1051 static struct pci_driver ehci_pci_driver = {
1052 .name = (char *) hcd_name,
1053 .id_table = pci_ids,
1055 .probe = usb_hcd_pci_probe,
1056 .remove = usb_hcd_pci_remove,
1059 .suspend = usb_hcd_pci_suspend,
1060 .resume = usb_hcd_pci_resume,
1067 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1069 MODULE_DESCRIPTION (DRIVER_INFO);
1070 MODULE_AUTHOR (DRIVER_AUTHOR);
1071 MODULE_LICENSE ("GPL");
1073 static int __init init (void)
1078 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1080 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
1081 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
1083 return pci_module_init (&ehci_pci_driver);
1087 static void __exit cleanup (void)
1089 pci_unregister_driver (&ehci_pci_driver);
1091 module_exit (cleanup);