2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/config.h>
21 #ifdef CONFIG_USB_DEBUG
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/smp_lock.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/reboot.h>
42 #include <linux/usb.h>
43 #include <linux/moduleparam.h>
44 #include <linux/dma-mapping.h>
46 #include "../core/hcd.h"
48 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
55 /*-------------------------------------------------------------------------*/
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
75 * <sojkam@centrum.cz>, updates by DB).
77 * 2002-11-29 Correct handling for hw async_next register.
78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
79 * only scheduling is different, no arbitrary limitations.
80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
81 * clean up HC run state handshaking.
82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
85 * 2002-05-07 Some error path cleanups to report better errors; wmb();
86 * use non-CVS version id; better iso bandwidth claim.
87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
88 * errors in submit path. Bugfixes to interrupt scheduling/processing.
89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
90 * more checking to generic hcd framework (db). Make it work with
91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
92 * 2002-01-14 Minor cleanup; version synch.
93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
94 * 2002-01-04 Control/Bulk queuing behaves.
96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
97 * 2001-June Works with usb-storage and NEC EHCI on 2.4
100 #define DRIVER_VERSION "2004-May-10"
101 #define DRIVER_AUTHOR "David Brownell"
102 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
104 static const char hcd_name [] = "ehci_hcd";
107 #undef EHCI_VERBOSE_DEBUG
108 #undef EHCI_URB_TRACE
114 /* magic numbers that can affect system performance */
115 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
116 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
117 #define EHCI_TUNE_RL_TT 0
118 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
119 #define EHCI_TUNE_MULT_TT 1
120 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
122 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
123 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
124 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
125 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
127 /* Initial IRQ latency: lower than default */
128 static int log2_irq_thresh = 0; // 0 to 6
129 module_param (log2_irq_thresh, int, S_IRUGO);
130 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
132 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
134 /*-------------------------------------------------------------------------*/
137 #include "ehci-dbg.c"
139 /*-------------------------------------------------------------------------*/
142 * handshake - spin reading hc until handshake completes or fails
143 * @ptr: address of hc register to be read
144 * @mask: bits to look at in result of read
145 * @done: value of those bits when handshake succeeds
146 * @usec: timeout in microseconds
148 * Returns negative errno, or zero on success
150 * Success happens when the "mask" bits have the specified value (hardware
151 * handshake done). There are two failure modes: "usec" have passed (major
152 * hardware flakeout), or the register reads as all-ones (hardware removed).
154 * That last failure should_only happen in cases like physical cardbus eject
155 * before driver shutdown. But it also seems to be caused by bugs in cardbus
156 * bridge shutdown: shutting down the bridge before the devices using it.
158 static int handshake (u32 *ptr, u32 mask, u32 done, int usec)
163 result = readl (ptr);
164 if (result == ~(u32)0) /* card removed */
176 * hc states include: unknown, halted, ready, running
177 * transitional states are messy just now
178 * trying to avoid "running" unless urbs are active
179 * a "ready" hc can be finishing prefetched work
182 /* force HC to halt state from unknown (EHCI spec section 2.3) */
183 static int ehci_halt (struct ehci_hcd *ehci)
185 u32 temp = readl (&ehci->regs->status);
187 if ((temp & STS_HALT) != 0)
190 temp = readl (&ehci->regs->command);
192 writel (temp, &ehci->regs->command);
193 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
196 /* reset a non-running (STS_HALT == 1) controller */
197 static int ehci_reset (struct ehci_hcd *ehci)
199 u32 command = readl (&ehci->regs->command);
201 command |= CMD_RESET;
202 dbg_cmd (ehci, "reset", command);
203 writel (command, &ehci->regs->command);
204 ehci->hcd.state = USB_STATE_HALT;
205 ehci->next_statechange = jiffies;
206 return handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
209 /* idle the controller (from running) */
210 static void ehci_ready (struct ehci_hcd *ehci)
215 if (!HCD_IS_RUNNING (ehci->hcd.state))
219 /* wait for any schedule enables/disables to take effect */
221 if (ehci->async->qh_next.qh)
223 if (ehci->next_uframe != -1)
225 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
226 temp, 16 * 125) != 0) {
227 ehci->hcd.state = USB_STATE_HALT;
231 /* then disable anything that's still active */
232 temp = readl (&ehci->regs->command);
233 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
234 writel (temp, &ehci->regs->command);
236 /* hardware can take 16 microframes to turn off ... */
237 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
239 ehci->hcd.state = USB_STATE_HALT;
244 /*-------------------------------------------------------------------------*/
246 static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
248 #include "ehci-hub.c"
249 #include "ehci-mem.c"
251 #include "ehci-sched.c"
253 /*-------------------------------------------------------------------------*/
255 static void ehci_watchdog (unsigned long param)
257 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
260 spin_lock_irqsave (&ehci->lock, flags);
262 /* lost IAA irqs wedge things badly; seen with a vt8235 */
264 u32 status = readl (&ehci->regs->status);
266 if (status & STS_IAA) {
267 ehci_vdbg (ehci, "lost IAA\n");
268 COUNT (ehci->stats.lost_iaa);
269 writel (STS_IAA, &ehci->regs->status);
270 ehci->reclaim_ready = 1;
274 /* stop async processing after it's idled a bit */
275 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
276 start_unlink_async (ehci, ehci->async);
278 /* ehci could run by timer, without IRQs ... */
279 ehci_work (ehci, NULL);
281 spin_unlock_irqrestore (&ehci->lock, flags);
286 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
287 * off the controller (maybe it can boot from highspeed USB disks).
289 static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
291 if (cap & (1 << 16)) {
293 struct pci_dev *pdev = to_pci_dev(ehci->hcd.self.controller);
295 /* request handoff to OS */
297 pci_write_config_dword(pdev, where, cap);
299 /* and wait a while for it to happen */
303 pci_read_config_dword(pdev, where, &cap);
304 } while ((cap & (1 << 16)) && msec);
305 if (cap & (1 << 16)) {
306 ehci_err (ehci, "BIOS handoff failed (%d, %04x)\n",
310 ehci_dbg (ehci, "BIOS handoff succeeded\n");
318 ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
320 struct ehci_hcd *ehci;
322 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
324 /* make BIOS/etc use companion controller during reboot */
325 writel (0, &ehci->regs->configured_flag);
330 /* called by khubd or root hub init threads */
332 static int ehci_hc_reset (struct usb_hcd *hcd)
334 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
336 unsigned count = 256/4;
338 spin_lock_init (&ehci->lock);
340 ehci->caps = (struct ehci_caps *) hcd->regs;
341 ehci->regs = (struct ehci_regs *) (hcd->regs +
342 HC_LENGTH (readl (&ehci->caps->hc_capbase)));
343 dbg_hcs_params (ehci, "reset");
344 dbg_hcc_params (ehci, "reset");
347 writel(0, &ehci->regs->intr_enable);
348 /* EHCI 0.96 and later may have "extended capabilities" */
349 if (hcd->self.controller->bus == &pci_bus_type)
350 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
353 while (temp && count--) {
356 pci_read_config_dword (to_pci_dev(ehci->hcd.self.controller),
358 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
359 switch (cap & 0xff) {
360 case 1: /* BIOS/SMM/... handoff */
361 if (bios_handoff (ehci, temp, cap) != 0)
364 case 0x0a: /* appendix C */
365 ehci_dbg (ehci, "debug registers, BAR %d offset %d\n",
366 (cap >> 29) & 0x07, (cap >> 16) & 0x0fff);
368 case 0: /* illegal reserved capability */
369 ehci_warn (ehci, "illegal capability!\n");
372 default: /* unknown */
375 temp = (cap >> 8) & 0xff;
378 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
383 /* cache this readonly data; minimize PCI reads */
384 ehci->hcs_params = readl (&ehci->caps->hcs_params);
386 /* force HC to halt state */
387 return ehci_halt (ehci);
390 static int ehci_start (struct usb_hcd *hcd)
392 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
394 struct usb_device *udev;
400 init_timer (&ehci->watchdog);
401 ehci->watchdog.function = ehci_watchdog;
402 ehci->watchdog.data = (unsigned long) ehci;
405 * hw default: 1K periodic list heads, one per frame.
406 * periodic_size can shrink by USBCMD update if hcc_params allows.
408 ehci->periodic_size = DEFAULT_I_TDPS;
409 if ((retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
412 /* controllers may cache some of the periodic schedule ... */
413 hcc_params = readl (&ehci->caps->hcc_params);
414 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
416 else // N microframes cached
417 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
420 ehci->next_uframe = -1;
422 /* controller state: unknown --> reset */
424 /* EHCI spec section 4.1 */
425 if ((retval = ehci_reset (ehci)) != 0) {
426 ehci_mem_cleanup (ehci);
429 writel (INTR_MASK, &ehci->regs->intr_enable);
430 writel (ehci->periodic_dma, &ehci->regs->frame_list);
433 if (hcd->self.controller->bus == &pci_bus_type) {
434 struct pci_dev *pdev;
437 pdev = to_pci_dev(hcd->self.controller);
439 /* Serial Bus Release Number is at PCI 0x60 offset */
440 pci_read_config_byte(pdev, 0x60, &sbrn);
442 /* port wake capability, reported by boot firmware */
443 pci_read_config_word(pdev, 0x62, &port_wake);
444 hcd->can_wakeup = (port_wake & 1) != 0;
446 /* help hc dma work well with cachelines */
449 /* chip-specific init */
450 switch (pdev->vendor) {
451 case PCI_VENDOR_ID_ARC:
452 if (pdev->device == PCI_DEVICE_ID_ARC_EHCI)
453 ehci->is_arc_rh_tt = 1;
461 * dedicate a qh for the async ring head, since we couldn't unlink
462 * a 'real' qh without stopping the async schedule [4.8]. use it
463 * as the 'reclamation list head' too.
464 * its dummy is used in hw_alt_next of many tds, to prevent the qh
465 * from automatically advancing to the next td after short reads.
467 ehci->async->qh_next.qh = 0;
468 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
469 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
470 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
471 ehci->async->hw_qtd_next = EHCI_LIST_END;
472 ehci->async->qh_state = QH_STATE_LINKED;
473 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
474 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
477 * hcc_params controls whether ehci->regs->segment must (!!!)
478 * be used; it constrains QH/ITD/SITD and QTD locations.
479 * pci_pool consistent memory always uses segment zero.
480 * streaming mappings for I/O buffers, like pci_map_single(),
481 * can return segments above 4GB, if the device allows.
483 * NOTE: the dma mask is visible through dma_supported(), so
484 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
485 * Scsi_Host.highmem_io, and so forth. It's readonly to all
486 * host side drivers though.
488 if (HCC_64BIT_ADDR (hcc_params)) {
489 writel (0, &ehci->regs->segment);
491 // this is deeply broken on almost all architectures
492 if (!pci_set_dma_mask (to_pci_dev(ehci->hcd.self.controller), 0xffffffffffffffffULL))
493 ehci_info (ehci, "enabled 64bit PCI DMA\n");
497 /* clear interrupt enables, set irq latency */
498 temp = readl (&ehci->regs->command) & 0x0fff;
499 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
501 temp |= 1 << (16 + log2_irq_thresh);
502 // if hc can park (ehci >= 0.96), default is 3 packets per async QH
503 if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
504 /* periodic schedule size can be smaller than default */
506 temp |= (EHCI_TUNE_FLS << 2);
507 switch (EHCI_TUNE_FLS) {
508 case 0: ehci->periodic_size = 1024; break;
509 case 1: ehci->periodic_size = 512; break;
510 case 2: ehci->periodic_size = 256; break;
514 temp &= ~(CMD_IAAD | CMD_ASE | CMD_PSE),
515 // Philips, Intel, and maybe others need CMD_RUN before the
516 // root hub will detect new devices (why?); NEC doesn't
518 writel (temp, &ehci->regs->command);
519 dbg_cmd (ehci, "init", temp);
521 /* set async sleep time = 10 us ... ? */
523 /* wire up the root hub */
524 bus = hcd_to_bus (hcd);
525 udev = usb_alloc_dev (NULL, bus, 0);
528 ehci_mem_cleanup (ehci);
533 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
534 * are explicitly handed to companion controller(s), so no TT is
535 * involved with the root hub.
537 ehci->reboot_notifier.notifier_call = ehci_reboot;
538 register_reboot_notifier (&ehci->reboot_notifier);
540 ehci->hcd.state = USB_STATE_RUNNING;
541 writel (FLAG_CF, &ehci->regs->configured_flag);
542 readl (&ehci->regs->command); /* unblock posted write */
544 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
546 "USB %x.%x enabled, EHCI %x.%02x, driver %s\n",
547 ((sbrn & 0xf0)>>4), (sbrn & 0x0f),
548 temp >> 8, temp & 0xff, DRIVER_VERSION);
551 * From here on, khubd concurrently accesses the root
552 * hub; drivers will be talking to enumerated devices.
554 * Before this point the HC was idle/ready. After, khubd
555 * and device drivers may start it running.
557 udev->speed = USB_SPEED_HIGH;
558 if (hcd_register_root (udev, hcd) != 0) {
559 if (hcd->state == USB_STATE_RUNNING)
567 create_debug_files (ehci);
572 /* always called by thread; normally rmmod */
574 static void ehci_stop (struct usb_hcd *hcd)
576 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
578 ehci_dbg (ehci, "stop\n");
580 /* no more interrupts ... */
581 if (hcd->state == USB_STATE_RUNNING)
583 if (in_interrupt ()) { /* must not happen!! */
584 ehci_err (ehci, "stopped in_interrupt!\n");
587 del_timer_sync (&ehci->watchdog);
590 /* let companion controllers work when we aren't */
591 writel (0, &ehci->regs->configured_flag);
592 unregister_reboot_notifier (&ehci->reboot_notifier);
594 remove_debug_files (ehci);
596 /* root hub is shut down separately (first, when possible) */
597 spin_lock_irq (&ehci->lock);
599 ehci_work (ehci, NULL);
600 spin_unlock_irq (&ehci->lock);
601 ehci_mem_cleanup (ehci);
604 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
605 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
606 ehci->stats.lost_iaa);
607 ehci_dbg (ehci, "complete %ld unlink %ld\n",
608 ehci->stats.complete, ehci->stats.unlink);
611 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
614 static int ehci_get_frame (struct usb_hcd *hcd)
616 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
617 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
620 /*-------------------------------------------------------------------------*/
624 /* suspend/resume, section 4.3 */
626 /* These routines rely on PCI to handle powerdown and wakeup, and
627 * transceivers that don't need any software attention to set up
628 * the right sort of wakeup.
631 static int ehci_suspend (struct usb_hcd *hcd, u32 state)
633 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
635 while (time_before (jiffies, ehci->next_statechange))
638 #ifdef CONFIG_USB_SUSPEND
639 (void) usb_suspend_device (hcd->self.root_hub);
641 /* FIXME lock root hub */
642 (void) ehci_hub_suspend (hcd);
645 // save (PCI) FLADJ in case of Vaux power loss
650 static int ehci_resume (struct usb_hcd *hcd)
652 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
655 // maybe restore (PCI) FLADJ
657 while (time_before (jiffies, ehci->next_statechange))
660 #ifdef CONFIG_USB_SUSPEND
661 retval = usb_resume_device (hcd->self.root_hub);
663 /* FIXME lock root hub */
664 retval = ehci_hub_resume (hcd);
667 hcd->self.controller->power.power_state = 0;
673 /*-------------------------------------------------------------------------*/
676 * ehci_work is called from some interrupts, timers, and so on.
677 * it calls driver completion functions, after dropping ehci->lock.
679 static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
681 timer_action_done (ehci, TIMER_IO_WATCHDOG);
682 if (ehci->reclaim_ready)
683 end_unlink_async (ehci, regs);
684 scan_async (ehci, regs);
685 if (ehci->next_uframe != -1)
686 scan_periodic (ehci, regs);
688 /* the IO watchdog guards against hardware or driver bugs that
689 * misplace IRQs, and should let us run completely without IRQs.
690 * such lossage has been observed on both VT6202 and VT8235.
692 if ((ehci->async->qh_next.ptr != 0) || (ehci->periodic_sched != 0))
693 timer_action (ehci, TIMER_IO_WATCHDOG);
696 /*-------------------------------------------------------------------------*/
698 static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
700 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
704 spin_lock (&ehci->lock);
706 status = readl (&ehci->regs->status);
710 spin_unlock (&ehci->lock);
714 /* e.g. cardbus physical eject */
715 if (status == ~(u32) 0) {
716 ehci_dbg (ehci, "device removed\n");
721 if (!status) /* irq sharing? */
724 /* clear (just) interrupts */
725 writel (status, &ehci->regs->status);
726 readl (&ehci->regs->command); /* unblock posted write */
729 #ifdef EHCI_VERBOSE_DEBUG
730 /* unrequested/ignored: Frame List Rollover */
731 dbg_status (ehci, "irq", status);
734 /* INT, ERR, and IAA interrupt rates can be throttled */
736 /* normal [4.15.1.2] or error [4.15.1.1] completion */
737 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
738 if (likely ((status & STS_ERR) == 0))
739 COUNT (ehci->stats.normal);
741 COUNT (ehci->stats.error);
745 /* complete the unlinking of some qh [4.15.2.3] */
746 if (status & STS_IAA) {
747 COUNT (ehci->stats.reclaim);
748 ehci->reclaim_ready = 1;
752 /* remote wakeup [4.3.1] */
753 if ((status & STS_PCD) && ehci->hcd.remote_wakeup) {
754 unsigned i = HCS_N_PORTS (ehci->hcs_params);
756 /* resume root hub? */
757 status = readl (&ehci->regs->command);
758 if (!(status & CMD_RUN))
759 writel (status | CMD_RUN, &ehci->regs->command);
762 status = readl (&ehci->regs->port_status [i]);
763 if (status & PORT_OWNER)
765 if (!(status & PORT_RESUME)
766 || ehci->reset_done [i] != 0)
769 /* start 20 msec resume signaling from this port,
770 * and make khubd collect PORT_STAT_C_SUSPEND to
771 * stop that signaling.
773 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
774 mod_timer (&ehci->hcd.rh_timer,
775 ehci->reset_done [i] + 1);
776 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
780 /* PCI errors [4.15.2.4] */
781 if (unlikely ((status & STS_FATAL) != 0)) {
782 ehci_err (ehci, "fatal error\n");
785 /* generic layer kills/unlinks all urbs, then
786 * uses ehci_stop to clean up the rest
792 ehci_work (ehci, regs);
794 spin_unlock (&ehci->lock);
798 /*-------------------------------------------------------------------------*/
801 * non-error returns are a promise to giveback() the urb later
802 * we drop ownership so next owner (or urb unlink) can get it
804 * urb + dev is in hcd.self.controller.urb_list
805 * we're queueing TDs onto software and hardware lists
807 * hcd-specific init for hcpriv hasn't been done yet
809 * NOTE: control, bulk, and interrupt share the same code to append TDs
810 * to a (possibly active) QH, and the same QH scanning code.
812 static int ehci_urb_enqueue (
817 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
818 struct list_head qtd_list;
820 INIT_LIST_HEAD (&qtd_list);
822 switch (usb_pipetype (urb->pipe)) {
823 // case PIPE_CONTROL:
826 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
828 return submit_async (ehci, urb, &qtd_list, mem_flags);
831 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
833 return intr_submit (ehci, urb, &qtd_list, mem_flags);
835 case PIPE_ISOCHRONOUS:
836 if (urb->dev->speed == USB_SPEED_HIGH)
837 return itd_submit (ehci, urb, mem_flags);
839 return sitd_submit (ehci, urb, mem_flags);
843 /* remove from hardware lists
844 * completions normally happen asynchronously
847 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
849 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
853 spin_lock_irqsave (&ehci->lock, flags);
854 switch (usb_pipetype (urb->pipe)) {
855 // case PIPE_CONTROL:
858 qh = (struct ehci_qh *) urb->hcpriv;
862 /* if we need to use IAA and it's busy, defer */
863 if (qh->qh_state == QH_STATE_LINKED
865 && HCD_IS_RUNNING (ehci->hcd.state)
867 struct ehci_qh *last;
869 for (last = ehci->reclaim;
871 last = last->reclaim)
873 qh->qh_state = QH_STATE_UNLINK_WAIT;
876 /* bypass IAA if the hc can't care */
877 } else if (!HCD_IS_RUNNING (ehci->hcd.state) && ehci->reclaim)
878 end_unlink_async (ehci, NULL);
880 /* something else might have unlinked the qh by now */
881 if (qh->qh_state == QH_STATE_LINKED)
882 start_unlink_async (ehci, qh);
886 qh = (struct ehci_qh *) urb->hcpriv;
889 if (qh->qh_state == QH_STATE_LINKED) {
890 /* messy, can spin or block a microframe ... */
891 intr_deschedule (ehci, qh, 1);
892 /* qh_state == IDLE */
894 qh_completions (ehci, qh, NULL);
896 /* reschedule QH iff another request is queued */
897 if (!list_empty (&qh->qtd_list)
898 && HCD_IS_RUNNING (ehci->hcd.state)) {
901 status = qh_schedule (ehci, qh);
902 spin_unlock_irqrestore (&ehci->lock, flags);
905 // shouldn't happen often, but ...
906 // FIXME kill those tds' urbs
907 err ("can't reschedule qh %p, err %d",
914 case PIPE_ISOCHRONOUS:
917 // wait till next completion, do it then.
918 // completion irqs can wait up to 1024 msec,
921 spin_unlock_irqrestore (&ehci->lock, flags);
925 /*-------------------------------------------------------------------------*/
927 // bulk qh holds the data toggle
930 ehci_endpoint_disable (struct usb_hcd *hcd, struct hcd_dev *dev, int ep)
932 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
937 /* ASSERT: any requests/urbs are being unlinked */
938 /* ASSERT: nobody can be submitting urbs for this any more */
940 epnum = ep & USB_ENDPOINT_NUMBER_MASK;
941 if (epnum != 0 && (ep & USB_DIR_IN))
945 spin_lock_irqsave (&ehci->lock, flags);
946 qh = (struct ehci_qh *) dev->ep [epnum];
950 /* endpoints can be iso streams. for now, we don't
951 * accelerate iso completions ... so spin a while.
953 if (qh->hw_info1 == 0) {
954 ehci_vdbg (ehci, "iso delay\n");
958 if (!HCD_IS_RUNNING (ehci->hcd.state))
959 qh->qh_state = QH_STATE_IDLE;
960 switch (qh->qh_state) {
961 case QH_STATE_UNLINK: /* wait for hw to finish? */
963 spin_unlock_irqrestore (&ehci->lock, flags);
964 set_current_state (TASK_UNINTERRUPTIBLE);
965 schedule_timeout (1);
967 case QH_STATE_IDLE: /* fully unlinked */
968 if (list_empty (&qh->qtd_list)) {
972 /* else FALL THROUGH */
974 /* caller was supposed to have unlinked any requests;
975 * that's not our job. just leak this memory.
977 ehci_err (ehci, "qh %p (#%d) state %d%s\n",
978 qh, epnum, qh->qh_state,
979 list_empty (&qh->qtd_list) ? "" : "(has tds)");
984 spin_unlock_irqrestore (&ehci->lock, flags);
988 /*-------------------------------------------------------------------------*/
990 static const struct hc_driver ehci_driver = {
991 .description = hcd_name,
994 * generic hardware linkage
997 .flags = HCD_MEMORY | HCD_USB2,
1000 * basic lifecycle operations
1002 .reset = ehci_hc_reset,
1003 .start = ehci_start,
1005 .suspend = ehci_suspend,
1006 .resume = ehci_resume,
1011 * memory lifecycle (except per-request)
1013 .hcd_alloc = ehci_hcd_alloc,
1014 .hcd_free = ehci_hcd_free,
1017 * managing i/o requests and associated device resources
1019 .urb_enqueue = ehci_urb_enqueue,
1020 .urb_dequeue = ehci_urb_dequeue,
1021 .endpoint_disable = ehci_endpoint_disable,
1024 * scheduling support
1026 .get_frame_number = ehci_get_frame,
1031 .hub_status_data = ehci_hub_status_data,
1032 .hub_control = ehci_hub_control,
1035 /*-------------------------------------------------------------------------*/
1037 /* EHCI 1.0 doesn't require PCI */
1041 /* PCI driver selection metadata; PCI hotplugging uses this */
1042 static const struct pci_device_id pci_ids [] = { {
1043 /* handle any USB 2.0 EHCI controller */
1044 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
1045 .driver_data = (unsigned long) &ehci_driver,
1047 { /* end: all zeroes */ }
1049 MODULE_DEVICE_TABLE (pci, pci_ids);
1051 /* pci driver glue; this is a "new style" PCI driver module */
1052 static struct pci_driver ehci_pci_driver = {
1053 .name = (char *) hcd_name,
1054 .id_table = pci_ids,
1056 .probe = usb_hcd_pci_probe,
1057 .remove = usb_hcd_pci_remove,
1060 .suspend = usb_hcd_pci_suspend,
1061 .resume = usb_hcd_pci_resume,
1068 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1070 MODULE_DESCRIPTION (DRIVER_INFO);
1071 MODULE_AUTHOR (DRIVER_AUTHOR);
1072 MODULE_LICENSE ("GPL");
1074 static int __init init (void)
1079 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1081 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
1082 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
1084 return pci_module_init (&ehci_pci_driver);
1088 static void __exit cleanup (void)
1090 pci_unregister_driver (&ehci_pci_driver);
1092 module_exit (cleanup);