2 * Copyright (c) 2001-2003 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow *
47 periodic_next_shadow (union ehci_shadow *periodic, __le32 tag)
51 return &periodic->qh->qh_next;
53 return &periodic->fstn->fstn_next;
55 return &periodic->itd->itd_next;
58 return &periodic->sitd->sitd_next;
62 /* returns true after successful unlink */
63 /* caller must hold ehci->lock */
64 static int periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
66 union ehci_shadow *prev_p = &ehci->pshadow [frame];
67 __le32 *hw_p = &ehci->periodic [frame];
68 union ehci_shadow here = *prev_p;
69 union ehci_shadow *next_p;
71 /* find predecessor of "ptr"; hw and shadow lists are in sync */
72 while (here.ptr && here.ptr != ptr) {
73 prev_p = periodic_next_shadow (prev_p, Q_NEXT_TYPE (*hw_p));
74 hw_p = &here.qh->hw_next;
77 /* an interrupt entry (at list end) could have been shared */
79 dbg ("entry %p no longer on frame [%d]", ptr, frame);
82 // vdbg ("periodic unlink %p from frame %d", ptr, frame);
84 /* update hardware list ... HC may still know the old structure, so
85 * don't change hw_next until it'll have purged its cache
87 next_p = periodic_next_shadow (&here, Q_NEXT_TYPE (*hw_p));
88 *hw_p = here.qh->hw_next;
90 /* unlink from shadow list; HCD won't see old structure again */
97 /* how many of the uframe's 125 usecs are allocated? */
99 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
101 __le32 *hw_p = &ehci->periodic [frame];
102 union ehci_shadow *q = &ehci->pshadow [frame];
106 switch (Q_NEXT_TYPE (*hw_p)) {
108 /* is it in the S-mask? */
109 if (q->qh->hw_info2 & cpu_to_le32 (1 << uframe))
110 usecs += q->qh->usecs;
112 if (q->qh->hw_info2 & cpu_to_le32 (1 << (8 + uframe)))
113 usecs += q->qh->c_usecs;
114 hw_p = &q->qh->hw_next;
118 /* for "save place" FSTNs, count the relevant INTR
119 * bandwidth from the previous frame
121 if (q->fstn->hw_prev != EHCI_LIST_END) {
122 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
124 hw_p = &q->fstn->hw_next;
125 q = &q->fstn->fstn_next;
128 usecs += q->itd->usecs [uframe];
129 hw_p = &q->itd->hw_next;
130 q = &q->itd->itd_next;
133 /* is it in the S-mask? (count SPLIT, DATA) */
134 if (q->sitd->hw_uframe & cpu_to_le32 (1 << uframe)) {
135 if (q->sitd->hw_fullspeed_ep &
136 __constant_cpu_to_le32 (1<<31))
137 usecs += q->sitd->stream->usecs;
138 else /* worst case for OUT start-split */
139 usecs += HS_USECS_ISO (188);
142 /* ... C-mask? (count CSPLIT, DATA) */
143 if (q->sitd->hw_uframe &
144 cpu_to_le32 (1 << (8 + uframe))) {
145 /* worst case for IN complete-split */
146 usecs += q->sitd->stream->c_usecs;
149 hw_p = &q->sitd->hw_next;
150 q = &q->sitd->sitd_next;
158 err ("overallocated uframe %d, periodic is %d usecs",
159 frame * 8 + uframe, usecs);
164 /*-------------------------------------------------------------------------*/
166 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
168 if (!dev1->tt || !dev2->tt)
170 if (dev1->tt != dev2->tt)
173 return dev1->ttport == dev2->ttport;
178 /* return true iff the device's transaction translator is available
179 * for a periodic transfer starting at the specified frame, using
180 * all the uframes in the mask.
182 static int tt_no_collision (
183 struct ehci_hcd *ehci,
185 struct usb_device *dev,
190 if (period == 0) /* error */
193 /* note bandwidth wastage: split never follows csplit
194 * (different dev or endpoint) until the next uframe.
195 * calling convention doesn't make that distinction.
197 for (; frame < ehci->periodic_size; frame += period) {
198 union ehci_shadow here;
201 here = ehci->pshadow [frame];
202 type = Q_NEXT_TYPE (ehci->periodic [frame]);
206 type = Q_NEXT_TYPE (here.itd->hw_next);
207 here = here.itd->itd_next;
210 if (same_tt (dev, here.qh->dev)) {
213 mask = le32_to_cpu (here.qh->hw_info2);
214 /* "knows" no gap is needed */
219 type = Q_NEXT_TYPE (here.qh->hw_next);
220 here = here.qh->qh_next;
223 if (same_tt (dev, here.itd->urb->dev)) {
226 mask = le32_to_cpu (here.sitd
228 /* FIXME assumes no gap for IN! */
233 type = Q_NEXT_TYPE (here.qh->hw_next);
234 here = here.sitd->sitd_next;
239 "periodic frame %d bogus type %d\n",
243 /* collision or error */
252 /*-------------------------------------------------------------------------*/
254 static int enable_periodic (struct ehci_hcd *ehci)
259 /* did clearing PSE did take effect yet?
260 * takes effect only at frame boundaries...
262 status = handshake (&ehci->regs->status, STS_PSS, 0, 9 * 125);
264 ehci->hcd.state = USB_STATE_HALT;
268 cmd = readl (&ehci->regs->command) | CMD_PSE;
269 writel (cmd, &ehci->regs->command);
270 /* posted write ... PSS happens later */
271 ehci->hcd.state = USB_STATE_RUNNING;
273 /* make sure ehci_work scans these */
274 ehci->next_uframe = readl (&ehci->regs->frame_index)
275 % (ehci->periodic_size << 3);
279 static int disable_periodic (struct ehci_hcd *ehci)
284 /* did setting PSE not take effect yet?
285 * takes effect only at frame boundaries...
287 status = handshake (&ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
289 ehci->hcd.state = USB_STATE_HALT;
293 cmd = readl (&ehci->regs->command) & ~CMD_PSE;
294 writel (cmd, &ehci->regs->command);
295 /* posted write ... */
297 ehci->next_uframe = -1;
301 /*-------------------------------------------------------------------------*/
303 // FIXME microframe periods not yet handled
305 static void intr_deschedule (
306 struct ehci_hcd *ehci,
311 unsigned frame = qh->start;
314 periodic_unlink (ehci, frame, qh);
317 } while (frame < ehci->periodic_size);
319 qh->qh_state = QH_STATE_UNLINK;
320 qh->qh_next.ptr = NULL;
321 ehci->periodic_sched--;
323 /* maybe turn off periodic schedule */
324 if (!ehci->periodic_sched)
325 status = disable_periodic (ehci);
328 ehci_vdbg (ehci, "periodic schedule still enabled\n");
332 * If the hc may be looking at this qh, then delay a uframe
333 * (yeech!) to be sure it's done.
334 * No other threads may be mucking with this qh.
336 if (((ehci_get_frame (&ehci->hcd) - frame) % qh->period) == 0) {
339 qh->hw_next = EHCI_LIST_END;
341 /* we may not be IDLE yet, but if the qh is empty
342 * the race is very short. then if qh also isn't
343 * rescheduled soon, it won't matter. otherwise...
345 ehci_vdbg (ehci, "intr_deschedule...\n");
348 qh->hw_next = EHCI_LIST_END;
350 qh->qh_state = QH_STATE_IDLE;
352 /* update per-qh bandwidth utilization (for usbfs) */
353 hcd_to_bus (&ehci->hcd)->bandwidth_allocated -=
354 (qh->usecs + qh->c_usecs) / qh->period;
356 ehci_dbg (ehci, "descheduled qh%d/%p frame=%d count=%d, urbs=%d\n",
357 qh->period, qh, frame,
358 atomic_read (&qh->kref.refcount), ehci->periodic_sched);
361 static int check_period (
362 struct ehci_hcd *ehci,
368 /* complete split running into next frame?
369 * given FSTN support, we could sometimes check...
375 * 80% periodic == 100 usec/uframe available
376 * convert "usecs we need" to "max already claimed"
383 // FIXME delete when intr_submit handles non-empty queues
384 // this gives us a one intr/frame limit (vs N/uframe)
385 // ... and also lets us avoid tracking split transactions
386 // that might collide at a given TT/hub.
387 if (ehci->pshadow [frame].ptr)
390 claimed = periodic_usecs (ehci, frame, uframe);
394 // FIXME update to handle sub-frame periods
395 } while ((frame += period) < ehci->periodic_size);
401 static int check_intr_schedule (
402 struct ehci_hcd *ehci,
405 const struct ehci_qh *qh,
409 int retval = -ENOSPC;
411 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
419 /* This is a split transaction; check the bandwidth available for
420 * the completion too. Check both worst and best case gaps: worst
421 * case is SPLIT near uframe end, and CSPLIT near start ... best is
422 * vice versa. Difference can be almost two uframe times, but we
423 * reserve unnecessary bandwidth (waste it) this way. (Actually
424 * even better cases exist, like immediate device NAK.)
426 * FIXME don't even bother unless we know this TT is idle in that
427 * range of uframes ... for now, check_period() allows only one
428 * interrupt transfer per frame, so needn't check "TT busy" status
429 * when scheduling a split (QH, SITD, or FSTN).
431 * FIXME ehci 0.96 and above can use FSTNs
433 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
434 qh->period, qh->c_usecs))
436 if (!check_period (ehci, frame, uframe + qh->gap_uf,
437 qh->period, qh->c_usecs))
440 *c_maskp = cpu_to_le32 (0x03 << (8 + uframe + qh->gap_uf));
446 static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
451 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
453 qh_refresh(ehci, qh);
454 qh->hw_next = EHCI_LIST_END;
457 /* reuse the previous schedule slots, if we can */
458 if (frame < qh->period) {
459 uframe = ffs (le32_to_cpup (&qh->hw_info2) & 0x00ff);
460 status = check_intr_schedule (ehci, frame, --uframe,
468 /* else scan the schedule to find a group of slots such that all
469 * uframes have enough periodic bandwidth available.
472 frame = qh->period - 1;
474 for (uframe = 0; uframe < 8; uframe++) {
475 status = check_intr_schedule (ehci,
481 } while (status && frame--);
486 /* reset S-frame and (maybe) C-frame masks */
487 qh->hw_info2 &= ~__constant_cpu_to_le32(0xffff);
488 qh->hw_info2 |= cpu_to_le32 (1 << uframe) | c_mask;
490 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
492 /* stuff into the periodic schedule */
493 qh->qh_state = QH_STATE_LINKED;
495 "scheduled qh%d/%p usecs %d/%d starting %d.%d (gap %d)\n",
496 qh->period, qh, qh->usecs, qh->c_usecs,
497 frame, uframe, qh->gap_uf);
499 if (unlikely (ehci->pshadow [frame].ptr != 0)) {
501 // FIXME -- just link toward the end, before any qh with a shorter period,
502 // AND accommodate it already having been linked here (after some other qh)
503 // AS WELL AS updating the schedule checking logic
507 ehci->pshadow [frame].qh = qh_get (qh);
508 ehci->periodic [frame] =
509 QH_NEXT (qh->qh_dma);
513 } while (frame < ehci->periodic_size);
515 /* update per-qh bandwidth for usbfs */
516 hcd_to_bus (&ehci->hcd)->bandwidth_allocated +=
517 (qh->usecs + qh->c_usecs) / qh->period;
519 /* maybe enable periodic schedule processing */
520 if (!ehci->periodic_sched++)
521 status = enable_periodic (ehci);
526 static int intr_submit (
527 struct ehci_hcd *ehci,
529 struct list_head *qtd_list,
538 struct list_head empty;
540 /* get endpoint and transfer/schedule data */
541 epnum = usb_pipeendpoint (urb->pipe);
542 is_input = usb_pipein (urb->pipe);
546 spin_lock_irqsave (&ehci->lock, flags);
547 dev = (struct hcd_dev *)urb->dev->hcpriv;
549 /* get qh and force any scheduling errors */
550 INIT_LIST_HEAD (&empty);
551 qh = qh_append_tds (ehci, urb, &empty, epnum, &dev->ep [epnum]);
556 if (qh->qh_state == QH_STATE_IDLE) {
557 if ((status = qh_schedule (ehci, qh)) != 0)
561 /* then queue the urb's tds to the qh */
562 qh = qh_append_tds (ehci, urb, qtd_list, epnum, &dev->ep [epnum]);
565 /* ... update usbfs periodic stats */
566 hcd_to_bus (&ehci->hcd)->bandwidth_int_reqs++;
569 spin_unlock_irqrestore (&ehci->lock, flags);
571 qtd_list_free (ehci, urb, qtd_list);
576 /*-------------------------------------------------------------------------*/
578 /* ehci_iso_stream ops work with both ITD and SITD */
580 static struct ehci_iso_stream *
581 iso_stream_alloc (int mem_flags)
583 struct ehci_iso_stream *stream;
585 stream = kmalloc(sizeof *stream, mem_flags);
586 if (likely (stream != 0)) {
587 memset (stream, 0, sizeof(*stream));
588 INIT_LIST_HEAD(&stream->td_list);
589 INIT_LIST_HEAD(&stream->free_list);
590 stream->next_uframe = -1;
591 stream->refcount = 1;
598 struct ehci_iso_stream *stream,
599 struct usb_device *dev,
604 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
607 unsigned epnum, maxp;
612 * this might be a "high bandwidth" highspeed endpoint,
613 * as encoded in the ep descriptor's wMaxPacket field
615 epnum = usb_pipeendpoint (pipe);
616 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
618 maxp = dev->epmaxpacketin [epnum];
621 maxp = dev->epmaxpacketout [epnum];
625 /* knows about ITD vs SITD */
626 if (dev->speed == USB_SPEED_HIGH) {
627 unsigned multi = hb_mult(maxp);
629 stream->highspeed = 1;
631 maxp = max_packet(maxp);
635 stream->buf0 = cpu_to_le32 ((epnum << 8) | dev->devnum);
636 stream->buf1 = cpu_to_le32 (buf1);
637 stream->buf2 = cpu_to_le32 (multi);
639 /* usbfs wants to report the average usecs per frame tied up
640 * when transfers on this endpoint are scheduled ...
642 stream->usecs = HS_USECS_ISO (maxp);
643 bandwidth = stream->usecs * 8;
644 bandwidth /= 1 << (interval - 1);
649 addr = dev->ttport << 24;
650 addr |= dev->tt->hub->devnum << 16;
653 stream->usecs = HS_USECS_ISO (maxp);
658 stream->c_usecs = stream->usecs;
659 stream->usecs = HS_USECS_ISO (1);
660 stream->raw_mask = 1;
662 /* pessimistic c-mask */
663 tmp = usb_calc_bus_time (USB_SPEED_FULL, 1, 0, maxp)
665 stream->raw_mask |= 3 << (tmp + 9);
667 stream->raw_mask = smask_out [maxp / 188];
668 bandwidth = stream->usecs + stream->c_usecs;
669 bandwidth /= 1 << (interval + 2);
671 /* stream->splits gets created from raw_mask later */
672 stream->address = cpu_to_le32 (addr);
674 stream->bandwidth = bandwidth;
678 stream->bEndpointAddress = is_input | epnum;
679 stream->interval = interval;
684 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
688 /* free whenever just a dev->ep reference remains.
689 * not like a QH -- no persistent state (toggle, halt)
691 if (stream->refcount == 1) {
693 struct hcd_dev *dev = stream->udev->hcpriv;
695 // BUG_ON (!list_empty(&stream->td_list));
697 while (!list_empty (&stream->free_list)) {
698 struct list_head *entry;
700 entry = stream->free_list.next;
703 /* knows about ITD vs SITD */
704 if (stream->highspeed) {
705 struct ehci_itd *itd;
707 itd = list_entry (entry, struct ehci_itd,
709 dma_pool_free (ehci->itd_pool, itd,
712 struct ehci_sitd *sitd;
714 sitd = list_entry (entry, struct ehci_sitd,
716 dma_pool_free (ehci->sitd_pool, sitd,
721 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
722 stream->bEndpointAddress &= 0x0f;
723 dev->ep[is_in + stream->bEndpointAddress] = NULL;
725 if (stream->rescheduled) {
726 ehci_info (ehci, "ep%d%s-iso rescheduled "
727 "%lu times in %lu seconds\n",
728 stream->bEndpointAddress, is_in ? "in" : "out",
730 ((jiffies - stream->start)/HZ)
738 static inline struct ehci_iso_stream *
739 iso_stream_get (struct ehci_iso_stream *stream)
741 if (likely (stream != 0))
746 static struct ehci_iso_stream *
747 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
751 struct ehci_iso_stream *stream;
754 epnum = usb_pipeendpoint (urb->pipe);
755 if (usb_pipein(urb->pipe))
758 spin_lock_irqsave (&ehci->lock, flags);
760 dev = (struct hcd_dev *)urb->dev->hcpriv;
761 stream = dev->ep [epnum];
763 if (unlikely (stream == 0)) {
764 stream = iso_stream_alloc(GFP_ATOMIC);
765 if (likely (stream != 0)) {
766 /* dev->ep owns the initial refcount */
767 dev->ep[epnum] = stream;
768 iso_stream_init(stream, urb->dev, urb->pipe,
772 /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
773 } else if (unlikely (stream->hw_info1 != 0)) {
774 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
775 urb->dev->devpath, epnum & 0x0f,
776 (epnum & 0x10) ? "in" : "out");
780 /* caller guarantees an eventual matching iso_stream_put */
781 stream = iso_stream_get (stream);
783 spin_unlock_irqrestore (&ehci->lock, flags);
787 /*-------------------------------------------------------------------------*/
789 /* ehci_iso_sched ops can be shared, ITD-only, or SITD-only */
791 static struct ehci_iso_sched *
792 iso_sched_alloc (unsigned packets, int mem_flags)
794 struct ehci_iso_sched *iso_sched;
795 int size = sizeof *iso_sched;
797 size += packets * sizeof (struct ehci_iso_packet);
798 iso_sched = kmalloc (size, mem_flags);
799 if (likely (iso_sched != 0)) {
800 memset(iso_sched, 0, size);
801 INIT_LIST_HEAD (&iso_sched->td_list);
808 struct ehci_iso_sched *iso_sched,
809 struct ehci_iso_stream *stream,
814 dma_addr_t dma = urb->transfer_dma;
816 /* how many uframes are needed for these transfers */
817 iso_sched->span = urb->number_of_packets * stream->interval;
819 /* figure out per-uframe itd fields that we'll need later
820 * when we fit new itds into the schedule.
822 for (i = 0; i < urb->number_of_packets; i++) {
823 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
828 length = urb->iso_frame_desc [i].length;
829 buf = dma + urb->iso_frame_desc [i].offset;
831 trans = EHCI_ISOC_ACTIVE;
832 trans |= buf & 0x0fff;
833 if (unlikely (((i + 1) == urb->number_of_packets))
834 && !(urb->transfer_flags & URB_NO_INTERRUPT))
835 trans |= EHCI_ITD_IOC;
836 trans |= length << 16;
837 uframe->transaction = cpu_to_le32 (trans);
839 /* might need to cross a buffer page within a td */
840 uframe->bufp = (buf & ~(u64)0x0fff);
842 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
849 struct ehci_iso_stream *stream,
850 struct ehci_iso_sched *iso_sched
855 // caller must hold ehci->lock!
856 list_splice (&iso_sched->td_list, &stream->free_list);
861 itd_urb_transaction (
862 struct ehci_iso_stream *stream,
863 struct ehci_hcd *ehci,
868 struct ehci_itd *itd;
872 struct ehci_iso_sched *sched;
875 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
876 if (unlikely (sched == 0))
879 itd_sched_init (sched, stream, urb);
881 if (urb->interval < 8)
882 num_itds = 1 + (sched->span + 7) / 8;
884 num_itds = urb->number_of_packets;
886 /* allocate/init ITDs */
887 spin_lock_irqsave (&ehci->lock, flags);
888 for (i = 0; i < num_itds; i++) {
890 /* free_list.next might be cache-hot ... but maybe
891 * the HC caches it too. avoid that issue for now.
894 /* prefer previously-allocated itds */
895 if (likely (!list_empty(&stream->free_list))) {
896 itd = list_entry (stream->free_list.prev,
897 struct ehci_itd, itd_list);
898 list_del (&itd->itd_list);
899 itd_dma = itd->itd_dma;
904 spin_unlock_irqrestore (&ehci->lock, flags);
905 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
907 spin_lock_irqsave (&ehci->lock, flags);
910 if (unlikely (0 == itd)) {
911 iso_sched_free (stream, sched);
912 spin_unlock_irqrestore (&ehci->lock, flags);
915 memset (itd, 0, sizeof *itd);
916 itd->itd_dma = itd_dma;
917 list_add (&itd->itd_list, &sched->td_list);
919 spin_unlock_irqrestore (&ehci->lock, flags);
921 /* temporarily store schedule info in hcpriv */
923 urb->error_count = 0;
927 /*-------------------------------------------------------------------------*/
931 struct ehci_hcd *ehci,
940 /* can't commit more than 80% periodic == 100 usec */
941 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
945 /* we know urb->interval is 2^N uframes */
947 } while (uframe < mod);
953 struct ehci_hcd *ehci,
955 struct ehci_iso_stream *stream,
957 struct ehci_iso_sched *sched,
964 mask = stream->raw_mask << (uframe & 7);
966 /* for IN, don't wrap CSPLIT into the next frame */
970 /* this multi-pass logic is simple, but performance may
971 * suffer when the schedule data isn't cached.
974 /* check bandwidth */
975 uframe %= period_uframes;
982 /* tt must be idle for start(s), any gap, and csplit.
983 * assume scheduling slop leaves 10+% for control/bulk.
985 if (!tt_no_collision (ehci, period_uframes << 3,
986 stream->udev, frame, mask))
989 /* check starts (OUT uses more than one) */
990 max_used = 100 - stream->usecs;
991 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
992 if (periodic_usecs (ehci, frame, uf) > max_used)
996 /* for IN, check CSPLIT */
997 if (stream->c_usecs) {
998 max_used = 100 - stream->c_usecs;
1002 if ((stream->raw_mask & tmp) == 0)
1004 if (periodic_usecs (ehci, frame, uf)
1010 /* we know urb->interval is 2^N uframes */
1011 uframe += period_uframes;
1012 } while (uframe < mod);
1014 stream->splits = cpu_to_le32(stream->raw_mask << (uframe & 7));
1019 * This scheduler plans almost as far into the future as it has actual
1020 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1021 * "as small as possible" to be cache-friendlier.) That limits the size
1022 * transfers you can stream reliably; avoid more than 64 msec per urb.
1023 * Also avoid queue depths of less than ehci's worst irq latency (affected
1024 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1025 * and other factors); or more than about 230 msec total (for portability,
1026 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1029 #define SCHEDULE_SLOP 10 /* frames */
1032 iso_stream_schedule (
1033 struct ehci_hcd *ehci,
1035 struct ehci_iso_stream *stream
1038 u32 now, start, max, period;
1040 unsigned mod = ehci->periodic_size << 3;
1041 struct ehci_iso_sched *sched = urb->hcpriv;
1043 if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1044 ehci_dbg (ehci, "iso request %p too long\n", urb);
1049 if ((stream->depth + sched->span) > mod) {
1050 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1051 urb, stream->depth, sched->span, mod);
1056 now = readl (&ehci->regs->frame_index) % mod;
1058 /* when's the last uframe this urb could start? */
1061 /* typical case: reuse current schedule. stream is still active,
1062 * and no gaps from host falling behind (irq delays etc)
1064 if (likely (!list_empty (&stream->td_list))) {
1065 start = stream->next_uframe;
1068 if (likely ((start + sched->span) < max))
1070 /* else fell behind; someday, try to reschedule */
1075 /* need to schedule; when's the next (u)frame we could start?
1076 * this is bigger than ehci->i_thresh allows; scheduling itself
1077 * isn't free, the slop should handle reasonably slow cpus. it
1078 * can also help high bandwidth if the dma and irq loads don't
1079 * jump until after the queue is primed.
1081 start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1083 stream->next_uframe = start;
1085 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1087 period = urb->interval;
1088 if (!stream->highspeed)
1091 /* find a uframe slot with enough bandwidth */
1092 for (; start < (stream->next_uframe + period); start++) {
1095 /* check schedule: enough space? */
1096 if (stream->highspeed)
1097 enough_space = itd_slot_ok (ehci, mod, start,
1098 stream->usecs, period);
1100 if ((start % 8) >= 6)
1102 enough_space = sitd_slot_ok (ehci, mod, stream,
1103 start, sched, period);
1106 /* schedule it here if there's enough bandwidth */
1108 stream->next_uframe = start % mod;
1113 /* no room in the schedule */
1114 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1115 list_empty (&stream->td_list) ? "" : "re",
1120 iso_sched_free (stream, sched);
1125 urb->start_frame = stream->next_uframe;
1129 /*-------------------------------------------------------------------------*/
1132 itd_init (struct ehci_iso_stream *stream, struct ehci_itd *itd)
1136 itd->hw_next = EHCI_LIST_END;
1137 itd->hw_bufp [0] = stream->buf0;
1138 itd->hw_bufp [1] = stream->buf1;
1139 itd->hw_bufp [2] = stream->buf2;
1141 for (i = 0; i < 8; i++)
1144 /* All other fields are filled when scheduling */
1149 struct ehci_itd *itd,
1150 struct ehci_iso_sched *iso_sched,
1156 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1157 unsigned pg = itd->pg;
1159 // BUG_ON (pg == 6 && uf->cross);
1162 itd->index [uframe] = index;
1164 itd->hw_transaction [uframe] = uf->transaction;
1165 itd->hw_transaction [uframe] |= cpu_to_le32 (pg << 12);
1166 itd->hw_bufp [pg] |= cpu_to_le32 (uf->bufp & ~(u32)0);
1167 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(uf->bufp >> 32));
1169 /* iso_frame_desc[].offset must be strictly increasing */
1170 if (unlikely (!first && uf->cross)) {
1171 u64 bufp = uf->bufp + 4096;
1173 itd->hw_bufp [pg] |= cpu_to_le32 (bufp & ~(u32)0);
1174 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(bufp >> 32));
1179 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1181 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1182 itd->itd_next = ehci->pshadow [frame];
1183 itd->hw_next = ehci->periodic [frame];
1184 ehci->pshadow [frame].itd = itd;
1187 ehci->periodic [frame] = cpu_to_le32 (itd->itd_dma) | Q_TYPE_ITD;
1190 /* fit urb's itds into the selected schedule slot; activate as needed */
1193 struct ehci_hcd *ehci,
1196 struct ehci_iso_stream *stream
1199 int packet, first = 1;
1200 unsigned next_uframe, uframe, frame;
1201 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1202 struct ehci_itd *itd;
1204 next_uframe = stream->next_uframe % mod;
1206 if (unlikely (list_empty(&stream->td_list))) {
1207 hcd_to_bus (&ehci->hcd)->bandwidth_allocated
1208 += stream->bandwidth;
1210 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1211 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1212 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1214 next_uframe >> 3, next_uframe & 0x7);
1215 stream->start = jiffies;
1217 hcd_to_bus (&ehci->hcd)->bandwidth_isoc_reqs++;
1219 /* fill iTDs uframe by uframe */
1220 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1222 /* ASSERT: we have all necessary itds */
1223 // BUG_ON (list_empty (&iso_sched->td_list));
1225 /* ASSERT: no itds for this endpoint in this uframe */
1227 itd = list_entry (iso_sched->td_list.next,
1228 struct ehci_itd, itd_list);
1229 list_move_tail (&itd->itd_list, &stream->td_list);
1230 itd->stream = iso_stream_get (stream);
1231 itd->urb = usb_get_urb (urb);
1233 itd_init (stream, itd);
1236 uframe = next_uframe & 0x07;
1237 frame = next_uframe >> 3;
1239 itd->usecs [uframe] = stream->usecs;
1240 itd_patch (itd, iso_sched, packet, uframe, first);
1243 next_uframe += stream->interval;
1244 stream->depth += stream->interval;
1248 /* link completed itds into the schedule */
1249 if (((next_uframe >> 3) != frame)
1250 || packet == urb->number_of_packets) {
1251 itd_link (ehci, frame % ehci->periodic_size, itd);
1255 stream->next_uframe = next_uframe;
1257 /* don't need that schedule data any more */
1258 iso_sched_free (stream, iso_sched);
1261 timer_action (ehci, TIMER_IO_WATCHDOG);
1262 if (unlikely (!ehci->periodic_sched++))
1263 return enable_periodic (ehci);
1267 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1271 struct ehci_hcd *ehci,
1272 struct ehci_itd *itd,
1273 struct pt_regs *regs
1275 struct urb *urb = itd->urb;
1276 struct usb_iso_packet_descriptor *desc;
1280 struct ehci_iso_stream *stream = itd->stream;
1281 struct usb_device *dev;
1283 /* for each uframe with a packet */
1284 for (uframe = 0; uframe < 8; uframe++) {
1285 if (likely (itd->index[uframe] == -1))
1287 urb_index = itd->index[uframe];
1288 desc = &urb->iso_frame_desc [urb_index];
1290 t = le32_to_cpup (&itd->hw_transaction [uframe]);
1291 itd->hw_transaction [uframe] = 0;
1292 stream->depth -= stream->interval;
1294 /* report transfer status */
1295 if (unlikely (t & ISO_ERRS)) {
1297 if (t & EHCI_ISOC_BUF_ERR)
1298 desc->status = usb_pipein (urb->pipe)
1299 ? -ENOSR /* hc couldn't read */
1300 : -ECOMM; /* hc couldn't write */
1301 else if (t & EHCI_ISOC_BABBLE)
1302 desc->status = -EOVERFLOW;
1303 else /* (t & EHCI_ISOC_XACTERR) */
1304 desc->status = -EPROTO;
1306 /* HC need not update length with this error */
1307 if (!(t & EHCI_ISOC_BABBLE))
1308 desc->actual_length = EHCI_ITD_LENGTH (t);
1309 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1311 desc->actual_length = EHCI_ITD_LENGTH (t);
1318 list_move (&itd->itd_list, &stream->free_list);
1319 iso_stream_put (ehci, stream);
1321 /* handle completion now? */
1322 if (likely ((urb_index + 1) != urb->number_of_packets))
1325 /* ASSERT: it's really the last itd for this urb
1326 list_for_each_entry (itd, &stream->td_list, itd_list)
1327 BUG_ON (itd->urb == urb);
1330 /* give urb back to the driver ... can be out-of-order */
1331 dev = usb_get_dev (urb->dev);
1332 ehci_urb_done (ehci, urb, regs);
1335 /* defer stopping schedule; completion can submit */
1336 ehci->periodic_sched--;
1337 if (unlikely (!ehci->periodic_sched))
1338 (void) disable_periodic (ehci);
1339 hcd_to_bus (&ehci->hcd)->bandwidth_isoc_reqs--;
1341 if (unlikely (list_empty (&stream->td_list))) {
1342 hcd_to_bus (&ehci->hcd)->bandwidth_allocated
1343 -= stream->bandwidth;
1345 "deschedule devp %s ep%d%s-iso\n",
1346 dev->devpath, stream->bEndpointAddress & 0x0f,
1347 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1349 iso_stream_put (ehci, stream);
1355 /*-------------------------------------------------------------------------*/
1357 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb, int mem_flags)
1359 int status = -EINVAL;
1360 unsigned long flags;
1361 struct ehci_iso_stream *stream;
1363 /* Get iso_stream head */
1364 stream = iso_stream_find (ehci, urb);
1365 if (unlikely (stream == 0)) {
1366 ehci_dbg (ehci, "can't get iso stream\n");
1369 if (unlikely (urb->interval != stream->interval)) {
1370 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1371 stream->interval, urb->interval);
1375 #ifdef EHCI_URB_TRACE
1377 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1378 __FUNCTION__, urb->dev->devpath, urb,
1379 usb_pipeendpoint (urb->pipe),
1380 usb_pipein (urb->pipe) ? "in" : "out",
1381 urb->transfer_buffer_length,
1382 urb->number_of_packets, urb->interval,
1386 /* allocate ITDs w/o locking anything */
1387 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1388 if (unlikely (status < 0)) {
1389 ehci_dbg (ehci, "can't init itds\n");
1393 /* schedule ... need to lock */
1394 spin_lock_irqsave (&ehci->lock, flags);
1395 status = iso_stream_schedule (ehci, urb, stream);
1396 if (likely (status == 0))
1397 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1398 spin_unlock_irqrestore (&ehci->lock, flags);
1401 if (unlikely (status < 0))
1402 iso_stream_put (ehci, stream);
1406 #ifdef CONFIG_USB_EHCI_SPLIT_ISO
1408 /*-------------------------------------------------------------------------*/
1411 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1412 * TTs in USB 2.0 hubs. These need microframe scheduling.
1417 struct ehci_iso_sched *iso_sched,
1418 struct ehci_iso_stream *stream,
1423 dma_addr_t dma = urb->transfer_dma;
1425 /* how many frames are needed for these transfers */
1426 iso_sched->span = urb->number_of_packets * stream->interval;
1428 /* figure out per-frame sitd fields that we'll need later
1429 * when we fit new sitds into the schedule.
1431 for (i = 0; i < urb->number_of_packets; i++) {
1432 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1437 length = urb->iso_frame_desc [i].length & 0x03ff;
1438 buf = dma + urb->iso_frame_desc [i].offset;
1440 trans = SITD_STS_ACTIVE;
1441 if (((i + 1) == urb->number_of_packets)
1442 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1444 trans |= length << 16;
1445 packet->transaction = cpu_to_le32 (trans);
1447 /* might need to cross a buffer page within a td */
1450 packet->buf1 = buf & ~0x0fff;
1451 if (packet->buf1 != (buf & ~(u64)0x0fff))
1454 /* OUT uses multiple start-splits */
1455 if (stream->bEndpointAddress & USB_DIR_IN)
1457 length = 1 + (length / 188);
1458 packet->buf1 |= length;
1459 if (length > 1) /* BEGIN vs ALL */
1460 packet->buf1 |= 1 << 3;
1465 sitd_urb_transaction (
1466 struct ehci_iso_stream *stream,
1467 struct ehci_hcd *ehci,
1472 struct ehci_sitd *sitd;
1473 dma_addr_t sitd_dma;
1475 struct ehci_iso_sched *iso_sched;
1476 unsigned long flags;
1478 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1482 sitd_sched_init (iso_sched, stream, urb);
1484 /* allocate/init sITDs */
1485 spin_lock_irqsave (&ehci->lock, flags);
1486 for (i = 0; i < urb->number_of_packets; i++) {
1488 /* NOTE: for now, we don't try to handle wraparound cases
1489 * for IN (using sitd->hw_backpointer, like a FSTN), which
1490 * means we never need two sitds for full speed packets.
1493 /* free_list.next might be cache-hot ... but maybe
1494 * the HC caches it too. avoid that issue for now.
1497 /* prefer previously-allocated sitds */
1498 if (!list_empty(&stream->free_list)) {
1499 sitd = list_entry (stream->free_list.prev,
1500 struct ehci_sitd, sitd_list);
1501 list_del (&sitd->sitd_list);
1502 sitd_dma = sitd->sitd_dma;
1507 spin_unlock_irqrestore (&ehci->lock, flags);
1508 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1510 spin_lock_irqsave (&ehci->lock, flags);
1514 iso_sched_free (stream, iso_sched);
1515 spin_unlock_irqrestore (&ehci->lock, flags);
1518 memset (sitd, 0, sizeof *sitd);
1519 sitd->sitd_dma = sitd_dma;
1520 list_add (&sitd->sitd_list, &iso_sched->td_list);
1523 /* temporarily store schedule info in hcpriv */
1524 urb->hcpriv = iso_sched;
1525 urb->error_count = 0;
1527 spin_unlock_irqrestore (&ehci->lock, flags);
1531 /*-------------------------------------------------------------------------*/
1535 struct ehci_iso_stream *stream,
1536 struct ehci_sitd *sitd,
1537 struct ehci_iso_sched *iso_sched,
1541 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1542 u64 bufp = uf->bufp;
1544 sitd->hw_next = EHCI_LIST_END;
1545 sitd->hw_fullspeed_ep = stream->address;
1546 sitd->hw_uframe = stream->splits;
1547 sitd->hw_results = uf->transaction;
1548 sitd->hw_backpointer = EHCI_LIST_END;
1551 sitd->hw_buf [0] = cpu_to_le32 (bufp);
1552 sitd->hw_buf_hi [0] = cpu_to_le32 (bufp >> 32);
1554 sitd->hw_buf [1] = cpu_to_le32 (uf->buf1);
1557 sitd->hw_buf_hi [1] = cpu_to_le32 (bufp >> 32);
1559 sitd->index = index;
1563 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1565 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1566 sitd->sitd_next = ehci->pshadow [frame];
1567 sitd->hw_next = ehci->periodic [frame];
1568 ehci->pshadow [frame].sitd = sitd;
1569 sitd->frame = frame;
1571 ehci->periodic [frame] = cpu_to_le32 (sitd->sitd_dma) | Q_TYPE_SITD;
1574 /* fit urb's sitds into the selected schedule slot; activate as needed */
1577 struct ehci_hcd *ehci,
1580 struct ehci_iso_stream *stream
1584 unsigned next_uframe;
1585 struct ehci_iso_sched *sched = urb->hcpriv;
1586 struct ehci_sitd *sitd;
1588 next_uframe = stream->next_uframe;
1590 if (list_empty(&stream->td_list)) {
1591 /* usbfs ignores TT bandwidth */
1592 hcd_to_bus (&ehci->hcd)->bandwidth_allocated
1593 += stream->bandwidth;
1595 "sched dev%s ep%d%s-iso [%d] %dms/%04x\n",
1596 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1597 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1598 (next_uframe >> 3) % ehci->periodic_size,
1599 stream->interval, le32_to_cpu (stream->splits));
1600 stream->start = jiffies;
1602 hcd_to_bus (&ehci->hcd)->bandwidth_isoc_reqs++;
1604 /* fill sITDs frame by frame */
1605 for (packet = 0, sitd = NULL;
1606 packet < urb->number_of_packets;
1609 /* ASSERT: we have all necessary sitds */
1610 BUG_ON (list_empty (&sched->td_list));
1612 /* ASSERT: no itds for this endpoint in this frame */
1614 sitd = list_entry (sched->td_list.next,
1615 struct ehci_sitd, sitd_list);
1616 list_move_tail (&sitd->sitd_list, &stream->td_list);
1617 sitd->stream = iso_stream_get (stream);
1618 sitd->urb = usb_get_urb (urb);
1620 sitd_patch (stream, sitd, sched, packet);
1621 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1624 next_uframe += stream->interval << 3;
1625 stream->depth += stream->interval << 3;
1627 stream->next_uframe = next_uframe % mod;
1629 /* don't need that schedule data any more */
1630 iso_sched_free (stream, sched);
1633 timer_action (ehci, TIMER_IO_WATCHDOG);
1634 if (!ehci->periodic_sched++)
1635 return enable_periodic (ehci);
1639 /*-------------------------------------------------------------------------*/
1641 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1642 | SITD_STS_XACT | SITD_STS_MMF | SITD_STS_STS)
1646 struct ehci_hcd *ehci,
1647 struct ehci_sitd *sitd,
1648 struct pt_regs *regs
1650 struct urb *urb = sitd->urb;
1651 struct usb_iso_packet_descriptor *desc;
1654 struct ehci_iso_stream *stream = sitd->stream;
1655 struct usb_device *dev;
1657 urb_index = sitd->index;
1658 desc = &urb->iso_frame_desc [urb_index];
1659 t = le32_to_cpup (&sitd->hw_results);
1661 /* report transfer status */
1662 if (t & SITD_ERRS) {
1664 if (t & SITD_STS_DBE)
1665 desc->status = usb_pipein (urb->pipe)
1666 ? -ENOSR /* hc couldn't read */
1667 : -ECOMM; /* hc couldn't write */
1668 else if (t & SITD_STS_BABBLE)
1669 desc->status = -EOVERFLOW;
1670 else /* XACT, MMF, etc */
1671 desc->status = -EPROTO;
1674 desc->actual_length = desc->length - SITD_LENGTH (t);
1679 sitd->stream = NULL;
1680 list_move (&sitd->sitd_list, &stream->free_list);
1681 stream->depth -= stream->interval << 3;
1682 iso_stream_put (ehci, stream);
1684 /* handle completion now? */
1685 if ((urb_index + 1) != urb->number_of_packets)
1688 /* ASSERT: it's really the last sitd for this urb
1689 list_for_each_entry (sitd, &stream->td_list, sitd_list)
1690 BUG_ON (sitd->urb == urb);
1693 /* give urb back to the driver */
1694 dev = usb_get_dev (urb->dev);
1695 ehci_urb_done (ehci, urb, regs);
1698 /* defer stopping schedule; completion can submit */
1699 ehci->periodic_sched--;
1700 if (!ehci->periodic_sched)
1701 (void) disable_periodic (ehci);
1702 hcd_to_bus (&ehci->hcd)->bandwidth_isoc_reqs--;
1704 if (list_empty (&stream->td_list)) {
1705 hcd_to_bus (&ehci->hcd)->bandwidth_allocated
1706 -= stream->bandwidth;
1708 "deschedule devp %s ep%d%s-iso\n",
1709 dev->devpath, stream->bEndpointAddress & 0x0f,
1710 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1712 iso_stream_put (ehci, stream);
1719 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb, int mem_flags)
1721 int status = -EINVAL;
1722 unsigned long flags;
1723 struct ehci_iso_stream *stream;
1725 // FIXME remove when csplits behave
1726 if (usb_pipein(urb->pipe)) {
1727 ehci_dbg (ehci, "no iso-IN split transactions yet\n");
1731 /* Get iso_stream head */
1732 stream = iso_stream_find (ehci, urb);
1734 ehci_dbg (ehci, "can't get iso stream\n");
1737 if (urb->interval != stream->interval) {
1738 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1739 stream->interval, urb->interval);
1743 #ifdef EHCI_URB_TRACE
1745 "submit %p dev%s ep%d%s-iso len %d\n",
1746 urb, urb->dev->devpath,
1747 usb_pipeendpoint (urb->pipe),
1748 usb_pipein (urb->pipe) ? "in" : "out",
1749 urb->transfer_buffer_length);
1752 /* allocate SITDs */
1753 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
1755 ehci_dbg (ehci, "can't init sitds\n");
1759 /* schedule ... need to lock */
1760 spin_lock_irqsave (&ehci->lock, flags);
1761 status = iso_stream_schedule (ehci, urb, stream);
1763 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1764 spin_unlock_irqrestore (&ehci->lock, flags);
1768 iso_stream_put (ehci, stream);
1775 sitd_submit (struct ehci_hcd *ehci, struct urb *urb, int mem_flags)
1777 ehci_dbg (ehci, "split iso support is disabled\n");
1781 static inline unsigned
1783 struct ehci_hcd *ehci,
1784 struct ehci_sitd *sitd,
1785 struct pt_regs *regs
1787 ehci_err (ehci, "sitd_complete %p?\n", sitd);
1791 #endif /* USB_EHCI_SPLIT_ISO */
1793 /*-------------------------------------------------------------------------*/
1796 scan_periodic (struct ehci_hcd *ehci, struct pt_regs *regs)
1798 unsigned frame, clock, now_uframe, mod;
1801 mod = ehci->periodic_size << 3;
1804 * When running, scan from last scan point up to "now"
1805 * else clean up by scanning everything that's left.
1806 * Touches as few pages as possible: cache-friendly.
1808 now_uframe = ehci->next_uframe;
1809 if (HCD_IS_RUNNING (ehci->hcd.state))
1810 clock = readl (&ehci->regs->frame_index);
1812 clock = now_uframe + mod - 1;
1816 union ehci_shadow q, *q_p;
1820 /* don't scan past the live uframe */
1821 frame = now_uframe >> 3;
1822 if (frame == (clock >> 3))
1823 uframes = now_uframe & 0x07;
1825 /* safe to scan the whole frame at once */
1831 /* scan each element in frame's queue for completions */
1832 q_p = &ehci->pshadow [frame];
1833 hw_p = &ehci->periodic [frame];
1835 type = Q_NEXT_TYPE (*hw_p);
1838 while (q.ptr != 0) {
1840 union ehci_shadow temp;
1843 live = HCD_IS_RUNNING (ehci->hcd.state);
1846 /* handle any completions */
1847 temp.qh = qh_get (q.qh);
1848 type = Q_NEXT_TYPE (q.qh->hw_next);
1850 modified = qh_completions (ehci, temp.qh, regs);
1851 if (unlikely (list_empty (&temp.qh->qtd_list)))
1852 intr_deschedule (ehci, temp.qh, 0);
1856 /* for "save place" FSTNs, look at QH entries
1857 * in the previous frame for completions.
1859 if (q.fstn->hw_prev != EHCI_LIST_END) {
1860 dbg ("ignoring completions from FSTNs");
1862 type = Q_NEXT_TYPE (q.fstn->hw_next);
1863 q = q.fstn->fstn_next;
1866 /* skip itds for later in the frame */
1868 for (uf = live ? uframes : 8; uf < 8; uf++) {
1869 if (0 == (q.itd->hw_transaction [uf]
1872 q_p = &q.itd->itd_next;
1873 hw_p = &q.itd->hw_next;
1874 type = Q_NEXT_TYPE (q.itd->hw_next);
1881 /* this one's ready ... HC won't cache the
1882 * pointer for much longer, if at all.
1884 *q_p = q.itd->itd_next;
1885 *hw_p = q.itd->hw_next;
1886 type = Q_NEXT_TYPE (q.itd->hw_next);
1888 modified = itd_complete (ehci, q.itd, regs);
1892 if ((q.sitd->hw_results & SITD_ACTIVE)
1894 q_p = &q.sitd->sitd_next;
1895 hw_p = &q.sitd->hw_next;
1896 type = Q_NEXT_TYPE (q.sitd->hw_next);
1900 *q_p = q.sitd->sitd_next;
1901 *hw_p = q.sitd->hw_next;
1902 type = Q_NEXT_TYPE (q.sitd->hw_next);
1904 modified = sitd_complete (ehci, q.sitd, regs);
1908 dbg ("corrupt type %d frame %d shadow %p",
1909 type, frame, q.ptr);
1914 /* assume completion callbacks modify the queue */
1915 if (unlikely (modified))
1919 /* stop when we catch up to the HC */
1921 // FIXME: this assumes we won't get lapped when
1922 // latencies climb; that should be rare, but...
1923 // detect it, and just go all the way around.
1924 // FLR might help detect this case, so long as latencies
1925 // don't exceed periodic_size msec (default 1.024 sec).
1927 // FIXME: likewise assumes HC doesn't halt mid-scan
1929 if (now_uframe == clock) {
1932 if (!HCD_IS_RUNNING (ehci->hcd.state))
1934 ehci->next_uframe = now_uframe;
1935 now = readl (&ehci->regs->frame_index) % mod;
1936 if (now_uframe == now)
1939 /* rescan the rest of this frame, then ... */