drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  11 {
  12         int             last = urb_priv->length - 1;
  13
  14         if (last >= 0) {
  15                 int             i;
  16                 struct td       *td;
  17
  18                 for (i = 0; i <= last; i++) {
  19                         td = urb_priv->td [i];
  20                         if (td)
  21                                 td_free (hc, td);
  22                 }
  23         }
  24
  25         list_del (&urb_priv->pending);
  26         kfree (urb_priv);
  27 }
  28
  29 /*-------------------------------------------------------------------------*/
  30
  31 /*
  32  * URB goes back to driver, and isn't reissued.
  33  * It's completely gone from HC data structures.
  34  * PRECONDITION:  ohci lock held, irqs blocked.
  35  */
  36 static void
  37 finish_urb (struct ohci_hcd *ohci, struct urb *urb, struct pt_regs *regs)
  38 __releases(ohci->lock)
  39 __acquires(ohci->lock)
  40 {
  41         // ASSERT (urb->hcpriv != 0);
  42
  43         urb_free_priv (ohci, urb->hcpriv);
  44         urb->hcpriv = NULL;
  45
  46         spin_lock (&urb->lock);
  47         if (likely (urb->status == -EINPROGRESS))
  48                 urb->status = 0;
  49         /* report short control reads right even though the data TD always
  50          * has TD_R set.  (much simpler, but creates the 1-td limit.)
  51          */
  52         if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK)
  53                         && unlikely (usb_pipecontrol (urb->pipe))
  54                         && urb->actual_length < urb->transfer_buffer_length
  55                         && usb_pipein (urb->pipe)
  56                         && urb->status == 0) {
  57                 urb->status = -EREMOTEIO;
  58         }
  59         spin_unlock (&urb->lock);
  60
  61         switch (usb_pipetype (urb->pipe)) {
  62         case PIPE_ISOCHRONOUS:
  63                 hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs--;
  64                 break;
  65         case PIPE_INTERRUPT:
  66                 hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs--;
  67                 break;
  68         }
  69
  70 #ifdef OHCI_VERBOSE_DEBUG
  71         urb_print (urb, "RET", usb_pipeout (urb->pipe));
  72 #endif
  73
  74         /* urb->complete() can reenter this HCD */
  75         spin_unlock (&ohci->lock);
  76         usb_hcd_giveback_urb (&ohci->hcd, urb, regs);
  77         spin_lock (&ohci->lock);
  78
  79         /* stop periodic dma if it's not needed */
  80         if (hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs == 0
  81                         && hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs == 0) {
  82                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  83                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  84         }
  85 }
  86
  87
  88 /*-------------------------------------------------------------------------*
  89  * ED handling functions
  90  *-------------------------------------------------------------------------*/
  91
  92 /* search for the right schedule branch to use for a periodic ed.
  93  * does some load balancing; returns the branch, or negative errno.
  94  */
  95 static int balance (struct ohci_hcd *ohci, int interval, int load)
  96 {
  97         int     i, branch = -ENOSPC;
  98
  99         /* iso periods can be huge; iso tds specify frame numbers */
 100         if (interval > NUM_INTS)
 101                 interval = NUM_INTS;
 102
 103         /* search for the least loaded schedule branch of that period
 104          * that has enough bandwidth left unreserved.
 105          */
 106         for (i = 0; i < interval ; i++) {
 107                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 108 #if 1   /* CONFIG_USB_BANDWIDTH */
 109                         int     j;
 110
 111                         /* usb 1.1 says 90% of one frame */
 112                         for (j = i; j < NUM_INTS; j += interval) {
 113                                 if ((ohci->load [j] + load) > 900)
 114                                         break;
 115                         }
 116                         if (j < NUM_INTS)
 117                                 continue;
 118 #endif
 119                         branch = i;
 120                 }
 121         }
 122         return branch;
 123 }
 124
 125 /*-------------------------------------------------------------------------*/
 126
 127 /* both iso and interrupt requests have periods; this routine puts them
 128  * into the schedule tree in the apppropriate place.  most iso devices use
 129  * 1msec periods, but that's not required.
 130  */
 131 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 132 {
 133         unsigned        i;
 134
 135         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 136                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 137                 ed, ed->branch, ed->load, ed->interval);
 138
 139         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 140                 struct ed       **prev = &ohci->periodic [i];
 141                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 142                 struct ed       *here = *prev;
 143
 144                 /* sorting each branch by period (slow before fast)
 145                  * lets us share the faster parts of the tree.
 146                  * (plus maybe: put interrupt eds before iso)
 147                  */
 148                 while (here && ed != here) {
 149                         if (ed->interval > here->interval)
 150                                 break;
 151                         prev = &here->ed_next;
 152                         prev_p = &here->hwNextED;
 153                         here = *prev;
 154                 }
 155                 if (ed != here) {
 156                         ed->ed_next = here;
 157                         if (here)
 158                                 ed->hwNextED = *prev_p;
 159                         wmb ();
 160                         *prev = ed;
 161                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 162                         wmb();
 163                 }
 164                 ohci->load [i] += ed->load;
 165         }
 166         hcd_to_bus (&ohci->hcd)->bandwidth_allocated += ed->load / ed->interval;
 167 }
 168
 169 /* link an ed into one of the HC chains */
 170
 171 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 172 {
 173         int     branch;
 174
 175         if (ohci->hcd.state == USB_STATE_QUIESCING)
 176                 return -EAGAIN;
 177
 178         ed->state = ED_OPER;
 179         ed->ed_prev = NULL;
 180         ed->ed_next = NULL;
 181         ed->hwNextED = 0;
 182         wmb ();
 183
 184         /* we care about rm_list when setting CLE/BLE in case the HC was at
 185          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 186          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 187          *
 188          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 189          * periodic ones are singly linked (ed_next). that's because the
 190          * periodic schedule encodes a tree like figure 3-5 in the ohci
 191          * spec:  each qh can have several "previous" nodes, and the tree
 192          * doesn't have unused/idle descriptors.
 193          */
 194         switch (ed->type) {
 195         case PIPE_CONTROL:
 196                 if (ohci->ed_controltail == NULL) {
 197                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 198                         ohci_writel (ohci, ed->dma,
 199                                         &ohci->regs->ed_controlhead);
 200                 } else {
 201                         ohci->ed_controltail->ed_next = ed;
 202                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 203                                                                 ed->dma);
 204                 }
 205                 ed->ed_prev = ohci->ed_controltail;
 206                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 207                         wmb();
 208                         ohci->hc_control |= OHCI_CTRL_CLE;
 209                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 210                         ohci_writel (ohci, ohci->hc_control,
 211                                         &ohci->regs->control);
 212                 }
 213                 ohci->ed_controltail = ed;
 214                 break;
 215
 216         case PIPE_BULK:
 217                 if (ohci->ed_bulktail == NULL) {
 218                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 219                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 220                 } else {
 221                         ohci->ed_bulktail->ed_next = ed;
 222                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 223                                                                 ed->dma);
 224                 }
 225                 ed->ed_prev = ohci->ed_bulktail;
 226                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 227                         wmb();
 228                         ohci->hc_control |= OHCI_CTRL_BLE;
 229                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 230                         ohci_writel (ohci, ohci->hc_control,
 231                                         &ohci->regs->control);
 232                 }
 233                 ohci->ed_bulktail = ed;
 234                 break;
 235
 236         // case PIPE_INTERRUPT:
 237         // case PIPE_ISOCHRONOUS:
 238         default:
 239                 branch = balance (ohci, ed->interval, ed->load);
 240                 if (branch < 0) {
 241                         ohci_dbg (ohci,
 242                                 "ERR %d, interval %d msecs, load %d\n",
 243                                 branch, ed->interval, ed->load);
 244                         // FIXME if there are TDs queued, fail them!
 245                         return branch;
 246                 }
 247                 ed->branch = branch;
 248                 periodic_link (ohci, ed);
 249         }
 250
 251         /* the HC may not see the schedule updates yet, but if it does
 252          * then they'll be properly ordered.
 253          */
 254         return 0;
 255 }
 256
 257 /*-------------------------------------------------------------------------*/
 258
 259 /* scan the periodic table to find and unlink this ED */
 260 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 261 {
 262         int     i;
 263
 264         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 265                 struct ed       *temp;
 266                 struct ed       **prev = &ohci->periodic [i];
 267                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 268
 269                 while (*prev && (temp = *prev) != ed) {
 270                         prev_p = &temp->hwNextED;
 271                         prev = &temp->ed_next;
 272                 }
 273                 if (*prev) {
 274                         *prev_p = ed->hwNextED;
 275                         *prev = ed->ed_next;
 276                 }
 277                 ohci->load [i] -= ed->load;
 278         }
 279         hcd_to_bus (&ohci->hcd)->bandwidth_allocated -= ed->load / ed->interval;
 280
 281         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 282                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 283                 ed, ed->branch, ed->load, ed->interval);
 284 }
 285
 286 /* unlink an ed from one of the HC chains.
 287  * just the link to the ed is unlinked.
 288  * the link from the ed still points to another operational ed or 0
 289  * so the HC can eventually finish the processing of the unlinked ed
 290  * (assuming it already started that, which needn't be true).
 291  *
 292  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 293  * it won't.  ED_SKIP means the HC will finish its current transaction,
 294  * but won't start anything new.  The TD queue may still grow; device
 295  * drivers don't know about this HCD-internal state.
 296  *
 297  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 298  *
 299  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 300  *    immediately.  HC should be working on them.
 301  *
 302  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 303  *    to care about this ED; safe to disable the endpoint.
 304  *
 305  * When finish_unlinks() runs later, after SOF interrupt, it will often
 306  * complete one or more URB unlinks before making that state change.
 307  */
 308 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 309 {
 310         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 311         wmb ();
 312         ed->state = ED_UNLINK;
 313
 314         /* To deschedule something from the control or bulk list, just
 315          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 316          * head/current registers until later, and "later" isn't very
 317          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 318          * the HC is reading the ED queues (while we modify them).
 319          *
 320          * For now, ed_schedule() is "later".  It might be good paranoia
 321          * to scrub those registers in finish_unlinks(), in case of bugs
 322          * that make the HC try to use them.
 323          */
 324         switch (ed->type) {
 325         case PIPE_CONTROL:
 326                 /* remove ED from the HC's list: */
 327                 if (ed->ed_prev == NULL) {
 328                         if (!ed->hwNextED) {
 329                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 330                                 ohci_writel (ohci, ohci->hc_control,
 331                                                 &ohci->regs->control);
 332                                 // a ohci_readl() later syncs CLE with the HC
 333                         } else
 334                                 ohci_writel (ohci,
 335                                         hc32_to_cpup (ohci, &ed->hwNextED),
 336                                         &ohci->regs->ed_controlhead);
 337                 } else {
 338                         ed->ed_prev->ed_next = ed->ed_next;
 339                         ed->ed_prev->hwNextED = ed->hwNextED;
 340                 }
 341                 /* remove ED from the HCD's list: */
 342                 if (ohci->ed_controltail == ed) {
 343                         ohci->ed_controltail = ed->ed_prev;
 344                         if (ohci->ed_controltail)
 345                                 ohci->ed_controltail->ed_next = NULL;
 346                 } else if (ed->ed_next) {
 347                         ed->ed_next->ed_prev = ed->ed_prev;
 348                 }
 349                 break;
 350
 351         case PIPE_BULK:
 352                 /* remove ED from the HC's list: */
 353                 if (ed->ed_prev == NULL) {
 354                         if (!ed->hwNextED) {
 355                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 356                                 ohci_writel (ohci, ohci->hc_control,
 357                                                 &ohci->regs->control);
 358                                 // a ohci_readl() later syncs BLE with the HC
 359                         } else
 360                                 ohci_writel (ohci,
 361                                         hc32_to_cpup (ohci, &ed->hwNextED),
 362                                         &ohci->regs->ed_bulkhead);
 363                 } else {
 364                         ed->ed_prev->ed_next = ed->ed_next;
 365                         ed->ed_prev->hwNextED = ed->hwNextED;
 366                 }
 367                 /* remove ED from the HCD's list: */
 368                 if (ohci->ed_bulktail == ed) {
 369                         ohci->ed_bulktail = ed->ed_prev;
 370                         if (ohci->ed_bulktail)
 371                                 ohci->ed_bulktail->ed_next = NULL;
 372                 } else if (ed->ed_next) {
 373                         ed->ed_next->ed_prev = ed->ed_prev;
 374                 }
 375                 break;
 376
 377         // case PIPE_INTERRUPT:
 378         // case PIPE_ISOCHRONOUS:
 379         default:
 380                 periodic_unlink (ohci, ed);
 381                 break;
 382         }
 383 }
 384
 385
 386 /*-------------------------------------------------------------------------*/
 387
 388 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 389  * of usb_set_configuration() or usb_set_interface() ... but the USB stack
 390  * isn't very stateful, so we re-init whenever the HC isn't looking.
 391  */
 392 static struct ed *ed_get (
 393         struct ohci_hcd         *ohci,
 394         struct usb_device       *udev,
 395         unsigned int            pipe,
 396         int                     interval
 397 ) {
 398         int                     is_out = !usb_pipein (pipe);
 399         int                     type = usb_pipetype (pipe);
 400         struct hcd_dev          *dev = (struct hcd_dev *) udev->hcpriv;
 401         struct ed               *ed;
 402         unsigned                ep;
 403         unsigned long           flags;
 404
 405         ep = usb_pipeendpoint (pipe) << 1;
 406         if (type != PIPE_CONTROL && is_out)
 407                 ep |= 1;
 408
 409         spin_lock_irqsave (&ohci->lock, flags);
 410
 411         if (!(ed = dev->ep [ep])) {
 412                 struct td       *td;
 413
 414                 ed = ed_alloc (ohci, GFP_ATOMIC);
 415                 if (!ed) {
 416                         /* out of memory */
 417                         goto done;
 418                 }
 419                 dev->ep [ep] = ed;
 420
 421                 /* dummy td; end of td list for ed */
 422                 td = td_alloc (ohci, GFP_ATOMIC);
 423                 if (!td) {
 424                         /* out of memory */
 425                         ed_free (ohci, ed);
 426                         ed = NULL;
 427                         goto done;
 428                 }
 429                 ed->dummy = td;
 430                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 431                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 432                 ed->state = ED_IDLE;
 433                 ed->type = type;
 434         }
 435
 436         /* NOTE: only ep0 currently needs this "re"init logic, during
 437          * enumeration (after set_address).
 438          */
 439         if (ed->state == ED_IDLE) {
 440                 u32     info;
 441
 442                 info = usb_pipedevice (pipe);
 443                 info |= (ep >> 1) << 7;
 444                 info |= usb_maxpacket (udev, pipe, is_out) << 16;
 445                 if (udev->speed == USB_SPEED_LOW)
 446                         info |= ED_LOWSPEED;
 447                 /* only control transfers store pids in tds */
 448                 if (type != PIPE_CONTROL) {
 449                         info |= is_out ? ED_OUT : ED_IN;
 450                         if (type != PIPE_BULK) {
 451                                 /* periodic transfers... */
 452                                 if (type == PIPE_ISOCHRONOUS)
 453                                         info |= ED_ISO;
 454                                 else if (interval > 32) /* iso can be bigger */
 455                                         interval = 32;
 456                                 ed->interval = interval;
 457                                 ed->load = usb_calc_bus_time (
 458                                         udev->speed, !is_out,
 459                                         type == PIPE_ISOCHRONOUS,
 460                                         usb_maxpacket (udev, pipe, is_out))
 461                                                 / 1000;
 462                         }
 463                 }
 464                 ed->hwINFO = cpu_to_hc32(ohci, info);
 465         }
 466
 467 done:
 468         spin_unlock_irqrestore (&ohci->lock, flags);
 469         return ed;
 470 }
 471
 472 /*-------------------------------------------------------------------------*/
 473
 474 /* request unlinking of an endpoint from an operational HC.
 475  * put the ep on the rm_list
 476  * real work is done at the next start frame (SF) hardware interrupt
 477  * caller guarantees HCD is running, so hardware access is safe,
 478  * and that ed->state is ED_OPER
 479  */
 480 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 481 {
 482         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 483         ed_deschedule (ohci, ed);
 484
 485         /* rm_list is just singly linked, for simplicity */
 486         ed->ed_next = ohci->ed_rm_list;
 487         ed->ed_prev = NULL;
 488         ohci->ed_rm_list = ed;
 489
 490         /* enable SOF interrupt */
 491         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 492         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 493         // flush those writes, and get latest HCCA contents
 494         (void) ohci_readl (ohci, &ohci->regs->control);
 495
 496         /* SF interrupt might get delayed; record the frame counter value that
 497          * indicates when the HC isn't looking at it, so concurrent unlinks
 498          * behave.  frame_no wraps every 2^16 msec, and changes right before
 499          * SF is triggered.
 500          */
 501         ed->tick = ohci_frame_no(ohci) + 1;
 502
 503 }
 504
 505 /*-------------------------------------------------------------------------*
 506  * TD handling functions
 507  *-------------------------------------------------------------------------*/
 508
 509 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 510
 511 static void
 512 td_fill (struct ohci_hcd *ohci, u32 info,
 513         dma_addr_t data, int len,
 514         struct urb *urb, int index)
 515 {
 516         struct td               *td, *td_pt;
 517         struct urb_priv         *urb_priv = urb->hcpriv;
 518         int                     is_iso = info & TD_ISO;
 519         int                     hash;
 520
 521         // ASSERT (index < urb_priv->length);
 522
 523         /* aim for only one interrupt per urb.  mostly applies to control
 524          * and iso; other urbs rarely need more than one TD per urb.
 525          * this way, only final tds (or ones with an error) cause IRQs.
 526          * at least immediately; use DI=6 in case any control request is
 527          * tempted to die part way through.  (and to force the hc to flush
 528          * its donelist soonish, even on unlink paths.)
 529          *
 530          * NOTE: could delay interrupts even for the last TD, and get fewer
 531          * interrupts ... increasing per-urb latency by sharing interrupts.
 532          * Drivers that queue bulk urbs may request that behavior.
 533          */
 534         if (index != (urb_priv->length - 1)
 535                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 536                 info |= TD_DI_SET (6);
 537
 538         /* use this td as the next dummy */
 539         td_pt = urb_priv->td [index];
 540
 541         /* fill the old dummy TD */
 542         td = urb_priv->td [index] = urb_priv->ed->dummy;
 543         urb_priv->ed->dummy = td_pt;
 544
 545         td->ed = urb_priv->ed;
 546         td->next_dl_td = NULL;
 547         td->index = index;
 548         td->urb = urb;
 549         td->data_dma = data;
 550         if (!len)
 551                 data = 0;
 552
 553         td->hwINFO = cpu_to_hc32 (ohci, info);
 554         if (is_iso) {
 555                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 556                 td->hwPSW [0] = cpu_to_hc16 (ohci, (data & 0x0FFF) | 0xE000);
 557                 td->ed->last_iso = info & 0xffff;
 558         } else {
 559                 td->hwCBP = cpu_to_hc32 (ohci, data);
 560         }
 561         if (data)
 562                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 563         else
 564                 td->hwBE = 0;
 565         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 566
 567         /* append to queue */
 568         list_add_tail (&td->td_list, &td->ed->td_list);
 569
 570         /* hash it for later reverse mapping */
 571         hash = TD_HASH_FUNC (td->td_dma);
 572         td->td_hash = ohci->td_hash [hash];
 573         ohci->td_hash [hash] = td;
 574
 575         /* HC might read the TD (or cachelines) right away ... */
 576         wmb ();
 577         td->ed->hwTailP = td->hwNextTD;
 578 }
 579
 580 /*-------------------------------------------------------------------------*/
 581
 582 /* Prepare all TDs of a transfer, and queue them onto the ED.
 583  * Caller guarantees HC is active.
 584  * Usually the ED is already on the schedule, so TDs might be
 585  * processed as soon as they're queued.
 586  */
 587 static void td_submit_urb (
 588         struct ohci_hcd *ohci,
 589         struct urb      *urb
 590 ) {
 591         struct urb_priv *urb_priv = urb->hcpriv;
 592         dma_addr_t      data;
 593         int             data_len = urb->transfer_buffer_length;
 594         int             cnt = 0;
 595         u32             info = 0;
 596         int             is_out = usb_pipeout (urb->pipe);
 597         int             periodic = 0;
 598
 599         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 600          * use the device toggle bits for resetting, and rely on the fact
 601          * that resetting toggle is meaningless if the endpoint is active.
 602          */
 603         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 604                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 605                         is_out, 1);
 606                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 607         }
 608
 609         urb_priv->td_cnt = 0;
 610         list_add (&urb_priv->pending, &ohci->pending);
 611
 612         if (data_len)
 613                 data = urb->transfer_dma;
 614         else
 615                 data = 0;
 616
 617         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 618          * using TD_CC_GET, as well as by seeing them on the done list.
 619          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 620          */
 621         switch (urb_priv->ed->type) {
 622
 623         /* Bulk and interrupt are identical except for where in the schedule
 624          * their EDs live.
 625          */
 626         case PIPE_INTERRUPT:
 627                 /* ... and periodic urbs have extra accounting */
 628                 periodic = hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs++ == 0
 629                         && hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs == 0;
 630                 /* FALLTHROUGH */
 631         case PIPE_BULK:
 632                 info = is_out
 633                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 634                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 635                 /* TDs _could_ transfer up to 8K each */
 636                 while (data_len > 4096) {
 637                         td_fill (ohci, info, data, 4096, urb, cnt);
 638                         data += 4096;
 639                         data_len -= 4096;
 640                         cnt++;
 641                 }
 642                 /* maybe avoid ED halt on final TD short read */
 643                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 644                         info |= TD_R;
 645                 td_fill (ohci, info, data, data_len, urb, cnt);
 646                 cnt++;
 647                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 648                                 && cnt < urb_priv->length) {
 649                         td_fill (ohci, info, 0, 0, urb, cnt);
 650                         cnt++;
 651                 }
 652                 /* maybe kickstart bulk list */
 653                 if (urb_priv->ed->type == PIPE_BULK) {
 654                         wmb ();
 655                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 656                 }
 657                 break;
 658
 659         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 660          * any DATA phase works normally, and the STATUS ack is special.
 661          */
 662         case PIPE_CONTROL:
 663                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 664                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 665                 if (data_len > 0) {
 666                         info = TD_CC | TD_R | TD_T_DATA1;
 667                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 668                         /* NOTE:  mishandles transfers >8K, some >4K */
 669                         td_fill (ohci, info, data, data_len, urb, cnt++);
 670                 }
 671                 info = is_out
 672                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 673                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 674                 td_fill (ohci, info, data, 0, urb, cnt++);
 675                 /* maybe kickstart control list */
 676                 wmb ();
 677                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 678                 break;
 679
 680         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 681          * Each TD could handle multiple consecutive frames (interval 1);
 682          * we could often reduce the number of TDs here.
 683          */
 684         case PIPE_ISOCHRONOUS:
 685                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
 686                         int     frame = urb->start_frame;
 687
 688                         // FIXME scheduling should handle frame counter
 689                         // roll-around ... exotic case (and OHCI has
 690                         // a 2^16 iso range, vs other HCs max of 2^10)
 691                         frame += cnt * urb->interval;
 692                         frame &= 0xffff;
 693                         td_fill (ohci, TD_CC | TD_ISO | frame,
 694                                 data + urb->iso_frame_desc [cnt].offset,
 695                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 696                 }
 697                 periodic = hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs++ == 0
 698                         && hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs == 0;
 699                 break;
 700         }
 701
 702         /* start periodic dma if needed */
 703         if (periodic) {
 704                 wmb ();
 705                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 706                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 707         }
 708
 709         // ASSERT (urb_priv->length == cnt);
 710 }
 711
 712 /*-------------------------------------------------------------------------*
 713  * Done List handling functions
 714  *-------------------------------------------------------------------------*/
 715
 716 /* calculate transfer length/status and update the urb
 717  * PRECONDITION:  irqsafe (only for urb->status locking)
 718  */
 719 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 720 {
 721         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 722         int     cc = 0;
 723
 724         list_del (&td->td_list);
 725
 726         /* ISO ... drivers see per-TD length/status */
 727         if (tdINFO & TD_ISO) {
 728                 u16     tdPSW = hc16_to_cpu (ohci, td->hwPSW [0]);
 729                 int     dlen = 0;
 730
 731                 /* NOTE:  assumes FC in tdINFO == 0 (and MAXPSW == 1) */
 732
 733                 cc = (tdPSW >> 12) & 0xF;
 734                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 735                         return;
 736
 737                 if (usb_pipeout (urb->pipe))
 738                         dlen = urb->iso_frame_desc [td->index].length;
 739                 else {
 740                         /* short reads are always OK for ISO */
 741                         if (cc == TD_DATAUNDERRUN)
 742                                 cc = TD_CC_NOERROR;
 743                         dlen = tdPSW & 0x3ff;
 744                 }
 745                 urb->actual_length += dlen;
 746                 urb->iso_frame_desc [td->index].actual_length = dlen;
 747                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 748
 749                 if (cc != TD_CC_NOERROR)
 750                         ohci_vdbg (ohci,
 751                                 "urb %p iso td %p (%d) len %d cc %d\n",
 752                                 urb, td, 1 + td->index, dlen, cc);
 753
 754         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 755          * except that "setup" bytes aren't counted and "short" transfers
 756          * might not be reported as errors.
 757          */
 758         } else {
 759                 int     type = usb_pipetype (urb->pipe);
 760                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 761
 762                 cc = TD_CC_GET (tdINFO);
 763
 764                 /* update packet status if needed (short is normally ok) */
 765                 if (cc == TD_DATAUNDERRUN
 766                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 767                         cc = TD_CC_NOERROR;
 768                 if (cc != TD_CC_NOERROR && cc < 0x0E) {
 769                         spin_lock (&urb->lock);
 770                         if (urb->status == -EINPROGRESS)
 771                                 urb->status = cc_to_error [cc];
 772                         spin_unlock (&urb->lock);
 773                 }
 774
 775                 /* count all non-empty packets except control SETUP packet */
 776                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 777                         if (td->hwCBP == 0)
 778                                 urb->actual_length += tdBE - td->data_dma + 1;
 779                         else
 780                                 urb->actual_length +=
 781                                           hc32_to_cpup (ohci, &td->hwCBP)
 782                                         - td->data_dma;
 783                 }
 784
 785                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 786                         ohci_vdbg (ohci,
 787                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 788                                 urb, td, 1 + td->index, cc,
 789                                 urb->actual_length,
 790                                 urb->transfer_buffer_length);
 791         }
 792 }
 793
 794 /*-------------------------------------------------------------------------*/
 795
 796 static inline struct td *
 797 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
 798 {
 799         struct urb              *urb = td->urb;
 800         struct ed               *ed = td->ed;
 801         struct list_head        *tmp = td->td_list.next;
 802         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 803
 804         /* clear ed halt; this is the td that caused it, but keep it inactive
 805          * until its urb->complete() has a chance to clean up.
 806          */
 807         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 808         wmb ();
 809         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 810
 811         /* put any later tds from this urb onto the donelist, after 'td',
 812          * order won't matter here: no errors, and nothing was transferred.
 813          * also patch the ed so it looks as if those tds completed normally.
 814          */
 815         while (tmp != &ed->td_list) {
 816                 struct td       *next;
 817                 __hc32          info;
 818
 819                 next = list_entry (tmp, struct td, td_list);
 820                 tmp = next->td_list.next;
 821
 822                 if (next->urb != urb)
 823                         break;
 824
 825                 /* NOTE: if multi-td control DATA segments get supported,
 826                  * this urb had one of them, this td wasn't the last td
 827                  * in that segment (TD_R clear), this ed halted because
 828                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 829                  * then we need to leave the control STATUS packet queued
 830                  * and clear ED_SKIP.
 831                  */
 832                 info = next->hwINFO;
 833                 info |= cpu_to_hc32 (ohci, TD_DONE);
 834                 info &= ~cpu_to_hc32 (ohci, TD_CC);
 835                 next->hwINFO = info;
 836
 837                 next->next_dl_td = rev;
 838                 rev = next;
 839
 840                 ed->hwHeadP = next->hwNextTD | toggle;
 841         }
 842
 843         /* help for troubleshooting:  report anything that
 844          * looks odd ... that doesn't include protocol stalls
 845          * (or maybe some other things)
 846          */
 847         switch (cc) {
 848         case TD_DATAUNDERRUN:
 849                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 850                         break;
 851                 /* fallthrough */
 852         case TD_CC_STALL:
 853                 if (usb_pipecontrol (urb->pipe))
 854                         break;
 855                 /* fallthrough */
 856         default:
 857                 ohci_dbg (ohci,
 858                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 859                         urb, urb->dev->devpath,
 860                         usb_pipeendpoint (urb->pipe),
 861                         usb_pipein (urb->pipe) ? "in" : "out",
 862                         hc32_to_cpu (ohci, td->hwINFO),
 863                         cc, cc_to_error [cc]);
 864         }
 865
 866         return rev;
 867 }
 868
 869 /* replies to the request have to be on a FIFO basis so
 870  * we unreverse the hc-reversed done-list
 871  */
 872 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 873 {
 874         u32             td_dma;
 875         struct td       *td_rev = NULL;
 876         struct td       *td = NULL;
 877
 878         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 879         ohci->hcca->done_head = 0;
 880         wmb();
 881
 882         /* get TD from hc's singly linked list, and
 883          * prepend to ours.  ed->td_list changes later.
 884          */
 885         while (td_dma) {
 886                 int             cc;
 887
 888                 td = dma_to_td (ohci, td_dma);
 889                 if (!td) {
 890                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 891                         break;
 892                 }
 893
 894                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 895                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 896
 897                 /* Non-iso endpoints can halt on error; un-halt,
 898                  * and dequeue any other TDs from this urb.
 899                  * No other TD could have caused the halt.
 900                  */
 901                 if (cc != TD_CC_NOERROR
 902                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 903                         td_rev = ed_halted (ohci, td, cc, td_rev);
 904
 905                 td->next_dl_td = td_rev;
 906                 td_rev = td;
 907                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 908         }
 909         return td_rev;
 910 }
 911
 912 /*-------------------------------------------------------------------------*/
 913
 914 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 915 static void
 916 finish_unlinks (struct ohci_hcd *ohci, u16 tick, struct pt_regs *regs)
 917 {
 918         struct ed       *ed, **last;
 919
 920 rescan_all:
 921         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 922                 struct list_head        *entry, *tmp;
 923                 int                     completed, modified;
 924                 __hc32                  *prev;
 925
 926                 /* only take off EDs that the HC isn't using, accounting for
 927                  * frame counter wraps and EDs with partially retired TDs
 928                  */
 929                 if (likely (regs && HCD_IS_RUNNING(ohci->hcd.state))) {
 930                         if (tick_before (tick, ed->tick)) {
 931 skip_ed:
 932                                 last = &ed->ed_next;
 933                                 continue;
 934                         }
 935
 936                         if (!list_empty (&ed->td_list)) {
 937                                 struct td       *td;
 938                                 u32             head;
 939
 940                                 td = list_entry (ed->td_list.next, struct td,
 941                                                         td_list);
 942                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 943                                                                 TD_MASK;
 944
 945                                 /* INTR_WDH may need to clean up first */
 946                                 if (td->td_dma != head)
 947                                         goto skip_ed;
 948                         }
 949                 }
 950
 951                 /* reentrancy:  if we drop the schedule lock, someone might
 952                  * have modified this list.  normally it's just prepending
 953                  * entries (which we'd ignore), but paranoia won't hurt.
 954                  */
 955                 *last = ed->ed_next;
 956                 ed->ed_next = NULL;
 957                 modified = 0;
 958
 959                 /* unlink urbs as requested, but rescan the list after
 960                  * we call a completion since it might have unlinked
 961                  * another (earlier) urb
 962                  *
 963                  * When we get here, the HC doesn't see this ed.  But it
 964                  * must not be rescheduled until all completed URBs have
 965                  * been given back to the driver.
 966                  */
 967 rescan_this:
 968                 completed = 0;
 969                 prev = &ed->hwHeadP;
 970                 list_for_each_safe (entry, tmp, &ed->td_list) {
 971                         struct td       *td;
 972                         struct urb      *urb;
 973                         urb_priv_t      *urb_priv;
 974                         __hc32          savebits;
 975
 976                         td = list_entry (entry, struct td, td_list);
 977                         urb = td->urb;
 978                         urb_priv = td->urb->hcpriv;
 979
 980                         if (urb->status == -EINPROGRESS) {
 981                                 prev = &td->hwNextTD;
 982                                 continue;
 983                         }
 984
 985                         /* patch pointer hc uses */
 986                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 987                         *prev = td->hwNextTD | savebits;
 988
 989                         /* HC may have partly processed this TD */
 990                         td_done (ohci, urb, td);
 991                         urb_priv->td_cnt++;
 992
 993                         /* if URB is done, clean up */
 994                         if (urb_priv->td_cnt == urb_priv->length) {
 995                                 modified = completed = 1;
 996                                 finish_urb (ohci, urb, regs);
 997                         }
 998                 }
 999                 if (completed && !list_empty (&ed->td_list))
1000                         goto rescan_this;
1001
1002                 /* ED's now officially unlinked, hc doesn't see */
1003                 ed->state = ED_IDLE;
1004                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1005                 ed->hwNextED = 0;
1006                 wmb ();
1007                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1008
1009                 /* but if there's work queued, reschedule */
1010                 if (!list_empty (&ed->td_list)) {
1011                         if (HCD_IS_RUNNING(ohci->hcd.state))
1012                                 ed_schedule (ohci, ed);
1013                 }
1014
1015                 if (modified)
1016                         goto rescan_all;
1017         }
1018
1019         /* maybe reenable control and bulk lists */
1020         if (HCD_IS_RUNNING(ohci->hcd.state)
1021                         && ohci->hcd.state != USB_STATE_QUIESCING
1022                         && !ohci->ed_rm_list) {
1023                 u32     command = 0, control = 0;
1024
1025                 if (ohci->ed_controltail) {
1026                         command |= OHCI_CLF;
1027                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1028                                 control |= OHCI_CTRL_CLE;
1029                                 ohci_writel (ohci, 0,
1030                                         &ohci->regs->ed_controlcurrent);
1031                         }
1032                 }
1033                 if (ohci->ed_bulktail) {
1034                         command |= OHCI_BLF;
1035                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1036                                 control |= OHCI_CTRL_BLE;
1037                                 ohci_writel (ohci, 0,
1038                                         &ohci->regs->ed_bulkcurrent);
1039                         }
1040                 }
1041
1042                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1043                 if (control) {
1044                         ohci->hc_control |= control;
1045                         ohci_writel (ohci, ohci->hc_control,
1046                                         &ohci->regs->control);
1047                 }
1048                 if (command)
1049                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1050         }
1051 }
1052
1053
1054
1055 /*-------------------------------------------------------------------------*/
1056
1057 /*
1058  * Process normal completions (error or success) and clean the schedules.
1059  *
1060  * This is the main path for handing urbs back to drivers.  The only other
1061  * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
1062  * scanning the (re-reversed) donelist as this does.
1063  */
1064 static void
1065 dl_done_list (struct ohci_hcd *ohci, struct pt_regs *regs)
1066 {
1067         struct td       *td = dl_reverse_done_list (ohci);
1068
1069         while (td) {
1070                 struct td       *td_next = td->next_dl_td;
1071                 struct urb      *urb = td->urb;
1072                 urb_priv_t      *urb_priv = urb->hcpriv;
1073                 struct ed       *ed = td->ed;
1074
1075                 /* update URB's length and status from TD */
1076                 td_done (ohci, urb, td);
1077                 urb_priv->td_cnt++;
1078
1079                 /* If all this urb's TDs are done, call complete() */
1080                 if (urb_priv->td_cnt == urb_priv->length)
1081                         finish_urb (ohci, urb, regs);
1082
1083                 /* clean schedule:  unlink EDs that are no longer busy */
1084                 if (list_empty (&ed->td_list)) {
1085                         if (ed->state == ED_OPER)
1086                                 start_ed_unlink (ohci, ed);
1087
1088                 /* ... reenabling halted EDs only after fault cleanup */
1089                 } else if ((ed->hwINFO & cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE))
1090                                         == cpu_to_hc32 (ohci, ED_SKIP)) {
1091                         td = list_entry (ed->td_list.next, struct td, td_list);
1092                         if (!(td->hwINFO & cpu_to_hc32 (ohci, TD_DONE))) {
1093                                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP);
1094                                 /* ... hc may need waking-up */
1095                                 switch (ed->type) {
1096                                 case PIPE_CONTROL:
1097                                         ohci_writel (ohci, OHCI_CLF,
1098                                                 &ohci->regs->cmdstatus);
1099                                         break;
1100                                 case PIPE_BULK:
1101                                         ohci_writel (ohci, OHCI_BLF,
1102                                                 &ohci->regs->cmdstatus);
1103                                         break;
1104                                 }
1105                         }
1106                 }
1107
1108                 td = td_next;
1109         }
1110 }