1 #ifndef __LINUX_UHCI_HCD_H
2 #define __LINUX_UHCI_HCD_H
4 #include <linux/list.h>
7 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8 #define PIPE_DEVEP_MASK 0x0007ff00
11 * Universal Host Controller Interface data structures and defines
14 /* Command register */
16 #define USBCMD_RS 0x0001 /* Run/Stop */
17 #define USBCMD_HCRESET 0x0002 /* Host reset */
18 #define USBCMD_GRESET 0x0004 /* Global reset */
19 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
20 #define USBCMD_FGR 0x0010 /* Force Global Resume */
21 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
22 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
23 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
27 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
28 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
29 #define USBSTS_RD 0x0004 /* Resume Detect */
30 #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
31 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
32 #define USBSTS_HCH 0x0020 /* HC Halted */
34 /* Interrupt enable register */
36 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
37 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
38 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
39 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
42 #define USBFLBASEADD 8
45 /* USB port status and control registers */
48 #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
49 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
50 #define USBPORTSC_PE 0x0004 /* Port Enable */
51 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
52 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
53 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
54 #define USBPORTSC_RD 0x0040 /* Resume Detect */
55 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
56 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
57 #define USBPORTSC_PR 0x0200 /* Port Reset */
58 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
59 #define USBPORTSC_OC 0x0400 /* Over Current condition */
60 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
61 #define USBPORTSC_SUSP 0x1000 /* Suspend */
62 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
63 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
64 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
66 /* Legacy support register */
67 #define USBLEGSUP 0xc0
68 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
70 #define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */
72 #define UHCI_PTR_BITS cpu_to_le32(0x000F)
73 #define UHCI_PTR_TERM cpu_to_le32(0x0001)
74 #define UHCI_PTR_QH cpu_to_le32(0x0002)
75 #define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
76 #define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
78 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
79 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
80 #define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */
82 struct uhci_frame_list {
83 u32 frame[UHCI_NUMFRAMES];
85 void *frame_cpu[UHCI_NUMFRAMES];
87 dma_addr_t dma_handle;
93 * One role of a QH is to hold a queue of TDs for some endpoint. Each QH is
94 * used with one URB, and qh->element (updated by the HC) is either:
95 * - the next unprocessed TD for the URB, or
96 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or
97 * - the QH for the next URB queued to the same endpoint.
99 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
100 * can easily splice a QH for some endpoint into the schedule at the right
101 * place. Then qh->element is UHCI_PTR_TERM.
103 * In the frame list, qh->link maintains a list of QHs seen by the HC:
104 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
107 /* Hardware fields */
108 u32 link; /* Next queue */
109 u32 element; /* Queue element pointer */
111 /* Software fields */
112 dma_addr_t dma_handle;
114 struct usb_device *dev;
115 struct urb_priv *urbp;
117 struct list_head list; /* P: uhci->frame_list_lock */
118 struct list_head remove_list; /* P: uhci->remove_list_lock */
119 } __attribute__((aligned(16)));
124 #define td_status(td) le32_to_cpu((td)->status)
125 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
126 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
127 #define TD_CTRL_C_ERR_SHIFT 27
128 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
129 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
130 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
131 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
132 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
133 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
134 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
135 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
136 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
137 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
138 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
140 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
141 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
143 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
144 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
145 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
148 * for TD <info>: (a.k.a. Token)
150 #define td_token(td) le32_to_cpu((td)->token)
151 #define TD_TOKEN_DEVADDR_SHIFT 8
152 #define TD_TOKEN_TOGGLE_SHIFT 19
153 #define TD_TOKEN_TOGGLE (1 << 19)
154 #define TD_TOKEN_EXPLEN_SHIFT 21
155 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n - 1 */
156 #define TD_TOKEN_PID_MASK 0xFF
158 #define uhci_explen(len) ((len) << TD_TOKEN_EXPLEN_SHIFT)
160 #define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK)
161 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
162 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
163 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
164 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
165 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
166 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
167 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
170 * The documentation says "4 words for hardware, 4 words for software".
172 * That's silly, the hardware doesn't care. The hardware only cares that
173 * the hardware words are 16-byte aligned, and we can have any amount of
174 * sw space after the TD entry as far as I can tell.
176 * But let's just go with the documentation, at least for 32-bit machines.
177 * On 64-bit machines we probably want to take advantage of the fact that
178 * hw doesn't really care about the size of the sw-only area.
180 * Alas, not anymore, we have more than 4 words for software, woops.
181 * Everything still works tho, surprise! -jerdfelt
183 * td->link points to either another TD (not necessarily for the same urb or
184 * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs)
187 /* Hardware fields */
193 /* Software fields */
194 dma_addr_t dma_handle;
196 struct usb_device *dev;
199 struct list_head list; /* P: urb->lock */
200 struct list_head remove_list; /* P: uhci->td_remove_list_lock */
202 int frame; /* for iso: what frame? */
203 struct list_head fl_list; /* P: uhci->frame_list_lock */
204 } __attribute__((aligned(16)));
207 * The UHCI driver places Interrupt, Control and Bulk into QH's both
208 * to group together TD's for one transfer, and also to faciliate queuing
209 * of URB's. To make it easy to insert entries into the schedule, we have
210 * a skeleton of QH's for each predefined Interrupt latency, low-speed
211 * control, full-speed control and terminating QH (see explanation for
212 * the terminating QH below).
214 * When we want to add a new QH, we add it to the end of the list for the
217 * For instance, the queue can look like this:
226 * skel low-speed control QH
228 * skel full-speed control QH
232 * skel terminating QH
234 * The terminating QH is used for 2 reasons:
235 * - To place a terminating TD which is used to workaround a PIIX bug
236 * (see Intel errata for explanation)
237 * - To loop back to the full-speed control queue for full-speed bandwidth
240 * Isochronous transfers are stored before the start of the skeleton
241 * schedule and don't use QH's. While the UHCI spec doesn't forbid the
242 * use of QH's for Isochronous, it doesn't use them either. Since we don't
243 * need to use them either, we follow the spec diagrams in hope that it'll
244 * be more compatible with future UHCI implementations.
247 #define UHCI_NUM_SKELQH 12
248 #define skel_int128_qh skelqh[0]
249 #define skel_int64_qh skelqh[1]
250 #define skel_int32_qh skelqh[2]
251 #define skel_int16_qh skelqh[3]
252 #define skel_int8_qh skelqh[4]
253 #define skel_int4_qh skelqh[5]
254 #define skel_int2_qh skelqh[6]
255 #define skel_int1_qh skelqh[7]
256 #define skel_ls_control_qh skelqh[8]
257 #define skel_fs_control_qh skelqh[9]
258 #define skel_bulk_qh skelqh[10]
259 #define skel_term_qh skelqh[11]
262 * Search tree for determining where <interval> fits in the skelqh[]
265 * An interrupt request should be placed into the slowest skelqh[]
266 * which meets the interval/period/frequency requirement.
267 * An interrupt request is allowed to be faster than <interval> but not slower.
269 * For a given <interval>, this function returns the appropriate/matching
270 * skelqh[] index value.
272 static inline int __interval_to_skel(int interval)
277 return 7; /* int1 for 0-1 ms */
278 return 6; /* int2 for 2-3 ms */
281 return 5; /* int4 for 4-7 ms */
282 return 4; /* int8 for 8-15 ms */
286 return 3; /* int16 for 16-31 ms */
287 return 2; /* int32 for 32-63 ms */
290 return 1; /* int64 for 64-127 ms */
291 return 0; /* int128 for 128-255 ms (Max.) */
295 * Device states for the host controller.
297 * To prevent "bouncing" in the presence of electrical noise,
298 * we insist on a 1-second "grace" period, before switching to
299 * the RUNNING or SUSPENDED states, during which the state is
300 * not allowed to change.
302 * The resume process is divided into substates in order to avoid
303 * potentially length delays during the timer handler.
305 * States in which the host controller is halted must have values <= 0.
309 UHCI_RUNNING_GRACE, /* Before RUNNING */
310 UHCI_RUNNING, /* The normal state */
311 UHCI_SUSPENDING_GRACE, /* Before SUSPENDED */
312 UHCI_SUSPENDED = -10, /* When no devices are attached */
317 #define hcd_to_uhci(hcd_ptr) container_of(hcd_ptr, struct uhci_hcd, hcd)
318 #define uhci_dev(u) ((u)->hcd.self.controller)
321 * This describes the full uhci information.
323 * Note how the "proper" USB information is just
324 * a subset of what the full implementation needs.
329 #ifdef CONFIG_PROC_FS
331 struct proc_dir_entry *proc_entry;
334 /* Grabbed from PCI */
335 unsigned long io_addr;
337 struct dma_pool *qh_pool;
338 struct dma_pool *td_pool;
342 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
343 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */
345 spinlock_t schedule_lock;
346 struct uhci_frame_list *fl; /* P: uhci->schedule_lock */
347 int fsbr; /* Full-speed bandwidth reclamation */
348 unsigned long fsbrtimeout; /* FSBR delay */
350 enum uhci_state state; /* FIXME: needs a spinlock */
351 unsigned long state_end; /* Time of next transition */
352 int resume_detect; /* Need a Global Resume */
353 unsigned int saved_framenumber; /* Save during PM suspend */
355 /* Main list of URB's currently controlled by this HC */
356 struct list_head urb_list; /* P: uhci->schedule_lock */
358 /* List of QH's that are done, but waiting to be unlinked (race) */
359 struct list_head qh_remove_list; /* P: uhci->schedule_lock */
360 unsigned int qh_remove_age; /* Age in frames */
362 /* List of TD's that are done, but waiting to be freed (race) */
363 struct list_head td_remove_list; /* P: uhci->schedule_lock */
364 unsigned int td_remove_age; /* Age in frames */
366 /* List of asynchronously unlinked URB's */
367 struct list_head urb_remove_list; /* P: uhci->schedule_lock */
368 unsigned int urb_remove_age; /* Age in frames */
370 /* List of URB's awaiting completion callback */
371 struct list_head complete_list; /* P: uhci->schedule_lock */
375 struct timer_list stall_timer;
377 wait_queue_head_t waitqh; /* endpoint_disable waiters */
381 struct list_head urb_list;
385 struct uhci_qh *qh; /* QH for this URB */
386 struct list_head td_list; /* P: urb->lock */
388 int fsbr : 1; /* URB turned on FSBR */
389 int fsbr_timeout : 1; /* URB timed out on FSBR */
390 int queued : 1; /* QH was queued (not linked in) */
391 int short_control_packet : 1; /* If we get a short packet during */
392 /* a control transfer, retrigger */
393 /* the status phase */
395 unsigned long inserttime; /* In jiffies */
396 unsigned long fsbrtime; /* In jiffies */
398 struct list_head queue_list; /* P: uhci->frame_list_lock */
404 * Almost everything relating to the hardware schedule and processing
405 * of URBs is protected by uhci->schedule_lock. urb->status is protected
406 * by urb->lock; that's the one exception.
408 * To prevent deadlocks, never lock uhci->schedule_lock while holding
409 * urb->lock. The safe order of locking is:
411 * #1 uhci->schedule_lock